Failure detection circuit and inverter system

Abstract

A failure detection circuit (103) for detecting an abnormality in an inrush current prevention circuit (102) which includes an inrush resistor (200) and an inrush relay (201) that are arranged in parallel comprises: a resistive voltage divider circuit (301) that divides a voltage across both ends of an inrush current prevention circuit (102); an amplification circuit (302) that amplifies the difference between the voltages obtained by dividing the voltage by the resistive voltage divider circuit (301); a peak hold circuit (303) that performs temporary peak hold of the voltage divided by the resistive voltage divider circuit (301); and a control unit (304) that, on the basis of respective signals output from the amplification circuit (302) and the peak hold circuit (303), detects a disconnection failure of the inrush resistor (200), a short-circuit failure of the inrush relay (201), and an open failure of the inrush relay (201), wherein the amplification circuit (302) and the peak hold circuit (303) are connected in parallel between the resistive voltage divider circuit (301) and the control unit (304).

Description

Fault Detection Circuit and Inverter System

[0001] The present disclosure relates to a fault detection circuit and an inverter system for an inrush current prevention unit of a power supply smoothed by a capacitor.

[0002] Generally, electrical equipment that receives power supply from a commercial power supply includes an inrush current prevention circuit that prevents a large current from flowing through electronic components due to inrush current. When charging a capacitor provided inside the electrical equipment, the inrush current prevention circuit initially charges through a resistor to prevent an excessive charging current from flowing through the capacitor. On the other hand, if charging through the resistor continues, the temperature of the resistor will exceed the allowable temperature. Therefore, after the capacitor is charged to a certain extent, a relay that bypasses both ends of the resistor is turned on to charge the capacitor without passing through the resistor.

[0003] When using electrical equipment in a state where the relay or resistor constituting the inrush current prevention circuit is faulty, an excessive inrush current may occur, or the components may overheat, which may cause a failure of the electrical equipment.

[0004] Patent Document 1 discloses a fault detection circuit that includes a peak hold circuit between an inrush resistor and a comparator, and monitors the voltage across both ends of the inrush resistor and the inrush relay connected in parallel to detect an open circuit fault of the inrush resistor and a short circuit fault of the inrush relay.

[0005] Japanese Unexamined Patent Application Publication No. 2022-59371

[0006] However, the fault detection circuit disclosed in Patent Document 1 cannot detect an open circuit fault of the inrush relay. Therefore, when an open circuit fault of the inrush relay occurs in electrical equipment such as a power converter, the reliability of the entire system may decrease, or the downtime during a fault may increase. For this reason, the realization of a fault detection circuit that can detect an open circuit fault of the inrush relay has been desired.

[0007] The present disclosure has been made in view of the above, and an object thereof is to obtain a fault detection circuit that can detect an open circuit fault of an inrush relay.

[0008] To solve the above-mentioned problems and achieve the objective, the fault detection circuit according to this disclosure detects abnormalities in an inrush current prevention circuit, including an inrush resistor and an inrush relay arranged in parallel. The fault detection circuit comprises a resistive voltage divider circuit that divides the voltage across the inrush current prevention circuit, an amplification circuit that amplifies the voltage difference divided by the resistive voltage divider circuit, a peak hold circuit that performs a temporary peak hold of the voltage divided by the resistive voltage divider circuit, and a control unit that detects open circuit faults of the inrush resistor, short circuit faults of the inrush relay, and open circuit faults of the inrush relay based on signals output from the amplification circuit and the peak hold circuit, respectively. The amplification circuit and the peak hold circuit are connected in parallel between the resistive voltage divider circuit and the control unit.

[0009] The fault detection circuit described herein has the effect of being able to detect an open fault in the inrush relay.

[0010]

[0011] The fault detection circuit and inverter system according to the embodiment will be described in detail below with reference to the drawings.

[0012] Embodiment 1. Figure 1 is a functional block diagram of a drive circuit equipped with a fault detection circuit according to Embodiment 1. The drive circuit 800 includes a rectifier circuit 100 for rectifying the AC power supply 10, a smoothing capacitor 101 for smoothing the pulsating current, an inrush current prevention circuit 102 for preventing a large current from flowing through the smoothing capacitor 101 due to inrush current, and a fault detection circuit 103 for detecting an abnormality in the inrush current prevention circuit 102. The drive circuit 800 is connected to an inverter 400. The drive circuit 800 and the inverter 400 form part of an inverter system 700 that supplies power to a load not shown. The inverter 400 is supplied with power whose voltage has been smoothed by the smoothing capacitor 101.

[0013] The inrush current prevention circuit 102 includes an inrush resistor 200 and an inrush relay 201 connected in parallel. The inrush current prevention circuit 102 prevents an excessive current from flowing when the power is turned on while the smoothing capacitor 101 has no charge.

[0014] The fault detection circuit 103 includes a resistive voltage divider circuit 301 that divides the voltage across the inrush current prevention circuit 102, an amplification circuit 302 that amplifies the output divided by the resistive voltage divider circuit 301, a peak hold circuit 303 that processes the voltage of the inrush current prevention circuit 102 as a signal, and a control unit 304 that determines a fault in the inrush current prevention circuit 102.

[0015] The resistive voltage divider circuit 301 divides the voltage applied across the inrush current prevention circuit 102. Since the busbar of the main circuit that supplies power to the inverter 400 has a voltage on the order of 100V, if this voltage were directly input to the control unit 304, the control unit 304 would be damaged. Therefore, the resistive voltage divider circuit 301 divides the voltage so that only a voltage on the order of 1V is input to the control unit 304.

[0016] Figure 2 shows an example of an amplification circuit for a fault detection circuit according to Embodiment 1. The amplification circuit 302 shown in Figure 2 amplifies the output divided by the resistor voltage divider circuit 301 shown in Figure 1 with an amplifier 401 and outputs it to the control unit 304 shown in Figure 1. Hereafter, the output voltage of the amplification circuit 302 will be referred to as Vr.

[0017] Figure 3 shows an example of a peak hold circuit according to Embodiment 1. The peak hold circuit 303 shown in Figure 3 temporarily holds the output divided by the resistor voltage divider circuit 301 shown in Figure 1 at the peak hold unit 501, and outputs it to the control unit 304 shown in Figure 1. Hereafter, the output voltage of the peak hold circuit 303 will be referred to as Vcg.

[0018] The control unit 304 detects whether the inrush resistor 200 and the inrush relay 201 are normal or abnormal based on the state of the voltage Vr output by the amplification circuit 302 and the voltage Vcg output by the peak hold circuit 303. In the case of an abnormal state, the control unit 304 distinguishes and detects whether it is an open circuit in the inrush resistor 200, an open fault in the inrush relay 201, or a short-circuit fault in the inrush relay 201.

[0019] Figure 4 shows the normal output voltage of the amplification circuit and peak hold circuit of the fault detection circuit according to Embodiment 1. In Figure 4, the vertical axis represents voltage and the horizontal axis represents time. In Figure 4, time t0 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In Figure 4, the dashed line represents voltage Vr and the solid line represents voltage Vcg. During normal operation, when the AC power supply 10 is turned on at time t0, the transformer that generates the voltage supplied to each circuit (not shown), including the fault detection circuit 103, starts up, and the generation of a control power supply with a voltage controlled for each circuit begins. At time t1, the control unit 304 starts up and the bus voltage becomes constant. Between time t0 and time t1, there is no charge in the smoothing capacitor 101, so a large charging current flows through the inrush resistor 200. From time t1 onward, due to the load on the control unit 304, a charging current with a component six times the AC power supply frequency flows through the inrush resistor 200 via the smoothing capacitor 101 by AC full-wave rectification. When the bus voltage exceeds a preset threshold, control is performed to turn on the inrush relay 201, and the inrush relay 201 turns on at time t2. When the inrush relay 201 is turned on, a charging current flows through the inrush relay 201, and no charging current flows through the inrush resistor 200. When the inverter output starts at time t3, a larger charging current flows through the inrush relay 201.

[0020] The behavior of the output voltage Vr of the amplifier circuit 302 and the output voltage Vcg of the peak hold circuit 303 under normal conditions is as follows. From time t1 onward, a charging current with a component six times the AC power supply frequency flows through the inrush resistor 200 due to AC full-wave rectification, so the output voltage Vr of the amplifier circuit 302 appears with a magnitude corresponding to the charging current. When the inrush relay 201 turns on at time t2, the discharge current stops flowing through the inrush resistor 200, so the output voltage Vr of the amplifier circuit 302 becomes 0V.

[0021] Furthermore, a large charging current flows through the inrush resistor 200 between time t0 and time t1, and the capacitor 503 is charged according to the voltage obtained by subtracting the forward voltage VF of the diode 502 of the peak hold section 501 from the divided voltage value of the resistor voltage divider circuit 301 at that time. At time t1, a voltage Vcg exceeding the judgment criterion value Vlevel 1 appears. After time t1, the charge of the capacitor 503 is discharged through the resistor 504, and the voltage Vcg decreases over time until it falls below the judgment criterion value Vlevel 1.

[0022] Figure 5 shows the voltage waveforms during an open fault of the inrush relay in the amplification circuit and peak hold circuit of the fault detection circuit according to Embodiment 1. In Figure 5, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 4, in Figure 5, time t0 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In Figure 5, the dashed line represents voltage Vr and the solid line represents voltage Vcg. In the case of an open fault of the inrush relay 201, even if control is performed to turn on the inrush relay 201 when the bus voltage exceeds a preset threshold, the inrush relay 201 does not turn on at time t2, so the charging current continues to flow through the inrush resistor 200 even after time t2. For this reason, in the case of an open fault of the inrush relay 201, the voltage Vr continues to appear at a constant value even after time t2. When the inverter 400's output is turned on at time t3, more charging current flows through the inrush resistor 200, causing the voltage Vr to increase further. The control unit 304 detects an open fault in the inrush relay 201 when the voltage Vr exceeds the judgment criterion value Vlevel 1.

[0023] Figure 6 shows the voltage waveforms when the inrush resistor of the amplification circuit and peak hold circuit of the fault detection circuit according to Embodiment 1 is disconnected. In Figure 6, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 4, in Figure 6, time t0 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In Figure 6, the dashed line represents voltage Vr and the solid line represents voltage Vcg. When the inrush resistor 200 is disconnected, the charging path to the smoothing capacitor 101 from time t0 when the AC power supply 10 is turned on is only the high-resistance resistive voltage divider circuit 301, so the voltage across the inrush current prevention circuit 102 is high at least from time t1 to time t3. In other words, when the inrush resistor 200 has a break in the circuit, the voltage Vr will remain at a constant value exceeding the judgment criterion value Vlevel 1 for at least the period from time t1 to time t3. The control unit 304 detects the break in the circuit of the inrush resistor 200 when the voltage Vr remains at a constant value exceeding the judgment criterion value Vlevel 1 from time t1 onward. Note that if the inrush relay 201 is turned on while the inrush resistor 200 has a break in the circuit, a large current will flow through the smoothing capacitor 101. Therefore, the control unit 304 detects the break in the circuit of the inrush resistor 200 before the control to turn on the inrush relay 201 is completed at time t2. For this reason, in actual control, the inrush relay 201 is not turned on even at time t2, when the control to turn on the inrush relay 201 is completed.

[0024] Figure 7 shows the voltage waveforms during a short-circuit failure of the inrush relay in the amplification circuit and peak hold circuit of the fault detection circuit according to Embodiment 1. In Figure 7, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 4, in Figure 7, time t0 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In Figure 7, the dashed line represents voltage Vr and the solid line represents voltage Vcg. In the event of a short-circuit failure of the inrush relay 201, no charge / discharge current flows through the inrush resistor 200 between time t0 when the AC power supply 10 is turned on and time t2 when the inrush relay 201 turns on. Therefore, even after time t1 when the control unit 304 is started, the voltage Vcg does not exceed the judgment criterion value Vlevel 1. The control unit 304 detects a short-circuit failure of the inrush relay 201 if the voltage Vcg does not exceed the judgment criterion value Vlevel1 between time t1 and time t2 when the control to turn on the inrush relay 201 is completed.

[0025] Figure 8 shows a modified example of the amplification circuit of the fault detection circuit according to Embodiment 1. The amplification circuit 302 according to the modified example includes a resistor 402 installed on the positive electrode 405, a resistor 403 installed between the positive electrode 405 and the negative electrode 406, and a diode 404 installed in parallel with the resistor 403 between the positive electrode 405 and the negative electrode 406. Between time t1 and time t2, current also flows in the discharge direction, but in the amplification circuit 302 according to the modified example, the voltage Vr becomes less than -0.3V due to the addition of resistors 402, 403 and the diode 404, and the control unit 304 is protected. The protection of the control unit 304 is not limited to the example circuit configuration, and any circuit configuration that can obtain a similar effect is acceptable.

[0026] Figure 9 shows a modified example of the peak hold circuit of the fault detection circuit according to Embodiment 1. The modified peak hold circuit 303 includes an overvoltage protection circuit 900. The overvoltage protection circuit 900 includes a first bipolar transistor 901, a second bipolar transistor 902, and a plurality of resistors 903, 904, 905, and 906. Since the withstand voltage of the control unit 304 before startup is approximately 0.3V, if the control unit 304 does not start up before voltage is charged to the capacitor 503, the control unit 304 may be damaged. However, when the control power supply is supplied, the second bipolar transistor 902 turns on, and then the first bipolar transistor 901 also turns on, so that the voltage Vcg is input to the control unit 304 and the control unit 304 is started up. The protection of the control unit 304 is not limited to the example circuit configuration, and any circuit configuration that can obtain a similar effect is acceptable.

[0027] Next, a method for further improving the accuracy of abnormality detection of the inrush relay 201 will be described. Figure 10 is a diagram showing the normal output voltage of the amplification circuit and peak hold circuit of the fault detection circuit according to the first modified example of Embodiment 1. In Figure 10, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 4, in Figure 10, time t0 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In Figure 10, the dashed line represents voltage Vr and the solid line represents voltage Vcg. The fault detection circuit 103 according to the first modified example of Embodiment 1 has a second judgment criterion value Vlevel 2 set, which is a value smaller than the first judgment criterion value Vlevel 1. The control unit 304 also makes judgments about each fault mode based on both voltage Vr and voltage Vcg. The behavior of voltages Vr and Vcg is the same as that of the amplification circuit 302 and peak hold circuit 303 of the fault detection circuit 103 according to Embodiment 1 shown in Figure 4. Immediately after the control unit 304 is activated at time t1, voltage Vcg exceeds the second judgment criterion value Vlevel 2, and thereafter voltage Vcg gradually decreases to be below the second judgment criterion value Vlevel 2.

[0028] Figure 11 shows the voltage waveforms during an open fault of the inrush relay in the amplification circuit and peak hold circuit of the fault detection circuit according to the first modification of Embodiment 1. In Figure 11, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 4, time t0 in Figure 11 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In Figure 11, the dashed line represents voltage Vr and the solid line represents voltage Vcg. When the inrush relay 201 has an open fault, a large charging current flows through the inrush resistor 200 between time t0 and time t1, and the capacitor 503 is charged according to the voltage obtained by subtracting the forward voltage VF of the diode 502 of the peak hold unit 501 from the divided voltage value of the resistor voltage divider circuit 301 at that time. At time t1, a voltage Vcg appears that exceeds the first reference value Vlevel1. After time t1, the charge of the capacitor 503 is discharged through the resistor 504, and the voltage Vcg decreases over time until it falls below the first judgment reference value Vlevel1. In the event of an open fault in the inrush relay 201, even if control is performed to turn on the inrush relay 201, the inrush relay 201 does not turn on at time t2, so the charging current continues to flow to the inrush resistor 200. For this reason, in the event of an open fault in the inrush relay 201, the voltage Vr continues to appear at a constant value even after time t2. Therefore, the control unit 304 detects an open fault in the inrush relay 201 when the voltage Vcg falls below the second judgment reference value Vlevel2 and the voltage Vr remains above the second judgment reference value Vlevel2 for a certain period of time after time t2. This allows for earlier detection of an open fault in the inrush relay 201 than the method shown in Figure 5.

[0029] In addition, depending on the load on the control unit 304, the voltage Vr may not exceed the second judgment criterion value Vlevel 2 even if the charging current continues to flow through the inrush resistor 200. To avoid failing to detect an open fault in the inrush relay 201 in such cases, the control unit 304 also detects an open fault in the inrush relay 201 when the voltage Vr exceeds the first judgment criterion value Vlevel 1 after the output of the inverter 400 is turned on, similar to the method shown in Figure 5.

[0030] Figure 12 shows the voltage waveforms during a short-circuit failure of the inrush relay in the amplification circuit and peak hold circuit of the fault detection circuit according to the first modification of Embodiment 1. In Figure 12, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 4, in Figure 12, time t0 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In Figure 12, the dashed line represents voltage Vr and the solid line represents voltage Vcg. In the event of a short-circuit failure of the inrush relay 201, no charge / discharge current flows through the inrush resistor 200 between time t0 when the AC power supply 10 is turned on and time t2 when the inrush relay 201 turns on. Therefore, even after time t1 when the control unit 304 is started, the voltages Vcg and Vr remain below the second judgment criterion value Vlevel 2. The control unit 304 detects a short-circuit failure in the inrush relay 201 based on the fact that the voltages Vcg and Vr are less than or equal to the second judgment criterion value Vlevel2 for a certain period of time between time t1 and time t2. The set value for the certain period of time can be set in advance according to the equipment and system used by the user.

[0031] In this way, by setting a fixed time that is shorter than the time from time t1 to time t3, which is the start timing of operation of the inverter 400, in addition to the first judgment criterion value Vlevel1 and the second judgment criterion value Vlevel2, the detection of a short-circuit fault in the inrush relay 201 can be achieved without any problems.

[0032] By detecting a short-circuit failure in the inrush relay 201 on the condition that voltages Vcg and Vr remain below the second judgment criterion value Vlevel 2 for a certain period of time after time t2, it is expected that false detections related to short-circuit failures in the inrush relay 201 can be prevented. Specifically, even in cases where a certain amount of charge has accumulated in the smoothing capacitor 101, suppressing the inrush current and preventing voltage Vcg from rising to the first judgment criterion value Vlevel 1, false detections of short-circuit failures in the inrush relay 201 can be prevented.

[0033] Furthermore, the method for determining a break in the inrush resistance 200 is the same as when only the first judgment criterion value Vlevel1 is used, and adding the second judgment criterion value Vlevel2 does not affect the determination.

[0034] The above explanation uses the example of a three-phase AC step input power supply, but the fault detection circuit 103 will operate without problems even with lamp input, single-phase AC, or DC input. The operation in various modes when the power supply is changed will be explained below.

[0035] Figure 13 shows the normal voltage waveforms of the amplification circuit and peak hold circuit of the fault detection circuit according to the first modification of Embodiment 1 when a three-phase AC lamp is input. In Figure 13, the vertical axis represents voltage and the horizontal axis represents time. In Figure 13, time t0 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes constant, and time t5 is the time when the inverter 400 starts outputting. In Figure 13, the dashed line represents voltage Vr and the solid line represents voltage Vcg. During normal operation, when the AC power supply 10 is turned on at time t0, the transformer that generates the voltage supplied to each circuit, including the fault detection circuit 103, is started, and each control power supply is generated.

[0036] At time t1, the control unit 304 is activated. Since the power supply is a lamp input, no large inrush current flows. After time t1, there is a load on the control unit 304, so a charging current with a component six times the AC power supply frequency flows through the inrush resistor 200 via the smoothing capacitor 101 by AC full-wave rectification. At time t2, when the bus voltage exceeds a threshold, the inrush relay 201 is controlled to turn on. At time t3, the inrush relay 201 turns on. When the inrush relay 201 turns on, a charging current flows through the inrush relay 201, and no charging current flows through the inrush resistor 200. At time t5, when the inverter 400 starts outputting, more charging current flows through the inrush relay 201. The voltage Vr appears in proportion to the charging current because after time t1, a charging current with a component six times the AC power supply frequency flows through the inrush resistor 200 by AC full-wave rectification. When the inrush relay 201 turns on at time t3, no charge / discharge current flows through the inrush resistor 200, and the voltage Vr becomes 0V. Because the power supply is a lamp input, a large charging current does not flow, so the voltage Vcg hardly appears after time t0.

[0037] Figure 14 shows the voltage waveforms of the amplification circuit and peak hold circuit of the fault detection circuit according to the first modification of Embodiment 1 when an inrush relay has an open fault during a three-phase AC lamp input. In Figure 14, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 13, in Figure 14, time t0 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes constant, and time t5 is the time when the inverter 400 starts outputting. In Figure 14, the dashed line represents voltage Vr and the solid line represents voltage Vcg. In the event of an open fault in the inrush relay 201, the inrush relay 201 does not turn on at time t3, so the charging current continues to flow through the inrush resistor 200 even after time t3, and the voltage Vr continues to appear at a value above a certain magnitude. When the inverter output turns on at time t5, more charging current flows through the inrush resistor 200, causing the value of the voltage Vr to increase even further. The control unit 304 detects an open fault in the inrush relay 201 when the value of the voltage Vr exceeds the first judgment criterion value Vlevel1.

[0038] In the case of an open fault in the inrush relay 201 when a three-phase AC lamp is input, the voltage Vcg hardly appears after time t0, so the method of using the fact that the voltage Vcg has dropped to below the second judgment criterion value Vlevel2, as shown in Figure 11, becomes unusable. Therefore, when a three-phase AC lamp is input, the voltage Vr is used to detect the open fault of the inrush relay 201.

[0039] Figure 15 shows the voltage waveforms during a break in the inrush resistance of the amplification circuit and peak hold circuit of the fault detection circuit according to the first modification of Embodiment 1 when a three-phase AC lamp is input. In Figure 15, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 13, in Figure 15, time t0 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes constant, and time t5 is the time when the inverter 400 starts outputting. In Figure 15, the dashed line represents voltage Vr and the solid line represents voltage Vcg. When the inrush resistor 200 has a broken circuit, from time t0 when the AC power supply 10 for the lamp input is turned on, the charging path to the smoothing capacitor 101 becomes only the high-resistance resistive voltage divider circuit 301, and the voltage across the inrush current prevention circuit 102 becomes high at least from time t1 to time t5. In other words, when the inrush resistor 200 has a broken circuit, from time t1 to at least time t5, the voltages Vr and Vcg exceed the judgment criterion value Vlevel1. The control unit 304 detects the inrush resistor 200's broken circuit when the voltages Vr and Vcg continue to exceed the judgment criterion value Vlevel1 for a predetermined first time from time t1 onwards. The setting value for the first time can be predetermined according to the equipment and system used by the user. Furthermore, if the inrush relay 201 is turned on while the inrush resistor 200 is broken, a large current will flow through the smoothing capacitor 101. Therefore, the control unit 304 detects the inrush resistor 200's broken fault before the control to turn on the inrush relay 201 is completed at time t3. For this reason, in actual control, the inrush relay 201 is not turned on even at time t3, when the control to turn on the inrush relay 201 is completed.

[0040] Figure 16 shows the voltage waveforms of the amplification circuit and peak hold circuit of the fault detection circuit according to the first modification of Embodiment 1 when a short-circuit failure occurs in the inrush relay when a three-phase AC lamp is input. In Figure 16, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 13, in Figure 16, time t0 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes constant, and time t5 is the time when the inverter 400 starts outputting. In Figure 16, the dashed line represents voltage Vr and the solid line represents voltage Vcg. When a short-circuit failure occurs in the inrush relay 201, no charge / discharge current flows through the inrush resistor 200 between time t0 when the AC power supply 10 for the lamp input is turned on and time t3 when the inrush relay 201 turns on. In other words, even after the time t1 when the control unit 304 is activated, the voltages Vcg and Vr continue to remain below the second judgment criterion value Vlevel2 without exceeding it. After the control unit 304 is activated, the control unit 304 detects a short-circuit fault in the inrush relay 201 based on the fact that the voltages Vcg and Vr remain below the second judgment criterion value Vlevel2 for a predetermined second time or longer. Furthermore, the detection of a short-circuit fault in the inrush relay 201 can be achieved without problems by setting the second time in the same manner as in Figure 12 described above. The setting value for the second time can be set in advance according to the equipment and system used by the user.

[0041] Figure 17 shows the normal power waveforms of the amplification circuit and peak hold circuit of the fault detection circuit according to the first modification of Embodiment 1 when DC step input is applied. In Figure 17, the vertical axis represents voltage and the horizontal axis represents time. In Figure 17, time t0 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In Figure 17, the dashed line represents voltage Vr and the solid line represents voltage Vcg. During normal operation, when the DC power supply is turned on at time t0, the transformer that generates the voltage supplied to each circuit, including the fault detection circuit 103, is started, and each control power supply is generated. Then, at time t1, the control unit 304 is started, and the bus voltage becomes constant. Between time t0 and time t1, there is no charge in the smoothing capacitor 101, so a large charging current flows through the inrush resistor 200. From time t1 onward, although there is a load on the control unit 304, unlike AC power supply, the smoothing capacitor 101 is fully charged, so no charging current flows through the inrush resistor 200. At time t2, the inrush relay 201 turns on and clamps the potential of the inrush resistor 200 to 0V. At time t3, the inverter 400 starts outputting, and the charging current from the output of the inverter 400 flows through the inrush relay 201.

[0042] Unlike AC input, power is supplied from the power source to the control load without going through the smoothing capacitor 101 even after time t1, so no charging current with a component six times the AC power supply frequency flows. Therefore, no voltage Vr appears during the period from time t0 to time t2. After time t2, the inrush relay 201 turns on, so even when the inverter 400 starts outputting, no voltage Vr appears.

[0043] Between time t0 and time t1, a large charging current flows through the inrush resistor 200, and the capacitor 503 is charged according to the voltage obtained by subtracting the forward voltage VF of the diode 502 of the peak hold circuit 303 from the divided voltage value of the resistor voltage divider circuit 301 at that time. As a result, at time t1, a voltage Vcg exceeding the first judgment criterion value Vlevel1 appears. After time t1, the charge of the capacitor 503 is discharged through the resistor 504, and the voltage Vcg decreases over time until it becomes less than or equal to the first judgment criterion value Vlevel1.

[0044] Figure 18 shows the voltage waveform during an open fault of the inrush relay when a DC step input is applied to the fault detection circuit according to the first modification of Embodiment 1. In Figure 18, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 17, in Figure 18, time t0 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In Figure 18, the dashed line represents voltage Vr and the solid line represents voltage Vcg. In the case of an open fault of the inrush relay 201, even if the control to turn on the inrush relay 201 is performed, the inrush relay 201 does not turn on at time t2, but since the charging current does not flow to the inrush resistor 200, the voltage Vr does not appear. When the output of the inverter 400 is turned on at time t3, the charging current during operation flows to the inrush resistor 200, so the value of the voltage Vr increases. When the voltage Vr exceeds the first judgment criterion value Vlevel1, the control unit 304 detects an open fault in the inrush relay 201. In the case of DC step input, the voltage Vr is hardly present, so the method of detecting an open fault in the inrush relay 201 before the start of operation, as shown in Figure 11, cannot be used.

[0045] Figure 19 shows the voltage waveform during a break in the inrush resistor when a DC step input occurs in the fault detection circuit according to the first modification of Embodiment 1. In Figure 19, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 17, in Figure 19, time t0 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In Figure 19, the dashed line represents voltage Vr and the solid line represents voltage Vcg. When a break in the inrush resistor 200 occurs, the charging path to the smoothing capacitor 101 from time t0 when the step input DC power supply is turned on is only the high-resistance resistive voltage divider circuit 301, so the voltage across the inrush current prevention circuit 102 is high at least from time t1 to time 3. In other words, when the inrush resistor 200 has a break-connection fault, the voltage Vr will exceed the first judgment criterion value Vlevel1 for at least the period from time t1 until time t3. The control unit 304 detects the break-connection fault of the inrush resistor 200 when the voltage Vr remains at a constant value exceeding the first judgment criterion value Vlevel1 for a predetermined first time period from time t1 onward. The setting value for the first time can be predetermined according to the equipment and system used by the user. Note that if the inrush relay 201 is turned on while the inrush resistor 200 has a break-connection fault, a large current will flow through the smoothing capacitor 101. Therefore, the control unit 304 detects the break-connection fault of the inrush resistor 200 before the control to turn on the inrush relay 201 is completed at time t2. For this reason, in actual control, the inrush relay 201 is not turned on even at time t2, when the control to turn on the inrush relay 201 is completed.

[0046] Figure 20 shows the voltage waveform during a short-circuit failure of the inrush relay when a DC step input is applied to the fault detection circuit according to the first modification of Embodiment 1. In Figure 20, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 17, in Figure 20, time t0 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In Figure 20, the dashed line represents voltage Vr and the solid line represents voltage Vcg. When the inrush relay 201 short-circuits, no charge / discharge current flows through the inrush resistor 200 between time t0, when the DC power supply for the step input is turned on, and time t2, when the inrush relay 201 turns on. That is, even at time t1, when the control unit 304 is started, the voltages Vcg and Vr are less than or equal to the second judgment criterion value Vlevel2. The control unit 304 detects a short-circuit failure in the inrush relay 201 when the voltages Vcg and Vr are between a predetermined second time and a second judgment criterion value Vlevel2 from time t1. The setting value for the second time can be predetermined according to the equipment and system used by the user.

[0047] Figure 21 shows the voltage waveform during normal operation when a DC lamp is input to the fault detection circuit according to the first modification of Embodiment 1. In Figure 21, the vertical axis represents voltage and the horizontal axis represents time. In Figure 21, time t0 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes a constant value, and time t5 is the time when the inverter 400 starts outputting. In Figure 21, the dashed line represents voltage Vr and the solid line represents voltage Vcg. During normal operation, when the DC lamp input is started at time t0, the transformer that generates the voltage supplied to each circuit, including the fault detection circuit 103, is started, and each control power supply is generated. Thereafter, the control unit 304 is started at time t1. Since the DC power input is the lamp input, no large inrush current flows through the inrush resistor 200. After time t1, a charging current flows through the inrush resistor 200 via the smoothing capacitor 101. Then, when the inrush relay 201 is turned on at time t3, the charging current stops flowing through the inrush resistor 200. When the inverter output starts at time t5, the charging current from the inverter 400 output begins to flow through the inrush relay 201.

[0048] Figure 22 shows the voltage waveform during an open fault of the inrush relay when a DC lamp is input to the fault detection circuit according to the first modification of Embodiment 1. In Figure 22, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 21, in Figure 22, time t0 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes a constant value, and time t5 is the time when the inverter 400 starts outputting. In Figure 22, the dashed line represents voltage Vr and the solid line represents voltage Vcg. In the case of an open fault of the inrush relay 201, the inrush relay 201 does not turn on at time t3, so the charging current continues to flow through the inrush resistor 200 until the bus voltage becomes a constant value at time t4. Therefore, a constant voltage Vr continues to appear during the period from time t1 to time t4. After time t4, charging current stops flowing through the inrush resistor 200, so the voltage Vr gradually decreases and disappears. When the inverter output is turned on at time t5, the charging current during operation flows through the inrush resistor 200, causing the voltage Vr to increase. The control unit 304 detects an open fault in the inrush relay 201 when the voltage Vr exceeds the first judgment criterion value Vlevel1. In the case of an open fault in the inrush relay 201, the voltage Vcg hardly appears after time t0, so the method of detecting an open fault in the inrush relay 201 before the start of operation, as shown in Figure 11, cannot be used.

[0049] Figure 23 is a diagram showing the voltage waveform during a break in the inrush resistance when a DC lamp is input to the fault detection circuit according to the first modification of Embodiment 1. In Figure 23, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 21, in Figure 23, time t0 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes constant, and time t5 is the time when the inverter 400 starts outputting. In Figure 23, the dashed line represents voltage Vr and the solid line represents voltage Vcg. When the inrush resistor 200 has a break-connection fault, the charging path to the smoothing capacitor 101 becomes solely through the high-resistance resistive voltage divider circuit 301 from time t0, when the DC lamp input from the DC power supply begins. Therefore, the voltage across the inrush current prevention circuit 102 becomes high at least from time 1 to time t5. In other words, when the inrush resistor 200 has a break-connection fault, the voltages Vr and Vcg exceed the first judgment criterion value Vlevel1 from time t1 to at least time t5. The control unit 304 detects the inrush resistor 200's break-connection fault when the voltages Vr and Vcg continue to exceed the judgment criterion value Vlevel1 for a predetermined first time from time t1 onward. The setting value for the first time can be predetermined according to the equipment and system used by the user. Furthermore, if the inrush relay 201 is turned on while the inrush resistor 200 is broken, a large current will flow through the smoothing capacitor 101. Therefore, the control unit 304 detects the inrush resistor 200's broken fault before the control to turn on the inrush relay 201 is completed at time t3. For this reason, in actual control, the inrush relay 201 is not turned on even at time t3, when the control to turn on the inrush relay 201 is completed. Also, the voltage Vcg continues to rise until the bus voltage reaches a constant value at time t4.

[0050] Figure 24 shows the voltage waveform during a short-circuit failure of the inrush relay when a DC lamp input is received in the fault detection circuit according to the first modification of Embodiment 1. In Figure 24, the vertical axis represents voltage and the horizontal axis represents time. Similar to Figure 21, in Figure 24, time t0 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes constant, and time t5 is the time when the inverter 400 starts outputting. In Figure 24, the dashed line represents voltage Vr and the solid line represents voltage Vcg. When a short-circuit failure occurs in the inrush relay 201, no charge / discharge current flows through the inrush resistor 200 between time t0, when the DC lamp input from the DC power supply is started, and time t3, when the inrush relay 201 is turned on. Specifically, at the time t1 when the control unit 304 is activated, the voltages Vcg and Vr become less than or equal to the second judgment criterion value Vlevel2. The control unit 304 detects a short-circuit fault in the inrush relay 201 if the voltages Vcg and Vr remain less than or equal to the second judgment criterion value Vlevel2 for a predetermined second time or longer from time t1. Furthermore, the detection of a short-circuit fault in the inrush relay 201 can be achieved without problems by setting the second time in the same manner as in Figure 12 described above. The setting value for the second time can be set in advance according to the equipment and system used by the user.

[0051] In single-phase AC, the operation is the same as in three-phase AC except in the case of a wire break with an inrush resistance of 200. Therefore, only the operation in the case of a wire break with an inrush resistance of 200 will be explained here.

[0052] Figure 25 shows the voltage waveform during a break in the inrush resistor when a single-phase AC input occurs in the fault detection circuit according to the first modification of Embodiment 1. In Figure 25, the vertical axis represents voltage and the horizontal axis represents time. In Figure 25, time t0 is the time when the single-phase AC power supply is turned on, time t1 is the time when the control unit 304 is started up, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In Figure 25, the dashed line represents voltage Vr and the solid line represents voltage Vcg. When a break in the inrush resistor 200 of the three-phase AC occurs, the charging path to the smoothing capacitor 101 becomes only the high-resistance resistive voltage divider circuit 301 after the power-on time t0, so the voltage across the inrush current prevention circuit 102 is high at least from time t1 to time t3. Therefore, in the event of a break in the inrush resistor 200, the voltage Vr will exceed the first judgment criterion value Vlevel 1 from time t1 onward. However, in the case of single-phase AC, the voltage Vr also decreases at the same time that the power supply voltage drops to around 0V. Therefore, there is a period of time when the voltage Vr is below the first judgment criterion value Vlevel 1, and there is a risk that the break in the inrush resistor 200 will not be detected. If the break in the inrush resistor 200 is not detected and the inrush relay 201 turns on, the charging path will consist only of the inrush relay 201 and the smoothing capacitor 101, which is hardly charged, resulting in an excessive charging current flowing. For this reason, the control unit 304 detects the break in the inrush resistor 200 if the proportion of time during which the voltage Vr exceeds the first judgment criterion value Vlevel 1 before the inrush relay 201 turns on is equal to or greater than a preset value. Furthermore, if the inrush relay 201 is turned on while the inrush resistor 200 is broken, a large current will flow through the smoothing capacitor 101. Therefore, the control unit 304 detects the inrush resistor 200's broken fault before the control to turn on the inrush relay 201 is completed at time t2. For this reason, in actual control, the inrush relay 201 is not turned on even at time t2, when the control to turn on the inrush relay 201 is completed.

[0053] The operation in the event of a break in the inrush resistance of 200 is the same whether the single-phase AC is input in steps or in a ramp. Therefore, the single-phase AC input method can be either step input or ramp input.

[0054] The setting value for the percentage of time during which the voltage Vr exceeds the first judgment criterion value Vlevel 1 should be set according to the environmental conditions of the equipment and system used by the user. The setting value for the percentage of time during which the voltage Vr exceeds the first judgment criterion value Vlevel 1 can be uniquely determined mainly according to the input frequency of the single-phase AC power supply, provided that the input section of the inverter 400 has a typical circuit configuration. By setting a value for the percentage of time during which the voltage Vr exceeds the first judgment criterion value Vlevel 1 in addition to the first judgment criterion value Vlevel 1, the detection of open-circuit faults in the inrush resistance 200 can be achieved without any problems.

[0055] As described above, the detection of short-circuit faults and open-circuit faults of the inrush relay 201 is the same as in the case of three-phase AC. That is, the control unit 304 detects an open-circuit fault of the inrush relay 201 when the voltage Vr exceeds the second judgment criterion value Vlevel 2 for a predetermined first time or longer after the voltage Vcg has fallen to or below the second judgment criterion value Vlevel 2. The control unit 304 also detects a short-circuit fault of the inrush relay 201 when the voltage Vr and voltage Vcg are less than or equal to the second judgment criterion value Vlevel 2 for a predetermined second time or longer after the control unit 304 has started up.

[0056] As described above, the fault detection circuit 103 according to Embodiment 1 can detect three abnormal modes—a disconnection fault in the inrush resistor 200 of the inrush current prevention circuit 102, an open fault in the inrush relay 201, and a short fault in the inrush relay 201—by utilizing two voltage signals: the voltage Vr output by the amplification circuit 302 and the voltage Vcg output by the peak hold circuit 303. Furthermore, the fault detection circuit 103 according to a modified embodiment of Embodiment 1 can detect the above three abnormal modes with high accuracy by setting two judgment criteria values ​​that serve as thresholds for determining abnormalities.

[0057] Embodiment 2. FIG. 26 is a diagram showing the configuration of a drive circuit including a failure detection circuit according to Embodiment 2. The drive circuit 800 according to Embodiment 2 includes an inrush current prevention circuit 102 having two inrush relays 201 １ , 201 ２ connected in parallel. Further, the failure detection circuit 103 includes a plurality of thermistors 600 １ , 600 ２ installed one by one around the inrush relays 201 １ , 600 ２ , a differential amplifier 601 that amplifies a voltage corresponding to a temperature detection value output by the thermistors 600 １ , 600 ２ , and a diode 602 that combines the output voltage amplified by the differential amplifier 601. Hereinafter, when collectively referring to all the thermistors 600 １ , 600 ２ , they are referred to as thermistors 600. Also, when collectively referring to all the inrush relays 201 １ , 201 ２ , they are referred to as inrush relay 201. The thermistors 600 detect the temperature of the inrush relay 201 １ , 201 ２ . In order to avoid an adverse effect on the temperature detection accuracy of the inrush relay 201 １ , 201 ２ , heat-generating components with a large amount of heat are not arranged around the thermistors 600.

[0058] Next, the signal processing of the temperature detection by the thermistors 600 will be described. First, an output voltage corresponding to the temperature detection value of the thermistors 600 is amplified by the differential amplifier 601. The amplified output voltage is combined via the diode 602. As a result, the differential voltage of the temperature detection voltage of the thermistors 600 can be taken out as an output.

[0059] The value of the differential voltage output by the diode 602 indicates the temperature difference between the thermistors 600 １ , 600 ２ . By inputting this output in parallel to the control unit 304 with the voltage Vr of the amplifier circuit 302 in Embodiment 1, when the voltage Vr becomes a certain value or more, the inrush relays 201 connected in parallel １,201 ２ It is possible to detect that either of these has an open fault.

[0060] During normal operation, the magnitude of the current flowing through each thermistor 600 installed around the inrush relay 201 is approximately the same, so the temperature of the thermistors 600 is approximately the same. Therefore, the change in resistance due to temperature changes in the thermistors 600 is also approximately the same, and the output voltage is also the same. Then, the differential amplifier 601 and diode 602 output the difference as voltage Vr, so when there is no temperature difference between the thermistors 600 under normal conditions, the output of the differential amplifier 601 is approximately 0V.

[0061] When any of the inrush relays 201 experience an open fault, current concentrates in the normally functioning inrush relays 201, causing the temperature around the normal inrush relays 201 to rise. Since no current flows through the faulty inrush relay 201, the temperature around the faulty inrush relay 201 hardly changes. This results in a difference in the change in the resistance value of the thermistor 600, causing a change in the output voltage, which can then be output as voltage Vr by the differential amplifier 601 and diode 602. The control unit 304 detects that any of the parallel-connected inrush relays 201 have experienced an open fault when the voltage Vr exceeds a certain value during inverter operation.

[0062] The threshold value for the voltage Vr indicating an open fault should be determined according to the user's desired tolerance for degradation of the inrush relay 201. The tolerance for degradation of the inrush relay 201 corresponds to the temperature difference between each inrush relay 201 connected in parallel.

[0063] For example, if the allowable temperature difference of the inrush relay 201 in the inverter 400 system is set to a temperature difference of 15°C between parallel components, and considering the constant variations of the thermistor 600, diode 602, and step-down resistor (not shown) implemented in the circuit, then the voltage Vr will be judged based on a value of Vr = 1.0V. In other words, in the above case, if Vr exceeds 1.0V, it indicates that one of the parallel-connected inrush relays 201 is in an open fault state.

[0064] In the configuration shown in Figure 26, only the combination with the largest temperature difference is output, making it impossible to identify which inrush relay 201 has experienced an open fault. Therefore, by providing multiple terminals in the control unit 304 and enabling the differential amplifier 601 to output multiple voltages Vr, it becomes possible to detect the temperature difference of each inrush relay 201. This configuration makes it possible to identify the inrush relay 201 that has experienced an open fault. In other words, by providing multiple terminals for detecting open faults of the inrush relays 201 in the control unit 304, improvements in work efficiency, such as replacing faulty parts during maintenance, can be obtained.

[0065] Figure 27 shows a drive circuit equipped with a fault detection circuit according to the first modified example of Embodiment 2. Only the inrush current prevention circuit 102 and the fault detection circuit 103 are shown, and other parts are omitted from the illustration. In addition, the resistor voltage divider circuit 301, the amplification circuit 302 and the control unit 304 of the fault detection circuit 103 are omitted from the illustration. In the inrush current prevention circuit 102 according to the first modified example of Embodiment 2, the number of parallel connections of the inrush relay 201 is n, and the inrush relay 201 １ Relay 201 ｎ The fault detection circuit 103 differs from the inrush current prevention circuit 102 according to Embodiment 2 in that it is equipped with a thermistor 600. Here, n is a real number of 3 or more. １ From Thermistor 600 ｎ It is equipped with this feature. By increasing the number of parallel connections, it becomes possible to realize a configuration of the inrush relay 201 that can be installed in a high-capacity inverter 400. Therefore, open fault detection of parallel-connected inrush relays 201 is possible across a wide range of capacity classes of inverters 400, achieving both functional safety for the user and cost reduction for the manufacturer of inverters 400, etc. Furthermore, even when the number of parallel-connected inrush relays 201 is increased to three or more, the above-mentioned improvement in maintainability can be obtained by adding an open fault detection terminal to the control unit 304.

[0066] Figure 28 shows an example of temperature simulation results using the fault detection circuit according to Embodiment 2. The temperature simulation results shown in Figure 28 were obtained using Femtet®, manufactured by Murata Software Co., Ltd. Inrush relay 201 １ ,201 ２ A Panasonic relay, model number ALFG2PF18 C01L, was used. Thermistor 600 １ ,600 ２ Each entry relay 201 １ ,201 ２ It was positioned 5 mm away from the sheet metal section for high current, which generates the most heat. The temperature simulation conditions were as follows: inrush relay 201 １ ,201 ２ Assuming the contact resistance is 2 mΩ, one side of the inrush relay 201 １ ,201 ２ A current of 33A was passed through it. As a result, the inrush relay 201 functioned normally. １ Thermistor 600 around １ The temperature was 18.3°C, and the inrush relay 201 had an open failure. ２ Surrounding thermistor 600 ２ The temperature rose by 3.2°C. Two thermistors 600 １ ,600 ２ The temperature difference between them is 15.1°C, and the voltage Vr exceeds 1.0V, so the inrush relay 201 １ ,201 ２ It is possible to detect that one of the circuits is experiencing an open fault.

[0067] Figure 29 shows an example of temperature simulation results using a fault detection circuit according to the first modified example of Embodiment 2. Note that three inrush relays 201 are used here. １ ,201 ２ ,201 ３ Let's take a fault detection circuit 103 that detects a failure in the inrush current prevention circuit 102 equipped with the following as an example. The temperature simulation results shown in Figure 29 are the results of a temperature simulation performed using Femtet®, manufactured by Murata Software Co., Ltd. Inrush relay 201 １ ,201 ２ ,201 ３A Panasonic relay, model number ALFG2PF18 C01L, was used. Thermistor 600 １ ,600 ２ ,600 ３ Each entry relay 201 １ ,201 ２ ,201 ３ It was positioned 5 mm away from the sheet metal section for high current, which generates the most heat. The temperature simulation conditions were as follows: inrush relay 201 １ ,201 ２ ,201 ３ Assuming the contact resistance is 2 mΩ, one side of the inrush relay 201 １ ,201 ２ ,201 ３ A current of 33A was passed through it. As a result, the inrush relay 201 functioned normally. ２ Surrounding thermistor 600 ２ The temperature was 18.2°C, and the inrush relay 201 had an open failure. １ Thermistor 600 around １ The temperature was 3.0℃, and the inrush relay 201 also experienced an open failure. ３ Thermistor 600 around ３ The temperature rose by 3.5°C. Three thermistors 600 １ ,600 ２ ,600 ３ The maximum temperature difference is the inrush relay 201 ２ Thermistor 600 installed around it ２ And the 201st Relay Race １ Thermistor 600 installed around it １ This results in a temperature difference between these two thermistors 600 １ ,600 ２ The temperature difference between them becomes 15.2°C, and the voltage Vr exceeds 1.0V. Therefore, the control unit 304 activates the inrush relay 201 １ ,201 ２ ,201 ３ It is possible to detect that one of them is an open fault.

[0068] The above shows an example of temperature simulation results using the fault detection circuit 103 of Embodiment 2 and an example of temperature simulation results using the fault detection circuit 103 according to the first modified example of Embodiment 2. However, a change in the arrangement relationship between the thermistor 600 and the inrush relay 201 affects the heat transfer of the inrush relay 201. If the arrangement relationship between the thermistor 600 and the inrush relay 201 is changed due to design constraints, the allowable temperature difference of the inrush relay 201 in parallel = 15°C can be maintained by suppressing constant variation by changing components or by changing the reference value of the voltage Vr. １ ,201 ２ ,201 ３ Replacing this with a different component changes the internal wiring structure, which in turn alters the heat transfer to the thermistor 600. (Inrush Relay 201) １ ,201 ２ ,201 ３ To address the changes, adjustments will be made by suppressing constant variation or changing the reference value of voltage Vr, rather than by changing the components as described above.

[0069] As described above, a thermistor 600 is placed around the inrush relay 201, the signal is amplified by the differential amplifier 601, and coupled via the diode 602 to output a differential voltage that becomes the temperature detection voltage for the inrush relay 201. By inputting this output voltage in parallel with the voltage Vr output by the amplification circuit 302, the control unit 304 receives the signal and can detect if any of the inrush relays 201 are malfunctioning.

[0070] Next, the hardware configuration of the control unit 304 will be described. Figure 30 is a diagram showing an example of a hardware configuration for realizing the control unit of the fault detection circuit according to Embodiment 1 and Embodiment 2. The control unit 304 is realized as a computer system by a processing circuit that includes a processor 91 for executing various processes, a memory 92 which is the main memory, and a storage device 93 for storing information.

[0071] The processor 91 may be an arithmetic means such as an arithmetic unit, a microprocessor, a microcomputer, a CPU (Central Processing Unit), or a DSP (Digital Signal Processor). Also, for the memory 92, a non-volatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), or an EEPROM (registered trademark) (Electrically Erasable Programmable Read Only Memory) can be used. The storage device 93 stores a program for executing a process of detecting a failure of the inrush resistor 200 and the inrush relay 201. The processor 91 reads out and executes the program stored in the storage device 93 in the memory 92. By the processor 91 reading out and executing the program stored in the storage device 93 in the memory 92, the function of the control unit 304 is realized.

[0072] The configuration shown in the above embodiments is an example of the content, and it is possible to combine it with another known technique, and it is also possible to omit or change a part of the configuration without departing from the gist.

[0073] 10 AC power supply, 91 processor, 92 memory, 93 storage device, 100 rectifier circuit, 101 smoothing capacitor, 102 inrush current prevention circuit, 103 failure detection circuit, 200 inrush resistor, 201, 201 １ , 201 ２ , 201 ３ , 201 ｎ Inrush relay, 301 resistor voltage division circuit, 302 amplifier circuit, 303 peak hold circuit, 304 control unit, 400 inverter, 401 amplifier, 402, 403, 504, 903, 904, 905, 906 resistors, 404, 502, 602 diodes, 405 positive electrode line, 406 negative electrode line, 501 peak hold section, 503 capacitor, 600, 600 １ , 600 ２ , 600 ３,600 ｎ Thermistor, 601 Differential amplifier, 700 Inverter system, 800 Drive circuit, 900 Overvoltage protection circuit, 901 First bipolar transistor, 902 Second bipolar transistor.

Claims

1. A fault detection circuit for detecting abnormalities in an inrush current prevention circuit including an inrush resistor and an inrush relay arranged in parallel, comprising: a resistive voltage divider circuit for dividing the voltage across the inrush current prevention circuit; an amplification circuit for amplifying the voltage difference divided by the resistive voltage divider circuit; a peak hold circuit for temporarily holding the voltage divided by the resistive voltage divider circuit; and a control unit for detecting an open circuit fault in the inrush resistor, a short circuit fault in the inrush relay, and an open circuit fault in the inrush relay based on signals output from the amplification circuit and the peak hold circuit, wherein the amplification circuit and the peak hold circuit are connected in parallel between the resistive voltage divider circuit and the control unit.

2. The fault detection circuit according to claim 1, wherein at least one judgment criterion value is set in advance for the voltage output by the amplification circuit and the voltage output by the peak hold circuit, and the control unit detects an open circuit fault of the inrush resistor, a short circuit fault of the inrush relay, and an open circuit fault of the inrush relay based on the result of comparing the voltage output by the amplification circuit and the voltage output by the peak hold circuit with the judgment criterion value.

3. The fault detection circuit according to claim 2, characterized in that the voltage applied to the resistor voltage divider circuit is a voltage obtained by rectifying a three-phase AC that is input in steps, one of the judgment criteria values ​​is set in advance, and the control unit detects an open circuit fault in the inrush resistor when the voltage output by the amplification circuit remains at a constant value exceeding the judgment criteria value after the control unit is started up, detects an open circuit fault in the inrush relay when the voltage output by the amplification circuit exceeds the judgment criteria value after the control to turn on the inrush relay is completed, and detects a short circuit fault in the inrush relay when the voltage output by the peak hold circuit does not exceed the judgment criteria value by the time the control to turn on the inrush relay is completed after the control unit is started up.

4. The fault detection circuit according to claim 2, characterized in that the voltage applied to the resistor voltage divider circuit is a voltage obtained by rectifying a three-phase AC that is input in steps, a first judgment criterion value and a second judgment criterion value smaller than the first judgment criterion value are set in advance for the voltage output by the amplifier circuit and the voltage output by the peak hold circuit, the control unit detects an open circuit fault in the inrush resistor if, after the control unit is started up, the voltage output by the amplifier circuit remains at a constant value that exceeds the first judgment criterion value, the control unit detects an open circuit fault in the inrush relay if, after the voltage output by the peak hold circuit drops to or below the second judgment criterion value, the voltage output by the amplifier circuit exceeds the second judgment criterion value for a predetermined period of time or longer, and the control unit detects a short circuit fault in the inrush relay if, after the control unit is started up, the voltage output by the amplifier circuit and the voltage output by the peak hold circuit do not exceed the second judgment criterion value by the time the control to turn on the inrush relay is completed.

5. The fault detection circuit according to claim 2, characterized in that the voltage applied to the resistor voltage divider circuit is a voltage obtained by rectifying the three-phase AC input to the lamp, a first judgment criterion value and a second judgment criterion value smaller than the first judgment criterion value are set in advance for the voltage output by the amplifier circuit and the voltage output by the peak hold circuit, the control unit detects an open circuit fault in the inrush resistor when the voltage output by the amplifier circuit and the voltage output by the peak hold circuit continue to exceed the first judgment criterion value for a predetermined first time after the control unit is started, an open circuit fault in the inrush relay when the voltage output by the amplifier circuit exceeds the first judgment criterion value after the control to turn on the inrush relay is completed, and a short circuit fault in the inrush relay is detected when the voltage output by the amplifier circuit and the voltage output by the peak hold circuit are less than or equal to the second judgment criterion value for a predetermined second time or more after the control unit is started.

6. The fault detection circuit according to claim 2, characterized in that the voltage applied to the resistor voltage divider circuit is a step-input DC voltage, a first judgment criterion value and a second judgment criterion value smaller than the first judgment criterion value are set in advance for the voltage output by the amplifier circuit and the voltage output by the peak hold circuit, the control unit detects an open circuit fault in the inrush resistor when the voltage output by the amplifier circuit remains at a constant value exceeding the first judgment criterion value for a predetermined first time after the control unit is started up, an open circuit fault in the inrush relay when the voltage output by the amplifier circuit exceeds the first judgment criterion value after the control to turn on the inrush relay is completed, and a short circuit fault in the inrush relay is detected when the voltage output by the amplifier circuit and the voltage output by the peak hold circuit are less than or equal to the second judgment criterion value for a predetermined second time or more after the control unit is started up.

7. The fault detection circuit according to claim 2, wherein the voltage applied to the resistor voltage divider circuit is a DC voltage input to the lamp, a first judgment criterion value and a second judgment criterion value smaller than the first judgment criterion value are set in advance for the voltage output by the amplifier circuit and the voltage output by the peak hold circuit, the control unit detects an open circuit fault in the inrush resistor when the voltage output by the amplifier circuit and the voltage output by the peak hold circuit remain at a constant value exceeding the first judgment criterion value for a predetermined first time after the control unit is started, an open circuit fault in the inrush relay when the voltage output by the amplifier circuit exceeds the first judgment criterion value after the control to turn on the inrush relay is completed, and a short circuit fault in the inrush relay is detected when the voltage output by the amplifier circuit and the voltage output by the peak hold circuit are less than or equal to the second judgment criterion value for a predetermined second time or longer after the control unit is started.

8. The fault detection circuit according to claim 2, characterized in that the voltage applied to the resistor voltage divider circuit is a voltage obtained by rectifying single-phase AC, a first judgment criterion value and a second judgment criterion value smaller than the first judgment criterion value are set in advance for the voltage output by the amplifier circuit and the voltage output by the peak hold circuit, the control unit detects an open circuit fault in the inrush resistor if the proportion of the voltage output by the amplifier circuit exceeding the first judgment criterion value is greater than or equal to a preset value between the start of the control unit and the completion of the control to turn on the inrush relay, the inrush relay detects an open circuit fault if the voltage output by the amplifier circuit exceeds the second judgment criterion value for a predetermined first time or longer after the voltage output by the peak hold circuit has fallen to or below the second judgment criterion value, and the inrush relay detects a short circuit fault if the voltage output by the amplifier circuit and the voltage output by the peak hold circuit are less than or equal to the second judgment criterion value for a predetermined second time or longer after the start of the control unit.

9. A fault detection circuit for detecting an abnormality in an inrush current prevention circuit including inrush relays arranged in parallel, comprising: a resistive voltage divider circuit for dividing the voltage across the inrush current prevention circuit; an amplification circuit for amplifying the voltage difference divided by the resistive voltage divider circuit; a thermistor arranged around each of the inrush relays for detecting the temperature of each of the inrush relays; a differential amplifier connected in series with each of the thermistors and outputting the largest difference among a plurality of pairs of differences based on the detection result of the thermistors; and a control unit that detects an open fault in the inrush relay based on signals output from the differential amplifier and the amplification circuit, respectively.

10. The fault detection circuit according to claim 9, wherein a single judgment criterion value is set in advance for the voltage output by the amplification circuit, and the control unit detects an open fault of the inrush relay with the highest temperature detected by the thermistor when the voltage output by the amplification circuit exceeds the judgment criterion value after the control to turn on the inrush relay is completed.

11. An inverter system characterized by comprising a drive circuit having a smoothing capacitor for smoothing pulsating current, an inrush current prevention circuit for preventing a large current from flowing through the smoothing capacitor due to inrush current, and a fault detection circuit according to any one of claims 1 to 10, and an inverter that operates by being supplied with power whose voltage has been smoothed by the smoothing capacitor.

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