Wiring board, electronic device, and electronic module

Abstract

A wiring board (1) comprises: a plate-shaped insulating substrate (10) that has a first surface (S1) having a mounting region (A1) for an integrated circuit (100), and a second surface (S2) on the side opposite of that of the first surface (S1); an electrode pad (21) that is located in the mounting region (A1); and a wiring conductor (30) that is located inside the insulating substrate (10) and is electrically connected to the electrode pad (21). The wiring conductor (30) includes a plurality of first layer via conductors (321) connected to the electrode pad (21). The plurality of first layer via conductors (321) include a first via conductor group (G1) clustered together and a second via conductor group (G2) clustered together and located so as to sandwich a gap region (A11) between the second via conductor group (G2) and the first via conductor group (G1), and the plurality of first layer via conductors (321) further include a plurality of supplemental via conductors (40) located in a region overlapping the gap region (A11) in a planar perspective view.

Description

Wiring Board, Electronic Device, and Electronic Module

[0001] The present disclosure relates to a wiring board, an electronic device, and an electronic module.

[0002] Japanese Patent Application Laid-Open No. 2003-249750 describes a technique for reducing the warpage of a wiring board by alternately reversing the punching directions of a plurality of through-holes through which via conductors pass.

[0003] The wiring board according to the present disclosure includes: a plate-shaped insulating substrate having a first surface with a mounting area for an integrated circuit and a second surface opposite to the first surface; electrode pads located in the mounting area; and wiring conductors located inside the insulating substrate and electrically connected to the electrode pads. The wiring conductors include a plurality of first-layer via conductors connected to the electrode pads. The plurality of first-layer via conductors include a first via conductor group gathered together and a second via conductor group gathered together and located with a gap region interposed therebetween. The wiring board further includes a plurality of supplementary via conductors located in a range overlapping the gap region when viewed in a plane perspective.

[0004] The electronic device according to the present disclosure includes the above wiring board and an integrated circuit mounted on the wiring board.

[0005] The electronic module according to the present disclosure includes the above electronic device and a module substrate on which the electronic device is mounted.

[0006] This is a plan view showing a wiring board of Embodiment 1 of the present invention. This is a side view showing a wiring board of Embodiment 1 of the present invention. This is an enlarged plan view showing the main part of the wiring board of Embodiment 1. This is a side view showing the main part of the wiring board of Embodiment 1. This is a plan view illustrating the warping of the wiring board of Embodiment 1. This is a schematic diagram showing a cross-section of line B-B illustrating the warping of the wiring board of Embodiment 1. This is a plan view illustrating the warping of a wiring board of a comparative example. This is a schematic diagram showing a cross-section of line B-B illustrating the warping of a wiring board of a comparative example. This is a side view showing a wiring board of Embodiment 2. This is an enlarged plan view showing a wiring board of Embodiment 3. This is a side view showing a wiring board of Embodiment 3. This is an enlarged plan view showing a wiring board of Embodiment 4. This is a side view showing a wiring board of Embodiment 4. This is an enlarged plan view showing a wiring board of Embodiment 5. This is a side view showing a wiring board of Embodiment 5. This is an enlarged plan view showing a wiring board of Embodiment 6. This is a side view showing a wiring board of Embodiment 6. This is a side view showing a wiring board of Embodiment 7. This is a side view showing a wiring board of Embodiment 8. This is a side view showing a wiring board of Embodiment 9. This is a diagram showing an electronic device and an electronic module of an embodiment of the present invention.

[0007] Each embodiment of this disclosure will be described in detail below with reference to the drawings. Hereinafter, the direction from the first surface S1 to the second surface S2 will be referred to as "downward," and the direction opposite to that direction will be referred to as "upward." Furthermore, the position below the first surface S1 will be referred to as "depth," and the direction along the first surface S1 will be referred to as the "horizontal direction."Hereinafter, "plane perspective" means perspective viewing from a direction perpendicular to the first surface S1.

[0008] (Embodiment 1) Figures 1A and 1B are a plan view and a side view, respectively, of a wiring board 1 according to Embodiment 1 of the present invention. Figures 2A and 2B are an enlarged plan view and a side view, respectively, of the main parts of the wiring board 1 according to Embodiment 1. In these figures, for components that have multiple parts, only a few are given reference numerals as representative. The same applies to the following drawings.

[0009] As shown in Figures 1A and 1B, the wiring board 1 of Embodiment 1 is a substrate having a mounting area A1 on which an integrated circuit 100, such as a semiconductor element, is connected via a flip-chip connection. The integrated circuit 100 has a plurality of electrodes 111 arranged in an array. The mounting area A1 of the wiring board 1 has a plurality of electrode pads 21 arranged in the same way as the electrodes 111 of the integrated circuit 100. The electrode pads 21 may be configured to be electrically connected to the electrodes 111 of the integrated circuit 100. Then, the plurality of electrodes 111 of the integrated circuit 100 are connected to the plurality of electrode pads 21 of the wiring board 1 via a bonding material such as solder bumps.

[0010] As shown in Figures 2A and 2B, the wiring board 1 includes a plate-shaped insulating substrate 10 having a first surface S1 and a second surface S2, a plurality of electrode pads 21 located on the first surface S1, a wiring conductor 30 located inside the insulating substrate 10, and a plurality of supplementary via conductors 40 located inside the insulating substrate 10. The wiring board 1 may further include a plurality of electrode pads 51 located on the second surface S2.

[0011] The wiring board 1 may be mounted on another wiring board, such as a module board, with the mounting area A1 of the integrated circuit 100 located on the first surface S1, while the second surface S2 is connected to the other wiring board. The multiple electrode pads 21 on the first surface S1 may be arranged at a narrow pitch to match the electrodes 111 of the integrated circuit 100, while the multiple electrode pads 51 on the second surface S2 may be arranged at a wide pitch, and the electrode pads 21 on the first surface S1 and the electrode pads 51 on the second surface S2 may be electrically connected by a wiring conductor 30. In this configuration, the wiring board 1 may be interposed between the module board and the integrated circuit 100, playing a role in electrically connecting the two. The wiring board 1 may also play a role in receiving heat from the integrated circuit 100 and dissipating that heat to the surrounding heat sink.

[0012] The insulating substrate 10 may have a plurality of laminated insulating layers 11, as shown in Figure 2B. The insulating substrate 10 may be an aluminum nitride sintered body, an aluminum oxide sintered body, a silicon carbide sintered body, a mullite sintered body, or a ceramic sintered body such as glass ceramics. Alternatively, the insulating substrate 10 may be an organic resin, or an organic resin containing an inorganic filler.

[0013] The wiring conductor 30 may include a plurality of film-like conductors 31 extending along one surface of the insulating layer 11 and a plurality of via conductors 32 penetrating the insulating layer 11. The via conductors 32 may be conductors extending in a direction perpendicular to the first surface S1. The plurality of film-like conductors 31 and the plurality of via conductors 32 may include conductors connected to the signal electrodes of the integrated circuit 100 and transmitting signals, and ground conductors connected to the ground potential.

[0014] The via conductor 32 may include a first-layer via conductor 321 connected to the electrode pad 21 and a deployment via conductor 322 that is physically connected to the film-like conductor 31 and physically separated from the electrode pad 21. The first-layer via conductor 321 may be physically connected to the electrode pad 21. Note that the first-layer via conductor 321 does not refer only to the via conductor 32 located in the uppermost insulating layer 11 of the multiple insulating layers 11. Any via conductor 32 that is connected to the electrode pad 21 and is located so as to linearly penetrate the multiple insulating layers 11 may also be considered a first-layer via conductor 321, including via conductors located in the upper-middle insulating layers 11.

[0015] In Figures 2A and 2B, an example is shown in which one first-layer via conductor 321 is connected to one electrode pad 21. However, multiple electrode pads 21 may include large electrode pads, and multiple first-layer via conductors 321 may be connected to one large electrode pad.

[0016] The multiple first-layer via conductors 321 may include a first via conductor group G1 that is clustered together when viewed from above, and a second via conductor group G2 that is positioned between the first via conductor group G1 and the second via conductor group G2 with a gap region A11 (see Figures 2A and 2B) in between. Embodiment 1 shows an example where the first via conductor group G1 and the second via conductor group G2 are separated by the gap region A11, but the first via conductor group G1 and the second via conductor group G2 may be connected at a position outside the gap region A11.

[0017] The gap region A11 is defined as a region that, in planar perspective, is large enough to encompass a square with sides that are at least 1.5 times the average pitch of the first layer via conductors 321 in the first via conductor group G1 and at least 1.5 times the average pitch of the first layer via conductors 321 in the second via conductor group G2, and in which no first layer via conductors 321 are located. The pitch of the first layer via conductors 321 in the first via conductor group G1, or the pitch of the first layer via conductors 321 in the second via conductor group G2, may vary depending on the location. In such cases, the above average pitch should be interpreted as the average pitch of the first layer via conductors 321 in the region adjacent to the gap region A11 in the first via conductor group G1 or the second via conductor group G2, and which has an area equivalent to the gap region A11 in planar perspective.

[0018] The gap region A11 may be an area that overlaps with the mounting region A1 on which one integrated circuit 100 is mounted in a planar perspective view. Alternatively, the gap region A11 may be an area that is sandwiched between mounting regions on which multiple integrated circuits are mounted in a planar perspective view, and at least a portion of it does not overlap with the integrated circuits.

[0019] <Supplementary via conductor> The supplementary via conductor 40 is a via conductor that is positioned to overlap the gap region A11 in a planar perspective view. That is, the supplementary via conductor 40 is a via conductor located in the gap region A11 (see Figures 2A and 2B), a via conductor located below the gap region A11, or a via conductor located across the gap region A11 and below the gap region A11.

[0020] Figures 3A and 3B are a plan view illustrating the warp of the wiring board 1 of Embodiment 1 and a schematic diagram showing a cross-section along line B-B. Figures 4A and 4B are a plan view illustrating the warp of the wiring board 80 of the comparative example and a schematic diagram showing a cross-section along line B-B. Figures 3B and 4B depict the warp in an exaggerated manner. The wiring board 80 of the comparative example has the same configuration as the wiring board 1 of Embodiment 1, but without the supplementary via conductor 40.

[0021] As in the comparative example wiring board 80, without supplemental via conductors 40, the density of via conductors in the gap region A11 and below the gap region A11 is significantly lower compared to the density of via conductors 32 in the first via conductor group G1 and the second via conductor group G2. Based on this difference in density, as shown in Figure 4B, the portion of the first via conductor group G1 with a high density of via conductors 32 warps in a mountain shape, and the portion of the gap region A11 with a low density of via conductors warps in a valley shape. Furthermore, the portion of the second via conductor group G2 with a high density of via conductors 32 warps in a mountain shape. As a result of this sequential warping of mountain shape, valley shape, and mountain shape, a large amount of warping B80 is located in the mounting area A1 of the integrated circuit 100.

[0022] On the other hand, according to the wiring board 1 of Embodiment 1 having supplemental via conductors 40, the difference between the density of via conductors 32 in the first via conductor group G1 and the density of via conductors in the gap region A11 and below the gap region A11 can be reduced. Similarly, the difference between the density of via conductors 32 in the second via conductor group G2 and the density of via conductors in the gap region A11 and below the gap region A11 can be reduced. Therefore, the effect of valley-shaped warping occurring in the gap region A11, as in the comparative example, is reduced, and as shown in Figure 3B, the warping of the wiring board 1 in the mounting region A1 of the integrated circuit 100 can be reduced to a small amount B1.

[0023] <Details of Supplementary Via Conductors> As shown in Figure 2B, at least a portion of each of the multiple supplementary via conductors 40 may be located above half the depth D1 of the insulating substrate 10. In the wiring board 1, the density of via conductors 32 is higher at a depth close to the first surface S1 of the mounting area A1 of the integrated circuit 100. Therefore, by positioning the supplementary via conductors 40 as described above, the density difference of the via conductors 32 can be reduced at a depth close to the first surface S1. Consequently, the occurrence of large warping due to conductor density differences can be further reduced.

[0024] The multiple supplemental via conductors 40 may be spaced apart from the first surface S1 and the second surface S2, as shown in Figure 2B. By being spaced apart from the first surface S1, it is possible to reduce the appearance of structures such as bulges caused by the supplemental via conductors 40 on the first surface S1. Therefore, interference between the integrated circuit 100 and the above structure can be reduced. Similarly, by being spaced apart from the second surface S2, it is possible to reduce the appearance of structures such as bulges caused by the supplemental via conductors 40 on the second surface S2. Therefore, interference between the above structure and a configuration connected on the second surface S2 side (for example, the module substrate 210 in Figure 13) can be reduced.

[0025] As shown in Figure 2B, the multiple supplementary via conductors 40 may have a length of 50% or more of the thickness T10 of the insulating substrate 10. With this configuration, the difference in conductor density between the first via conductor group G1 and the area below the first via conductor group G1, the gap region A11 and the area below the gap region A11, and the second via conductor group G2 and the area below the second via conductor group G2 can be reduced in most of the depth direction of the wiring board 1. Therefore, the warping of the wiring board 1 in the mounting region A1 can be made smaller.

[0026] As shown in Figure 2A, the multiple supplemental via conductors 40 may have the same diameter φ40 and pitch Pch40 as the first layer via conductor 321, with respect to the diameter φ321 and pitch Pch321. The diameters φ40 and φ321 may be, for example, 40 μm or more and 100 μm or less. The pitch may be, for example, 130 μm or more and 500 μm or less. Pitch refers to the distance between the centers of an adjacent pair of via conductors 32 (or an adjacent pair of supplemental via conductors 40). "Same" is not limited to strictly identical, but includes cases where the error is within ±10%. With this configuration, the conductor density can be brought closer in the regions where the first via conductor group G1, the second via conductor group G2, and the supplemental via conductors 40 are located. Therefore, the difference in conductor density can be reduced, and the warping of the wiring board 1 in the mounting region A1 can be reduced.

[0027] The multiple supplemental via conductors 40 may be configured not to be electrically connected to the wiring conductor 30, as shown in Figure 2B. Supplemental via conductors 40 in this configuration may be called dummy via conductors. This configuration reduces the electrical interference that the supplemental via conductors 40 may cause to the integrated circuit 100. Although not shown in the figure, the multiple supplemental via conductors 40 may include one that is connected to a ground conductor. The ground conductor may be a ground conductor included in the wiring conductor 30. By connecting to a ground conductor, the electrical interference that the supplemental via conductors 40 may cause to the integrated circuit 100 can be reduced.

[0028] (Embodiment 2-9) Next, the wiring boards 1A to 1H of Embodiments 2 to 9 will be described. The wiring boards 1A to 1H of Embodiments 2 to 9 differ mainly in the configuration of a part of the supplementary via conductor 40, while the other configurations are the same as in Embodiment 1. The wiring boards 1A, 1F, 1G, and 1H of Embodiments 2, 7, 8, and 9 have a unique configuration when the supplementary via conductor 40 is viewed from the side, and the wiring boards 1B, 1C, 1D, and 1E of Embodiments 3, 4, 5, and 6 have a unique configuration when the supplementary via conductor 40 is viewed from above. The unique configurations shown in wiring boards 1A, 1F, 1G, and 1H may also be applied to wiring boards 1, 1B, 1C, 1D, and 1E. The unique configurations shown in wiring boards 1B, 1C, 1D, and 1E may also be applied to wiring boards 1, 1A, 1F, 1G, and 1H.

[0029] Figure 5 is a side view showing a wiring board 1A according to Embodiment 2. The supplementary via conductor 40 may extend to the first surface S1, as shown in Figure 5. In this case, the supplementary via conductor 40 may be covered with an insulator 45 such as solder resist so as not to be exposed to the outside. There may be no electrode pads connected to the supplementary via conductor 40 on the first surface S1. With this configuration, the supplementary via conductor 40 can be positioned close to the first surface S1 where the density of the first layer via conductors 321 is high, while keeping the interference of the supplementary via conductor 40 with the integrated circuit 100 to a minimum. Therefore, the difference in conductor density can be reduced even at depths close to the first surface S1, and the warping of the wiring board 1A in the mounting area A1 can be made smaller.

[0030] The supplementary via conductor 40 may extend to the second surface S2, as shown in Figure 5. In this case, the supplementary via conductor 40 may be covered with an insulator 46 such as solder resist so as not to be exposed to the outside. There may be no electrode pads connected to the supplementary via conductor 40 on the second surface S2. With this configuration, the supplementary via conductor 40 can be positioned close to the second surface S2 while minimizing interference with the configuration connected to the second surface S2 side of the wiring board 1A (for example, a module board). Therefore, when the density of the first via conductor group G1 and the second via conductor group G2 is high even at the depth close to the second surface S2, the difference in conductor density at that depth can be reduced. Therefore, the warping of the wiring board 1A in the mounting area A1 can be made smaller.

[0031] Although not shown in the diagram, the supplementary via conductor 40 may be configured to extend to the first surface S1 while remaining separate from the second surface S2. Conversely, it may be configured to extend to the second surface S2 while remaining separate from the first surface S1.

[0032] Figures 6A and 6B are an enlarged plan view and a side view, respectively, of a wiring board 1B according to Embodiment 3. As shown in the figures, the supplemental via conductor 40 may have a larger diameter φ40b (e.g., 75 μm to 100 μm) and a larger pitch Pch40b (e.g., 200 μm to 500 μm) compared to the diameter φ321 (e.g., 40 μm to 60 μm) and pitch Pch321 (e.g., 130 μm to 350 μm) of the first layer via conductor 321. The pitch Pch321 may be, for example, 130 μm to 200 μm. By increasing the pitch Pch40b, the complexity of the process of forming the supplemental via conductor 40 can be reduced, and productivity can be improved. Furthermore, by increasing the diameter φ40b, the conductor density can be brought closer in the regions where the first via conductor group G1, the second via conductor group G2, and the supplemental via conductor 40 are located. Therefore, differences in conductor density can be reduced, and the warping of the wiring board 1B in the mounting area A1 can be reduced.

[0033] Figures 7A and 7B are an enlarged plan view and a side view, respectively, of a wiring board 1C according to Embodiment 4. As shown in the figures, the supplemental via conductor 40 may have a smaller diameter φ40c (e.g., 40 μm to 60 μm) and a smaller pitch Pch40c (e.g., 130 μm to 350 μm) compared to the diameter φ321c (e.g., 75 μm to 100 μm) and pitch Pch321c (e.g., 200 μm to 500 μm) of the first layer via conductor 321. By reducing the pitch Pch40c, the change in conductor distribution in the gap region A11 and below the gap region A11 can be smoothed out, enabling fine control of the stress applied to that area. Furthermore, by reducing the diameter φ40c, the conductor density can be brought closer in the regions where the first via conductor group G1, the second via conductor group G2, and the supplemental via conductor 40 are located. Therefore, differences in conductor density can be reduced, and the warping of the wiring board 1C in the mounting area A1 can be reduced.

[0034] Figures 8A and 8B are an enlarged plan view and a side view, respectively, of a wiring board 1D according to Embodiment 5. In the wiring board 1D of Embodiment 5, the first layer via conductor 321 of the first via conductor group G1 has a first diameter φ321d1 (e.g., 40 μm to 60 μm) and a first pitch Pch321d1 (e.g., 130 μm to 350 μm). "Having a pitch of ~" means that multiple via conductors included in the group are arranged at a pitch of ~. Furthermore, the first layer via conductor 321 of the second via conductor group G2 has a second diameter φ321d2 (e.g., 75 μm to 100 μm) and a second pitch Pch321d2 (e.g., 200 μm to 500 μm). The first diameter φ321d1 is smaller than the second diameter φ321d2. The first pitch Pch321d1 is smaller than the second pitch Pch321d2.

[0035] In the gap region A11 sandwiched between the first via conductor group G1 and the second via conductor group G2 as described above, the supplementary via conductor 40 has a third diameter φ40d (e.g., 50 μm to 90 μm) and a third pitch Pch40d (e.g., 200 μm to 400 μm). The third diameter φ40d may be 60 μm to 75 μm. The third diameter φ40d is greater than or equal to the first diameter φ321d1 and less than or equal to the second diameter φ321d2. The third pitch Pch40d is greater than the first pitch Pch321d1 and less than the second pitch Pch321d2.

[0036] With this configuration, the conductor density can be brought closer in the regions where the first via conductor group G1, the second via conductor group G2, and the supplementary via conductor 40 are located. Furthermore, the conductor distribution can be smoothly changed in these regions. As a result, the warping of the wiring board 1D in the mounting region A1 can be reduced, and the change in stress distribution can be made smoother.

[0037] In Embodiment 5, either the first via conductor group G1 or the second via conductor group G2 may be a collection of thermal vias intended for heat dissipation from the integrated circuit 100. In the case of a collection of thermal vias, the electrode pad 21 may have a large area, and a plurality of first-layer via conductors 321, which are thermal vias, may be connected to a single electrode pad 21. Furthermore, the plurality of first-layer via conductors 321, which are thermal vias, may be via conductors that extend from the first surface S1 to the second surface S2.

[0038] Figures 9A and 9B are an enlarged plan view and a side view, respectively, of a wiring board 1E according to Embodiment 6. The pitch of the supplemental via conductor 40 may be a pitch Pch40e (for example, 260 μm to 700 μm) which is n times (n is an integer from 2 to 4) the pitch Pch321 (for example, 130 μm to 350 μm) of the first layer via conductor 321. This configuration corresponds to a configuration in which some supplemental via conductors 40 are thinned out from a configuration in which multiple supplemental via conductors 40 are formed at the same pitch as the first layer via conductor 321 during the design phase. With this configuration, the conductor density in the region where the supplemental via conductor 40 is located can be easily adjusted at the design stage. Furthermore, by reducing the number of supplemental via conductors 40, the complexity of the process of forming the supplemental via conductors 40 is reduced, and productivity can be improved.

[0039] In addition, in the wiring boards 1B to 1E of Embodiments 3 to 6, in one or both of the first via conductor group G1 and the second via conductor group G2, a configuration in which the diameter and pitch of the first layer via conductor 321 differ depending on the location may be adopted. In this case, the diameter and pitch of the first layer via conductor 321 described above may be reinterpreted as the diameter and pitch of the first layer via conductor 321 in the region adjacent to the gap region A11 in the corresponding one or both of the first via conductor group G1 and the second via conductor group G2, and having the same area as the gap region A11 in a planar perspective view.

[0040] Figure 10 is a side view showing a wiring board 1F according to Embodiment 7. At least one of the multiple supplementary via conductors 40 includes a plurality of series via conductors 41 arranged in a single row in the vertical direction, and the plurality of series via conductors 41 may be arranged with gaps 11a connected to one or more insulating layers 11 in between. As in the example of Figure 10, each of the plurality of series via conductors 41 has the length of one layer of the insulating layer 11, while the gaps 11a similarly have the length of one layer of the insulating layer 11, and the series via conductors 41 and gaps 11a may be arranged alternately with each layer of the insulating layer 11. Note that a configuration in which any of the series via conductors 41 have the length of two or more layers may be adopted. A configuration in which any of the gaps 11a have the length of two or more layers may be adopted.

[0041] This configuration allows for adjustment to slightly lower the conductor density by inserting a gap 11a in the middle of the supplementary via conductor 40 in the gap region A11 and below the gap region A11. Therefore, it is possible to achieve a conductor distribution in the gap region A11 and below the gap region A11 that matches the conductor distribution in the first via conductor group G1 and below the first via conductor group G1, and the conductor distribution in the second via conductor group G2 and below the second via conductor group G2. Thus, the warping of the wiring board 1F in the mounting region A1 can be further reduced.

[0042] Figure 11 is a side view showing a wiring board 1G according to Embodiment 8. The multiple supplementary via conductors 40 may be configured to be located on the first surface S1 side from half the depth D1 of the insulating substrate 10, as shown in the figure, and not on the second surface S2 side from half the depth D1 of the insulating substrate 10. Below half the depth D1 of the insulating substrate 10, the density of via conductors 32 may decrease as the wiring conductors 30 spread out horizontally. Furthermore, a lower conductor density below the gap region A11, below half the depth D1, may reduce the warping of the wiring board 1G. With the above configuration, the warping of the wiring board 1G in the mounting region A1 can be further reduced in response to this case.

[0043] FIG. 12 is a side view showing the wiring board 1H according to Embodiment 9. At least one of the plurality of supplementary via conductors 40 includes a plurality of series via conductors 41a and 41b arranged in a row in the vertical direction with a gap 11a interposed therebetween, and the length L1 of the series via conductor 41a closer to the first surface S1 may be larger than the individual length L2 of the series via conductor 41b closer to the second surface S2. In the gap region A11 and below the gap region A11, reducing the warpage of the wiring board 1H may be possible by increasing the conductor density on the first surface S1 side and slightly decreasing the conductor density on the second surface S2 side. With the above configuration, in response to this case, the warpage of the wiring board 1H in the mounting region A1 can be further reduced.

[0044] Note that two or more of the supplementary via conductors 40 shown in Embodiments 1, 2, 7 to 9 may be mixed in one wiring board 1. With this configuration, when there are differences in the density and distribution of the via conductors 32 that induce warpage of the wiring board 1 at a plurality of locations different in the horizontal direction, the density and distribution of the supplementary via conductors 40 can be adjusted so that the warpage is reduced for each location in accordance with the differences.

[0045] (Electronic Device) FIG. 13 is a side view showing the electronic device 150 and the electronic module 200 according to the embodiment of the present disclosure. The electronic device 150 of the present embodiment includes the wiring board 1 shown in Embodiment 1 and the integrated circuit 100 mounted in the mounting region A1. The integrated circuit 100 has a plurality of electrodes on its lower surface and is flip-chip connected to the plurality of electrode pads 21 of the wiring board 1.

[0046] The electronic module 200 of the present embodiment includes a module substrate 210 and the electronic device 150 mounted on the module substrate 210. In addition to the electronic device 150, various types of electronic components, electrical components, etc. may be mounted on the module substrate 210.

[0047] The electronic device 150 has a plurality of electrode pads 51 on the second surface S2 of the wiring board 1, while the module substrate 210 has a plurality of connection terminals 212. The plurality of electrode pads 51 of the electronic device 150 are flip-chip connected to the plurality of connection terminals 212 of the module substrate 210 via a bonding material 230.

[0048] In the electronic device 150 and the electronic module 200, the wiring board 1 may be substituted for the wiring boards 1A to 1H of the other embodiments described above.

[0049] According to the electronic device 150 and the electronic module 200 of the present embodiment, since the warp of the wiring board 1 is reduced in the mounting area A1, the workability when mounting the integrated circuit 100 can be improved, and the reliability of the mounting can also be improved.

[0050] The embodiments of the present disclosure have been described above. However, the wiring board and the electronic device of the present disclosure are not limited to the above embodiments. The details shown in the embodiments can be appropriately changed without departing from the gist of the invention.

[0051] Hereinafter, an embodiment of the present disclosure will be shown. In one embodiment, (1) the wiring board includes: a plate-shaped insulating substrate having a first surface with a mounting area for an integrated circuit and a second surface opposite to the first surface; electrode pads located in the mounting area; and wiring conductors located inside the insulating substrate and electrically connected to the electrode pads. The wiring conductors include a plurality of first-layer via conductors connected to the electrode pads. The plurality of first-layer via conductors include a first via conductor group gathered together and a second via conductor group gathered together and located with a gap region sandwiched therebetween. The wiring board further includes a plurality of supplementary via conductors located in a range overlapping the gap region when viewed in a plane perspective.

[0052] (2) In the wiring board of (1) above, at least a part of each of the plurality of supplementary via conductors is located closer to the first surface side than half the depth of the insulating substrate.

[0053] (3) In the wiring board of (1) or (2) above, the plurality of supplementary via conductors are separated from the first surface and the second surface.

[0054] (4) In any one of the wiring boards of (1) to (3) above, the plurality of supplementary via conductors have no electrical connection with the wiring conductors except for the ground conductor.

[0055] (5) In any one of the wiring boards described in (1) to (4) above, the plurality of supplementary via conductors have the same diameter and pitch as the plurality of first layer via conductors.

[0056] (6) In any one of the wiring boards described in (1) to (4) above, the plurality of supplementary via conductors have a larger diameter and pitch compared to the plurality of first layer via conductors.

[0057] (7) In any one of the wiring boards described in (1) to (4) above, the plurality of supplementary via conductors have a smaller diameter and pitch compared to the plurality of first layer via conductors.

[0058] (8) Any one of the wiring boards described in (1) to (4) above, wherein the diameter and pitch of the first layer via conductor included in the first via conductor group are a first diameter and a first pitch, the diameter and pitch of the first layer via conductor included in the second via conductor group are a second diameter which is larger than the first diameter and a second pitch which is wider than the first pitch, and the diameter and pitch of the plurality of supplementary via conductors are a third diameter which is greater than or equal to the first diameter and less than or equal to the second diameter and a third pitch which is between the first pitch and the second pitch.

[0059] (9) In any one of the wiring boards described in (1) to (4) above, the pitch of the plurality of supplementary via conductors is n times the pitch of the plurality of first layer via conductors (where n is an integer from 2 to 4).

[0060] (10) In any one of the wiring boards described in (1) to (9) above, the plurality of supplementary via conductors have a length of 50% or more of the thickness of the insulating substrate.

[0061] (11) Any one of the wiring boards described in (1) to (9) above, wherein the insulating substrate has a structure in which a plurality of insulating layers are stacked, at least one of the plurality of supplementary via conductors includes a plurality of series via conductors arranged in a row in the vertical direction, and the plurality of series via conductors are arranged with a gap connected to one or more of the insulating layers in between.

[0062] (12) In any one of the wiring boards described in (1) to (9) above, the plurality of supplementary via conductors are located on the first surface side from half the depth of the insulating substrate and not on the second surface side from half the depth of the insulating substrate.

[0063] In one embodiment, (13) the electronic device comprises one of the wiring boards described in (1) to (12) above, and an integrated circuit mounted on the wiring board.

[0064] In one embodiment, (14) the electronic module comprises the electronic device described in (13) above, and a module substrate on which the electronic device is mounted.

[0065] This disclosure can be used in wiring boards, electronic devices, and electronic modules.

[0066] 1, 1A-1H Wiring board 10 Insulating substrate 11 Insulating layer 11a Gap 21, 51 Electrode pad 30 Wiring conductor 31 Film conductor 32 Via conductor 321 First layer via conductor 322 Deployment via conductor 40 Supplementary via conductor 41, 41a, 41b Series via conductor 45, 46 Insulator 100 Integrated circuit 111 Electrode 150 Electronic device 200 Electronic module A1 Mounting area A11 Gap area G1 First via conductor group G2 Second via conductor group S1 First surface S2 Second surface φ40, φ40b, φ40c, φ40d, φ321, φ321c, φ321d1, φ321d2 Diameter Pch40, Pch40c, Pch40d, Pch321, Pch321c, Pch321d1, Pch321d2 pitch

Claims

1. A wiring board comprising: a plate-shaped insulating substrate having a first surface having a mounting area for an integrated circuit and a second surface opposite to the first surface; electrode pads located in the mounting area; and wiring conductors located inside the insulating substrate and electrically connected to the electrode pads, wherein the wiring conductors include a plurality of first layer via conductors connected to the electrode pads, and the plurality of first layer via conductors include a group of first via conductors clustered together and a group of second via conductors clustered together with a gap region between them, and further comprising a plurality of supplementary via conductors located in a range that overlaps the gap region when viewed from a plane.

2. The wiring board according to claim 1, wherein at least a portion of each of the plurality of supplemental via conductors is located on the first surface side of half the depth of the insulating substrate.

3. The wiring board according to claim 1 or claim 2, wherein the plurality of supplemental via conductors are separated from the first and second surfaces.

4. The wiring board according to any one of claims 1 to 3, wherein the plurality of supplemental via conductors, except for the ground conductor, do not have an electrical connection with the wiring conductor.

5. The wiring board according to any one of claims 1 to 4, wherein the plurality of supplementary via conductors have the same diameter and pitch as the plurality of first layer via conductors.

6. The wiring board according to any one of claims 1 to 4, wherein the plurality of supplemental via conductors have a larger diameter and pitch than the plurality of first layer via conductors.

7. The wiring board according to any one of claims 1 to 4, wherein the plurality of supplemental via conductors have a smaller diameter and pitch compared to the plurality of first layer via conductors.

8. The wiring board according to any one of claims 1 to 4, wherein the diameter and pitch of the first layer via conductor included in the first via conductor group are a first diameter and a first pitch, the diameter and pitch of the first layer via conductor included in the second via conductor group are a second diameter larger than the first diameter and a second pitch wider than the first pitch, and the diameter and pitch of the plurality of supplementary via conductors are a third diameter greater than or equal to the first diameter and less than or equal to the second diameter, and a third pitch between the first pitch and the second pitch.

9. The wiring board according to any one of claims 1 to 4, wherein the pitch of the plurality of supplementary via conductors is n times the pitch of the plurality of first layer via conductors (where n is an integer from 2 to 4).

10. The wiring board according to any one of claims 1 to 9, wherein the plurality of supplemental via conductors have a length of 50% or more of the thickness of the insulating substrate.

11. The wiring board according to any one of claims 1 to 9, wherein the insulating substrate has a structure in which a plurality of insulating layers are stacked, at least one of the plurality of supplementary via conductors includes a plurality of series via conductors arranged in a row in the vertical direction, and the plurality of series via conductors are arranged with a gap connected to one or more of the insulating layers in between.

12. The wiring board according to any one of claims 1 to 9, wherein the plurality of supplemental via conductors are located on the first surface side from half the depth of the insulating substrate and are not located on the second surface side from half the depth of the insulating substrate.

13. An electronic device comprising: a wiring board according to any one of claims 1 to 12; and an integrated circuit mounted on the wiring board.

14. An electronic module comprising: an electronic device according to claim 13; and a module substrate on which the electronic device is mounted.

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