Semiconductor component, in particular vcsel for emitting laser light, and method
By employing multiple metallization areas with a bridge-like third area, the semiconductor device achieves precise conductor track formation, addressing manufacturing accuracy issues and improving yield and reliability in high-topography VCSELs.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- WESTERN DIGITAL TECHNOLOGIES INC
- Filing Date
- 2025-12-01
- Publication Date
- 2026-06-11
Smart Images
Figure EP2025084818_11062026_PF_FP_ABST
Abstract
Description
[0001] Semiconductor device, in particular VCSEL for emitting laser light and methods
[0002] The present invention relates to a semiconductor device, in particular a VCSEL (Vertical Cavity Surface Emitting Laser) for emitting laser light, and a method for manufacturing a semiconductor device.
[0003] In the semiconductor industry, particularly in the field of light-emitting diodes and lasers, VCSELs represent a key technology used in applications such as optical communication, sensing, and lighting. A surface emitter, or VCSEL, features a laser diode that emits light perpendicular to the plane of the semiconductor chip, unlike an edge-emitting laser diode where the light exits at one or two edges of the chip. The laser resonator is formed by two Bragg mirrors arranged parallel to the plane of the wafer, within which an active zone for generating the laser radiation is embedded. Typically, the construction of VCSELs with the Bragg mirrors and the active zone uses a mesa design with a mesa section raised above the chip surface or the surface of the wafer.Therefore, a relatively high topography in the vertical direction with a height difference of several micrometers is used.
[0004] VCSELs with a raised mesa section are known from the prior art. For example, DE 10 2022 114 856 A1 and WO 2023 / 241993 A1 describe a VCSEL for emitting laser light with a base body having a mesa section comprising a stack of different layers stacked in a stacking direction, wherein an emission region is formed on the upper surface of the mesa section from which the laser light formed in an active layer in the stack emerges, wherein electrical contacts for supplying electrical energy to the active layer are provided on the base body, wherein at least one side section of an electrical contact is arranged on a side surface of the base body, the side surfaces being oriented transversely to the layers.
[0005] However, one challenge in the manufacturing of semiconductor devices with mesa sections and high topology is the limited manufacturing accuracy of electrical conductor tracks in the horizontal direction, which must overcome high topographies in the vertical direction - for example, from the top of a mesa section to the bottom of a side contact on the base body.
[0006] Against this background, it is an objective of the present disclosure to provide a further improved semiconductor device with a raised mesa section for emitting laser light and a corresponding manufacturing process.
[0007] In particular, it would be desirable to further improve semiconductor devices with high topographies, such as those with a mesa section >5 pm high. Furthermore, it would be desirable to improve manufacturing accuracy, increase the yield in manufacturing, and / or improve the reliability and long-term stability of semiconductor devices with high topographies.
[0008] According to a first aspect of the present disclosure, a semiconductor device, in particular a VCSEL for emitting laser light, is proposed comprising: a base body; a mesa section arranged on the base body; a first metallization area extending from a top surface of the base body along a side surface of the mesa section to a top surface of the mesa section; a second metallization area extending from a side surface of the base body to a top surface of the base body; and a third metallization area (hereinafter also referred to as the bridge) arranged adjacent to the mesa section on the top surface of the base body; wherein the first metallization area overlaps and electrically contacts the third metallization area; and wherein the second metallization area overlaps and electrically contacts the third metallization area.
[0009] According to a further aspect of the present disclosure, a method for manufacturing a semiconductor device, in particular a VCSEL for emitting laser light, is proposed comprising the steps of: providing a base body with a mesa section arranged on the base body; depositing a third metallization area arranged adjacent to the mesa section on the top surface of the base body; depositing a second metallization area extending from a side face of the base body to a top surface of the base body, wherein the second metallization area overlaps and electrically contacts the third metallization area; and depositing a first metallization area extending from a top surface of the base body along a side face of the mesa section to a top surface of the mesa section, wherein the first metallization area overlaps and electrically contacts the third metallization area.
[0010] In the case of a semiconductor device, in particular a VCSEL for emitting laser light, with a mesa section arranged on the substrate, and a metallization which extends from a top surface of the mesa section along a side surface of the substrate and forms, for example, a side contact, it is necessary to overcome a topography that is quite high in the vertical direction for semiconductor manufacturing processes (in particular >5pm).
[0011] Furthermore, semiconductor devices such as VCSELs may have specific requirements for metallization areas to ensure reliable conductive traces. A minimum metal thickness may be necessary to guarantee low conduction resistance. For example, a minimum thickness of 200 nm may be required, although the thickness depends on the required current. To prevent potential contact failures, conductive traces must be continuous. To enable contact with contacts formed on a side face of the substrate, flanks with a slope greater than 70° to the horizontal should also be covered. Additionally, a limited layer thickness or lateral feature width, and thus manufacturing accuracy in the horizontal direction, typically less than 1 to 2 pm, would be desirable to avoid overlap with other component structures. Electroplating can be used in mechanization technology to meet these requirements.
[0012] For components with a high topography (> 5 pm), especially those with multiple high topography levels, electroplating, a lithography process, is only partially capable of guaranteeing the required structural fidelity in the horizontal direction across all levels. This is due to the required thickness of the photoresist and the exposure technology. These limitations mean that the required structural fidelity of ± 2 pm, and especially ± 1 pm, in the horizontal direction across all vertical levels cannot be reliably maintained.
[0013] The problem is that with VCSELs featuring high topography, the conductor tracks cannot be produced with the required tolerance in a single metallization step, at least not easily or with a high yield. Even metallization areas located laterally on a side face of the substrate can currently only be produced with limited manufacturing tolerances.
[0014] While it would be theoretically possible to use sputtering technology as a metallization technology, for example, by sputtering the entire wafer with a 1 pm layer of gold and then structuring it via a lithography process and metal etching step, the disadvantages of such a solution would be extremely long processing times, high metallization costs, and the expensive processing of the metal etching step, as large feature heights would have to be removed.
[0015] Instead, a semiconductor device with a substrate and a mesa section mounted on the substrate is proposed, in which multiple metallization areas are provided. Here, the metallization areas (e.g., the first and second metallization areas) can be provided in several metallization steps, in particular in separate metallization steps for different height levels or planes. Different topographic planes in the vertical direction can thus be processed with separate metallization steps. An advantage of this solution is that VCSELs with high topography can be provided with very tight manufacturing tolerances, especially of no more than ±1 pm.
[0016] The first metallization area extends from the top surface of the base body along a side face of the mesa section to the top surface of the mesa section. This first metallization area can be configured to provide an upper terminal contact for the VCSEL on the top surface of the mesa section. Thus, the first metallization area can be connected to an upper terminal contact of the VCSEL on the top surface of the mesa section. The second metallization area extends from a side face of the base body to the top surface of the base body. Therefore, the first metallization area can be located, at least partially, on a higher topographic plane than the second metallization area and can be manufactured in a separate manufacturing step. This can improve manufacturing accuracy.
[0017] Additionally, a third metallization area is provided on the top surface of the base body. This third metallization area can be located next to the mesa section on the top surface of the base body. The first metallization area overlaps the third metallization area and makes electrical contact with it. The second metallization area also overlaps the third metallization area and makes electrical contact with it.
[0018] It has been found that fractures or defects can occur at direct interfaces or overlaps between metal layers, such as between a first metal layer for the first metallization zone and an overlapping second metal layer for the second metallization zone, due to the edge shape of the individual metal layers. These can impair the yield in production and also lead to failures later on. By introducing a third metallization zone, for example, another flat metal layer on the top surface of the base body, the problematic edges of a direct transition between the first and second metallization zones can be spatially separated.A reliable electrical connection between the first and second metallization regions can be established indirectly via the third metallization region. The third metallization region can be configured as a flat metal layer or a flat plate. Optionally, the first and second metallization regions can overlap, but a reliable electrical connection is still provided by the third metallization region. The thickness of the third metallization region can be less than 70%, in particular less than 50%, in particular less than 35%, and in particular less than 20% of the thickness of the first and / or second metallization regions. The thickness can refer to the layer thickness of the deposited layer that would result from deposition onto a planar plane. The third metallization region can also be referred to as a bridge or distribution plate.Side contacts, especially 90° side contacts, on a component flank or on a side surface of the base body can also be connected to the top surface by first guiding the side contact with the second metallization area onto the bridge or the third metallization area, and then, with the first metallization area, onto a top surface of the mesa section, where it is electrically connected to an upper terminal contact of the VCSEL. The intermediate metallization of the third metallization area preferably ensures a reliable connection and prevents potential contact breaks.
[0019] Within the scope of the present disclosure, the side surface of the base body can extend transversely to the top surface of the base body. The side surface can be arranged at an angle of at least 70°, and in particular at least 80°, to the top surface of the base body. The side surface is also referred to as the flank of the base body.
[0020] The semiconductor device can be a VCSEL for emitting laser light. The VCSEL can have a layer stack with an upper DBR (dead-end layer), an active layer for emitting the laser light, and a lower DBR. The mesa section can comprise at least a portion of the layer stack. The solution described herein can be advantageously used for a VCSEL with a mesa section, as high topographies must be overcome depending on the layer sequence. Furthermore, high manufacturing accuracy and thus a well-defined arrangement of the second metallization area, which extends at least partially over the side surface of the substrate, can facilitate the alignment of the VCSEL on a support structure such as a PCB or a cooling device. For example, the semiconductor device with the second metallization area can be soldered onto a PCB in a self-aligning manner.
[0021] The substrate can be formed from a semiconductor material. For example, it can be a substrate made of gallium arsenide (GaAs) or indium phosphide (InP). The mesa section can have a height of at least 5 pm, particularly at least 7.5 pm, and especially at least 10 pm, above the top surface of the substrate. One advantage is that VCSELs with high topography and high layer heights can be provided.
[0022] The second metallization region can extend over a height of at least 30 pm, in particular at least 40 pm, and in particular at least 50 pm, along the side face of the base body. Within the scope of this disclosure, a height can refer to an extension in a thickness direction orthogonal to the top surface of the base body or parallel to a vertical emission direction of a VCSEL. Alternatively or additionally, the second metallization region can extend over a height of not more than 200 pm, in particular not more than 150 pm, and in particular not more than 120 pm, along the side face of the base body. The metallization region can extend over the entire height or only over a portion of the base body.
[0023] The third metallization area can have a thickness of less than 1 pm, particularly less than 0.5 pm. As mentioned above, the thickness of the third metallization area can be less than 70%, particularly less than 50%, particularly less than 35%, and particularly less than 20% of the thickness of the first and / or second metallization area. Due to the small thickness of the third metallization area, the first and / or second metallization area only needs to overcome a small height difference to overlap the third metallization area. This can reduce the risk of fractures or defects. By providing the third metallization area only on the top surface of the base body and not covering any side surface of the mesa section or the base body, the third metallization area can be thinner than the first and / or second metallization areas.
[0024] The third metallization layer can be designed such that it has no undercut in the area of overlap with the first and / or second metallization layers. While the third metallization layer can optionally have a thickness of at least 1 µm, the absence of an undercut in the third metallization layer prevents breaks or defects in the overlap area. Since the third metal layer is on the bottom and the first and / or second metal layers are processed on top of it, preferably perpendicular edges or flanks without undercuts are provided. This can be achieved, for example, with a vapor-deposited metal layer as the third metallization layer.
[0025] The third metallization layer can be formed by vapor deposition. This allows the third metallization layer to be produced with a small layer thickness and / or without undercutting. The first and / or second metallization layer can be formed by electroplating. This allows the first and / or second metallization layer to reliably cover the side surface of the mesa section or the side surface of the base body. Furthermore, a first and / or second metallization layer produced by electroplating can easily overlap a third metallization layer produced by vapor deposition and establish a reliable electrical connection to it.
[0026] The first and second metallization areas can overlap the third metallization area in different regions. This allows for spatially disjoint overlap zones. An advantage of this approach is the avoidance of fractures or defects that can occur with a direct overlap of the first and second metallization areas. This can further improve reliability.
[0027] The first, second, and / or third metallization region can have a metallization thickness of at least 150 nm, particularly at least 200 nm, particularly at least 300 nm, and particularly at least 350 nm. An advantage of this is the ability to provide low power resistance. Alternatively or additionally, the first, second, and / or third metallization region can have a layer thickness of no more than 1 to 2 pm, at least in certain sections. An advantage of this is the ability to avoid or at least reduce overlap with other component structures. The third metallization region can be electrically insulated from the semiconductor device substrate. In particular, the third metallization region can be arranged on a passivation layer.In other words, the third metallization area does not necessarily serve to establish an electrical connection to the substrate, but rather represents an intermediate layer located on the top of the substrate, electrically insulated from it, to establish an electrical connection between the second and first metallization areas. It is understood that the first and / or second metallization areas may also be insulated from the substrate of the semiconductor device. For example, the section of the second metallization area located on the side face of the substrate can provide power to a top contact, i.e., a contact on the upper side, of a VCSEL.
[0028] In one embodiment, a semiconductor device, in particular a VCSEL for emitting laser light, can be provided with: a fourth metallization area extending from a side face of the base body to the top of the base body; a fifth metallization area arranged on the top of the base body adjacent to the mesa section and the third metallization area; and a sixth metallization area arranged on the top of the base body and electrically connected to the mesa section, in particular to a bottom of the mesa section; wherein the fourth metallization area overlaps and electrically contacts the fifth metallization area; and wherein the sixth metallization area overlaps and electrically contacts the fifth metallization area. For example, the first metallization area can be configured to form a top contact or a bottom contact.The upper contact of the VCSEL is electrically contacted, and the sixth metallization area can be configured to electrically contact a bottom contact of the VCSEL. The term "electrically contacted" here includes the possibility that a section of the first metallization area can form a top contact of the VCSEL and / or that a section of the sixth metallization area can form a bottom contact of the VCSEL. It is understood that multiple mesa sections may be provided, and the metallization area may extend to the top surfaces of multiple mesa sections. A mesa section may have one or more light-emitting areas.
[0029] At least one section of the second metallization area on the side face of the substrate can be configured as a lateral electrical contact for the semiconductor device. At least one section of the fourth metallization area on the substrate can be configured as another lateral electrical contact for the semiconductor device. The respective electrical contacts can be located on the same or different sides of the substrate. The contact of the second metallization area can be designated as the first contact and, for example, be electrically connected to a top contact of the VCSEL. The contact of the fourth metallization area can be designated as the second contact and, for example, be electrically connected to a bottom contact of the VCSEL.
[0030] At least one section of the second metallization area on the side face of the base body can be configured as a lateral solder pad for the semiconductor device. Similarly, at least one section of the fourth metallization area on one or more sides of the base body can be configured as a lateral solder pad for the semiconductor device. The corresponding electrical contacts enable the semiconductor device to be mounted onto a circuit board using a mass-production-ready soldering process.
[0031] The advantages described above in detail for the first aspect of the invention apply accordingly to the other aspects of the invention.
[0032] It is understood that the features mentioned above and those to be explained below can be used not only in the combinations specified, but also in other combinations or individually, without departing from the scope of the present invention. Exemplary embodiments of aspects of the invention are shown in the following drawings and are explained in more detail in the following description.
[0033] Fig. 1 shows a schematic representation of an exemplary semiconductor component in a top view;
[0034] Fig. 2 shows a schematic sectional view of the semiconductor device from Fig. 1 in a first side view;
[0035] Fig. 3 shows a schematic sectional view of the semiconductor device from Fig. 1 in a second side view;
[0036] Fig. 4 shows a schematic representation with different metallization areas;
[0037] Fig. 5 shows a microscopic image of a section with different metallization areas corresponding to Fig. 4;
[0038] Fig. 6 shows another schematic representation with different metallization areas;
[0039] Fig. 7 shows another microscopic image of a section with different metallization areas corresponding to Fig. 6;
[0040] Fig. 8 shows a schematic representation of another exemplary semiconductor device in a perspective view;
[0041] Fig. 9 shows a flowchart of a process for manufacturing a semiconductor device, in particular a VCSEL for emitting laser light. Fig. 1 shows a schematic top view of an exemplary semiconductor device 1. The semiconductor device 1 is a VCSEL (vertical-cavity surface-emitting laser) for emitting laser light 2. The semiconductor device 1 has a base body 10 and a mesa section 20 arranged on the base body. The mesa section 20 is raised above the base body 10, as can be seen from the side view or sectional view in Fig. 2. The mesa section 20 can have a height of at least 5 pm, in particular at least 7.5 pm, and in particular at least 10 pm, above the top surface 11 of the base body 10.The base body 10 can be formed, for example, by a semiconductor substrate, in particular by a substrate of gallium arsenide, GaAs, or of indium phosphide, InP.
[0042] The semiconductor device 1 has several metallization regions 31 , 32 , 33. However, the metallization regions are not created in a single step, but in several metallization steps for different height levels or planes.
[0043] The first metallization area 31 extends from the top surface 11 of the base body 10 along a side surface 22 of the mesa section 20 to a top surface 21 of the mesa section. The first metallization area 31 is connected to an upper terminal contact 23 of the VCSEL on the top surface 31 of the mesa section 20. The second metallization area 32 extends from a side surface 12 of the base body 10 to the top surface 11 of the base body 10. The first metallization area 31 can therefore be located, at least partially, on a higher topographic plane than the second metallization area 32 and can be manufactured in a separate manufacturing step. This improves manufacturing accuracy. The second metallization area can, for example, extend over a height of at least 30 pm, in particular at least 40 pm, and especially at least 50 pm, along the side surface of the base body.
[0044] Additionally, a third metallization area 33 is provided on the top surface 11 of the base body 10. This third metallization area 33 can be located next to the mesa section 20 on the top surface 11 of the base body 10. The first metallization area 31 overlaps the third metallization area 33 and makes electrical contact with it. The second metallization area 32 also overlaps the third metallization area 33 and makes electrical contact with it. This is shown by way of example in Figures 1 and 2 and also in the perspective view of the further embodiment in Figure 8.
[0045] Fig. 2 illustrates the different topographic levels A, B, and C by way of example. The first metallization area 31 can provide a side contact 41, which contacts the VCSEL from topographic level C in Fig. 2 via an upper connection contact 23 in the area of the highest point on topographic level A. The fabrication of the mesa section 20 results in a further height level B, which lies between A and C and over which the electrical connection must run. There is very little space on the upper surface 21 of the mesa at topographic level A, and depending on the application, very small contact areas and a fine structure are required (see also the perspective view of the further embodiment in Fig. 8). Therefore, a coating in the area A to B must be very thin to enable these fine structures. At the same time, large height differences must be overcome between B and C.Therefore, the coating in area B to C must be thick enough to reliably cover and overcome the height differences. To meet both requirements, instead of a single metallization area extending over all height levels A to C from a top surface 21 of the mesa section 20 to a bottom surface of the side contact 41, a division into a first metallization area 31 and a second metallization area 32 can be implemented, with the two metallization areas 31 and 32 being electrically connected to each other.
[0046] The first metallization area 31 and the second metallization area 32 can preferably be produced by electroplating. An advantage of this method is that even very steep flanks, such as a side surface 22 of the mesa section 20 and a side surface 12 of the base body 10, can be covered.
[0047] However, as shown in Figures 4 and 5, it has been found that a direct connection between the two metallization areas 31 and 32 can lead to defects. While the first metallization area 31 and the second metallization area 32 could be directly connected, undercuts 51 can occur at the edges of the metallization areas during manufacturing, as schematically illustrated in Figures 4 and 5. The undercut 51 of a material layer forming the second metallization area 32 can result in a reduced thickness 52 or even a complete break 53 in the material layer forming the first metallization area 31.
[0048] As shown in Figures 6 and 7, it is therefore proposed to provide a third metallization area 33 on the top surface of the base body 10. The first metallization area 31 overlaps the third metallization area 33 and makes electrical contact with it. The second metallization area 32 also overlaps the third metallization area 33 and makes electrical contact with it. The third metallization area 33 can have a smaller thickness than the first and / or second metallization area 31, 32. For example, the third metallization area 33 can have a thickness of less than 1 pm. Thanks to the smaller step height between the third metallization area 33 and the metallization area(s) 31, 32, the risk of a break (see Figure 53 in Figure 5) or an increase in conductor resistance due to a reduction in the thickness of a metallization area (see Figure 52 in Figure 5) can be reduced.4. Alternatively or additionally, the third metallization region 33 can be designed such that it has no undercut 51 in the area of overlap with the first and / or second metallization regions 31, 32. For example, the third metallization region 33 can have a vertical or rising flank without an undercut at an edge. For example, the third metallization region 33 can be formed by vapor deposition. This avoids an undercut at an edge region. The first and second metallization regions 31, 32, on the other hand, can be formed by electroplating, so that the side surfaces 12, 22 of mesa section 20 and base body 10 can also be efficiently covered. It is also possible for the third metallization region 33 to have a thickness of at least 1 pm. This improves the conductivity.
[0049] As shown in Fig. 6, the first metallization area 31 and the second metallization area 32 can overlap the third metallization area 33 in different regions. Thus, spatially disjoint overlap areas can be provided. An advantage of this is that breaks or defects, which can occur with a direct overlap of the first and second metallization areas 31, 32, can be avoided. Reliability can be further improved. Spatially separated overlap areas are also shown in Figs. 1, 2, and 8.
[0050] As shown in Fig. 7, the first metallization area 31 and the second metallization area 32 can optionally overlap. Even if a fracture occurs in an area of an undercut 51 at the edge of the second metallization area 32, an electrical connection between the first and second metallization areas 31, 32 is still indirectly provided via the third metallization area 33, since the first metallization area 31 overlaps and electrically contacts the third metallization area 33 at least in the area designated by reference numeral 54, and the second metallization area 32 overlaps and electrically contacts the third metallization area 33 at least in the area designated by reference numeral 55.
[0051] As shown in Fig. 2 and also in Fig. 7, the third metallization region 33 can be electrically insulated from the base body 10 of the semiconductor device 1. The third metallization region 33 can, for example, be arranged on a passivation layer 42. Likewise, the first metallization region 31 and / or the second metallization region 32 can be electrically insulated from the base body 10 of the semiconductor device 1. For this purpose, one or more suitable intermediate layers 42, 43 can be provided. Thus, the power supply for the upper terminal 23 of the VCSEL can be provided without electrically contacting the base body or the substrate.
[0052] A lower terminal 25 for the mesa section 20 of the semiconductor device 1, here the VCSEL for emitting laser light 2, can be provided in various ways. For example, a semiconductor device 1, as shown in the top view in Fig. 1 and the side view or sectional view in Fig. 3, can be provided with: a fourth metallization area 34 extending from a side surface 12 of the base body 10 to the top surface 11 of the base body 10; a fifth metallization area 35 arranged next to the mesa section 20 and the third metallization area 33 on the top surface 11 of the base body 10; and a sixth metallization area 36 arranged on the top surface 11 of the base body 10 and electrically connected to the mesa section 20, in particular to a bottom surface 24 of the mesa section 20.The fourth metallization area 34 overlaps the fifth metallization area 35 and makes electrical contact with it. The sixth metallization area 36 overlaps the fifth metallization area 35 and makes electrical contact with it. The corresponding metallization steps for the fourth, sixth, and fifth metallization areas can be used as for the first, second, and third metallization areas.
[0053] Optionally, a seventh metallization area 37 can be provided to supply a lower terminal contact 25 for the mesa section 20. In this case, the seventh metallization area 37 and the fifth metallization area 35 can be produced in the same metallization step. However, it is also possible for an electrical connection to the underside 24 of the mesa section to be provided by a direct connection of the fourth metallization area 34, the fifth metallization area 35, or the sixth metallization area 36. Any further metallization areas not required can be omitted in this case. However, one or more metallization areas can advantageously be used to provide an electrical connection near the underside 24 of the mesa section 20. Optionally, one or more of the metallization areas 34, 35, 36 can be electrically insulated from the base body 10 of the semiconductor device 1.For example, one or more of the metallization areas can be arranged at least partially on a passivation layer 44. The fourth metallization area 34 can provide a side contact 45, which is electrically connected to the VCSEL via a lower terminal contact 24 at topography level B.
[0054] As shown in the side view in Fig. 2, the semiconductor device 1 can be a VCSEL for emitting laser light, wherein the mesa section 20 has a layer stack with an upper DBR 26, an active layer 27 for emitting the laser light, and a lower DBR 27. However, it is also possible that at least part of the layers, in particular the layer sequence forming the lower DBR, is part of the substrate 10.
[0055] Figure 8 shows a schematic perspective view of another exemplary semiconductor device 1. The corresponding elements are designated with the same reference numerals. It is understood that the details of the design of the VCSEL or the mesa section and its areas are not limited to a specific configuration. In the embodiment shown in Figure 8, a plurality of light-emitting areas are provided. Furthermore, additional structural features, such as recesses for the insertion of oxide diaphragms, etc., may be provided.
[0056] Optionally, one or more mounting elements can be provided, for example, to attach the semiconductor component 1 to a circuit board. In the example shown in Fig. 8, a pad 61 can be provided, which can serve for so-called flip-chip mounting on a circuit board. Furthermore, a conductor track for contacting the underside of the mesa section 20 is brought into close proximity to the mesa section 20 by the fifth metallization area 35.
[0057] Figure 9 shows a flowchart of a method 100 for fabricating a semiconductor device, in particular a VCSEL for emitting laser light. In a first step S101, a substrate with a mesa section arranged on the substrate is provided. In a second step S102, a third metallization area, arranged adjacent to the mesa section on the top surface of the substrate, is deposited. In a third step S103, a second metallization area is deposited, extending from a side face of the substrate to the top surface of the substrate; the second metallization area overlaps the third metallization area and makes electrical contact with it.In a fourth step, S104, a first metallization region is deposited, extending from a top surface of the substrate along a side surface of the mesa section to a top surface of the mesa section; the first metallization region overlaps and electrically contacts the third metallization region. The order of steps S103 and S104 can be interchanged. In summary, aspects of the solution proposed herein can provide a further improved semiconductor device with a raised mesa section for emitting laser light and a corresponding fabrication method. For example, semiconductor devices with high topographies, such as those with a mesa section >5 pm high, can be further improved. Furthermore, a contribution is made to improving fabrication accuracy and yield.to increase manufacturing yield and / or improve the reliability and long-term stability of semiconductor devices with high topographies.
Claims
Patent claims 1. Semiconductor device (1), in particular VCSEL for emitting laser light (2), comprising: a base body (10); a mesa section (20) arranged on the base body; a first metallization area (31) extending from a top surface (11) of the base body (10) along a side surface (22) of the mesa section (20) to a top surface (21) of the mesa section; a second metallization area (32) extending from a side surface (12) of the base body (10) to the top surface (11) of the base body; a third metallization area (33) arranged adjacent to the mesa section (20) on the top surface (11) of the base body (10); wherein the first metallization area (31) overlaps and electrically contacts the third metallization area (33); and wherein the second metallization area (32) overlaps and electrically contacts the third metallization area (33).
2. Semiconductor device according to claim 1, wherein the semiconductor device (1) is a VCSEL for emitting laser light (2), wherein the mesa section (20) comprises a layer stack with an upper DBR (26), an active layer (27) for emitting the laser light, and a lower DBR (28).
3. Semiconductor device according to one of the preceding claims, wherein the base body (10) is formed by a semiconductor substrate, in particular a substrate of gallium arsenide, GaAs, or of indium phosphide, InP.
4. Semiconductor device according to one of the preceding claims, wherein the mesa section (20) has a height of at least 5 pm, in particular at least 7.5 pm, in particular at least 10 pm, relative to the top surface (11) of the base body (10).
5. Semiconductor device according to one of the preceding claims, wherein the second metallization area (32) extends over a height of at least 30 pm, in particular at least 40 pm, in particular at least 50 pm, along the side surface (12) of the base body (10).
6. Semiconductor device according to one of the preceding claims, wherein the third metallization area (33) has a thickness of less than 1 pm.
7. Semiconductor device according to one of the preceding claims, wherein the third metallization region (33) has no undercut (51) in the area of overlap with the first and / or second metallization region (31, 32); in particular, wherein the third metallization region (33) has a thickness of at least 1 pm.
8. Semiconductor device according to one of the preceding claims, wherein the third metallization area (33) is formed by gas phase separation; and wherein the first and / or second metallization area (31, 32) is formed by electroplating.
9. Semiconductor device according to one of the preceding claims, wherein the first metallization area (31) and the second metallization area (32) overlap the third metallization area (33) in different areas.
10. Semiconductor device according to one of the preceding claims, wherein the first metallization area (31), the second metallization area (32) and / or the third metallization area (33) has a metallization thickness of at least 150 nm, in particular at least 200 nm, in particular at least 300 nm, in particular at least 350 nm.
11. Semiconductor device according to one of the preceding claims, wherein the third metallization area (33) is opposite the base body (10) of the semiconductor device (1) is electrically insulated; in particular wherein the third metallization area (33) is arranged on a passivation layer (42).
12. Semiconductor device according to one of the preceding claims, comprising a fourth metallization area (34) extending from a side face (12) of the base body (10) to the top (11) of the base body (10); a fifth metallization area (35) arranged on the top (11) of the base body (10) adjacent to the mesa section (20) and the third metallization area (33); and a sixth metallization area (36) arranged on the top (11) of the base body (10) and electrically connected to the mesa section (20), in particular to a bottom (24) of the mesa section (20); wherein the fourth metallization area (34) overlaps and electrically contacts the fifth metallization area (35); wherein the sixth metallization area (36) overlaps and electrically contacts the fifth metallization area (35).
13. Semiconductor device according to one of the preceding claims, wherein at least one section of the second metallization area (32) on the side surface (12) of the base body (10) is formed as a lateral electrical connection contact for the semiconductor device (1).
14. Semiconductor device according to one of the preceding claims, wherein at least one section of the second metallization area (32) on the side surface of the base body (10) is formed as a lateral soldering surface for the semiconductor device (1).
15. Method (100) for manufacturing a semiconductor device, in particular a VCSEL for emitting laser light, comprising the steps: Providing a base body with a mesa section arranged on the base body (S101); Deposition of a third metallization area located next to the mesa section on the top of the base body (S102); Deposition of a second metallization area extending from a side face of the base body to the top of the base body; wherein the second metallization area overlaps and electrically contacts the third metallization area (S103); and Deposition of a first metallization area extending from a top surface of the base body along a side surface of the mesa section to a top surface of the mesa section; wherein the first metallization area overlaps and electrically contacts the third metallization area (S104).