Circuit board and semiconductor package

Abstract

This circuit board comprises: a build-up insulator including a plurality of insulating layers stacked in the vertical direction; a protective layer disposed on the build-up insulator; and bonding portions disposed on the upper surface of the build-up insulator, wherein the bonding portions each includes a wiring portion and a plurality of protrusion portions protruding from the surface of the wiring portion.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Electronic components employed in electronic devices include various active and passive circuit elements, and these circuit elements can be integrated into a semiconductor chip or die. Additionally, the semiconductor chip or die can be provided in the form of an electronic package mounted on a substrate containing circuit wiring, such as a printed circuit board (PCB).

[0004] Meanwhile, flip-chip connection structures utilizing connection structures are widely applied in electronic packages when mounting semiconductor chips on printed circuit boards and electrically connecting them. For example, flip-chip connection structures using bumps are advantageous for implementing stacked structures of various types of semiconductor chips. Furthermore, flip-chip connection structures facilitate the adoption of multiple connection structures to secure a large number of input / output (I / O) terminals.

[0005] Among the methods for forming such connection structures, there is the Solder-On-Pad (hereinafter SOP) method. The SOP method manufactures a connection structure by printing with a metallic paste or mounting ball-shaped solder onto connection pads on the upper surface of a printed circuit board exposed by a solder mask pattern, and then reflowing the solder to form spherical solder sections through the surface tension effect. However, as the integration density of semiconductor chips increases and their size decreases, there is a problem in that the SOP method faces limitations in realizing connection members with fine pitch. For example, there is a problem where short circuits occur between adjacent solder sections due to reduced contact with the pads during the solder section formation process.

[0006]

[0007] The present invention provides a circuit board and a semiconductor package capable of preventing short circuits between adjacent bonding parts by increasing the contact area with the solder part in a structure in which electrical connections are made between multiple bonding parts.

[0008]

[0009] A circuit board according to the present embodiment comprises a build-up insulator including a plurality of insulating layers stacked along a vertical direction; a protective layer disposed on the build-up insulator; and a bonding portion disposed on the upper surface of the build-up insulator, wherein the bonding portion includes a wiring portion and a plurality of protrusions protruding from the surface of the wiring portion.

[0010] The vertical thickness of the bonding portion may be thinner than the vertical thickness of the protective layer.

[0011] The above protective layer may include a hole in which the bonding portion is disposed.

[0012] The vertical length of the above wiring section may be longer than the vertical length of the above protrusion.

[0013] The above bonding portions are provided in multiple numbers and arranged along the horizontal direction, and the horizontal spacing between adjacent multiple wiring portions may be shorter than the vertical length of the protrusion.

[0014] The shortest horizontal distance from the side of the protrusion to the side of the wiring portion may be longer than the shortest horizontal distance between the sides of a plurality of adjacent protrusions.

[0015] The cross-section of the above-mentioned protrusion may be any one of a circle, a triangle, or a polygon.

[0016] The above plurality of protrusions may be arranged radially with respect to the center of the wiring portion.

[0017] The above wiring section includes a first section and a second section disposed on the first section, and the size of the crystal grains of the first section may be larger than the size of the crystal grains of the second section.

[0018] A semiconductor package according to the present embodiment comprises: a build-up insulator including a plurality of insulating layers stacked along a vertical direction; a protective layer disposed on the build-up insulator; a bonding portion disposed on the upper surface of the build-up insulator; and an electronic element coupled to the bonding portion, wherein the bonding portion includes a wiring portion and a plurality of protrusions protruding from the surface of the wiring portion.

[0019]

[0020] Through this embodiment, the occurrence of solder bridges can be prevented due to the increased contact area with the solder portion through a plurality of protrusions, thereby minimizing short circuits between adjacent bonding portions.

[0021]

[0022] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0023] FIG. 2 is a cross-sectional view illustrating the bonding structure of a bonding part and an electronic element according to an embodiment of the present invention.

[0024] FIG. 3 is a perspective view illustrating a bonding portion disposed on a build-up insulator according to an embodiment of the present invention.

[0025] FIGS. 4 to 6 are drawings for explaining various shapes of a protrusion according to an embodiment of the present invention.

[0026] FIGS. 7 to 10 are drawings for explaining the process of forming a bonding portion of a circuit board according to an embodiment of the present invention.

[0027]

[0028] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0029] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0030] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0031] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) shall be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Commonly used terms, such as those defined in a dictionary, shall be interpreted in consideration of their contextual meaning as described in the present invention. If a commonly used term defined in a dictionary does not match the meaning it has in the context of the description of the present invention, it shall be interpreted in accordance with the meaning it has in the context of the description of the present invention. Furthermore, even if not explicitly defined in this application, it shall not be interpreted in an ideal or overly formal sense based on the description of the present invention.

[0032] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text.

[0033] Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the meaning of the components is not limited by the ordinal numbers. Terms containing ordinal numbers are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. Furthermore, if the meaning of the component does not depart from the scope of the present invention even without ordinal numbers such as "first" and "second," the component may be referred to by excluding the ordinal number.

[0034] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. Such a term is used merely to distinguish a component from other components and is not limited by the nature, order, sequence, etc. of the component.

[0035] In this application, terms such as “comprising,” “provided,” and “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0036] When referring to directions, vertical and horizontal directions are used for convenience of explanation. Additionally, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, and a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. Furthermore, if the vertical and horizontal directions follow a Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively; if they follow a cylindrical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (ρ) direction (or centrifugal direction) separated from a specific configuration; and if they follow a spherical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (r) direction (or centrifugal direction) separated from a specific configuration. In particular, the vertical direction may refer to the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used by combining the Cartesian coordinate system, the cylindrical coordinate system, and the spherical coordinate system described above. However, unless otherwise specified, the vertical direction refers to the Z-axis according to the Cartesian coordinate system, and the horizontal direction refers to any direction that can be defined on the XY plane; when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction refers to the X-axis and the second horizontal direction refers to the Y-axis.

[0037] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0038] Furthermore, the meaning that Configuration A is positioned between Configuration B and Configuration C may include the meaning that Configuration A is positioned such that at least a portion of it overlaps with Configurations B and C in the horizontal and / or vertical directions. Unless otherwise noted, even if Configuration C is located between a virtual line extending vertically and / or horizontally from Configuration A and a virtual line extending vertically and / or horizontally from Configuration B, the meaning may include that Configuration C is positioned between Configuration A and Configuration B.

[0039] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product; and unless there are special circumstances, it should not be understood as meaning that the entirety of Configuration A is covered by Configuration B. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration C, in addition to Configurations A and B, covers Configuration A exposed from Configuration B.

[0040] Additionally, where it is stated that a component is 'connected,' 'combined,' 'connected,' or 'contacted' with another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component. Accordingly, if component A is to be understood only as being directly 'connected,' 'combined,' 'connected,' or 'contacted' with component B, it is described as being 'directly connected,' 'directly combined,' 'directly connected,' or 'directly contacted.'

[0041] In addition, when it is stated that configuration A is 'fixed' to configuration B, it should be understood that configuration A is indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specifically mentioned, considering the function and purpose to be solved, and in cases where configuration A is to be understood only as being 'directly fixed' to configuration B, it is stated as being 'directly fixed'.

[0042] In addition, when described as “flat” or “located on the same plane,” it should not be interpreted according to the dictionary definition, but rather understood by a person with ordinary knowledge in the relevant technical field to the extent that process deviations are taken into account.

[0043] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is a cross-sectional view illustrating a bonding structure of a bonding part and an electronic element according to an embodiment of the present invention, FIG. 3 is a perspective view illustrating a bonding part disposed on a build-up insulator according to an embodiment of the present invention, and FIG. 4 to 6 are drawings for explaining various shapes of a protrusion according to an embodiment of the present invention.

[0044] Referring to FIGS. 1 to 6, a circuit board (10) according to an embodiment of the present invention may include a build-up structure and a protective layer (191, 196).

[0045] The build-up structure may include a build-up insulator (100) and a build-up wiring.

[0046] The build-up insulator (100) may include a plurality of insulating layers stacked along a vertical direction. The plurality of insulating layers may include a core layer (110), a first insulating layer (120), and a second insulating layer (130). The number of insulating layers constituting the build-up insulator (100) is exemplary, and the circuit board (10) may have a greater number of insulating layers stacked in the vertical direction.

[0047] The core layer (110) may be a component forming the basis of the circuit board (10). Based on the vertical direction of the circuit board (10), the core layer (110) may be positioned in the center of the circuit board (10). The material of the core layer (110) may include at least one selected from the group consisting of glass, resin, plastic, and metal. The core layer (110) may be omitted. Additionally, although not illustrated, the core layer (110) may be composed of two or more insulating layers arranged in the vertical direction.

[0048] The first insulating layer (120) may be disposed on the upper surface of the core layer (110). The first insulating layer (120) may include at least one insulating layer.

[0049] The second insulating layer (130) may be disposed on the lower surface of the core layer (110). With respect to the core layer (110), the second insulating layer (130) may be disposed facing the first insulating layer (120) in a vertical direction. The second insulating layer (130) may include at least one insulating layer.

[0050] The number of insulating layers constituting the first insulating layer (120) and the number of insulating layers constituting the second insulating layer (130) are exemplary, and a greater number of insulating layers can be stacked in the vertical direction to constitute the first insulating layer (120) and the second insulating layer (130), respectively.

[0051] The first insulating layer (120) and the second insulating layer (130) may each be any insulating material, such as a photocurable and / or thermosetting material. As a thermosetting insulating material, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, may be used, and a prepreg (PPG) containing glass fibers within a resin may be used. Additionally, the resins mentioned above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. If at least a portion of the insulating layer constituting the first insulating layer (120) or the second insulating layer (130) is a photocurable insulator, at least a portion of the insulating layer constituting the first insulating layer (120) or the second insulating layer (130) may each be a PID (Photo Imageable Dielectric).

[0052] The circuit board (10) may include a protective layer (191, 196). The protective layer (191, 196) may include a first protective layer (191) disposed on the surface of a first insulating layer (120) and a second protective layer (196) disposed on the surface of a second insulating layer (130). When a semiconductor element is disposed on the surface of the circuit board (10) using a material such as solder, the first protective layer (191) and the second protective layer (196) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent the problem of external contaminants penetrating into the build-up structure and reducing reliability. The first protective layer (191) and the second protective layer (196) may each utilize a photocurable insulating material. Accordingly, the first protective layer (191) and the second protective layer (196) are provided with a solder resist other than the aforementioned ABF, PPG, BT resin, and PID. However, they are not limited thereto and may be provided with various materials capable of performing low wettability with solder and thus preventing short circuits between solders as described above.

[0053] The first protective layer (191) may include a hole (192) for exposing upward a bonding portion (150) disposed on the surface of the first insulating layer (120). The second protective layer (196) may include a hole (197) for exposing downward a wiring portion (134) disposed on the surface of the second insulating layer (130) to the circuit board (10).

[0054] The circuit board (10) may include a build-up wiring for transmitting electrical signals and / or power to an electronic device such as a semiconductor chip. The build-up wiring may include a plurality of wiring portions, a plurality of via portions, and a bonding portion (150).

[0055] A plurality of wiring portions may each be disposed on the surface of a plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of the plurality of wiring portions is embedded within a plurality of insulating layers or protective layers and exposed to the outside from the surface. A wiring portion may also be referred to as a metal portion. Furthermore, the surface of the plurality of insulating layers includes a first surface, a second surface, and a side between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. The meaning of a wiring portion being disposed on the surface is that it is disposed on at least one of the first surface, the second surface, or the side between the plurality of insulating layers. A structure may be provided in which wiring portions are disposed on the first surface and the second surface of some of the insulating layers, respectively, and in which wiring portions are disposed on only the first surface or the second surface of other parts of the plurality of insulating layers.

[0056] A plurality of wiring sections may include a first wiring section (131) disposed on the upper surface of the core layer (110), a second wiring section (133) disposed on the lower surface of the core layer (110), and a third wiring section (134) disposed on the lower surface of the second insulating layer (130). A plurality of wiring sections may include a bonding section (150). The bonding section (150) may be disposed on the first insulating layer (120). As shown in FIG. 2, the bonding section (150) may be coupled with an electronic element (1000). A semiconductor package may be realized through the coupling of the circuit board (10) and the electronic element (1000).

[0057] A via portion may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect a plurality of wiring portions facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and a via portion may be disposed within the via hole.

[0058] The via section may include a first via section (141) penetrating at least a portion of the first insulating layer (120), a second via section (142) penetrating at least a portion of the core layer (110), and a third via section (143) penetrating at least a portion of the second insulating layer (130).

[0059] The first via (141) can electrically connect the bonding section (150) and the first wiring section (131). The second via (142) can electrically connect the first wiring section (131) and the second wiring section (133). The third via (143) can electrically connect the second wiring section (133) and the third wiring section (134).

[0060] A plurality of wiring portions and a plurality of via portions can each be implemented through a seed layer disposed on the surface of an insulating layer or the inner wall of a via hole and an electroplated layer formed on the surface of the seed layer by an electroplating method.

[0061] The circuit board (10) may include a bonding portion (150). The bonding portion (150) may be disposed on the upper surface of the build-up insulator (100). The bonding portion (150) may be exposed to the surface of the circuit board (10) through a hole (192) in the first protective layer (191). The bonding portion (150) may be provided in multiple numbers and arranged along the horizontal direction. The multiple bonding portions (150) may be spaced apart in the horizontal direction.

[0062] The vertical thickness of the bonding portion (150) may be smaller than the vertical thickness of the protective layer (191). Accordingly, the bonding area of ​​the electronic device (1000) according to the bonding portion (150) and the solder portion (1200) can be guided through the hole (192) of the protective layer (191), and a short circuit through the protective layer (191) can be efficiently prevented during the formation process of the solder portion (1200).

[0063] The bonding portion (150) may include a wiring portion (152) and a plurality of protrusions (160).

[0064] The wiring portion (152) may be disposed on the first insulating layer (120). The wiring portion (152) may be electrically connected to the wiring portion (131) disposed on the core layer (110) through the first via portion (141). The wiring portion (152) may have a circular cross-sectional shape. The wiring portion (152) may have a first length (H1) in the vertical direction. The horizontal width of the wiring portion (152) may be greater than the horizontal width of each of the plurality of protrusions (160).

[0065] As illustrated in FIG. 10, the wiring portion (152) may include a first portion formed by a seed layer (300) and a second portion disposed on the first portion. The second portion may be implemented on the seed layer (300) by an electroplating method. The size of the crystal grains constituting the second portion may be smaller than the size of the crystal grains constituting the first portion. The vertical length of the second portion may be longer than the vertical length of the first portion.

[0066] The wiring section (152) can also be named as a pad section.

[0067] A plurality of protrusions (160) may have a shape that protrudes upward in a vertical direction from the wiring section (152). With respect to a single wiring section (152), a plurality of protrusions (160) may be provided and arranged spaced apart along the horizontal direction. A plurality of protrusions (160) may be arranged radially with respect to the center of the wiring section (152). A plurality of protrusions (160) may be arranged to form equal intervals along the circumferential direction of the wiring section (152).

[0068] As shown in FIG. 4, each of the plurality of protrusions (160) may have a circular cross-sectional shape. This is not limited to this, and as shown in FIG. 5, each of the plurality of protrusions (160) may have a triangular cross-sectional shape, or as shown in FIG. 6, each of the plurality of protrusions (160) may have a polygonal cross-sectional shape including a square.

[0069] The bonding portion (150) can be combined with the electronic element (1000) through the solder portion (1200). The electronic element (1000) includes a terminal portion (1100) that is combined with the bonding portion (150), and the solder portion (1200) can be positioned between the terminal portion (1100) and the wiring portion (152) of the electronic element (1000). At least a portion of the solder portion (1200) may be positioned to overlap horizontally with a plurality of protrusions (160), and another portion may be positioned between the protrusions (160) and the terminal portion (1100). The solder portion (1200) may be positioned between a plurality of protrusions (160) on the wiring portion (152).

[0070] According to the embodiment, the contact area with the solder portion (1200) through the plurality of protrusions (160) increases, thereby facilitating the bonding of the solder portion (1200) onto the bonding portion (150). Although there is a trend of decreasing the horizontal spacing between the plurality of wiring portions to achieve fine pitch, there is a risk of solder bridges occurring between adjacent wiring portions due to the reduced contact area with the solder portion caused by the reduction in the width of the wiring portions. Therefore, according to the embodiment, the occurrence of solder bridges can be prevented by increasing the contact area with the solder portion (1200) through the plurality of protrusions (160), thus minimizing short circuits between adjacent bonding portions. Furthermore, as the solder portion (1200) formation area is guided through the plurality of protrusions (160), the bonding process of the electronic device (1000) through the formation of the solder portion (1200) on the wiring portion (152) can be performed more easily.

[0071] The size of the crystal grains constituting the protrusion (160) may be the same as the size of the crystal grains of the second part of the wiring part (152).

[0072] The vertical length (H2) from the upper surface of the wiring portion (152) to the upper surface of the protrusion (160) may be shorter than the first length (H1), which is the vertical length of the wiring portion (152). Accordingly, a plurality of protrusions (160) with a relatively thin horizontal width can be firmly supported on the wiring portion (152), and the formation of a solder portion (1200, see FIG. 2) on the wiring portion (152) can be easily achieved.

[0073] As illustrated in FIG. 4, the shortest horizontal distance (t1) from the side of the protrusion (160) to the side of the wiring portion (152) may be longer than the shortest horizontal distance (t2) between the sides of adjacent protrusions (160). Accordingly, during the process of forming the solder portion (1200), the solder portion (1200) can be guided into the area between the plurality of protrusions (160), and the penetration of a portion of the solder portion (1200) to the outside through the side of the wiring portion (152) by the bonding force between the solder portion (1200) and the protrusion (160) can be minimized.

[0074] As shown in FIG. 2, the horizontal spacing (t3) between adjacent wiring sections (152) may be shorter than the vertical length (H2) of the protrusion (160). Accordingly, solder bridging can be prevented by increasing the contact area with the solder section (1200) through the protrusion (160).

[0075] FIGS. 7 to 10 are drawings for explaining the process of forming a bonding portion of a circuit board according to an embodiment of the present invention.

[0076] Referring to FIG. 7, in a vertical stacking structure of a core layer (110) and a plurality of insulating layers (120, 130), wiring portions (152, 134) may be formed on the upper surface of the first insulating layer (120) and the lower surface of the second insulating layer (130), respectively, which form the surface of the build-up insulator (100). The formation of the wiring portions (152, 134) may be achieved by an electroplating method on the seed layer (300) through the seed layer (300) disposed on the surface of each insulating layer (120, 130).

[0077] Next, as illustrated in FIG. 8, a mask (400) may be attached to the surface of an insulating layer on which a wiring portion (152) is formed. The mask (400) may include a hole pattern (410) corresponding to the area where the protrusion (160) is formed. The hole pattern (410) may be placed on the wiring portion (152). Accordingly, as illustrated in FIG. 9, a protrusion (160) may be formed on the wiring portion (152) by an electrolytic plating method within the hole pattern (410).

[0078] After the formation of the protrusions (160) within the hole pattern (410), the surfaces of the protrusions (160) can be polished so that the vertical height between the protrusions (160) is constant.

[0079] Afterward, as illustrated in FIG. 10, the mask (400) is removed from the build-up insulator (100), and a portion of the seed layer (300) disposed within the surface of the insulating layer can be removed through etching. In this case, as previously described, another portion of the seed layer (300) forms a portion of the wiring portion (152) and can form a first portion within the wiring portion (152). Accordingly, the seed layer (300) is disposed between the wiring portion (152) and the build-up insulator (100), but the seed layer does not exist between the wiring portion (152) and the protrusion (160).

[0080] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0081] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0082] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0083] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. A build-up insulator comprising a plurality of insulating layers stacked along a vertical direction; A protective layer disposed on the above-mentioned build-up insulator; and It includes a bonding portion disposed on the upper surface of the above-mentioned build-up insulator, and The above bonding portion is a circuit board comprising a wiring portion and a plurality of protrusions protruding from the surface of the wiring portion.

2. In Paragraph 1, A circuit board in which the vertical thickness of the bonding portion is thinner than the vertical thickness of the protective layer.

3. In Paragraph 1, The above protective layer is a circuit board including a hole where the bonding portion is disposed.

4. In Paragraph 1, A circuit board in which the vertical length of the above wiring portion is longer than the vertical length of the above protrusion.

5. In Paragraph 1, The above bonding parts are provided in multiple numbers and arranged along the horizontal direction, and A circuit board in which the horizontal spacing between adjacent multiple wiring sections is shorter than the vertical length of the protrusion.

6. In Paragraph 1, A circuit board in which the shortest horizontal distance from the side of the protrusion to the side of the wiring portion is longer than the shortest horizontal distance between the sides of a plurality of adjacent protrusions.

7. In Paragraph 1, A circuit board in which the cross-section of the above-mentioned protrusion is one of a circle, a triangle, or a polygon.

8. In Paragraph 1, The above plurality of protrusions are circuit boards arranged radially with respect to the center of the wiring portion.

9. In Paragraph 1, The above wiring section includes a first section and a second section disposed on the first section, and A circuit board in which the size of the crystal grains of the first part is larger than the size of the crystal grains of the second part.

10. A build-up insulator comprising a plurality of insulating layers stacked along a vertical direction; A protective layer disposed on the above-mentioned build-up insulator; A bonding portion disposed on the upper surface of the above-mentioned build-up insulator; and It includes an electronic element coupled to the above-mentioned bonding part, and The above bonding portion is a semiconductor package comprising a wiring portion and a plurality of protrusions protruding from the surface of the wiring portion.

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