Method and system for implementing FPGA-based readback in mipid-PHY low-power mode

Abstract

The present application discloses a method and system for implementing FPGA-based readback in an MIPID-PHY low-power mode. In a low-power mode, data is transmitted from a TCON IC unit to an FPGA chip by means of a dedicated receiving path, thereby ensuring accurate data reception and readback, effectively avoiding data loss or errors during transmission, and improving the communication reliability and stability.

Description

A method and system for implementing low-speed mode readback of MIPID-PHY based on FPGA Technical Field

[0001] This application relates to the field of Mura defect detection technology, and in particular to a method and system for implementing MIPID-PHY low-speed mode readback based on FPGA. Background Technology

[0002] In the field of panel inspection, the MIPID-PHY protocol, as an important communication interface standard, is widely used in data transmission. This protocol not only supports synchronous data transmission in high-speed mode (HS) but also has asynchronous data transmission capabilities in low-speed mode (LP). However, many FPGA devices currently on the market have functional limitations in supporting the MIPID-PHY protocol.

[0003] These FPGA devices can support data transmission in both high-speed (HS) and low-speed (LP) modes of the MIPID-PHY protocol, but they cannot implement data readback in low-speed (LP) mode. Due to the incomplete functionality of FPGA devices in MIPID-PHY protocol applications, the display panel industry faces a narrow range of choices when selecting FPGA devices, resulting in high development difficulty and cost, and failing to meet the needs of the panel industry. Technical issues

[0004] This application provides a method and system for implementing MIPID-PHY low-speed mode readback based on FPGA, which solves the problem that FPGA does not support bidirectional data communication in low-speed mode, and realizes data transmission and reception between FPGA chip and TCON IC unit in low-speed mode. Technical solutions

[0005] The first aspect of this application provides a method for implementing MIPID-PHY low-speed mode readback based on FPGA. The method is applied to a readback system, which includes: an FPGA chip, a high-speed RF switching unit, and a TCON IC unit.

[0006] When the FPGA chip sends data to the TCON IC unit, the FPGA chip switches to transmit mode and sends the data to the TCON IC unit through the transmit differential pair of the FPGA chip and the high-speed radio frequency switch unit;

[0007] In low-speed mode, when the FPGA chip reads back the target data from the TCON IC unit, the FPGA chip switches to receiving mode, and the data channel of the high-speed RF switch unit switches to a dedicated receiving path from the TCON IC unit to the FPGA chip. The dedicated receiving path is the signal transmission path formed after the high-speed RF switch unit switches the current contact to the target contact when the FPGA chip outputs a low level.

[0008] The TCON IC unit sends the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes the readback operation.

[0009] Optionally, the FPGA chip is provided with transmit differential pairs and receive differential pairs, wherein the transmit differential pairs are used for data transmission in high-speed mode and low-speed mode, and the receive differential pairs are used for data reception in low-speed mode.

[0010] Optionally, the high-speed radio frequency switching unit is provided with one set of CLK differential pairs and four sets of Data differential pairs.

[0011] Optionally, the high-speed radio frequency switch unit is integrated between the FPGA chip and the TCON IC unit.

[0012] Optionally, the TCON IC unit supports data reception in high-speed mode and data transmission or reception in low-speed mode.

[0013] Optionally, before transmitting the data to the TCON IC unit via the transmit differential pair of the FPGA chip and the high-speed RF switching unit, the method further includes:

[0014] Enable the transmit differential pair of the FPGA chip and disable the receive differential pair of the FPGA chip.

[0015] Optionally, before the TCON IC unit transmits the target data to the FPGA chip via the dedicated receiving path and the receiving differential pair of the FPGA chip, the method further includes:

[0016] Enable the receive differential pair of the FPGA chip and enable the transmit differential pair of the FPGA chip.

[0017] Optionally, when the FPGA chip sends data to the TCON IC unit, the FPGA chip is switched to transmit mode, and the multiple sets of data are sent to the TCON IC unit through the transmit differential pair of the FPGA chip and the high-speed RF switch unit, including:

[0018] In high-speed mode, when the FPGA chip sends multiple sets of data to the TCON IC unit, the FPGA chip is switched to transmit mode, and the data is sent to the TCON IC unit through the transmit differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

[0019] Optionally, when the FPGA chip sends data to the TCON IC unit, the FPGA chip is switched to transmit mode, and the data is transmitted to the TCON IC unit through the transmit differential pair of the FPGA chip and the high-speed RF switch unit, including:

[0020] In low-speed mode, when the FPGA chip sends multiple sets of data to the TCON IC unit, the FPGA chip is switched to transmit mode, and the first set of data in the multiple sets of data is sent to the TCON IC unit through the transmit differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

[0021] The second aspect of this application provides a system for implementing MIPID-PHY low-speed mode readback based on FPGA, the system comprising: an FPGA chip, a high-speed radio frequency switching unit, and a TCON IC unit;

[0022] The FPGA chip is used to switch to transmission mode when sending data to the TCON IC unit, and send the data to the TCON IC unit by transmitting differential pairs and the high-speed radio frequency switching unit;

[0023] The FPGA chip is used to switch to receiving mode in low-speed mode when reading back target data from the TCON IC unit;

[0024] The high-speed radio frequency switch unit is used to switch the data channel to a dedicated receiving path from the TCON IC unit to the FPGA chip. The dedicated receiving path is the signal transmission path formed after the high-speed radio frequency switch unit switches the current contact to the target contact when the FPGA chip outputs a low level.

[0025] The TCON IC unit is used to send the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes the readback operation.

[0026] Optionally, the FPGA chip is provided with transmit differential pairs and receive differential pairs, wherein the transmit differential pairs are used for data transmission in high-speed mode and low-speed mode, and the receive differential pairs are used for data reception in low-speed mode.

[0027] Optionally, the high-speed radio frequency switching unit is provided with one set of CLK differential pairs and four sets of Data differential pairs.

[0028] Optionally, the high-speed radio frequency switch unit is integrated between the FPGA chip and the TCON IC unit.

[0029] Optionally, the TCON IC unit supports data reception in high-speed mode and data transmission or reception in low-speed mode.

[0030] Optionally, the system further includes a first processing unit, which is used to enable the transmit differential pair of the FPGA chip and disable the receive differential pair of the FPGA chip.

[0031] Optionally, the system further includes a second processing unit, which is used to enable the receive differential pair of the FPGA chip and enable the transmit differential pair of the FPGA chip.

[0032] Optionally, in high-speed mode, when the FPGA chip sends multiple sets of data to the TCON IC unit, the FPGA chip is switched to transmit mode, and the multiple sets of data are sent to the TCON IC unit through the transmit differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

[0033] Optionally, in low-speed mode, when the FPGA chip sends multiple sets of data to the TCON IC unit, the FPGA chip is switched to transmit mode, and the first set of data in the multiple sets of data is sent to the TCON IC unit through the transmit differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

[0034] The third aspect of this application provides an apparatus for implementing MIPID-PHY low-speed mode readback based on FPGA, a system for implementing MIPID-PHY low-speed mode readback based on FPGA, and a platform for placing the system for implementing MIPID-PHY low-speed mode readback based on FPGA. The system for implementing MIPID-PHY low-speed mode readback based on FPGA includes: an FPGA chip, a high-speed radio frequency switch unit, and a TCON IC unit.

[0035] The FPGA chip is used to switch to transmission mode when sending data to the TCON IC unit, and send the data to the TCON IC unit by transmitting differential pairs and the high-speed radio frequency switching unit;

[0036] The FPGA chip is used to switch to receiving mode in low-speed mode when reading back target data from the TCON IC unit;

[0037] The high-speed radio frequency switch is used to switch the data channel to a dedicated receiving path from the TCON IC unit to the FPGA chip. The dedicated receiving path is the signal transmission path formed after the high-speed radio frequency switch unit switches the current contact to the target contact when the FPGA chip outputs a low level.

[0038] The TCON IC unit is used to send the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes the readback operation.

[0039] Optionally, the FPGA chip is provided with transmit differential pairs and receive differential pairs, wherein the transmit differential pairs are used for data transmission in high-speed mode and low-speed mode, and the receive differential pairs are used for data reception in low-speed mode. Beneficial effects

[0040] This application enables data to be transmitted from the TCON IC unit to the FPGA chip through a dedicated receiving path in low-speed mode, ensuring accurate data reception and readback. This effectively solves the problem that the FPGA does not support bidirectional data communication in low-speed mode, and realizes data transmission and reception between the FPGA chip and the TCON IC unit in low-speed mode. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 is a flowchart illustrating an embodiment of the method for implementing low-speed mode readback of MIPID-PHY based on FPGA in this application.

[0043] Figure 2 is a schematic diagram of an embodiment of the MIPID-PHY low-speed mode readback system based on FPGA according to this application;

[0044] Figure 3 is a schematic diagram of an embodiment of the device for implementing MIPID-PHY low-speed mode readback based on FPGA in this application;

[0045] Figure 4 is a schematic diagram of the implementation principle of the MIPID-PHY low-speed mode readback method based on FPGA in this application;

[0046] Figure 5 is a schematic diagram of data transmission and data reception of the FPGA chip;

[0047] Figure 6 is a schematic diagram of the high-speed radio frequency switching unit;

[0048] Figure 7 is a schematic diagram of the FPGA chip sending data to the TCON IC unit in high-speed mode;

[0049] Figure 8 is a schematic diagram of the FPGA chip sending data to the TCON IC unit in low-speed mode;

[0050] Figure 9 is a schematic diagram of the FPGA chip reading back data from the TCON IC unit in low-speed mode. Embodiments of the present invention

[0051] This application provides a method and system for implementing MIPID-PHY low-speed mode readback based on FPGA, which solves the problem that FPGA does not support bidirectional data communication in low-speed mode, and realizes data transmission and reception between FPGA chip and TCON IC unit in low-speed mode.

[0052] Please refer to Figure 1. The first aspect of this application provides an embodiment of a method for implementing low-speed mode readback of MIPID-PHY based on an FPGA. This method is applied to a readback system, which includes an FPGA chip, a high-speed RF switching unit, and a TCON IC unit. The high-speed RF switching unit is integrated between the FPGA chip and the TCON IC unit. The method includes:

[0053] 101. When the FPGA chip sends data to the TCON IC unit, the FPGA chip switches to the transmit mode and sends the data to the TCON IC unit through the transmit differential pair of the FPGA chip and the high-speed radio frequency switch unit;

[0054] 102. In low-speed mode, when the FPGA chip reads back the target data from the TCON IC unit, the FPGA chip switches to receiving mode, and the data channel of the high-speed RF switch switches to the dedicated receiving path from the TCON IC unit to the FPGA chip.

[0055] 103. The TCON IC unit sends the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes the readback operation.

[0056] In this embodiment, when the FPGA chip sends data to the TCON IC unit, the FPGA chip switches to transmit mode and sends the data to the TCON IC unit through the FPGA chip's transmit differential pair and high-speed RF switch unit. After the FPGA chip sends data to the TCON IC unit, in low-speed mode, when the FPGA chip reads back the target data from the TCON IC unit, the FPGA chip switches to receive mode. The data channel of the high-speed RF switch switches to the dedicated receive path from the TCON IC unit to the FPGA chip. The TCON IC unit sends the target data to the FPGA chip through the dedicated receive path and the FPGA chip's receive differential pair, so that the FPGA chip receives the target data and completes the readback operation.

[0057] In step 101, the FPGA chip sends data to the TCON IC unit. Before performing the sending operation, the FPGA chip first needs to switch to the sending mode. Through the configuration of the internal logic of the FPGA chip, it is ensured that the data can be correctly output from the sending port of the FPGA chip.

[0058] The FPGA chip outputs data via differential pairs. A high-speed RF switch unit acts as a path selector throughout the process, connecting the FPGA chip's output to the TCON IC unit's input based on control signals. Once the path is established, the FPGA chip begins sending data to the TCON IC unit. This transmitted data may include control commands, configuration information, or any data the TCON IC unit needs to process. No specific limitations are imposed on the transmitted data; it can be configured according to the actual situation.

[0059] In step 102, in low-speed mode, the FPGA chip reads back the target data from the TCON IC unit.

[0060] When data needs to be read back from the TCON IC unit, the FPGA chip first switches to receive mode and reconfigures the internal logic of the FPGA chip to ensure that it can correctly receive data from the TCON IC unit.

[0061] The data channel of the high-speed RF switching unit needs to be switched to a dedicated receiving path from the TCON IC unit to the FPGA chip according to the control signal. The purpose of this step is to ensure that the data can be transmitted from the TCON IC unit to the FPGA chip without error.

[0062] In low-speed mode, the data transmission speed is relatively low to meet the needs of readback operations or due to the output rate limitation of the TCON IC unit.

[0063] In step 103, the TCON IC unit sends data to the FPGA chip through a dedicated receiving path. The TCON IC unit supports data reception in high-speed mode and data transmission or reception in low-speed mode. After receiving a readback request, the TCON IC unit can send the data back to the FPGA chip through the established dedicated receiving path, that is, the path switched by the high-speed RF switch unit.

[0064] The FPGA chip receives data from the TCON IC unit through its receive differential pair. The receive differential pair helps reduce noise and interference during signal transmission and improves the accuracy of data reception.

[0065] Once the FPGA chip successfully receives the data, the readback operation is complete. This data can then be used by the FPGA chip for further processing, analysis, or storage.

[0066] In summary, this solution achieves data transmission and readback in low-speed mode through the collaborative work of the FPGA chip, high-speed RF switch unit, and TCON IC unit. It effectively solves the problem that the FPGA does not support bidirectional data communication in low-speed mode, and realizes data transmission and reception between the FPGA chip and the TCON IC unit in low-speed mode. Please refer to Figure 4 for the block diagram of the solution.

[0067] The FPGA chip is equipped with transmit differential pairs and receive differential pairs. The transmit differential pairs are used for data transmission in high-speed mode and low-speed mode, and the receive differential pairs are used for data reception in low-speed mode. For a schematic diagram of data transmission and data reception of the FPGA chip in high-speed mode and low-speed mode, please refer to Figure 5.

[0068] In the embodiments of this application, in high-speed mode, the FPGA chip sends data to the TCON IC unit by sending differential pairs. The differential pair consists of a pair of signal lines, usually marked as positive (e.g., TX+) and negative (e.g., TX-), and the voltage difference between the two represents the data to be transmitted.

[0069] High-speed data transmission requires the FPGA chip to have a high clock frequency and data processing capability to ensure accurate data transmission. Sending differential pairs helps reduce signal attenuation and interference during transmission, and improves signal integrity and reliability.

[0070] In addition to high-speed mode, the transmit differential pair is also used for data transmission in low-speed mode. In low-speed mode, although the data transmission speed is reduced, the requirements for signal quality and stability are not lowered. The transmit differential pair can provide stable signal transmission in low-speed mode, ensuring that data accurately reaches the receiving end. At this time, the FPGA chip adjusts its internal logic and clock settings to adapt to the data transmission requirements in low-speed mode.

[0071] In low-speed mode, the FPGA chip receives data from the TCON IC unit through a receive differential pair. The receive differential pair also consists of a pair of signal lines, usually marked as positive (e.g., RX+) and negative (e.g., RX-), used to capture the differential signal transmitted by the transmitter. The data transmission channel of the FPGA chip is a shared channel between high-speed and low-speed modes, and is switched through the instruction register inside the FPGA chip.

[0072] In low-speed mode data reception, the FPGA chip accurately identifies and processes the received signal. The receiving differential pair helps filter out noise and interference, improves the signal-to-noise ratio, and thus ensures accurate data reception.

[0073] It should be noted that the selection of the two differential pairs of the FPGA chip must meet the following conditions:

[0074] 1. Only one pair of transmit differential pairs and one pair of receive differential pairs are working at a time. In data transmission mode, the transmit differential pair is working and the receive differential pair is off. In data reception mode, the receive differential pair is working and the transmit differential pair is off.

[0075] Specifically, before sending data to the TCON IC unit through the FPGA chip's transmit differential pair and high-speed RF switch unit, the FPGA chip's transmit differential pair needs to be turned on, and the FPGA chip's receive differential pair needs to be turned off at the same time. This satisfies the condition that when the FPGA chip sends data to the TCON IC unit, the transmit differential pair is active and the receive differential pair is turned off.

[0076] Before the TCON IC unit sends the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, it is necessary to enable the receiving differential pair and the transmitting differential pair of the FPGA chip. This satisfies the condition that the receiving differential pair is active and the transmitting differential pair is closed when the FPGA chip receives data from the TCON IC unit.

[0077] 2. The transmit differential pair and the receive differential pair must be adjacent pins inside the FPGA chip to reduce signal reflection caused by an excessively long stub in a certain operating state. The reflection calculation conditions are as follows:

[0078] Where: L represents the stub length, ZC represents the characteristic impedance, ZI represents the load impedance, and f represents the signal frequency. By changing the stub length L, impedance matching can be achieved, thereby reducing signal reflection.

[0079] When the FPGA chip sends data to the TCON IC unit, it switches to transmit mode and transmits the data to the TCON IC unit through the FPGA chip's transmit differential pair and high-speed RF switching unit. This process can be divided into low-speed mode and high-speed mode. The data transmission from the FPGA chip to the TCON IC unit in low-speed mode and high-speed mode are described below:

[0080] 1. In high-speed mode, when the FPGA chip sends multiple sets of data to the TCON IC unit, the FPGA chip is switched to transmit mode, and the data is sent to the TCON IC unit through the transmit differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

[0081] 2. In low-speed mode, when the FPGA chip sends multiple sets of data to the TCON IC unit, the FPGA chip is switched to transmit mode, and the first set of data in the multiple sets of data is sent to the TCON IC unit through the transmit differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

[0082] The high-speed RF switch unit is equipped with one CLK differential pair and four Data differential pairs.

[0083] In this embodiment, the high-speed radio frequency switch unit is one of the key components in the readback system. The high-speed radio frequency switch unit is responsible for switching the signal path between the FPGA chip and the TCON IC unit to ensure accurate data transmission in different operating modes. The high-speed radio frequency switch unit has the characteristics of high-speed switching capability and low insertion loss, which can meet the requirements of high-speed data transmission.

[0084] Among them, the CLK differential pair is a differential pair specifically used for transmitting clock signals. In high-speed data transmission systems, clock signals are the key to synchronous data transmission. The CLK differential pair ensures that data transmission between the FPGA chip and the TCON IC unit can be synchronized by transmitting stable and accurate clock signals. The CLK differential pair adopts differential transmission mode, which can effectively resist common-mode interference and improve the stability and reliability of signal transmission.

[0085] Data differential pairs are differential pairs used to transmit data signals. In a readback system, the FPGA chip and the TCONIC unit need to exchange data frequently, including control commands, configuration information, and target data to be read back. Data differential pairs ensure that the system can operate normally and achieve the expected functions by transmitting these data signals.

[0086] The high-speed radio frequency switch unit in this application is equipped with four sets of data differential pairs, which means that the high-speed radio frequency switch unit has the ability to transmit multiple data signals simultaneously, thereby meeting the needs of parallel data transmission and improving the efficiency and speed of data transmission.

[0087] The high-speed RF switch unit is equipped with one CLK differential pair and four Data differential pairs. It is a 2-input 1-output high-speed switch, which can ensure that the FPGA chip and the TCON IC unit can transmit clock signals and data signals stably and accurately. For a schematic diagram of the high-speed RF switch unit, please refer to Figure 6.

[0088] It should be noted that the selection of high-speed RF switching units must meet the following conditions: high bandwidth, capable of transmitting a D-PHY signal of up to 2.5 Gbps in high-speed mode (HS); low loss; low intra-differential pair delay; and low inter-differential pair delay. Only when the above requirements are met can the selection of high-speed RF switching units in this application be deemed acceptable.

[0089] The TCON IC unit is an internal module of the panel. The TCON IC unit supports data reception in high-speed mode as well as data transmission and reception in low-speed mode.

[0090] Please refer to Figure 2. The second aspect of this application provides an embodiment of a system for implementing MIPID-PHY low-speed mode readback based on FPGA, including: FPGA chip 201, high-speed radio frequency switch unit 202 and TCON IC unit 203;

[0091] The FPGA chip 201 is used to switch to transmission mode when sending data to the TCONIC unit 203, and send the data to the TCONIC unit 203 by transmitting differential pairs and the high-speed radio frequency switch unit;

[0092] The FPGA chip 201 is used to switch to receiving mode in low-speed mode when reading back target data from the TCON IC unit 203;

[0093] The high-speed radio frequency switch 202 is used to switch the data channel to a dedicated receiving path from the TCON IC unit 203 to the FPGA chip 201;

[0094] The TCON IC unit 203 is used to send the target data to the FPGA chip 201 through the dedicated receiving path and the receiving differential pair of the FPGA chip 201, so that the FPGA chip 201 receives the target data and completes the readback operation.

[0095] The interaction process between the FPGA chip and the TCON IC unit can be divided into the following cases:

[0096] First: In high-speed mode, multiple sets of data transmissions must ensure that the data and clock are aligned. The clock and data of the switching unit inside the FPGA need to pass through the differential pair of the high-speed RF switching unit and then interact with the TCON IC unit. Please refer to Figure 7 for a specific schematic diagram.

[0097] Second: In low-speed mode, the FPGA chip only uses the first set of data from multiple sets of data. The data is exchanged with the TCON IC unit through the high-speed RF switching unit. Please refer to Figure 8 for a specific schematic diagram.

[0098] In practical applications, when the Sel_CH_0 of the FPGA chip outputs a high level, it selects the RF switch unit as group A -> COM group; when it outputs a low level, it selects the RF switch unit as group B -> COM group. When the TCON_IC unit acts as the transmitter, Sel_CH_0 is set to a low level, the high-speed RF unit switches to group B -> COM group, and the FPGA chip switches to data receiving mode, thereby performing low-speed readback from the TCON_IC unit to the FPGA chip. For a detailed schematic diagram, please refer to Figure 9.

[0099] Please refer to Figure 3, which is an embodiment of the FPGA-based device for implementing low-speed mode readback of MIPID-PHY provided in this application, including:

[0100] Processor 301, memory 302, input / output unit 303, and bus 304;

[0101] The processor 301 is connected to the memory 302, the input / output unit 303 and the bus 304;

[0102] The storage 302 stores a program, which the processor 301 invokes to execute the first aspect and any optional method of the first aspect.

[0103] This application also relates to a computer-readable storage medium on which a program is stored, which, when run on a computer, causes the computer to perform any of the optional methods described above.

[0104] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0105] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0106] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0107] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0108] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A method for implementing low-speed mode readback of MIPID-PHY based on FPGA, the method being applied to a readback system, the readback system comprising: The FPGA chip, high-speed RF switch unit, and TCON IC unit include: When the FPGA chip sends data to the TCON IC unit, the FPGA chip switches to transmit mode and sends the data to the TCON IC unit through the transmit differential pair of the FPGA chip and the high-speed radio frequency switch unit; In low-speed mode, when the FPGA chip reads back the target data from the TCON IC unit, the FPGA chip switches to receiving mode, and the data channel of the high-speed RF switch unit switches to a dedicated receiving path from the TCON IC unit to the FPGA chip. The dedicated receiving path is the signal transmission path formed after the high-speed RF switch unit switches the current contact to the target contact when the FPGA chip outputs a low level. The TCON IC unit sends the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes the readback operation.

2. The method for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 1, wherein, The FPGA chip is equipped with transmit differential pairs and receive differential pairs. The transmit differential pairs are used for data transmission in high-speed mode and low-speed mode, and the receive differential pairs are used for data reception in low-speed mode.

3. The method for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 1, wherein, The high-speed radio frequency switch unit is equipped with one CLK differential pair and four Data differential pairs.

4. The method for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 1, wherein, The high-speed radio frequency switch unit is integrated between the FPGA chip and the TCON IC unit.

5. The method for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 1, wherein, The TCON IC unit supports data reception in high-speed mode and data transmission or reception in low-speed mode.

6. The method for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 2, wherein, After the step of the FPGA chip switching to transmit mode when it sends data to the TCON IC unit, and before the step of transmitting the data to the TCON IC unit via the transmit differential pair of the FPGA chip and the high-speed RF switch unit, the method further includes: Enable the transmit differential pair of the FPGA chip and disable the receive differential pair of the FPGA chip.

7. The method for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 2, wherein, After the step of switching the data channel of the high-speed RF switch to a dedicated receive path from the TCON IC unit to the FPGA chip, and before the step of the TCON IC unit transmitting the target data to the FPGA chip via the dedicated receive path and the receive differential pair of the FPGA chip, the method further includes: Enable the receive differential pair of the FPGA chip and enable the transmit differential pair of the FPGA chip.

8. The method for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 1, wherein, When the FPGA chip sends data to the TCON IC unit, the FPGA chip switches to transmit mode, and the steps of sending the data to the TCON IC unit through the FPGA chip's transmit differential pair and the high-speed RF switch unit include: In high-speed mode, when the FPGA chip sends multiple sets of data to the TCON IC unit, the FPGA chip is switched to transmit mode, and the multiple sets of data are sent to the TCON IC unit through the transmit differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

9. The method for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 1, wherein, When the FPGA chip sends data to the TCON IC unit, the steps of switching the FPGA chip to transmit mode and transmitting the data to the TCON IC unit through the FPGA chip's transmit differential pair and the high-speed RF switch unit include: In low-speed mode, when the FPGA chip sends multiple sets of data to the TCON IC unit, the FPGA chip is switched to transmit mode, and the first set of data in the multiple sets of data is sent to the TCON IC unit through the transmit differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

10. A system for implementing low-speed mode readback of MIPID-PHY based on FPGA, wherein, The system includes: an FPGA chip, a high-speed radio frequency switching unit, and a TCON IC unit; The FPGA chip is used to switch to transmission mode when sending data to the TCON IC unit, and send the data to the TCON IC unit by transmitting differential pairs and the high-speed radio frequency switching unit; The FPGA chip is used to switch to receiving mode in low-speed mode when reading back target data from the TCON IC unit; The high-speed radio frequency switch unit is used to switch the data channel to a dedicated receiving path from the TCON IC unit to the FPGA chip. The dedicated receiving path is the signal transmission path formed after the high-speed radio frequency switch unit switches the current contact to the target contact when the FPGA chip outputs a low level. The TCON IC unit is used to send the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes the readback operation.

11. The system for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 10, wherein, The FPGA chip is equipped with transmit differential pairs and receive differential pairs. The transmit differential pairs are used for data transmission in high-speed mode and low-speed mode, and the receive differential pairs are used for data reception in low-speed mode.

12. The system for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 10, wherein, The high-speed radio frequency switch unit is equipped with one CLK differential pair and four Data differential pairs.

13. The system for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 10, wherein, The high-speed radio frequency switch unit is integrated between the FPGA chip and the TCON IC unit.

14. The system for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 10, wherein, The TCON IC unit supports data reception in high-speed mode and data transmission or reception in low-speed mode.

15. The system for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 10, wherein, The system further includes a first processing unit, which is used to enable the transmit differential pair of the FPGA chip and disable the receive differential pair of the FPGA chip.

16. The system for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 10, wherein, The system further includes a second processing unit, which is used to enable the receive differential pair of the FPGA chip and enable the transmit differential pair of the FPGA chip.

17. The system for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 10, wherein, In high-speed mode, when the FPGA chip sends multiple sets of data to the TCON IC unit, the FPGA chip is switched to transmit mode, and the multiple sets of data are sent to the TCON IC unit through the transmit differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

18. The system for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 10, wherein, In low-speed mode, when the FPGA chip sends multiple sets of data to the TCON IC unit, the FPGA chip is switched to transmit mode, and the first set of data in the multiple sets of data is sent to the TCON IC unit through the transmit differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

19. A device for implementing low-speed mode readback of MIPID-PHY based on FPGA, wherein: A system for implementing MIPID-PHY low-speed mode readback based on FPGA and a platform for placing the system for implementing MIPID-PHY low-speed mode readback based on FPGA. The system for implementing MIPID-PHY low-speed mode readback based on FPGA includes: an FPGA chip, a high-speed RF switch unit, and a TCON IC unit. The FPGA chip is used to switch to transmission mode when sending data to the TCON IC unit, and send the data to the TCON IC unit by transmitting differential pairs and the high-speed radio frequency switching unit; The FPGA chip is used to switch to receiving mode in low-speed mode when reading back target data from the TCON IC unit; The high-speed radio frequency switch is used to switch the data channel to a dedicated receiving path from the TCON IC unit to the FPGA chip. The dedicated receiving path is the signal transmission path formed after the high-speed radio frequency switch unit switches the current contact to the target contact when the FPGA chip outputs a low level. The TCON IC unit is used to send the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes the readback operation.

20. The apparatus for implementing low-speed mode readback of MIPID-PHY based on FPGA according to claim 19, wherein, The FPGA chip is equipped with transmit differential pairs and receive differential pairs. The transmit differential pairs are used for data transmission in high-speed mode and low-speed mode, and the receive differential pairs are used for data reception in low-speed mode.

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