High-speed serial interface and data transmission method therefor, and electronic device
By designing the transmit and receive ports of a high-speed serial interface, and combining it with arbitration, processing, and buffering modules, the problem of latency uncertainty in the DigRF v4 protocol was solved, achieving deterministic latency and low-cost data transmission, which is suitable for 5G communication environments.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SANECHIPS TECH CO LTD
- Filing Date
- 2025-11-04
- Publication Date
- 2026-06-18
AI Technical Summary
The existing high-speed serial interface of the DigRF v4 protocol has latency uncertainty issues in the context of 5G communication, which cannot meet the increasingly demanding latency requirements.
A high-speed serial interface is provided, including a transmit port and a receive port. Through an arbitration module, a processing module, and a buffer module, deterministic delay data transmission is achieved, ensuring that service data of different standards are transmitted according to the true sampling rate, thereby reducing chip cost and power consumption.
It achieves deterministic latency data transmission, reduces chip costs, improves transmission speed and control precision, and avoids bandwidth waste and increased power consumption.
Smart Images
Figure CN2025132287_18062026_PF_FP_ABST
Abstract
Description
High-speed serial interfaces and their data transmission methods, electronic devices
[0001] Cross-reference to related applications
[0002] This application claims priority to Chinese Patent Application No. 202411830001.9, filed on December 12, 2024, entitled "High-speed serial interface and data transmission method thereof, electronic device", the entire contents of which are incorporated herein by reference. Technical Field
[0003] This application relates to the field of communication technology, and in particular to high-speed serial interfaces and their data transmission methods and electronic devices. Background Technology
[0004] The DigRF v4 protocol provides a frame-based transmission protocol, but it is described based on the LTE (Long Term Evolution) product form. LTE has low latency requirements, but with the rapid evolution of communication protocols to 5G (5th Generation Mobile Communication Technology), latency requirements are becoming increasingly stringent. However, the DigRF v4 protocol does not have deterministic latency-related descriptions, resulting in latency uncertainty issues for high-speed serial interfaces using the DigRF v4 protocol. Summary of the Invention
[0005] The main objective of this application is to provide a high-speed serial interface and its data transmission method and electronic device, which aims to at least solve the problem of delay uncertainty in high-speed serial interfaces.
[0006] To achieve the above objectives, this application provides a high-speed serial interface, comprising: a transmitting port, which includes a request input module, an arbitration module, and a first processing module connected in sequence; the request input module is used to receive frame transmission requests; the arbitration module is used to respond to the frame transmission requests; the first processing module is used to encrypt the frame transmission requests, obtain transmission data, and output the transmission data; and a receiving port, which includes a second processing module and a buffer module connected in sequence; the second processing module is connected to the first processing module, and is used to receive the transmission data, decrypt the transmission data to obtain the frame transmission requests, and transmit the frame transmission requests to the buffer module; the buffer module is used to temporarily store the frame transmission requests according to a deterministic delay.
[0007] Furthermore, to achieve the above objectives, embodiments of this application also provide a data transmission method for a high-speed serial interface, the method comprising: receiving a frame transmission request through the transmitting port, responding to the frame transmission request, encrypting the frame transmission request to obtain transmission data; receiving the transmission data through the receiving port, decrypting the transmission data to obtain the frame transmission request, and temporarily storing the frame transmission request according to a deterministic delay.
[0008] In addition, to achieve the above objectives, this application also provides an electronic device, which includes: a high-speed serial interface as described above; or, a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the data transmission method of the high-speed serial interface as described above. Attached Figure Description
[0009] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0010] Figure 1 is a schematic diagram of a high-speed serial interface provided in an embodiment of this application;
[0011] Figure 2 is a schematic diagram of an application example of a high-speed serial interface provided in an embodiment of this application;
[0012] Figure 3 is a schematic diagram of the structure of an 8-bit message header of a frame request related to a high-speed serial interface provided in an embodiment of this application;
[0013] Figure 4 is a schematic diagram of a phase relationship before and after business data transmission according to an embodiment of this application;
[0014] Figure 5 is a schematic diagram of another phase relationship before and after business data transmission provided in an embodiment of this application;
[0015] Figure 6 is a schematic diagram of another phase relationship before and after business data transmission provided in an embodiment of this application;
[0016] Figure 7 is a schematic diagram of another high-speed serial interface provided in an embodiment of this application;
[0017] Figure 8 is a schematic diagram of another high-speed serial interface provided in an embodiment of this application;
[0018] Figure 9 is a flowchart illustrating a data transmission method for a high-speed serial interface according to an embodiment of this application;
[0019] Figure 10 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.
[0020] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.
[0021] The following are the diagram labels: 10. Sending port; 11. Request input module; 12. Arbitration module; 13. First processing module; 20. Receiving port; 21. Second processing module; 22. Buffer module; 14. First timing module; 23. Second timing module. Detailed Implementation
[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.
[0023] In related technologies, high-speed interface protocols are broadly divided into two categories: streaming protocols, such as CPRI, Aurora, and J204; and frame protocols, such as the DigRF series. Streaming protocols have been iterating, with increasingly higher line rates and more supported features. For example, J204B supports deterministic latency. However, streaming protocols also have their own drawbacks: first, they do not support low-power features. Given the increasingly demanding power requirements across various product forms, the adoption of power-saving high-speed interface designs for terminal chips is particularly important; second, in multi-standard concurrent scenarios, a framer must use the same sampling rate, leading to oversampling of low-sampling-rate data and wasted bandwidth; and third, CPRI, Aurora, and J204 do not support shared bandwidth between standard service data and control port messages. The DigRF v4 protocol provides a frame-based transmission protocol, but it is described based on the LTE product form. LTE has low latency requirements, but with the rapid evolution of communication protocols to 5G, latency requirements are becoming increasingly stringent. However, the DigRF v4 protocol does not have deterministic latency-related descriptions, resulting in latency uncertainty issues for high-speed serial interfaces using the DigRF v4 protocol.
[0024] Based on this, embodiments of this application provide a high-speed serial interface and its data transmission method and electronic device. For various service standards, this high-speed serial interface can ensure that service data and control ports share bandwidth for transmission. By sharing the high-speed serial differential interface with the control port, low-speed interface devices can be saved, reducing the number of chip IO (input / output) pins and lowering chip costs. The high-speed serial differential interface has a large bandwidth, enabling fast transmission of multiple control port messages with low latency and more precise control. Service data of different standards are transmitted according to their true sampling rate, avoiding bandwidth waste due to oversampling of low sampling rate data. For increasingly stringent latency requirements in high-level scenarios, embodiments of this application can meet the requirements of low latency and deterministic latency based on this high-speed serial interface.
[0025] The high-speed serial interface and its data transmission method and electronic device provided in the embodiments of this application at least solve the problem of delay uncertainty in high-speed serial interfaces in related technologies. The following embodiments illustrate this, first describing the high-speed serial interface in the embodiments of this application.
[0026] This application provides a high-speed serial interface. Referring to Figure 1, which is a schematic diagram of the structure of a high-speed serial interface according to an embodiment of this application, the high-speed serial interface includes: a transmitting port 10, which includes a request input module 11, an arbitration module 12, and a first processing module 13 connected in sequence; the request input module 11 is used to receive frame transmission requests; the arbitration module 12 is used to respond to frame transmission requests; the first processing module 13 is used to encrypt the frame transmission requests, obtain transmission data, and output the transmission data; and a receiving port 20, which includes a second processing module 21 and a buffer module 22 connected in sequence; the second processing module 21 is connected to the first processing module 13, and is used to receive transmission data, decrypt the transmission data to obtain frame transmission requests, and transmit the frame transmission requests to the buffer module 22; the buffer module 22 is used to temporarily store the frame transmission requests according to a deterministic delay.
[0027] The high-speed serial interface provided in this embodiment can be used in mobile terminal products. For example, radio frequency chips and terminal chips can use this interface to perform uplink and downlink data interaction. This interface can also be applied to baseband processing units or active antenna processing units. Taking the baseband processing unit as an example, two boards can perform cell data scheduling processing through the high-speed serial interface provided in this embodiment.
[0028] The high-speed serial interface includes: a transmitting port, which includes a request input module, an arbitration module, and a first processing module connected in sequence; the request input module is used to receive frame transmission requests; the arbitration module is used to respond to frame transmission requests; the first processing module is used to encrypt the frame transmission requests, obtain transmission data, and output the transmission data; and a receiving port, which includes a second processing module and a buffer module connected in sequence; the second processing module is connected to the first processing module, and is used to receive transmission data, decrypt the transmission data to obtain frame transmission requests, and transmit the frame transmission requests to the buffer module; the buffer module is used to temporarily store frame transmission requests according to a deterministic delay. This embodiment of the application configures a deterministic delay for the buffer module, enabling the high-speed serial interface to meet the deterministic delay requirements in certain scenarios.
[0029] In this embodiment, the input of the transmitting port 10 is connected to a forward external circuit or device capable of generating a frame transmission request, and the output of the receiving port 20 is connected to a backward external circuit or device that needs to receive the information carried by the frame transmission request.
[0030] As an example, referring to Figure 2, the transmit port 10 can be implemented using a BBIC (baseband integrated circuit), and the receive port 20 can be implemented using an RFIC (radio frequency front-end integrated circuit).
[0031] In this embodiment, the request input module 11 may include a data frame request input unit, a control frame request input unit, and a retransmission frame request input unit, enabling the control port to share high-speed differential bandwidth with service data without the need to open an additional low-speed interface, thus taking into account the advantages of fast transmission speed, low latency, precise control, and cost savings; similarly, the frame transmission request may be one or more of the data frame request, control frame request, and / or retransmission frame request from outside the high-speed serial interface.
[0032] As an example, in this embodiment, the request input module 11 may also include multiple data logic channels, each of which is independent of each other and has a different sampling rate (for example, each sampling rate is divided into 7 levels, or other numbers of levels, which are not limited in this embodiment). In this way, when multiple service data are transmitted concurrently, they can be transmitted according to the actual sampling rate without oversampling small sample data. On the one hand, this can save bandwidth, reduce chip area and size, thereby reducing costs. On the other hand, it can also avoid transmitting redundant data and reduce chip power consumption.
[0033] As an example, data frames and control frames can be distinguished by an 8-bit header, the meaning of each bit of which is shown in Figure 3.
[0034] Furthermore, in this embodiment, the arbitration module 12 may include an arbitrator. Since the high-speed serial interface provided in this embodiment is serially transmitted, the arbitration module 12 will only respond to one of the data frame request, control frame request, and / or retransmission frame request at the same time. Different types of frame requests cannot be responded to simultaneously. The response order can be determined according to the access timing of the frame transmission request. This embodiment does not impose any restrictions on this.
[0035] In this embodiment, the first processing module 13 may include a processor and any electronic device with encryption function, and the second processing module 21 may include a processor and any electronic device with decryption function. The processor in the first processing module 13 and the processor in the second processing module 21 are independent of each other.
[0036] As an example, in this embodiment, the process of encrypting the frame transmission request by the first processing module 13 may include framing, encoding, and parallel-to-serial conversion. That is, after the frame transmission request is processed by the first processing module 13 through framing, encoding, and parallel-to-serial conversion, the transmission data carrying the frame transmission request can be obtained. After receiving the transmission data from the sending port 10, the process of decrypting the transmission data by the second processing module 21 may include serial-to-parallel conversion, decoding, and deframing. That is, after the transmission data is processed by the second processing module 21 through serial-to-parallel conversion, decoding, and deframing, the frame transmission request can be restored to avoid leakage during data transmission.
[0037] As an example, to further understand the technical effects achievable by this embodiment, this embodiment uses NR2CC (New Radio; Carrier Aggregation) as an example, and refers to the three phase relationship diagrams shown in Figures 4, 5, and 6 to illustrate DigRF in related technologies. The v4 protocol suffers from latency uncertainty: As shown in Figure 4, the initial phase relationship of services a and b is basically the same. Both services need to be transmitted simultaneously. Since the RF interface transmits serially, the arbitrator responds to service a first, then service b. After the service data arrives at the RF chip, the phase difference between the two service data is t1. As can be seen from Figure 4, the phase relationship changes after the service data passes through the RF interface. As shown in Figure 5, the initial phase of services a and b is t. Since the RF interface transmits serially, the arbitrator responds to service a first, then service b. After service b collects one frame of data, service a has not yet finished transmitting. After the service data arrives at the RF chip, the phase difference between the two service data is still t1. As shown in Figure 6, the initial phase of services a and b is t'. Since the RF interface transmits serially, the arbitrator responds to service a first, then service b. After service b collects one frame of data, service a has finished transmitting and will immediately respond to service b. After the service data arrives at the RF chip, the phase difference between the two service data is still t'. As can be seen from Figures 4, 5, and 6, due to DigRF... The v4 protocol uses shared bandwidth and can only respond to one type of service data request at a time. Different arbitrator response orders can lead to differences in group latency.
[0038] In this embodiment, the cache module 22 may include a buffer (buffer register). In order to meet the requirements of deterministic latency, by configuring deterministic latency at the cache module 22, the cache module 22 can temporarily store the frame transmission request and allow the external device connected to the receiving port 20 to read the frame transmission request only after the deterministic latency is reached. This ensures that different service data will no longer have different group delays due to different response orders of the arbitrator.
[0039] Considering that the sources of latency jitter are mainly from the following aspects: 1) Different order in which the arbitrator responds to multiple requests will lead to differences in group latency; 2) Asynchronous cross-clock paths between different blocks will cause latency jitter; 3) Differences in board-level trace latency will also lead to differences in group latency.
[0040] Therefore, this embodiment proposes the following implementation methods for configuring deterministic latency.
[0041] In some feasible embodiments, the first processing module 13 is further configured to record the difference value of the response frame transmission request of the arbitration module 12 and integrate the difference value into the transmission data; the second processing module 21 is further configured to extract the difference value from the transmission data and adjust the actual cache value of the cache module 22 according to the difference value, wherein the difference value is negatively correlated with the actual cache value, and the deterministic delay is determined according to the difference value and the actual cache value.
[0042] In this embodiment, the problem of different group delays caused by different order of arbitrator responses to multiple requests is overcome by compensating the receiving port 20.
[0043] In this embodiment, after the service data is sent to the arbitration module 12 via the request input module 11, the arbitrator starts to respond to the request. At this time, the first processing module 13 can record the difference value of the arbitrator's response and transmit the difference value to the cache module 22 via the second processing module 21 through a control message. This allows the cache module 22 to adjust its actual cache value according to the difference value, so that there is no longer a group delay difference after different service data arrive at the receiving port 20.
[0044] As an example, the negative correlation between the difference value and the actual cache value means that the larger the difference value, the smaller the actual cache value; and the smaller the difference value, the larger the actual cache value. The cache module 22 can use its own maximum cache value as a reference for deterministic latency, ensuring that the sum of the difference value and the actual cache value is always the maximum cache value, thereby achieving the purpose of configuring deterministic latency.
[0045] In some feasible embodiments, referring to FIG7, the transmitting port 10 further includes a first timing module 14, which is connected to the request input module 11. The first timing module 14 is used to control the request input module 11 to access the frame transmission request at a first moment. The receiving port 20 further includes a second timing module 23, which is connected to the buffer module 22. The second timing module 23 is used to control the buffer module 22 to output the frame transmission request at a second moment. The deterministic delay is determined based on the difference between the second moment and the first moment.
[0046] In this embodiment, by adding a first timing module 14 to the transmitting port 10 to achieve timed transmission and adding a second timing module 23 to the receiving port 20 to achieve timed reception, the problem of delay jitter that occurs between different blocks in asynchronous cross-clock paths is overcome.
[0047] In this embodiment, the timing of service data transmission is determined by the first timing module 14. Under the control of the first timing module 14, assuming that the sending port 10 starts service data transmission at time t1, the service data passes through the arbitrator, and then through the first processing module 13 for framing, encoding, and parallel-to-serial conversion before reaching the receiving port 20. The receiving port 20 performs serial-to-parallel conversion, decoding, and deframing through the second processing module 21. Under the control of the second timing module 23, the service data is read from the buffer module 22 at time t1+T. Then, T can be regarded as the value of deterministic delay.
[0048] As an example, the first timing module 14 and the second timing module 23 can be any type of timer, as long as they can meet the timing control logic of this embodiment. This embodiment does not impose any restrictions on them.
[0049] In some feasible embodiments, referring to FIG8, the first timing module 14 and the second timing module 23 are connected. The first timing module 14 or the second timing module 23 is used to output a synchronization pulse so that the first timing module 14 and the second timing module 23 synchronize the time reference based on the synchronization pulse.
[0050] In this embodiment, the problem of group delay differences caused by board-level trace delay differences is overcome by connecting the first timing module 14 and the second timing module 23 to synchronize the time base.
[0051] In this embodiment, the first timing module 14 and the second timing module 23 can be connected by hardware pins. Either of the two timing modules can be used as a synchronization pulse output terminal to achieve synchronization control. That is, when synchronization is required, a pulse or periodic pulse is output by the first timing module 14 or the second timing module 23, so that the two timing modules are aligned to a time reference under the control of the pulse, thereby performing high-precision time delay control.
[0052] This embodiment provides a high-speed serial interface that can meet the requirements of deterministic latency by recording delay jitter values, setting timed transmission at the transmitting port, timed reading at the receiving port, and synchronizing timers at the transmitting and receiving ports. Simultaneously, it ensures that service data and control ports share bandwidth for transmission. By sharing the high-speed serial differential interface with the control port, low-speed interface devices can be saved, reducing the number of chip I / O (input / output) pins and lowering chip costs. Due to the large bandwidth of the high-speed serial differential interface, multiple control port messages can be transmitted quickly with low latency, resulting in more precise control. Service data of different standards are transmitted according to their true sampling rate, preventing bandwidth waste caused by oversampling of low-sampling-rate data.
[0053] In addition, this application embodiment also provides a data transmission method for a high-speed serial interface, applied to the high-speed serial interface provided in the above embodiment. Referring to FIG9, the data transmission method includes steps S10 and S20.
[0054] Step S10: By sending a frame transmission request through the port, responding to the frame transmission request, encrypting the frame transmission request, and obtaining the transmission data.
[0055] Step S20: Receive transmission data through the receiving port, decrypt the transmission data to obtain a frame transmission request, and temporarily store the frame transmission request according to the deterministic delay.
[0056] In some feasible embodiments, the data transmission method may further include: recording the difference value of the arbitration module's response frame transmission request through a first processing module and integrating the difference value into the transmission data; extracting the difference value from the transmission data through a second processing module and adjusting the actual cache value of the cache module according to the difference value, wherein the difference value is negatively correlated with the actual cache value, and the deterministic delay is determined based on the difference value and the actual cache value.
[0057] In some feasible embodiments, the data transmission method may further include: controlling the request input module to access the frame transmission request at a first moment through the first timing module; controlling the buffer module to output the frame transmission request at a second moment through the second timing module, wherein the deterministic delay is determined based on the difference between the second moment and the first moment.
[0058] In some feasible embodiments, the data transmission method may further include: outputting a synchronization pulse through a first timing module or a second timing module, so that the first timing module and the second timing module synchronize their time references based on the synchronization pulse.
[0059] The data transmission method of the high-speed serial interface proposed in this embodiment belongs to the same technical concept as the high-speed serial interface proposed in the above embodiments. Technical details not described in detail in this embodiment can be found in any of the above embodiments. Furthermore, this embodiment has the same beneficial effects as the above embodiments of the high-speed serial interface.
[0060] Furthermore, this application also provides an electronic device, which includes: the high-speed serial interface provided in the above embodiments; or, a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the data transmission method of the high-speed serial interface provided in the above embodiments.
[0061] Referring to Figure 10, which is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application, the electronic device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to realize communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as a disk storage device. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.
[0062] Those skilled in the art will understand that the structure shown in FIG10 does not constitute a limitation on the electronic device, and may include more or fewer components than shown, or combine certain components, or have different component arrangements. As shown in FIG10, the memory 1005, as a storage medium, may include an operating system, a data storage module, a network communication module, a user interface module, and computer programs.
[0063] In the electronic device shown in Figure 10, the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in this embodiment can be set in the electronic device. The electronic device calls the computer program stored in the memory 1005 through the processor 1001 and executes the data transmission method of the high-speed serial interface provided in any of the above embodiments.
[0064] The electronic device proposed in this embodiment belongs to the same technical concept as the high-speed serial interface and its data transmission method proposed in the above embodiments. Technical details not described in detail in this embodiment can be found in any of the above embodiments. Furthermore, this embodiment has the same beneficial effects as the above embodiments of the high-speed serial interface.
[0065] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.
[0066] Furthermore, in the embodiments of this application, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly defined. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B.
[0067] In the embodiments of this application, unless otherwise expressly specified and limited, the terms "connection" and "fixed" should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the meaning of the above terms in the embodiments of this application according to the circumstances.
[0068] It should also be understood that references to "one embodiment" or "some embodiments" in the specification of embodiments of this application mean that one or more embodiments of this application include the specific features, structures, or characteristics described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.
[0069] It should be noted that the technical solutions of the various embodiments of this application can be combined with each other, but only if they are implemented by those skilled in the art. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the embodiments of this application.
[0070] The above are merely optional embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A high-speed serial interface, the high-speed serial interface comprising: A sending port, comprising a request input module, an arbitration module, and a first processing module connected in sequence; The request input module is used to receive frame transmission requests; The arbitration module is used to respond to the frame transmission request; The first processing module is used to encrypt the frame transmission request, obtain transmission data, and output the transmission data; The receiving port includes a second processing module and a cache module connected in sequence; the second processing module is connected to the first processing module, and the second processing module is used to receive the transmitted data, decrypt the transmitted data to obtain the frame transmission request, and transmit the frame transmission request to the cache module; the cache module is used to temporarily store the frame transmission request according to a deterministic delay.
2. The high-speed serial interface as described in claim 1, wherein, The first processing module is further configured to record the difference value in the arbitration module's response to the frame transmission request, and integrate the difference value into the transmission data; The second processing module is further configured to extract the difference value from the transmitted data and adjust the actual cache value of the cache module according to the difference value, wherein the difference value is negatively correlated with the actual cache value, and the deterministic delay is determined according to the difference value and the actual cache value.
3. The high-speed serial interface as described in claim 1, wherein, The sending port further includes a first timing module, which is connected to the request input module. The first timing module is used to control the request input module to access the frame transmission request at a first moment. The receiving port further includes a second timing module, which is connected to the buffer module. The second timing module is used to control the buffer module to output the frame transmission request at a second time. The deterministic delay is determined based on the difference between the second time and the first time.
4. The high-speed serial interface as described in claim 3, wherein, The first timing module and the second timing module are connected. The first timing module or the second timing module is used to output a synchronization pulse so that the first timing module and the second timing module can synchronize their time references based on the synchronization pulse.
5. The high-speed serial interface as described in claim 1, wherein, The request input module includes multiple data logic channels, each of which is independent of the others and has a different sampling rate.
6. The high-speed serial interface as described in claim 1, wherein, The frame transmission request includes at least one data frame request, control frame request, and / or retransmission frame request.
7. The high-speed serial interface as described in claim 6, wherein, The arbitration module responds to only one of the data frame request, control frame request, and / or retransmission frame request at any given time.
8. The high-speed serial interface as described in claim 1, wherein, The first processing module encrypts the frame transmission request by framing, encoding, and parallel-to-serial conversion. The second processing module's decryption process for the transmitted data includes serial-to-parallel conversion, decoding, and frame de-framing.
9. A data transmission method for a high-speed serial interface, the method being applied to a high-speed serial interface as described in any one of claims 1 to 8, comprising: The system receives a frame transmission request through the sending port, responds to the frame transmission request, encrypts the frame transmission request, and obtains the transmission data. The transmission data is received through the receiving port, the transmission data is decrypted to obtain the frame transmission request, and the frame transmission request is temporarily stored according to the deterministic delay.
10. An electronic device, the electronic device comprising: High-speed serial interface as described in any one of claims 1 to 8; Alternatively, a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the data transmission method of the high-speed serial interface as described in claim 9.