Integrated packaging module with power semiconductor embedded into copper-clad high-thermal-conductivity insulating material

Abstract

An integrated packaging module with a power semiconductor embedded into a copper-clad high-thermal-conductivity insulating material. The integrated packaging module comprises an insulating substrate (10), wherein a chip (11) and a high-thermal-conductivity insulating layer (12) are embedded into the insulating substrate; the top surface of the insulating substrate is provided with a second copper-clad circuit (13) and a conductive via hole (15) electrically connected to the second copper-clad circuit; the top surface of the high-thermal-conductivity insulating layer is provided with a first copper-clad circuit (14), the conductive via hole is electrically connected to the first copper-clad circuit and the chip, and the bottom surface of the high-thermal-conductivity insulating layer is in contact connection with the top surface of a heat dissipation copper block (16). Since the chip and the high-thermal-conductivity insulating layer are embedded into the insulating substrate, the size of the high-thermal-conductivity insulating layer is reduced, and thermal stress is greatly reduced compared with that in the prior art, thereby mitigating copper trace cracking of PCBs in high-heat-generation environments.

Description

Integrated package module with power semiconductors embedded in copper-clad high thermal conductivity insulating material Technical Field

[0001] This invention relates to the field of printed circuit board technology, and more particularly to an integrated packaging module for power semiconductors embedded in copper-clad high thermal conductivity insulating materials. Background Technology

[0002] Ceramic-based packaging substrates offer excellent performance. When ceramic is used as a packaging substrate material, its surface must be copper-clad. The type of ceramic substrate and the stability of the bond between the substrate and the copper layer are closely related to the stability of power electronic devices during operation. However, in existing technologies, for large-sized thermally conductive ceramic plates welded onto a single heat-dissipating copper plate, or for a single heat-dissipating copper plate welded with a single thermally conductive ceramic plate of the same size, the mismatch between the coefficient of thermal expansion (CTE) of ceramic and the coefficient of thermal expansion (CET) of copper causes stress that leads to cracking of the ceramic plate or copper foil, resulting in product safety hazards.

[0003] In existing technologies, the large size of ceramic plates and the high cost of welding them to heat dissipation metal components result in a high overall cost for power device packaging heat dissipation modules.

[0004] In existing technologies, chips are attached to the surface of a ceramic substrate and then interconnected through bonding. This process leads to problems such as high connection resistance, high parasitic inductance, and high switching losses in power devices.

[0005] Therefore, improving the safety of power device packaging, saving costs, and ensuring the stability of electronic devices have become urgent technical problems to be solved. Summary of the Invention

[0006] This invention provides an integrated packaging module for power semiconductors embedded with copper-clad high thermal conductivity insulating material. It addresses the above-mentioned problems by preventing cracking of the ceramic substrate and the heat dissipation copper block, improving the stability of power devices, and significantly reducing costs.

[0007] The present invention adopts the following technical solution:

[0008] This invention provides an integrated packaging module for power semiconductors with embedded copper-clad high thermal conductivity insulating material, including an insulating substrate, with a plurality of high thermal conductivity insulating layers embedded inside the insulating substrate, and a first copper-clad circuit disposed on the top surface of the high thermal conductivity insulating layer; the top surface of the high thermal conductivity insulating layer contacts the first copper-clad circuit located below the chip, and the bottom surface of the high thermal conductivity insulating layer contacts and connects to the top surface of a heat dissipation copper block.

[0009] In this solution, firstly, because the thermal stress of the ceramic plate and the thermal stress of the heat dissipation copper plate are mismatched in the existing technology, after high temperature, the heat dissipation copper plate may bend or the ceramic plate may crack (or the copper foil may peel off), leading to product failure. The larger the size of the ceramic plate and the larger the size ratio of the ceramic plate to the heat dissipation copper plate, the greater the probability of the above situation occurring. Therefore, by miniaturizing the high thermal conductivity insulation layer, the stress caused by the mismatch between the thermal expansion coefficient CTE of the high thermal conductivity insulation layer and the expansion coefficient CET of the copper circuit on it will be significantly reduced compared with the existing technology, thereby reducing the cracking of the ceramic plate in the high heat generation environment of the power module and improving product safety.

[0010] Miniaturization of the high thermal conductivity insulation layer can also significantly reduce ceramic procurement costs.

[0011] The high thermal conductivity insulation layer and the heat dissipation copper block are integrated. The heat dissipation copper block itself can be used as a heat sink, or other heat dissipation devices can be connected to the heat dissipation copper block and extend out of the package for further heat dissipation.

[0012] With the miniaturization of the high thermal conductivity insulation layer, the amount of solder used is greatly reduced, further reducing solder usage costs.

[0013] As an improvement to the above solution, the chip is embedded inside an insulating substrate. The top surface of the insulating substrate is a second copper-clad circuit and a via electrically connected to the second copper-clad circuit. The via is electrically connected to the first copper-clad circuit and the chip. In this solution, the chip is embedded inside the insulating substrate, and the shielding space enclosed by the second copper-clad circuit and the heat dissipation copper block shields the chip from electromagnetic radiation from other electronic devices.

[0014] As an improvement to the above solution, the chip is electrically connected to the second copper-clad circuit via micro-via copper plating. In this solution, compared to existing technologies where chips are placed on the top surface of an insulating substrate and use bonding wires to connect chip electrodes and pins to the circuit's copper foil, this solution uses micro-via copper plating to connect the chip embedded in the insulating substrate, replacing traditional bonding wires. This simplifies the connection space, significantly reduces parasitic inductance, and enables ground inductance interconnection. In existing power device packaging modules, the chip is still designed on the top surface of the PCB board, typically requiring multiple ceramic plates to be spliced ​​together and interconnected via bonded aluminum wires. This process is costly and introduces problems such as high connection resistance, high parasitic inductance, and high switching losses in power devices. In this solution, the chip electrodes are connected to the second copper-clad circuit on the front side of the high thermal conductivity insulating layer via micro-via copper plating, eliminating the need for bonding aluminum wires, reducing costs, and simultaneously mitigating problems such as high connection resistance, high parasitic inductance, and high switching losses in power devices. Furthermore, in existing technologies, the circuitry is all on ceramic. Due to the fragile nature of ceramic, multiple ceramic pieces need to be connected into a whole by bonding wires. This process limits the layout design of the circuitry. In this solution, the first and second copper-clad circuits can be etched from a single piece of copper foil. Only the chip electrodes are laser-drilled, and copper is plated inside the holes to connect with the second copper-clad circuit on the front side. The first copper-clad circuit is connected to the second copper-clad circuit through a via. Engineers are not limited in the wiring range when designing products, and the use of bonding wires is greatly reduced, which can reduce parasitic inductance.

[0015] As an improvement to the above solution, an inner layer of copper foil circuitry is provided inside the insulating substrate. This inner layer of copper foil circuitry can be electrically connected to the second copper-clad circuitry, and / or the inner layer of copper foil circuitry can be electrically connected to the first copper-clad circuitry through vias. In this solution, the inner layer of copper foil circuitry is provided inside the insulating substrate, which improves the flexibility of PCB circuit design and wiring, and provides a foundation for realizing multilayer board circuits.

[0016] As an improvement to the above solution, electronic components are disposed on the top surface of the insulating substrate, which are electrically connected to the second copper-clad circuit. In this solution, apart from the high-heat-generating chip and electronic components, other components are disposed on the top surface of the insulating substrate. The chip is embedded in the PCB and is not on the same plane as other electronic components, thus shielding against interference. This solves the problems of large parasitic inductance and high switching losses in current controller signals, and enables high-density integration and performance improvement of the electric drive controller.

[0017] Preferably, the size of the high thermal conductivity insulating layer is adapted to the size of each chip. In this solution, a high thermal conductivity insulating layer with a size adapted to the chip size is provided under each chip, thus taking into account both thermal conductivity and insulation functions.

[0018] Preferably, the top surface of the heat dissipation copper block covers the entire bottom surface of the insulating substrate on which it is located. In this solution, the heat dissipation copper block completely covers the bottom surface of the insulating substrate, which improves the heat dissipation effect and provides better electromagnetic shielding for the chip and its processed signals.

[0019] Optionally, the high thermal conductivity insulating layer is made of ceramic, gallium nitride, diamond, or an insulating copper substrate.

[0020] Preferably, the high thermal conductivity insulating layer is a ceramic plate, and the material of the ceramic plate is aluminum nitride.

[0021] Optionally, the heat dissipation copper block is embedded inside the insulating substrate, with the bottom of the heat dissipation copper block exposed on the bottom surface of the insulating substrate. In this solution, targeted and independent heat dissipation is achieved for specific high-heat-generating chip modules, eliminating the need to cover the entire PCB board with the heat dissipation copper block, thus further saving costs.

[0022] Preferably, the dimensions of the heat-dissipating copper block are adapted to the planar dimensions of the length and width of the high thermal conductivity insulation layer. Attached Figure Description

[0023] Figure 1 is a schematic diagram of the PCB cross-sectional structure of an integrated packaging module for power semiconductors embedded with copper-clad high thermal conductivity insulating material according to Embodiment 1 of the present invention.

[0024] Figure 2 is a schematic diagram of the PCB cross-sectional structure of an integrated packaging module for power semiconductors embedded with copper-clad high thermal conductivity insulating material according to Embodiment 2 of the present invention. Detailed Implementation

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0026] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] Referring to Figure 1, it is a schematic diagram of the PCB cross-sectional structure of an integrated packaging module for power semiconductors embedded with copper-clad high thermal conductivity insulating material according to Embodiment 1 of the present invention. The packaging module includes an FR4 epoxy fiberglass cloth substrate (hereinafter referred to as FR4 substrate) 10, with a chip 11 and a ceramic plate 12 embedded inside the FR4 substrate 10; the top surface of the FR4 substrate is a second copper-clad line 13, and a through-hole 15 electrically connected to the second copper-clad line 13.

[0028] A first copper-clad line 14 is provided on the top surface of the ceramic plate 12. The first copper-clad line 14 and the chip 11 are connected through the through-hole 15. The bottom surface of the ceramic plate 12 is in contact with the top surface of a heat sink copper block 16. The top surface of the heat sink copper block is connected to and located on the bottom surface of the FR4 substrate 10.

[0029] Preferably, the size of the ceramic plate 12 is adapted to the size of each chip 11. The miniaturized ceramic plate prevents thermal stress cracking while significantly reducing costs.

[0030] Chip 11 is electrically connected to the first copper-clad trace 14 via micro-via copper plating, reducing costs and mitigating issues such as high connection resistance, high parasitic inductance, and high switching losses in power devices. A heat dissipation copper block 16 covers the entire bottom surface of the FR4 substrate 10. The heat dissipation copper block 16 is soldered to the aluminum heat sink using an explosive bonding method, or it functions as an integrated copper heat sink with the PCB. Electronic components 17 are mounted on the top surface of the FR4 substrate 10, electrically connected to the second copper-clad trace 13. Embedding chip 17 within the PCB, it is not on the same plane as other electronic components, avoiding shielding interference and enabling high-density integration and performance enhancement of the electric drive controller.

[0031] In this embodiment of the invention, since thermal stress is directly proportional to the size of the ceramic plate, the chip 11 and the ceramic plate 12 are embedded inside the FR4 substrate 10. The stress caused by the mismatch between the ceramic's coefficient of thermal expansion (CTE) and the copper's coefficient of thermal expansion (CET) is significantly reduced compared to existing technologies, thereby reducing ceramic plate cracking in high-heat environments. The internal structure of the FR4 substrate 10 further compresses and limits the stress caused by the mismatch between the ceramic's CTE and the copper's CET, further reducing ceramic plate cracking. The miniaturization of the ceramic plate significantly reduces costs while improving the stability of electronic device connections.

[0032] The ceramic substrate 12 can be replaced with a high thermal conductivity insulating layer made of gallium nitride, diamond, or an insulating copper substrate. Depending on the application environment of the integrated packaging module, appropriate amounts of impurity atoms (such as oxygen, silicon, etc.) can be doped into gallium nitride to significantly reduce its carrier concentration, thereby increasing its resistivity. This doping effect gives gallium nitride high insulation performance while also possessing high thermal conductivity. The insulating copper substrate consists of a copper plate wrapped with a thermally conductive insulating layer.

[0033] In this embodiment, the vertical heat dissipation direction is as follows: chip, solder (thermal conductivity approximately 65-180 W / (mk)), first copper-clad circuit 14 (thermal conductivity approximately 398 W / (mk)), ceramic plate 12 aluminum nitride AlN (thermal conductivity approximately 180 W / (mk)), solder (thermal conductivity approximately 65 W / (mk)), and heat dissipation copper block 16 (thermal conductivity approximately 398 W / (mk)). Based on the thermal conductivity of each layer, this embodiment demonstrates better vertical heat conduction compared to existing technologies that rely on thermally conductive silicone grease for heat transfer.

[0034] The FR4 substrate 10 has an inner copper foil circuit 18 inside, which can be electrically connected to the first copper-clad circuit 14, and / or the inner copper foil circuit 18 can be electrically connected to the second copper-clad circuit 13 through the via 15.

[0035] The FR4 substrate 10 has an embedded conductive copper block 19, which is electrically connected to the second copper-clad circuit 13 and the inner copper foil circuit 18 for overcurrent.

[0036] Referring to Figure 2, it is a schematic diagram of the PCB cross-sectional structure of an integrated packaging module for power semiconductors embedded with copper-clad high thermal conductivity insulating material according to Embodiment 2 of the present invention. The packaging module includes an FR4 epoxy fiberglass cloth substrate (hereinafter referred to as FR4 substrate) 20, and a ceramic plate 21 is embedded inside the FR4 substrate 20; a first copper-clad line 22 is provided on the top surface of the ceramic plate 21.

[0037] The first copper-clad line 22 on the top surface of the ceramic plate 21 is electrically connected to the copper-clad line 25 on the top surface of the FR4 substrate. Chip 23 is the main heat-generating device, and preferably, chip 23 is electrically connected to the first copper-clad line 22. The top surface of the ceramic plate 21 contacts the first copper-clad line 22 located below chip 23, and the bottom surface of the ceramic plate 21 contacts and connects to the top surface of a heat-dissipating copper block 24. The top surface of the heat-dissipating copper block 24 is connected to and located on the bottom surface of the FR4 substrate 20. Preferably, the size of the ceramic plate 21 is adapted to the size of each chip 23, resulting in a miniaturized ceramic plate that prevents thermal stress cracking while significantly reducing costs.

[0038] In this embodiment of the invention, since thermal stress is directly proportional to the size of the ceramic plate, the ceramic plate 21 is embedded inside the FR4 substrate 20. The stress caused by the mismatch between the ceramic's coefficient of thermal expansion (CTE) and the copper's coefficient of thermal expansion (CET) is significantly reduced compared to existing technologies, thereby reducing ceramic plate cracking in high-heat environments. The internal structure of the FR4 substrate 20 further compresses and limits the stress caused by the mismatch between the ceramic's CTE and the copper's CET, further reducing ceramic plate cracking. The miniaturization of the ceramic plate significantly reduces costs while improving the stability of electronic device connections.

[0039] The ceramic substrate 21 can be replaced with a high thermal conductivity insulating layer of gallium nitride, diamond, or an insulating copper substrate. Depending on the application environment of the integrated packaging module, an appropriate amount of impurity atoms (such as oxygen, silicon, etc.) can be doped into gallium nitride to significantly reduce its carrier concentration, thereby increasing its resistivity. This doping effect gives gallium nitride high insulation performance while also possessing high thermal conductivity. The insulating copper substrate consists of a copper plate wrapped with a thermally conductive insulating layer.

[0040] Embodiment 3 of this invention provides an integrated packaging module for power semiconductors embedded in copper-clad high thermal conductivity insulating material. Based on Embodiment 1 or 2 above, the difference lies in that the heat-dissipating copper block is embedded inside the insulating substrate, with the bottom of the copper block exposed above the bottom surface of the insulating substrate. The dimensions of the heat-dissipating copper block are adapted to the length and width planar dimensions of the ceramic plate. In this embodiment, targeted independent heat dissipation is achieved for specific high-heat-generating chip modules, eliminating the need to cover the entire PCB board with the heat-dissipating copper block, further saving costs.

[0041] Alternatively, a small number of high-heat-generating chips can be designed onto the same small ceramic plate for centralized heat dissipation. This miniaturized ceramic plate prevents thermal stress cracking while significantly reducing costs.

[0042] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. An integrated packaging module for power semiconductors embedded with copper-clad high thermal conductivity insulating material, comprising an insulating substrate, characterized in that, Several high thermal conductivity insulating layers are embedded inside the insulating substrate. A first copper-clad circuit is provided on the top surface of the high thermal conductivity insulating layer. The top surface of the high thermal conductivity insulating layer contacts the first copper-clad circuit located below the chip, and the bottom surface of the high thermal conductivity insulating layer is in contact with the top surface of a heat dissipation copper block.

2. The integrated packaging module for embedding power semiconductors with copper-clad high thermal conductivity insulating material as described in claim 1, characterized in that, The chip is embedded inside an insulating substrate. The top surface of the insulating substrate is a second copper-clad line and a via electrically connected to the second copper-clad line. The via is electrically connected to the first copper-clad line and the chip.

3. The integrated packaging module for embedding power semiconductors with copper-clad high thermal conductivity insulating material as described in claim 2, characterized in that, The chip is electrically connected to the first copper-clad circuit via copper plating through micro-vias.

4. The integrated packaging module for embedding power semiconductors with copper-clad high thermal conductivity insulating material as described in claim 2, characterized in that, The insulating substrate has an inner copper foil circuit inside, which can be electrically connected to the first copper-clad circuit, and / or the inner copper foil circuit is electrically connected to the first copper-clad circuit through a via.

5. The integrated packaging module for embedding power semiconductors with copper-clad high thermal conductivity insulating material as described in claim 2, characterized in that, Electronic components are disposed on the top surface of the insulating substrate and are electrically connected to the second copper-clad circuit.

6. The integrated packaging module for power semiconductors embedded in copper-clad high thermal conductivity insulating material as described in claim 1 or 2, characterized in that, The dimensions of the high thermal conductivity insulating layer are adapted to the dimensions of each chip.

7. The integrated packaging module for power semiconductors embedded in copper-clad high thermal conductivity insulating material as described in claim 1 or 2, characterized in that, The top surface of the heat dissipation copper block covers the entire bottom surface of the insulating substrate on which it is located.

8. The integrated packaging module for power semiconductors embedded in copper-clad high thermal conductivity insulating material as described in claim 1 or 2, characterized in that, The high thermal conductivity insulating layer is made of ceramic, gallium nitride, diamond, or an insulating copper substrate.

9. The integrated packaging module for power semiconductors embedded in copper-clad high thermal conductivity insulating material as described in claim 1 or 2, characterized in that, The heat dissipation copper block is embedded inside the insulating substrate, and the bottom of the heat dissipation copper block is exposed on the bottom surface of the insulating substrate.

10. The integrated packaging module for power semiconductors embedded in copper-clad high thermal conductivity insulating material as described in claim 1 or 2, characterized in that, The dimensions of the heat dissipation copper block are adapted to the planar dimensions of the length and width of the highly thermally conductive insulation layer.

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