Electronics assembly, inverter, and method for manufacturing an electronics assembly
By embedding power semiconductor devices with sinterable contact surfaces in a circuit carrier using copper-containing sintering paste, the reliability of power electronic arrangements is improved, addressing thermomechanical degradation and environmental exposure.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SCHAEFFLER TECHNOLOGIES AG & CO KG
- Filing Date
- 2025-11-17
- Publication Date
- 2026-06-18
AI Technical Summary
Existing power electronic arrangements in electric vehicles face reliability issues due to exposure to external environmental influences and thermomechanical degradation under thermal fluctuations.
Embedding power semiconductor devices with sinterable contact surfaces in a circuit carrier made of fiber-reinforced plastic or ceramic, using copper-containing sintering paste to create microvias for reliable electrical connections, which are thermomechanically stable and protected from external influences.
Enhances the reliability of power electronic arrangements by providing stable electrical connections that withstand significant thermal fluctuations, enabling the use of high-performance semiconductor devices like SiC MOSFETs.
Smart Images
Figure DE2025101069_18062026_PF_FP_ABST
Abstract
Description
[0001] 202301609
[0002] 1
[0003] Description
[0004] Electronic arrangement, inverter, method for manufacturing an electronic arrangement
[0005] Technical field:
[0006] The present invention relates to an electronic arrangement, in particular a power electronic arrangement, an inverter with said electronic arrangement, in particular a power inverter with said (power) electronic arrangement, specifically for an electrically powered motor vehicle. The invention further relates to a method for manufacturing said (power) electronic arrangement.
[0007] State of the art and object of the invention:
[0008] Electronic arrangements with embedded electrical (semiconductor) components, especially power electronic arrangements with embedded power semiconductor switches, are being used more and more widely thanks to their various advantages, such as their space-saving, cost-effective design and improved electrical properties. In particular, such power electronic arrangements are used as power modules in power inverters for electrically powered vehicles.
[0009] As with almost all technical arrangements, there is a general requirement for these (power) electronic arrangements or the (power) inverters with these electronic arrangements to make them more reliable.
[0010] The purpose of this application is therefore to provide a means of making the aforementioned (power) electronic arrangement or (power) inverter more reliable. 202301609
[0011] 2
[0012] Description of the invention:
[0013] This problem is solved by the subject matter of the independent claims. Advantageous embodiments are the subject matter of the dependent claims.
[0014] According to a first aspect of the invention, an electronic arrangement, in particular a power electronic arrangement or a power module, is provided specifically for a (power) inverter of an electric drive of a motor vehicle.
[0015] The electronic assembly includes (at least) one circuit carrier. The circuit carrier is formed, in particular, as a printed circuit board (PCB) with fiber-reinforced plastic, epoxy resin-impregnated glass fiber mats (FR4), prepreg, aluminum oxide, Teflon, or ceramic as the electrically insulating base material.
[0016] Furthermore, the electronic arrangement comprises (at least) one semiconductor device, in particular a power semiconductor device, specifically a (power) semiconductor switch, which is embedded in the circuit carrier and has (at least) an electrically conductive, sinterable contact surface (as a sinterable functional surface). The semiconductor device is embedded in the circuit carrier in such a way that its electrical contact surface is also embedded within the circuit carrier and thus lies below the outer surface or inside the circuit carrier (and is consequently protected from external environmental influences). The semiconductor device is, in particular, a silicon, silicon carbide, or gallium nitride semiconductor device, specifically a Si-IGBT or a SiC-MOSFET.The semiconductor device is formed as a bare die and has surface electrodes as contact surfaces, one of which is the aforementioned contact surface.
[0017] The contact surface of the semiconductor device (embedded in the circuit carrier) is physically and electrically contacted by means of (at least) one microvia, the microvia being made of a metallic sintered paste in 202301609
[0018] 3. The sintered paste is formed in a sintering process (directly on the contact surface) and is thus directly bonded to the contact surface. The sintered paste is, in particular, a copper-containing sintered paste, specifically made of copper or a copper alloy, or has copper or a copper alloy as its base material.
[0019] By forming the contact surface as a sinterable contact area and creating the microvia from a similarly sinterable sintering paste, reliable electrical connections can be established between the microvia and the contact surface. This ensures reliable electrical connections for the terminal electrode of the semiconductor device, exhibiting high thermomechanical stability. Consequently, in subsequent applications of the electronic assembly, these connections show little to no thermomechanical degradation under significant thermal fluctuations. Thanks to this advantageous property, high-performance semiconductor devices, such as SiC MOSFETs (silicon carbide MOSFETs), can be used in the electronic assembly.
[0020] This provides a way to make the aforementioned (power) electronics arrangement or (power) inverter more reliable.
[0021] For example, an end section of the microvia, facing away from the semiconductor device or its contact surface, protrudes beyond the surface of the circuit carrier or the area of the circuit carrier's surface surrounding this end section. This end section has a contact surface that is exposed (before the final assembly of the electronics) and serves to electrically connect the microvia and thus the contact surface of the semiconductor device to, for example, another (external) electrical component.
[0022] For example, the contact surface of the microvia, viewed in a direction perpendicular to the plane of extension of the semiconductor device, is a maximum of 10 micrometers higher than a surrounding area of the circuit carrier surface. 202301609
[0023] 4
[0024] Here, the semiconductor device extends in the plane of extension, which runs parallel to the surface of the circuit carrier. The aforementioned perpendicular direction is perpendicular to this plane of extension and thus also to the surface of the circuit carrier.
[0025] The sinterable contact surface of the semiconductor device can be formed from a further metallic, especially copper-containing, sintering paste on a terminal electrode of the semiconductor device, which is metallurgically bonded to the microvia. Alternatively, the contact surface of the semiconductor device can have a metallic, especially copper-containing, sintered layer to which the microvia is metallurgically bonded, especially through the aforementioned sintering process, and thus directly physically and electrically contacted. In particular, the sintered layer consists of copper or a copper alloy, or has copper or a copper alloy as its base material.
[0026] Advantageously, the sintering paste for forming the contact surface of the semiconductor device and the sintering paste for forming the microvia consist of the same, in particular copper-based, sintering material or have the same, in particular copper-based, sintering material as a base material.
[0027] For example, the circuit carrier may have fiber-reinforced plastic, epoxy resin, adhesive film, prepreg, aluminum oxide, Teflon and / or ceramic as electrical insulating material, in which the semiconductor component is embedded.
[0028] The microvia can have cavities with a porosity of between 5% and 10%, between 8% and 12%, or approximately 10%. In other words, the cavity filling with the microvia has a residual porosity of approximately 10%, which saves sintered material and also compensates for thermomechanical stresses in the material pairings in connections, further increasing the reliability of the electrical connection. 202301609
[0029] 5
[0030] According to a second aspect of the invention, an inverter, specifically a power inverter, e.g. for an electric drive of a motor vehicle, is provided.
[0031] The inverter comprises (at least) one previously described electronic arrangement, wherein the (at least one) semiconductor component is, in particular, a controllable (power) semiconductor switch. The inverter further comprises (at least) a control circuit, in particular a driver circuit, e.g., a gate driver, for controlling the (at least one) semiconductor switch, which is electrically connected to the semiconductor switch by means of (at least) one control signal connection.
[0032] The electronic arrangement forms in particular a power module of a power inverter, which in turn forms a bridge circuit or (at least) a switching bridge of the power inverter.
[0033] According to a third aspect of the invention, a method for manufacturing a previously described electronic arrangement is provided.
[0034] According to the method, at least one circuit carrier and at least one semiconductor device with at least one electrically conductive, sinterable contact surface are first provided. The semiconductor device is embedded in the circuit carrier. The semiconductor device is embedded in the circuit carrier in such a way that its contact surface is also embedded in the circuit carrier and thus lies below the outer surface of the circuit carrier or within the circuit carrier itself.
[0035] The contact surface of the semiconductor device is then physically and electrically contacted with (at least) one microvia. The microvia is sintered (directly) onto the contact surface in a sintering process using a metallic, especially copper-containing, sintering paste. The sintering paste is 202301609
[0036] 6 especially as copper-containing sintering paste made from copper or a copper alloy or has copper or a copper alloy as its base material.
[0037] In particular, the contact surface is formed on a surface electrode of the semiconductor device within a wafer level and during the process step of placing the semiconductor device. For this purpose, a further metallic or copper-containing sintering paste is printed or applied to the corresponding electrode of the semiconductor device within the wafer level of the semiconductor device. The semiconductor device is located on the wafer as a bare die alongside other bare semiconductor device chips and has not yet been cut into individual "chip cubes," or has been cut into individual chips but is still on the wafer. In the subsequent sintering process, this paste is sintered into a sinterable layer, which (after completion of the sintering process) forms the aforementioned sinterable contact surface of the semiconductor device.
[0038] The sinterable contact surface of the semiconductor device is thus already formed in the wafer level of the semiconductor device, so that the semiconductor device with the correspondingly formed, sinterable contact surface is embedded in the circuit carrier.
[0039] The semiconductor device is typically manufactured and supplied as a semiconductor chip, especially a MOSFET or a SiC MOSFET, on a wafer (wafer level). At this wafer level, the semiconductor device usually has (at least) one top-side electrode (top-side electrode contact surface), for example, in the case of a SiC MOSFET, this electrode consists of a Ni:P / Pd / Au layer. At this wafer level, the sintering paste is applied to this electrode, forming the sinterable contact surface of the semiconductor device. After the semiconductor device is embedded in the circuit carrier, the aforementioned microvia is formed onto this surface from the sintering paste in a subsequent sintering process. 202301609
[0040] 7
[0041] The remaining sintering paste can be pressure-sintered onto the terminal electrode of the semiconductor device, which is still in the wafer, using a soft or hard tool under a vacuum atmosphere, and especially with the aid of a reducing process gas. This creates a flat, smooth, and oxide-free sintered layer as the sinterable contact surface. The semiconductor device with the finished sinterable contact surface is then singulated from the wafer and embedded in the circuit carrier.
[0042] To embed the semiconductor device in the circuit carrier, the semiconductor device, with its finished, sinterable contact surface, can be placed, for example, on a substrate (or a printed circuit board substrate) of the circuit carrier and encapsulated with an electrical insulating material, such as epoxy resin, adhesive film, or a comparable circuit carrier insulating material. The insulating material then forms the circuit carrier with the substrate (e.g., after hardening), together with the substrate, containing the embedded semiconductor device.
[0043] Alternatively, the semiconductor device with its finished, sinterable contact surface can be positioned in a pre-formed cavity of the circuit carrier designed for embedding the semiconductor device. In this case, the spaces between the semiconductor device and the inner wall of the circuit carrier around the cavity are filled, for example, with electrical insulating material such as epoxy resin or adhesive film.
[0044] The contact surface of the semiconductor device is then physically and electrically contacted with the (at least one) microvia. For this purpose, (at least) one hole (or blind hole), especially by laser cutting with an infrared laser, can be created in the circuit carrier or in the insulating material of the circuit carrier, extending from the surface of the circuit carrier to the contact surface of the semiconductor device. The hole is filled with the sintering paste. The sintering paste is then sintered in a subsequent sintering process, forming the microvia that is firmly bonded to the contact surface of the semiconductor device, especially by a metallurgical bond. 202301609
[0045] 8. The sintering paste is pressure-sintered to form the microvia (MV) at a temperature of max. 225°C or a temperature between 180°C and 225°C or a temperature between 190°C and 210°C or at a temperature of approx. 200°C.
[0046] The low sintering temperature reduces the thermal stress on materials surrounding the sintering paste, such as the insulating material protecting the semiconductor device. This allows for the use of a wide variety of cost-effective PCB base materials or adhesives. The temperature load from the sintering process is comparable to that of a standard SMD reflow soldering process.
[0047] To form the microvia, the hole is filled with sintering paste, for example, and the sintering paste is sintered to form the microvia in such a way that, after sintering, the microvia protrudes from the circuit carrier at an end section facing away from the semiconductor device and has an exposed contact surface for electrical contacting the microvia and thus the semiconductor device, wherein the contact surface of the microvia, viewed in a direction perpendicular to the plane of extension of the semiconductor device, is located, in particular, by a maximum of 10 micrometers higher than an area of the surface of the circuit carrier surrounding this contact surface of the microvia.
[0048] Furthermore, the hole can be filled with the sintering paste and the sintering paste can be sintered to form a microvia in such a way that, after sintering the sintering paste to form a microvia, the microvia has cavities with a pore content of between 5% and 10% or between 8% and 12% or approximately 10%.
[0049] In the case that the semiconductor component is a semiconductor switch, such as a SiC MOSFET, with top and bottom terminal electrodes, such as...
[0050] The gate / source / drain terminal electrodes of SiC MOSFETs are formed; all terminal electrodes at the wafer level of the semiconductor switch are sintered with a sintering paste to create sinterable contact surfaces. (According to 202301609)
[0051] 9
[0052] When embedding the semiconductor switch in the circuit carrier, all contact surfaces and thus all connection electrodes of the semiconductor switch are exposed by (blind) holes extending from the outer surfaces of the circuit carrier to the respective contact surfaces and contacted by sintering with microvias made of further sintering pastes as described above.
[0053] Advantageous embodiments of the electronic arrangement described above, insofar as they are otherwise transferable to the aforementioned method, are also to be regarded as advantageous embodiments of the method. Similarly, advantageous embodiments of the method described above, insofar as they are otherwise transferable to the aforementioned electronic arrangement, are also to be regarded as advantageous embodiments of the electronic arrangement.
[0054] The electronics arrangement described above can be used especially in the technical field of so-called "All on PCB" or "Embedded PCB" solutions.
[0055] Brief description of the drawings:
[0056] An exemplary embodiment of the invention is explained in more detail below with reference to the accompanying drawings. These show:
[0057] Figure 1 shows a schematic flowchart illustrating a method for manufacturing an electronic arrangement according to an exemplary embodiment of the invention; and
[0058] Figures 2A, 2B, 2C, 2D show schematic cross-sectional views of the electronic arrangement or its intermediate products after the respective process steps of the process shown in Figure 1.
[0059] Detailed description of the drawings: 202301609
[0060] 10
[0061] Figure 1 shows in a schematic flowchart process steps of an exemplary method for manufacturing an electronic arrangement EA according to an exemplary embodiment of the invention, wherein Figures 2A, 2B, 2C, 2D show in schematic cross-sectional views the electronic arrangement EA or its intermediate products after respective process steps of the said method.
[0062] In this embodiment, the electronic arrangement EA is designed as a power module with a printed circuit board as a circuit carrier ST and one or more SiC MOSFETs embedded in this printed circuit board as semiconductor components HB, which is used, for example, in a power inverter and forms one or more bridge circuits of the inverter.
[0063] According to process step S100 of the procedure, a circuit carrier ST or a printed circuit board is provided. The circuit carrier ST or the printed circuit board can be provided using two different methods.
[0064] Firstly, according to substep S110, components for manufacturing a circuit carrier ST or a printed circuit board (PCB) can be provided, namely a carrier substrate TS or a PCB substrate consisting of one or more electrical insulating layers with conductor layers formed without, on, or between these insulating layers, and electrical insulating material IM, such as epoxy resin or adhesive film. From these components, a circuit carrier ST or a PCB is manufactured in the process steps described below.
[0065] Alternatively, according to an alternative substep S120, a prefabricated circuit carrier ST or a prefabricated printed circuit board (with conductor layers designed according to the circuit layout) with one or more cavities for embedding semiconductor components HB, as well as electrical insulating material IM, such as epoxy resin or adhesive film, for filling the free spaces between the cavities after the semiconductor components HB have been embedded, are provided. 202301609
[0066] 11
[0067] According to a further process step S200 of the process, a semiconductor device HB, in particular a SiC MOSFET (or several semiconductor devices or SiC MOSFETs) with a sinterable electrical contact surface KF1 is provided.
[0068] For this purpose, a large number of (identical) semiconductor devices or SiC MOSFETs are first formed as bare chips on a wafer in accordance with substep S210 and in a manner known to those skilled in the art. The semiconductor devices are provided with top and bottom terminal electrodes, in the case of SiC MOSFETs made of Ni:P / Pd / Au layers, in a standard manner known to those skilled in the art.
[0069] In a further substep S220, copper-based sintering pastes are applied or printed onto the top and bottom terminal electrodes (or contact pads) of the respective semiconductor devices HB (and in the case of SiC MOSFETs, onto their drain and source electrodes) still located on the wafer (and not yet separated) and then sintered, thereby forming the sinterable contact surfaces KF1 of the semiconductor devices HB.
[0070] In this process, the sintering pastes are printed onto the terminal electrodes of the semiconductor devices HB, for example by means of stencil or screen printing, and pressure-sintered onto the terminal electrodes of the semiconductor devices HB, which are still in the wafer level, using a soft or hard tool under a vacuum atmosphere and especially with the aid of a reducing process gas, thereby forming a flat, smooth and oxide-free sintered layer as the sinterable contact surface KF1 on the respective terminal electrodes.
[0071] Pressure sintering produces a flat, glossy, oxide-free contact surface KF1. This flat, smooth, and oxide-free contact surface KF1 is advantageous for the laser process described below, which creates a hole LO extending to the contact surface KF1 using a laser.
[0072] 12
[0073] Infrared lasers, since the flat, smooth and oxide-free contact surface KF1 allows for the lowest possible absorption.
[0074] After the sinterable contact surfaces are formed on the terminal electrodes of the semiconductor devices HB still located in the wafer level according to substep S220, the semiconductor device HB with the sinterable contact surface KF1 is separated from the wafer according to a further substep S230 and embedded in the circuit carrier ST according to a subsequent process step S300.
[0075] In the case that, according to substep S110, components such as the substrate TS and electrical insulating material IM are provided for the production of a circuit carrier ST or a printed circuit board, the semiconductor device HB is placed on the substrate TS according to substep S310 and encapsulated with the insulating material IM according to substep S350. Furthermore, additional electrical insulating layers and additional conductor or conductor track layers are applied to the substrate TS according to the circuit layout and connected to the substrate TS and the insulating material IM in a manner known to those skilled in the art. After the insulating material IM has hardened, it forms a circuit carrier ST or a printed circuit board with one or more embedded semiconductor devices HB together with the substrate TS, the additional insulating layers, and the additional conductor or conductor track layers.An intermediate product following this substep S110 is shown as an example in Figure 2A.
[0076] In the event that, according to alternative substep S120, a prefabricated circuit carrier ST or a prefabricated printed circuit board (with conductor layers executed according to the circuit layout) with one or more cavities for embedding semiconductor devices HB is provided, the semiconductor device HB is inserted into the cavity of the prefabricated circuit carrier ST according to substep S320. The spaces between the semiconductor device HB and the inner wall of the cavity of the circuit carrier ST or the printed circuit board are then filled with 202301609 according to a further substep S360.
[0077] 13. The insulating material IM is filled. After the insulating material IM has hardened, the semiconductor component HB (or, in the case of multiple semiconductor components, the semiconductor components) is embedded in this circuit carrier ST (or in the printed circuit board) and protected from external environmental influences.
[0078] After embedding the semiconductor device HB with the sinterable electrical contact surface KF1 into the circuit carrier ST, the contact surface KF1 of the semiconductor device HB is directly contacted, both physically and electrically, in a subsequent process step S400 by means of at least one microvia MV.
[0079] For this purpose, a hole LO (or several holes) is first created in the circuit carrier ST according to substep S410. This hole extends from the (free) surface OF of the circuit carrier ST to the contact surface KF1 of the semiconductor device HB. The hole is drilled, for example, through the insulating material IM using an infrared laser. The contact surface KF1 of the semiconductor device HB is partially exposed through the hole LO. An intermediate product after this substep S410 is shown as an example in Figure 2B.
[0080] Subsequently, the hole LO is filled with a copper-based sintering paste SP according to a further substep S420, as exemplified in Figure 2C. According to a further substep S430, the sintering paste SP is pressure-sintered in a subsequent sintering process at a low sintering temperature of no more than 225°C, forming the microvia MV, which is metallurgically bonded to the contact surface KF1 of the semiconductor device HB. The sintering paste SP is filled into the hole LO, for example, by jetting, dispensing, stencil printing, or screen printing, possibly with multiple passes using a doctor blade. The hole LO is filled with the sintering paste SP and the paste is sintered to form the microvia MV such that the microvia MV has cavities with a porosity of approximately 10%.Furthermore, the amount of sintering paste SP is determined such that the microvia MV after the sintering process is located at an end section 202301609 facing away from the semiconductor device HB.
[0081] 14
[0082] AB protrudes from the circuit carrier ST and has an exposed contact surface KF2 for electrical contacting the microvia MV and thus the contact surface KF1 of the semiconductor device HB. This contact surface KF2 is located up to 10 micrometers higher than a region BR of the surface OF of the circuit carrier ST surrounding this contact surface KF2 of the microvia MV, when viewed in a direction perpendicular SR to the plane of extension of the semiconductor device HB. An intermediate product after this substep S430 is illustrated by way of example in Figure 2D. Subsequently, the circuit carrier ST, together with the embedded semiconductor device HB, which is electrically contacted via the microvia MV, is subjected to one or more further process steps S500 for the final assembly of the electronic arrangement EA. These steps include, for example, an SMD assembly step for placing further electrical components onto the circuit carrier ST.
Claims
202301609 15 Patent claims 1. Electronic assembly (EA), comprising: - a circuit carrier (ST), - a semiconductor device (HB) embedded in the circuit carrier (ST) and having an electrically conductive sinterable contact surface (KF1 ), - wherein the contact surface (KF1 ) of the semiconductor device (HB) is physically and electrically contacted by means of a microvia (MV), wherein the microvia (MV) is sintered onto the contact surface (KF1 ) of the semiconductor device (HB) from a metallic, in particular copper-containing, sintering paste (SP) in a sintering process.
2. Electronic arrangement (EA) according to claim 1, wherein an end section (AB) of the microvia (MV) facing away from the semiconductor device (HB) projects beyond a surface (OF) of the circuit carrier (ST) and has an exposed contact surface (KF2) for electrical contacting the microvia (MV).
3. Electronic arrangement (EA) according to claim 2, wherein the contact surface (KF2) of the microvia (MV) is located in a perpendicular direction (SR) to the extension plane (EE) of the semiconductor device (HB) and is located a maximum of 10 micrometers higher than a region (BR) of the surface (OF) of the circuit carrier (ST) surrounding this contact surface (KF2) of the microvia (MV).
4. Electronic arrangement (EA) according to one of the preceding claims, wherein the contact surface (KF1 ) of the semiconductor device (HB) is formed from a further metallic, in particular copper-containing, sintered paste on a terminal electrode of the semiconductor device (HB). 202301609 16 5. Electronic arrangement (EA) according to one of the preceding claims, wherein the contact surface (KF1 ) of the semiconductor device (HB) and the microvias (MV) are formed from the same sintered paste.
6. Electronic arrangement (EA) according to one of the preceding claims, wherein the contact surface (KF1 ) of the semiconductor device (HB) is metallurgically bonded to the microvia (MV).
7. Electronic arrangement (EA) according to one of the preceding claims, wherein the microvia (MV) has cavities with a pore content of between 5% and 10% or between 8% and 12% or of approximately 10%.
8. Inverter according to one of the preceding claims, comprising: - at least one electronic arrangement (EA) according to one of the preceding claims, wherein the semiconductor device (HB) is formed as a controllable semiconductor switch, - a control circuit for controlling the semiconductor switch, which is electrically connected to the semiconductor switch via a control signal connection.
9. Method for manufacturing an electronic assembly (EA) according to one of the preceding claims, comprising the following method steps: - Providing (S100) a circuit carrier (ST); - Providing (S200) a semiconductor device (HB) with an electrically sinterable contact surface (KF1 ), - Embedding (S300) the semiconductor device (HB) in the circuit carrier (ST), - Contacting (S400) the contact surface (KF1) of the semiconductor device (HB) with a microvia (MV) physically and electrically, wherein the microvia (MV) is made of a metallic, in particular copper-containing, sintering paste (SP) in a sintering process onto the 202301609 17 The contact surface (KF1) of the semiconductor device (HB) is sintered.
10. The method of claim 9, wherein the step of providing (S200) the semiconductor device (HB) comprises the following substeps: - Forming (S220) the contact surface (KF1 ) of the semiconductor device (HB) in a wafer level of the semiconductor device (HB), wherein in this wafer level of the semiconductor device (HB) a further metallic, in particular copper-containing, sintering paste is printed onto a terminal electrode of the semiconductor device (HB) and sintered to form the contact surface (KF1 ) of the semiconductor device (HB). - Separation (S230) of the semiconductor device (HB) from the wafer after forming (S220) the contact surface (KF1) of the semiconductor device (HB).
11. Method according to claim 10, wherein the step of forming (S220) the contact surface (KF1) of the semiconductor device (HB) further provides that the additional sintering paste is pressure-sintered onto the terminal electrode of the semiconductor device (HB), in particular by means of a soft or hard tool, under a vacuum atmosphere, and in particular with the aid of a reducing process gas, so that a flat, smooth and oxide-free sintered layer is formed as the contact surface (KF1) of the semiconductor device (HB).
12. Method according to any one of claims 9 to 11, wherein the step of embedding (S300) the semiconductor device (HB) into the circuit carrier (ST) further comprises the following substeps: - Placing (S310) the semiconductor device (HB) onto a support substrate (TS), - Encapsulation (S350) of the semiconductor device (HB) with an electrical insulating material (IM), in particular epoxy resin or adhesive film, 202301609 18 - wherein the carrier substrate (TS) together with the electrical insulating material (IM) forms the circuit carrier (ST).
13. Method according to any one of claims 9 to 11, wherein the step of embedding (S300) the semiconductor device (HB) into the circuit carrier (ST) further comprises the following substeps: - Placing (S320) the semiconductor device (HB) in a cavity of the circuit carrier (ST), - Filling (S360) a space in the cavity between the semiconductor device (HB) and the circuit carrier (ST) with an electrical insulating material (IM), especially epoxy resin or adhesive film.
14. Method according to any one of claims 9 to 13, wherein the step of contacting (S400) the contact surface (KF1) of the semiconductor device (HB) further comprises the following substeps: - Forming (S410) a hole (LO) extending to the contact surface (KF1) of the semiconductor device (HB) in the circuit carrier (ST), - Filling (S420) the hole (LO) with the sintering paste (SP), - Sintering (S430) of the sintering paste (SP) to form the microvia (MV), wherein in this sintering process the microvia (MV) is formed from the sintering paste (SP) and is firmly bonded to the contact surface (KF1) of the semiconductor device (HB), in particular by a material bond.
15. Method according to claim 14, wherein the step of sintering (S430) the sintering paste (SP) to the microvia (MV) further provides that the sintering paste (SP) is pressure-sintered to the microvia (MV) at a temperature of a maximum of 225°C or between 180°C and 225°C or between 190°C and 210°C or of approximately 200°C.