Information processing system and endian conversion method

Abstract

This system comprises an arithmetic processing unit for performing arithmetic processing, and a memory for storing data handled by the arithmetic processing unit. The system is provided with: a conversion circuit for executing, in hardware, conversion processing for converting the byte order of input data between big endian and little endian; and a table for storing access patterns corresponding to a transmission source and a reception destination of the input data. The conversion circuit determines the access pattern by referring to the table, and executes conversion into big endian or conversion into little endian according to the determined access pattern.

Description

Information Processing System and Endian Conversion Method

[0001] The present invention relates to an information processing system and an endian conversion method.

[0002] In an information processing device such as a computer, the data to be handled may be big-endian data or little-endian data. Big-endian arranges data byte by byte starting from the first byte. On the other hand, little-endian arranges data byte by byte starting from the last byte.

[0003] When processing data by a CPU (Central Processing Unit) or the like, or when a database stores data, there are cases of handling big-endian data and cases of handling little-endian data. Also, when the transferred data is different from the type of endian to be handled by a processing unit such as a CPU, endian conversion (Byte Swapping) needs to be performed.

[0004] Patent Document 1 describes a communication data byte order conversion device that converts the byte order of data by hardware processing.

[0005] Japanese Patent Laid-Open No. 5-292144

[0006] As described in Patent Document 1, an endian converter that converts the byte order of data has already been put into practical use, and the conversion is performed when data conversion between big-endian and little-endian is required. In particular, when executing the conversion process with a hardware configuration such as that described in Patent Document 1, an information processing device such as a CPU only needs to send data to the corresponding converter, so the burden of the conversion process can be reduced compared to the case of software processing.

[0007] However, when data supplied to an information processing device contains a mix of big-endian and little-endian formats, the device must perform a process to identify whether the data it is handling is big-endian or little-endian. Then, only when conversion between big-endian and little-endian is necessary, the data is transferred to an endianness converter for conversion. However, determining whether the data being handled is big-endian or little-endian requires some kind of determination process within the information processing device, which complicates the processing configuration of the information processing device.

[0008] The present invention was made to solve the above problems, and its objective is to provide an information processing system and an endianness conversion method that can perform endianness conversion without requiring complex software processing.

[0009] To solve the above problems, for example, the configuration described in the claims is adopted. The present invention includes multiple means for solving the above problems, but to give one example, the information processing system of the present invention has an arithmetic processing unit that performs arithmetic processing, and a memory that stores data handled by the arithmetic processing unit. The information processing system of the present invention also includes a conversion circuit that performs a conversion process in hardware to convert the byte order of input data between big-endian and little-endian, and a table that stores access patterns corresponding to the source and destination of the input data. The conversion circuit refers to the table to determine the access pattern of the input data, and performs a conversion to big-endian or a conversion to little-endian according to the determined access pattern.

[0010] According to the present invention, a hardware-based conversion circuit refers to a table to determine whether or not endian conversion is required for the input data, and executes the appropriate conversion process if conversion is necessary. Therefore, according to the present invention, software processing for endian conversion is reduced, resulting in fast and correctly ordered data. Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

[0011] This is a block diagram showing an example of an information processing system according to one embodiment of the present invention. This is a diagram showing an example of an access pattern by the information processing system according to one embodiment of the present invention. This is a flowchart showing the flow of endian conversion processing performed by the information processing system according to one embodiment of the present invention. This is a block diagram showing an example of an information processing system according to a modified example of one embodiment of the present invention.

[0012] Hereinafter, an information processing device and an endianness conversion method according to one embodiment of the present invention (hereinafter referred to as "this example") will be described with reference to the drawings.

[0013] [Configuration of the Information Processing Device] Figure 1 is a block diagram showing an example configuration of the information processing device 100, which is the information processing system in this example. The information processing device 100 in this example is an integrated circuit made of semiconductors called a SoC (System on Chip). The information processing device 100 includes a processing unit 110 and an FGPA (Field Programmable Gate Array) 120. A memory 200 and a CPU (Central Processing Unit) 300 are connected to the information processing device 100.

[0014] In this example, the processing unit 110 within the information processing device 100, described later, is a circuit that handles little-endian data. On the other hand, the CPU 300 is a circuit that handles big-endian data. In the diagram, areas marked "little" indicate areas that handle little-endian data, and areas marked "big" indicate areas that handle big-endian data.

[0015] The processing unit 110 comprises a plurality of arithmetic processing units consisting of a first core 111a, a second core 111b, ..., and an nth core 111n (where n is an arbitrary integer), and a DDR (Double Data Rate) controller 113. The plurality of cores 111a to 111n and the DDR controller 113 are connected to each other via a first bus 112, enabling data transfer between them.

[0016] The DDR controller 113 is connected to the external memory 200 of the information processing device 100 via the second bus 131. The DDR controller 113 controls data transfer between the cores 111a to 111n within the information processing device 100 and the circuits within the FGPA 120 (described later) and the memory 200. The second bus 131 is a bus that performs data transfer in accordance with the DDR standard, and data reading and writing to the memory 200 are performed via this second bus 131 in accordance with the DDR standard.

[0017] The memory 200 has a program area 210 and a data area 220. The program area 210 stores program data (software) that each core 111a to 111n executes. The data area 220 stores data required by the cores 111a to 111n and the CPU 300. The program data stored in the program area 210 is the program data required by the cores 111a to 111n and is little-endian data. The data stored in the data area 220 is big-endian data.

[0018] The FGPA 120, a hardware device integrating logic circuits, includes circuits for performing conversions during data transfer between the external CPU 300 and the information processing device 100. Specifically, the FGPA 120 comprises a first conversion circuit 121 and a second conversion circuit 122 for endian conversion, and an address table 123. The first conversion circuit 121 and the second conversion circuit 122, depending on their hardware configuration, convert input data from little-endian to big-endian, or from big-endian to little-endian. Alternatively, the first conversion circuit 121 and the second conversion circuit 122 can pass the data through without performing endian conversion.

[0019] The address table 123 is a table corresponding to the data source and destination. When the destination is memory 200, the address table 123 shows the correspondence for each address in memory 200. The address table 123 also shows the access pattern for each data source and destination. Specific examples of access patterns are explained in Figures 2 and 3. The first conversion circuit 121 and the second conversion circuit 122 perform endian conversion based on the access pattern obtained by referring to the address table 123.

[0020] Furthermore, the FGPA 120 includes a PU interface control unit 124, a memory interface control unit 125, and a bus interface control unit 126. The PU interface control unit 124 controls data transfer between the processing unit 110 and the FGPA 120. The memory interface control unit 125 controls data transfer between the memory 200 and the FGPA 120. The bus interface control unit 126 controls data transfer between the FGPA 120 and the CPU 300 via a third bus 132 connecting the FGPA 120 and the CPU 300.

[0021] [Examples of access patterns that perform conversion by conversion circuits] Figure 2 shows access patterns P1, P2, P3, and P4 for performing endian conversion by the first conversion circuit 121 and the second conversion circuit 122 provided in the information processing device 100. In Figure 2, access patterns P1, P2, and P3 show the case when data is transferred from the first core 111a, but the processing when data is transferred from the other cores 111b to 111n is the same as access patterns P1, P2, and P3.

[0022] The first access pattern P1 shown in Figure 2 illustrates the case where data is transferred from the first core 111a to the CPU 300. In this first access pattern P1, it is assumed that the source, the first core 111a, is a circuit that handles little-endian data, and the destination, the CPU 300, is a circuit that handles big-endian data. In the first access pattern P1, the little-endian data sent from the first core 111a to the first bus 112 undergoes endianness conversion in the first conversion circuit 121 to become big-endian data. The big-endian data converted in the first conversion circuit 121 is then transferred to the CPU 300 via the third bus 132 through the PU interface control unit 124 and the bus interface control unit 126.

[0023] The second access pattern P2 is a pattern used when transferring data from the first core 111a to the data area 220 of the memory 200 for storage. In this second access pattern P2, the source first core 111a is a circuit that handles little-endian data, and the destination memory 200 data area 220 is an area that stores big-endian data.

[0024] In the case of the second access pattern P2, the little-endian data sent from the first core 111a to the first bus 112 is converted to big-endian data by the first conversion circuit 121. The big-endian data converted by the first conversion circuit 121 is then supplied to the second conversion circuit 122 via the PU interface control unit 124 and the memory interface control unit 125. In the second conversion circuit 122, no endian conversion is performed, and the data transferred from the memory interface control unit 125 is directly transferred to the memory 200 by the DDR controller 113 and stored in the data area 220.

[0025] The third access pattern P3 is a case in which data is transferred from the first core 111a to the program area 210 of the memory 200, and program data is stored in the program area 210. In this third access pattern P3, the source first core 111a is a circuit that handles little-endian data, and the program area 210 of the receiving memory 200 is also an area that stores little-endian data.

[0026] In the third access pattern P3, the little-endian data sent from the first core 111a to the first bus 112 is converted to big-endian data by the first conversion circuit 121. The big-endian data converted by the first conversion circuit 121 is supplied to the second conversion circuit 122 via the PU interface control unit 124 and the memory interface control unit 125. In this second conversion circuit 122, the big-endian data is converted to little-endian data. The converted little-endian data is then transferred to the memory 200 by the DDR controller 113 and stored in the program area 210.

[0027] The fourth access pattern P4 is a pattern used when data is transferred from the CPU 300 to the data area 220 of the memory 200 and the program data is stored in the program area 210. In this fourth access pattern P4, the source CPU 300 is a circuit that handles big-endian data, and the data area 220 of the destination memory 200 is also an area that stores big-endian data.

[0028] In the case of the fourth access pattern P4, the big-endian data sent from the CPU 300 to the third bus 132 is supplied to the second conversion circuit 122 via the bus interface control unit 126 and the memory interface control unit 125. In this second conversion circuit 122, no endian conversion is performed, and the data is passed directly to the DDR controller 113, which then supplies the data to the data area 220 of the memory 200 via the second bus 131 for storage.

[0029] [Decision Processing During Endian Conversion] Figure 3 is a flowchart showing an example of the decision processing when the first conversion circuit 121 and the second conversion circuit 122 perform input data conversion for the four access patterns P1 to P4 described above. First, the first conversion circuit 121 and the second conversion circuit 122 of the FGPA 120 determine whether or not there is a data transfer request via the FGPA 120 (step S11). If there is no data transfer request in step S11 (No. in step S11), the first conversion circuit 121 and the second conversion circuit 122 wait until there is a data transfer request.

[0030] Then, if there is a request for data transfer in step S11 (Yes in step S11), the first conversion circuit 121 and the second conversion circuit 122 determine the data source and destination (step S12). The data source here is each core 111a to 111n or the CPU 300, and the data destination is the memory 200 or the CPU 300. In the case of memory 200, it is also indicated whether the destination is the program area 210 or the data area 220. The first conversion circuit 121 and the second conversion circuit 122 refer to the information in the address table 123 and select one of the four access patterns P1 to P4 shown in Figure 2, which is the combination of data source and destination determined in step S12 (step S13). This process in step S13 is the access pattern determination process.

[0031] Next, the first conversion circuit 121 and the second conversion circuit 122 determine whether the access pattern selected in step S13 is the first access pattern P1 (step S14). If it is determined in step S14 that it is the first access pattern P1 (Yes in step S14), the first conversion circuit 121 performs a conversion process to convert little-endian data to big-endian data (step S15).

[0032] Furthermore, if it is determined in step S14 that the access pattern is not the first access pattern P1 (No in step S14), the first conversion circuit 121 and the second conversion circuit 122 determine whether the access pattern selected in step S13 is the second access pattern P2 (step S16). If it is determined in step S16 that the access pattern is the second access pattern P2 (Yes in step S16), the first conversion circuit 121 performs the process of converting little-endian data to big-endian data, but the second conversion circuit 122 passes the supplied data through and does not perform the conversion process (step S17).

[0033] Furthermore, if it is determined in step S16 that the access pattern is not the second access pattern P2 (No in step S16), the first conversion circuit 121 and the second conversion circuit 122 determine whether the access pattern selected in step S13 is the third access pattern P3 (step S18). If it is determined in step S18 that the access pattern is the third access pattern P3 (Yes in step S18), the first conversion circuit 121 performs a process to convert little-endian data to big-endian data. Simultaneously with this conversion process, the second conversion circuit 122 performs a process to convert the supplied big-endian data to little-endian data (step S19).

[0034] Furthermore, if it is determined in step S18 that the data is not the third access pattern P3 (No. in step S18), the second conversion circuit 122 passes the supplied data through and does not perform the conversion process (step S20). The process in step S20 corresponds to the processing of the fourth access pattern P4. When the processing in steps S15, S17, S19, and S20 is completed, the conversion processing in the first conversion circuit 121 and the second conversion circuit 122 is completed. Then, when the next data transfer request is received, the processing from step S11 is repeated again.

[0035] As explained above, in the information processing device 100 of this example, the FGPA 120 is equipped with a first conversion circuit 121 and a second conversion circuit 122, which are configured in hardware, and when endian conversion is required, the conversion is performed using this hardware. Therefore, in the information processing device 100 of this example, endian conversion can be easily performed without requiring calculation processing as would be required when the conversion is performed by software processing.

[0036] Furthermore, in the case of the information processing device 100 in this example, whether or not an endian conversion is performed by the first conversion circuit 121 and the second conversion circuit 122, and which format of data to convert to, can be determined simply by referring to the address table 123. Therefore, it becomes possible to perform the correct endian conversion easily and quickly without performing complex software processing such as analyzing the contents of the transferred data. Also, in this example, since table 123 is an address table, the endian format of the stored data can be determined from the address to be stored in memory 200, making it easier for the first conversion circuit 121 and the second conversion circuit 122 to determine the access pattern.

[0037] [Modifications] It should be noted that the present invention is not limited to the embodiments described herein, but includes various modifications. For example, the embodiments described above are explained in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. Furthermore, some of the configurations in the embodiments can be added, deleted, or replaced with other configurations.

[0038] For example, the information processing device 100 shown in Figure 1 has a single chip comprising a processing unit 110 and an FGPA 120, but an information processing system in which similar processing is performed by multiple chips is also possible. The information processing system shown in Figure 4 is an example in which a processing unit 500 and an FGPA 600, each consisting of a separate chip, are connected to each other in a data transfer manner.

[0039] In the configuration shown in Figure 4, the processing unit 500 comprises a first core 501a to the nth core 501n, a first bus 502, and a DDR controller 503. The DDR controller 503 performs data transfer between the processing unit 500 and the memory 200 via the second bus 131. The configuration in Figure 1 is the same in that the memory 200 comprises a program area 210 and a data area 220.

[0040] Furthermore, the FGPA 600, which is a hardware-based circuit, includes a first conversion circuit 601, a second conversion circuit 602, an address table 603, a PU interface control unit 604, a memory interface control unit 605, and a bus interface control unit 606. The first conversion circuit 601 and the second conversion circuit 602 are circuits that perform endian conversion, similar to the first conversion circuit 121 and the second conversion circuit 122 shown in Figure 1. The bus interface control unit 606 performs data transfer with the CPU 300 via the third bus 132.

[0041] In the configuration shown in Figure 4, the processing unit 500 and the FGPA 600 are configured as separate chips, which is a difference from the information processing device 100 shown in Figure 1. Also, as shown in Figure 4, the four access patterns P1, P2, P3, and P4 executed by the processing unit 500 and the FGPA 600 are the same as the access patterns P1, P2, P3, and P4 shown in Figure 2. As shown in Figure 4, even when configured with multiple chips, endian conversion can be easily and quickly achieved, similar to the example in Figure 1, by referring to the address table 603 during endian conversion in the first conversion circuit 601 and the second conversion circuit 602 to determine whether conversion is necessary and to which format it should be converted.

[0042] Also, in the configurations shown in FIG. 1 and FIG. 4, as a circuit for performing endian conversion, a first conversion circuit and a second conversion circuit are provided. By providing two conversion circuits in this way, it is possible to handle cases where conversions from little endian to big endian and from big endian to little endian, such as the third access pattern P3, are performed almost simultaneously. On the other hand, for example, only one endian conversion circuit may be prepared, and the operations of the single endian conversion circuit may be alternately executed in a time-sharing manner for the conversion process from little endian to big endian and the conversion process from big endian to little endian. By providing two conversion circuits as in the configuration shown in FIG. 1, conversions from little endian to big endian and from big endian to little endian can be simultaneously executed in the hardware configuration, resulting in the effect of being able to perform conversions at a higher speed. On the other hand, in the case of a configuration with only one conversion circuit, the hardware configuration can be simplified accordingly.

[0043] Also, in the configuration shown in FIG. 1, an example is shown regarding the point where the CPU 300 is connected. An arithmetic processing unit other than the CPU 300 may be connected to the information processing apparatus 100. Similarly, in the case of the system configuration shown in FIG. 4, an arithmetic processing unit other than the CPU 300 may be connected. The use of the DDR method for data transfer to the memory 200 is also an example, and other data transfer methods may be used.

[0044] Also, in the above-described embodiment example, since the data reception destination may be the memory in some cases, the table provided in the conversion circuit is an address table that determines up to the storage area of the memory. On the other hand, when the data reception destination is other than the memory 200, there is no need to determine up to the address, and a table that determines the access pattern based simply on the data transmission source and the data reception destination may be used. Also, regarding the access patterns described in the above-described embodiment example, access patterns other than the access patterns P1 to P4 shown in FIG. 2 and FIG. 4 may be provided.

[0045] Furthermore, in the configuration diagrams shown in Figures 1, 2, and 4, only control lines and information lines deemed necessary for explanation are shown, and not all control lines and information lines are necessarily shown in the actual product. In reality, it can be assumed that almost all components are interconnected. Also, the flowchart shown in Figure 3 is just one example, and if the processing result is the same, some processing orders may be changed or multiple processes may be executed simultaneously.

[0046] 100... Information processing unit, 110... Processing unit, 111a-111n... Core, 112... First bus, 113... DDR controller, 120... FGPA, 121... First conversion circuit, 122... Second conversion circuit, 123... Address table, 124... PU interface control unit, 125... Memory interface control unit, 126... Bus interface control unit, 131... Second bus, 132... Third bus, 200... Memory, 210... Program area, 220... Data area, 300... CPU, 500... Processing unit, 501a-501n... Core, 502... First bus, 503... DDR controller, 600... FGPA, 601... First conversion circuit, 602... Second conversion circuit, 603... Address table, 604...PU interface control unit, 605...Memory interface control unit, 606...Bus interface control unit, P1, P2, P3, P4, p4...Access patterns

Claims

1. An information processing system having an arithmetic processing unit for performing arithmetic processing and a memory for storing data handled by the arithmetic processing unit, comprising: a conversion circuit that performs a conversion process in hardware to convert the byte order of input data between big-endian and little-endian; and a table that stores access patterns corresponding to the source and destination of the input data, wherein the conversion circuit refers to the table to determine the access pattern of the input data and performs a conversion to big-endian or a conversion to little-endian according to the determined access pattern.

2. The information processing system according to claim 1, wherein the table is an address table of the memory, and the conversion circuit determines an access pattern from the address of the memory that stores the data to be received.

3. The information processing system according to claim 1, comprising a first conversion circuit and a second conversion circuit as the conversion circuit, wherein the first conversion circuit converts little-endian data to big-endian data based on the access pattern determined by referring to the table, and the second conversion circuit stores the big-endian data in the memory without conversion.

4. The information processing system according to claim 1, wherein the memory is a memory element connected to a semiconductor chip that includes hardware constituting the conversion circuit.

5. The information processing system according to claim 1, wherein a plurality of arithmetic processing units are provided, at least some of the arithmetic processing units are configured on a semiconductor chip separate from the hardware constituting the conversion circuit, and the data supplied from the arithmetic processing unit of the separate semiconductor chip to the conversion circuit is passed through to the memory without being converted by the conversion circuit.

6. The information processing system according to claim 1, wherein a plurality of arithmetic processing units are provided, at least some of the arithmetic processing units are configured on a semiconductor chip separate from the hardware constituting the conversion circuit, and when data is transferred from an arithmetic processing unit on the semiconductor chip to an arithmetic processing unit on the other semiconductor chip, the conversion circuit performs a conversion from little-endian data to big-endian data.

7. An endian conversion method for performing data endian conversion when storing data for performing arithmetic processing in memory in an arithmetic processing unit that performs arithmetic processing, the method comprising: an access pattern determination process that determines an access pattern from the source and destination of the input data; and a conversion process that causes a hardware conversion circuit to perform conversion to big-endian or little-endian according to the access pattern determined in the access pattern determination process.

Images