Arithmetic processing unit and memory access method

By using data compression during memory access in arithmetic processing units, the memory bandwidth bottleneck in sparse matrix operations is addressed, enhancing performance and reducing fragmentation in graph analysis processing.

JP7870910B2Active Publication Date: 2026-06-08FUJITSU LTD +1
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
FUJITSU LTD
Filing Date
2022-03-02
Publication Date
2026-06-08

AI Technical Summary

Technical Problem

Graph analysis processing in scientific and technical computing often involves sparse matrix operations that can become a memory bandwidth bottleneck compared to core-level calculations.

Method used

An arithmetic processing unit interacts with the main memory and memory controller, employing data compression methods during transfer to optimize memory access, allowing for efficient switching between compressed and uncompressed data without requiring changes to LLC and core design.

Benefits of technology

This approach speeds up memory access and improves execution performance by reducing the memory bandwidth requirement, particularly in sparse matrix operations like SpMV, while maintaining computational accuracy and reducing memory fragmentation.

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Abstract

To provide an arithmetic processing device and a memory access method, which increase a speed of memory access.SOLUTION: A multi-core processor 10 includes a transfer IF 21 that refers to an attribute of a compression system for data on a main memory device 1 on data transfer between the main memory device 1 and a memory controller 2, and switches the compression system to execute the data transfer on the basis of the attribute to which reference is made. The attribute is a predetermined threshold value. The transfer IF switches the compression system on the basis of a comparison result between the predetermined threshold value and a value of a threshold register included in the memory controller 2.SELECTED DRAWING: Figure 4
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Citation Information

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