Low noise amplifier and driving method thereof

Abstract

A low noise amplifier according to an example of the present disclosure is provided. The low noise amplifier may comprise: an input signal source configured to provide an input signal; a matching network configured to perform input impedance matching; a first circuit including a first transistor and a second transistor connected in series with each other; and a second circuit connected in parallel with the first circuit, and including a third transistor and a fifth transistor connected in series with each other and a fourth transistor and a sixth transistor connected in series with each other, wherein a gate of the third transistor is connected to a gate of the sixth transistor at a first node, and a gate of the fourth transistor is connected to a gate of the fifth transistor at a second node.

Description

Low-noise amplifier and driving method thereof

[0001] The present disclosure relates to a low-noise amplifier and a driving method thereof.

[0002] Modern wireless communication systems, such as 4G LTE, 5G NR, Wi-Fi, and satellite communication, require high-performance receivers capable of processing weak signals even in environments with strong interference. A Low Noise Amplifier (LNA) is a component included in the receiver of a wireless communication system that amplifies weak signals received through an antenna into noise-resistant signals while minimizing the addition of noise to maintain the Signal-to-Noise Ratio (SNR). The LNA is a critical component that determines the noise performance of the receiver.

[0003] Meanwhile, the noise cancelling (NC) technique in a low-noise amplifier (LNA) is a method that cancels out noise generated from the transistor responsible for amplification in the first stage at the output stage by utilizing the phase difference of the noise in the second stage. Given the characteristics of the cascaded noise figure, where having low noise at the front end of the receiver is most important, this technique can lower the overall noise figure of the receiver by reducing the noise figure (NF) of the low-noise amplifier (LNA) located at the very front of the receiver through the noise cancelling technique.

[0004] Conventional LNA designs have often focused on achieving a low noise figure (NF) to ensure receiver sensitivity. However, modern communication environments are becoming increasingly congested, leading to a rise in strong out-of-band interference signals. These interference signals can generate intermodulation distortion components due to the nonlinearity of the low-noise amplifier (LNA), and these intermodulation distortion components can degrade receiver sensitivity.

[0005] Commonly used LNA architectures (e.g., common-source amplifiers or cascode amplifiers) provide adequate noise performance, but in many cases, they suffer from limited linearity. Techniques such as feedback networks, current steering, and passive intermodulation suppression have been used to improve linearity, but these approaches often result in trade-offs with noise performance, power consumption, or operating bandwidth.

[0006] In particular, while conventional noise canceling techniques can achieve a low noise figure, they require an additional noise cancelling stage, consume a large amount of power to satisfy noise canceling conditions, and have a structure where linearity control is difficult.

[0007] Therefore, there is a need for the development of low-noise amplifiers that operate at low power, featuring high linearity capable of withstanding strong interference signals without distortion, a low noise figure to maintain receiver sensitivity, and low power consumption.

[0008] Accordingly, the inventors of the present disclosure have invented a low-noise amplifier that can control the DC output voltage with high design freedom by applying a conventional noise canceling structure and utilizing a complementary stage and current bleeding circuit structure using NMOS and PMOS, and has characteristics of low power consumption, high voltage gain, low noise figure, and high linearity.

[0009] Accordingly, the problem to be solved by the present disclosure is to provide a low-noise amplifier designed to have high linearity, low noise, low power, and high gain characteristics, and a method for driving the same.

[0010] The problems that this disclosure aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below.

[0011] To solve the problem described above, a low-noise amplifier according to one example of the present disclosure is provided. The low-noise amplifier comprises an input signal source configured to provide an input signal, a matching network configured to perform input impedance matching, a first circuit including a first transistor and a second transistor connected in series with each other, and a second circuit connected in parallel with the first circuit and including a third transistor and a fifth transistor connected in series with each other, and a fourth transistor and a sixth transistor connected in series with each other, wherein the gate of the third transistor may be connected to the gate of the sixth transistor at a first node, and the gate of the fourth transistor may be connected to the gate of the fifth transistor at a second node.

[0012] According to the features of the present disclosure, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor, the drain of the first transistor is connected to a first LC tank connected to a power supply voltage (VDD), and the drain of the second transistor is connected to a second LC tank connected to a ground voltage (GND).

[0013] The source of the first transistor and the source of the second transistor are connected at a third node, and the third node may be a node connected to the matching network.

[0014] According to the features of the present disclosure, the third transistor and the fourth transistor may be connected to a power supply voltage (VDD), and the fifth transistor and the sixth transistor may be connected to a ground voltage (GND).

[0015] According to the features of the present disclosure, the drain of the third transistor, the drain of the fourth transistor, the drain of the fifth transistor, and the drain of the sixth transistor are connected at a fourth node, and the fourth node may be a node where an output signal is sensed.

[0016] According to the features of the present disclosure, the drain of the first transistor may be connected to the first node with a first inductor in between, and the drain of the second transistor may be connected to the second node with a second inductor in between.

[0017] According to the features of the present disclosure, the third node and the fourth node may be connected with a first resistor in between.

[0018] To solve the problem described above, a method of operation of a low-noise amplifier according to an example of the present disclosure is provided. This method of operation may include the step of amplifying a received input signal by a first circuit comprising a first NMOS transistor and a second PMOS transistor connected in series with each other to generate a first signal, and the step of receiving the first signal by a second circuit comprising a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor connected in parallel with the first circuit to generate a second signal corresponding to an output signal.

[0019] According to the features of the present disclosure, the third PMOS transistor and the fourth PMOS transistor may have a current bleeding structure.

[0020] According to the features of the present disclosure, the third PMOS transistor, the fourth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor may have a complementary structure.

[0021] Specific details of other embodiments are included in the detailed description and drawings.

[0022] A low-noise amplifier according to one example of the present disclosure is structured to have high linearity while applying noise cancellation technology, and is designed with a signal path having a cross-coupled and current reuse structure to obtain high voltage gain with low power.

[0023] A low-noise amplifier according to one example of the present disclosure can increase the sensitivity of a receiver with a low noise figure and, by having high linearity, can reduce inter-modulation distortion (IMD) caused by signals outside the UWB frequency band, thereby suppressing receiver saturation in the baseband and lowering noise.

[0024] The effects of the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art from the description below.

[0025] Figure 1a is a schematic circuit diagram showing a circuit using a multi-gate transistor technique according to a comparative example.

[0026] Figure 1b is a schematic circuit diagram showing the circuit of a low-noise amplifier with a post-linearization technique applied according to a comparative example.

[0027] FIG. 1c is a schematic circuit diagram showing a part of the circuit of a low-power amplifier with complementary NMOS transistor and PMOS transistor topologies according to a comparative example.

[0028] Figure 2 is a circuit diagram showing the circuit of a low-noise amplifier according to a comparative example.

[0029] FIG. 3 is a circuit diagram showing a circuit of a low-noise amplifier according to one embodiment of the present disclosure.

[0030] FIGS. 4a and 4b are graphs showing the simulation results of a low-noise amplifier according to one embodiment of the present disclosure.

[0031] FIG. 5 is a flowchart illustrating the operation method of a low-noise amplifier according to one embodiment of the present disclosure.

[0032] FIG. 6 is a block diagram showing a wireless communication device including a low-noise amplifier according to one embodiment of the present disclosure.

[0033] FIG. 7 is a block diagram showing a computing system including a low-noise amplifier according to one embodiment of the present disclosure.

[0034] The advantages and features of the present disclosure and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure is complete and to fully inform those skilled in the art of the scope of the invention, and the present disclosure is defined only by the scope of the claims. In connection with the description of the drawings, similar reference numerals may be used for similar components.

[0035] In this document, expressions such as "have," "can have," "include," or "can include" refer to the existence of the relevant feature (e.g., numerical values, functions, actions, or components, etc.) and do not exclude the existence of additional features.

[0036] In this document, expressions such as “A or B,” “at least one of A or / and B,” or “one or more of A or / and B” may include all possible combinations of items listed together. For example, “A or B,” “at least one of A and B,” or “at least one of A or B” may refer to cases including (1) at least one A, (2) at least one B, or (3) both at least one A and at least one B.

[0037] Expressions such as "first," "second," "first," or "second" used in this document may modify various components regardless of order and / or importance, and are used merely to distinguish one component from another without limiting such components. For example, the first user device and the second user device may represent different user devices regardless of order or importance. For example, without departing from the scope of rights set forth in this document, the first component may be named the second component, and similarly, the second component may be renamed the first component.

[0038] Where it is stated that a certain component (e.g., a first component) is "(operatively or communicatively) coupled with" or "connected to" another component (e.g., a second component), it should be understood that the said certain component may be directly connected to the said other component or connected through another component (e.g., a third component). On the other hand, where it is stated that a certain component (e.g., a first component) is "directly connected" or "directly connected" to another component (e.g., a second component), it may be understood that no other component (e.g., a third component) exists between the said certain component and the said other component.

[0039] As used in this document, the expression “configured to” may be replaced, depending on the context, with, for example, “suitable for,” “having the capacity to,” “designed to,” “adapted to,” “made to,” or “capable of.” The term “configured to” does not necessarily mean only “specifically designed to” in hardware. Instead, in some situations, the expression “device configured to” may mean that the device is “capable of” in conjunction with other devices or components. For example, the phrase “processor configured to perform A, B, and C” may mean a dedicated processor for performing those operations (e.g., an embedded processor) or a generic-purpose processor (e.g., a CPU or application processor) capable of performing those operations by executing one or more software programs stored in a memory device.

[0040] The terms used in this document are used merely to describe specific embodiments and are not intended to limit the scope of other embodiments. Singular expressions may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as generally understood by those skilled in the art described in this document. Terms used in this document that are defined in general dictionaries may be interpreted as having the same or similar meaning as they have in the context of the relevant technology, and are not to be interpreted in an ideal or overly formal sense unless explicitly defined in this document. In some cases, even terms defined in this document may not be interpreted to exclude the embodiments of this document.

[0041] The features of each of the various embodiments of the present disclosure may be combined or combined with one another, either partially or wholly, and as will be fully understood by those skilled in the art, various technical interlocking and operation are possible, and each embodiment may be implemented independently of one another or together in an interlocking relationship.

[0042] For clarity in the interpretation of this specification, the terms used in this specification are defined below.

[0043] Hereinafter, the present disclosure will be described in detail by explaining preferred embodiments of the present disclosure with reference to the attached drawings.

[0044]

[0045] FIG. 1a is a schematic circuit diagram showing a circuit using a multi-gate transistor technique according to a comparative example of the present disclosure.

[0046] Referring to FIG. 1a, a Multi-Gate Transistor (MGTR) circuit (100a) according to a comparative example is shown, in which a Multi-Gate Transistor (MGTR) technique is applied to improve linearity.

[0047] The MGTR technique is a method that makes the sum of nonlinear components zero at the output stage by setting the size and bias point of each of two or more transistor(s) differently. Here, the second coefficient represents the value of the second-order transconductance (gm'), and the third coefficient represents the value of the third-order transconductance (gm'').

[0048] The MGTR circuit (100a) according to the comparative example of the present disclosure includes two main transistors, M_P1 transistor (1) and M_N1 transistor (2), and four auxiliary transistors, M_P2 transistor (3), M_N2 transistor (4), M_P3 transistor (5) and M_N3 transistor (6). The main transistors and auxiliary transistors may be connected in parallel. The four auxiliary transistors (M_N2, M_N3, M_P2, M_P3) may be composed of a first auxiliary branch including M_N2 and M_P2 and a second auxiliary branch including M_N3 and M_P3.

[0049] The output current (I_drain) of the MGTR circuit according to the comparative example of the present disclosure may be the sum of the drain current of the main transistor and the drain current of the auxiliary transistor. By appropriately adjusting the size of the two main transistors (M_N1, M_P1) and the four auxiliary transistors (M_N2, M_N3, M_P2, M_P3) and the bias point input to the two main transistors (M_N1, M_P1), the values ​​of the second or third coefficient of the output current (I_drain) of the MGTR circuit according to the embodiment of the present disclosure can all be made to 0 or close to 0 at a specific bias point.

[0050] However, the MGTR circuit according to the comparative example of the present disclosure consumes about 50mW of power. Since each auxiliary branch of the low-noise amplifier according to the comparative example of the present disclosure has a different current path, there is a problem that it causes very high power consumption.

[0051]

[0052] FIG. 1b is a schematic circuit diagram showing the circuit of a low-noise amplifier applying a post-linearization technique according to a comparative example of the present disclosure.

[0053] Referring to FIG. 1b, a low-noise amplifier (100b) according to a comparative example is shown, in which a post-linearization technique is applied to improve linearity.

[0054] According to this comparative example, the post-linearization technique is a technique that cancels out the third-order non-linear component of the M_1 transistor (10), which is a common mode amplifier, at the output stage using the same principle as noise removal.

[0055] A low-noise amplifier (100b) according to a comparative example of the present disclosure may include a main transistor M_1 transistor (10), auxiliary transistors M_2 transistor (12), M_3 transistor (13), M_4 transistor (14), and M_5 transistor (15). A low-noise amplifier (100b) according to a comparative example includes an LO-part (Linearity-Optimization part, 16) for improving linearity.

[0056] According to FIG. 1b, the load at the drain of the M_1 transistor (10) is much greater than the load at the source, and accordingly, the noise generated from the M_1 transistor (10) in terms of voltage gain is measured significantly at the drain of the M_1 transistor (10). The low-noise amplifier (100b) according to the comparative example of the present disclosure includes an LO-part (16), which is a highly linear gain structure for the X node, to compensate for noise cancellation at the output stage, that is, to make the relatively large gain through the M_1 transistor (10) and the M_2 transistor (12) equal to the relatively small gain through the M_3 transistor (13). Since it is impossible to completely eliminate noise according to the conventional noise canceling structure, the low-noise amplifier (100b) according to the comparative example can compensate for the gain at the output stage using the post-linearization technique described above.

[0057]

[0058] FIG. 1c is a schematic circuit diagram showing a circuit of a low-power amplifier applying a complementary NMOS transistor and PMOS transistor topology according to a comparative example of the present disclosure.

[0059] Referring to FIG. 1c, a low-noise amplifier (100c) according to a comparative example is shown, which applies a complementary NMOS transistor and PMOS transistor topology to improve linearity.

[0060] The low-noise amplifier (100c) according to the comparative example of the present disclosure may be configured with a complementary NMOS transistor and PMOS transistor topology that provides current reuse characteristics. In other words, by implementing a common-gate amplifier and PMOS transistor M_p2 transistor (21) and a common-gate amplifier and NMOS transistor M_n2 transistor (22) as one signal branch, the transconductance (gm) of each transistor can be fully utilized, thereby increasing the amplifier gain. Thus, the low-noise amplifier (100c) according to the comparative example can be driven at low power.

[0061] In addition, the low-noise amplifier (100c) according to the comparative example of the present disclosure can eliminate a second-order non-linear component, i.e., a second-order transconductance (gm'), by utilizing a complementary NMOS transistor and PMOS transistor topology. Thus, the low-noise amplifier (100c) according to the comparative example of the present disclosure can be driven to have low power and high linearity characteristics.

[0062]

[0063] FIG. 2 is a circuit diagram showing a circuit of a low-noise amplifier according to a comparative example of the present disclosure.

[0064] Referring to FIG. 2, a low-noise amplifier according to a comparative example is shown, to which a noise canceling technique and a gm boosting technique are applied.

[0065] The Gm boosting technique is a design method that improves the voltage gain of a circuit or reduces power consumption by increasing the effective transconductance (effective gm) of the main transistor of a low-noise amplifier. In this comparative example, the Gm boosting technique is composed of a combination of parallel arrangement of transistors and a resonant circuit, and can provide low-noise and high-gain characteristics.

[0066] A low-noise amplifier according to a comparative example of the present disclosure may include an M_0 transistor (200), an M_1 transistor (201), an M_2 transistor (202), an M_3 transistor (203), and an M_4 transistor (204).

[0067] According to a comparative example of the present disclosure, the M_0 transistor is a common source amplifier. The M_0 transistor is an input transistor and can operate using a V_B0 bias voltage. The voltage gain of the input signal V_in generated from the M_0 transistor can be transferred to the gate of the M_1 transistor (201).

[0068] According to a comparative example of the present disclosure, the M_1 transistor (201) is a common gate amplifier, and the M_2 transistor (202) is a common source amplifier.

[0069] The M_1 transistor (201) and the M_2 transistor (202) can each generate output signals with a phase difference of 180 degrees. According to the structure of the M_1 transistor (201) and the M_2 transistor (202) according to the comparative example of the present disclosure, noise can be canceled.

[0070] According to a comparative example of the present disclosure, the M_3 transistor (203) and the M_4 transistor (204) are a common source amplifier. The voltage gain of the M_4 transistor (204) from the X node can obtain the effect according to the Gm boosting technique of the M_ transistor (203). The M_3 transistor (203) and the M_4 transistor (204) can be coupled with a resonant circuit including a C_6 capacitor and an L_1 inductor. The M_3 transistor (203) and the M_4 transistor (204) can maximize signal amplification at a specific frequency and suppress circuit noise, particularly in the high-frequency band.

[0071] A low-noise amplifier according to a comparative example of the present disclosure can output an output signal (V_out) from each of the M_1 transistor (201) and the M_2 transistor (202). By doing so, the low-noise amplifier according to the comparative example can output a signal with minimized noise.

[0072] However, the low-noise amplifier according to the comparative example has the disadvantage that it is difficult to adjust parameters to enhance linearity in order to satisfy noise canceling conditions. In other words, it is difficult to design a low-noise amplifier by adopting various design parameters related to linearity (e.g., bias point, transistor size) while satisfying noise canceling conditions.

[0073]

[0074] FIG. 3 is a circuit diagram showing a circuit of a low-noise amplifier according to one embodiment of the present disclosure.

[0075] Referring to FIG. 3, this is a circuit diagram showing a circuit of a low-noise amplifier including a current bleeding circuit in one embodiment of the present disclosure.

[0076] A low-noise amplifier according to one embodiment of the present disclosure includes an input signal source (300), a matching network (301), a complementary common gate structure (Complementary CG stage, 302), and a noise cancelling and linearization structure (Noise Cancelling and linearization stage, 303).

[0077] The matching network (301) is connected to the input signal source (300). The matching network (301) may be composed of one or more capacitors and one or more inductors. The matching network (301) can transfer power from the input signal source (300) to transistors (e.g., M_1 transistor (31), M_2 transistor (32)) through input impedance matching. The matching network (301) can provide optimal impedance matching at a specific frequency, minimize signal loss, and transfer maximum power.

[0078] The complementary common gate structure (Complementary CG stage, 302) includes an NMOS transistor M_1 transistor (31) and a PMOS transistor M_2 transistor (32). The complementary common gate structure (Complementary CG stage, 302) may be referred to as the 'first circuit'. The source of the M_1 transistor (31) and the source of the M_2 transistor (32) may be connected in series, and the node where the source of the M_1 transistor (31) and the source of the M_2 transistor (32) are connected may be referred to as the 'X node'.

[0079] The M_1 transistor (31) and the M_2 transistor (32) are main transistors of a low-noise amplifier according to one embodiment of the present disclosure and operate in a complementary manner. The M_1 transistor (31) may be connected to a first LC tank connected to a power supply voltage (VDD), and the M_2 transistor (32) may be connected to a second LC tank connected to a ground voltage (GND). Here, an LC tank is a parallel resonant circuit in which an inductor and a capacitor are connected in parallel. The M_1 transistor (31) and the M_2 transistor (32) have a current reuse structure and can increase power efficiency by sharing the same current. By driving both the M_1 transistor (31) and the M_2 transistor (32) with a single current, the gain can be increased while reducing current consumption. The second-order nonlinearity components of the M_1 transistor (31) and the M_2 transistor (32) cancel each other out, allowing for high second-order linearity.

[0080] The noise cancelling and linearization stage (303) includes a PMOS transistor M_3 transistor (33), a PMOS transistor M_4 transistor (34), an NMOS transistor M_5 transistor (35), and an NMOS transistor M_6 transistor (36). The noise cancelling and linearization stage (303) is connected in parallel with the first circuit and may be referred to as the 'second circuit'. The M_3 transistor (33), M_4 transistor (34), M_5 transistor (35), and M_6 transistor (36) may be referred to as 'auxiliary transistors'.

[0081] The M_3 transistor (33) and the M_5 transistor (35) (or the M_6 transistor (36)) are connected in series and operate in a complementary manner to have a current reuse structure. Similarly, the M_4 transistor (34) and the M_5 transistor (35) (or the M_6 transistor (36)) are connected in series and operate in a complementary manner to have a current reuse structure.

[0082] The M_3 transistor (33) and the M_4 transistor (34) can be connected to the power supply voltage (VDD). The M_5 transistor (35) and the M_6 transistor (36) can be connected to the ground voltage (GND).

[0083] According to an embodiment of the present disclosure, the M_3 transistor (33), M_4 transistor (34), M_5 transistor (35), and M_6 transistor (36) have a cross-coupled structure. Through the cross-coupled structure, a current bleeding circuit can be formed and used as a gain path.

[0084] Specifically, according to one embodiment of the present disclosure, the gate (N3) of the M_3 transistor (33) may be connected to the gate (N6) of the M_6 transistor (36). The node where the gate (N3) of the M_3 transistor (33) and the gate (N6) of the M_6 transistor (36) are connected may be referred to as the 'first node (N1)'. Additionally, the gate (N4) of the M_4 transistor (34) may be connected to the gate (N6) of the M_5 transistor (35). The node where the gate (N4) of the M_4 transistor (34) and the gate (N6) of the M_5 transistor (35) are connected may be referred to as the 'second node (N2)'.

[0085] According to one embodiment of the present disclosure, the drain of M_3 transistor (33), the drain of M_4 transistor (34), the drain of M_5 transistor (35), and the drain of M_6 transistor (36) may be connected. The node to which the drain of M_3 transistor (33), the drain of M_4 transistor (34), the drain of M_5 transistor (35), and the drain of M_6 transistor (36) are connected may be referred to as the 'Y node'.

[0086] In a low-noise amplifier according to one embodiment of the present disclosure, the drain of the M_1 transistor (31) may be connected to the gate of the M_3 transistor (33) (i.e., the first node (N1)). A capacitor may be provided between the drain of the M_1 transistor (31) and the gate of the M_3 transistor (33).

[0087] In a low-noise amplifier according to one embodiment of the present disclosure, the drain of the M_2 transistor (32) may be connected to the gate of the M_5 transistor (35) (i.e., the second node (N2)). A capacitor may be provided between the drain of the M_2 transistor (31) and the gate of the M_5 transistor (35).

[0088] A resistor may be provided between the 'X node', which is a node connected to the source of M_1 transistor (31) and the source of M_2 transistor (32), and the 'Y node', which is a node connected to the drain of M_3 transistor (33), the drain of M_4 transistor (34), the drain of M_5 transistor (35), and the drain of M_6 transistor (36). That is, the X node and the Y node may be connected with a resistor in between.

[0089] A low-noise amplifier according to one embodiment of the present disclosure includes a current bleeding circuit comprising an M_4 transistor (34) and an M_6 transistor (36) as an auxiliary stage.

[0090] A current bleeding circuit according to one embodiment of the present disclosure can prevent gain degradation of the main transistor and maintain or improve gain by providing an additional current path using M_4 transistor (34) and M_6 transistor (36). In addition, M_4 transistor (34) and M_6 transistor (36) can have a complementary structure with M_3 transistor (33) and M_5 transistor (35) to reduce signal distortion and improve linearity.

[0091] An auxiliary transistor according to one embodiment of the present disclosure not only provides additional current but is also used as a substantial signal path, so that the gain relative to the input power can be increased.

[0092] In addition, by adding M_4 transistor (34) and M_6 transistor (36), there are more options for adjusting various parameters (e.g., bias point or size), allowing for more diverse designs to optimize characteristics such as linearity or noise.

[0093] Accordingly, a low-noise amplifier according to one embodiment of the present disclosure can operate at low power by implementing current reuse characteristics using a complementary structure including NMOS transistors and PMOS transistors in all branches, and can obtain low second-order intermodulation (IM2), thereby obtaining a high second-order input intercept point (IIP2).

[0094] In addition, the current bleeding circuit implemented through auxiliary transistors M_4 transistor (34) and M_6 transistor (36), included in the low-noise amplifier according to one embodiment of the present disclosure, can provide high design freedom in parameter selection to achieve both optimal high-linearity conditions and noise canceling conditions. Since the current signal is reused for the linearization and noise canceling stages, high voltage gain can be achieved with low power consumption.

[0095]

[0096] FIGS. 4a and 4b are graphs showing the simulation results of a low-noise amplifier according to one embodiment of the present disclosure.

[0097] Referring to Fig. 4a, the simulation result graph shows the reflection coefficient, gain, and noise figure of the low-noise amplifier according to the target frequency.

[0098] According to the reflection coefficient (or S11 parameter) graph of a low-noise amplifier according to one embodiment of the present disclosure, when the target frequency of the input signal is 8 GHz, the reflection coefficient is -14.765 dB. The reflection coefficient represents the ratio of the signal reflected from the input and is used to evaluate input matching performance. A smaller reflection coefficient indicates that there is less input reflection and that the matching is good.

[0099] According to the gain graph of a low-noise amplifier according to one embodiment of the present disclosure, when the target frequency of the input signal is 8 GHz, the gain is 19.7 dB.

[0100] According to the noise figure graph of a low-noise amplifier according to one embodiment of the present disclosure, when the target frequency of the input signal is 8 GHz, the noise figure is 3.7 dB.

[0101] Referring to Fig. 4b, the simulation result graph shows the results of a simulation performed with two frequency inputs under the assumption that out-of-band signals in frequency bands f1 and f2 (e.g., 6.7 GHz, 5.3 GHz) are input. Here, it is assumed that the center frequency of the desired target signal is 8 GHz and the bandwidth is 500 MHz. At this time, the frequency of the third-order intermodulation distortion signal is (2f1 - f2) and is 8.1 GHz.

[0102] The simulation result graph shows the output signal power according to the input signal power, and the point where the two lines intersect represents the third-order input intercept point (IIP3). IM1 (dotted line graph) shown in the graph represents the output power of f1 (e.g., 6.7 GHz), which is one of the two out-of-band input signals, and this is not the signal at the desired target frequency of 8 GHz.

[0103] According to the graph of output signal power according to input signal power of a low-noise amplifier according to one embodiment of the present disclosure, when the input signal power is -30dBm, IM1 is approximately -10dBm and IM3 is approximately -87dBm, so IIP3 can be calculated as shown in Equation 1 below. In [Equation 1], IM1 is the output power at the fundamental frequency of the desired signal, and IM3 is the output power at the frequency (2f1 - f2) (e.g., 8.1GHz) corresponding to the intermodulation distortion signal.

[0104] [Mathematical Formula 1]

[0105] IIP3 = P_IN + (IM1 - IM3) / 2 = 8.5dBm

[0106]

[0107] Although not shown in the graph, according to the simulation results, the power of the low-noise amplifier according to one embodiment of the present disclosure was found to be 2.4mW.

[0108] Accordingly, a low-noise amplifier according to one embodiment of the present disclosure may have characteristics of low power consumption, high voltage gain, low noise figure, and high linearity.

[0109]

[0110] FIG. 5 is a flowchart illustrating the operation method of a low-noise amplifier according to one embodiment of the present disclosure.

[0111] Referring to FIG. 5, a first signal can be generated by amplifying an input signal received from an input signal source by a first circuit of a low-noise amplifier according to one embodiment of the present disclosure (S502).

[0112] Here, the first circuit may include a first NMOS transistor and a second PMOS transistor connected in series with each other. The first signal may be a signal amplified by the first NMOS transistor and the second PMOS transistor.

[0113] According to one embodiment of the present disclosure, a second circuit of a low-noise amplifier can receive a first signal and generate a second signal corresponding to an output signal (S502).

[0114] Here, the second circuit is connected in parallel with the first circuit and may include a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The second signal corresponds to the output signal of a low-noise amplifier according to one embodiment of the present disclosure.

[0115] The third PMOS transistor and the fourth PMOS transistor may have a current bleeding structure. Additionally, the third PMOS transistor, the fourth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor may have a complementary structure.

[0116] Accordingly, a low-noise amplifier according to one embodiment of the present disclosure may have characteristics of a low noise figure, high linearity, low power consumption, and high voltage gain.

[0117]

[0118] FIG. 6 is a block diagram showing a wireless communication device including a low-noise amplifier according to one embodiment of the present disclosure.

[0119] A wireless communication device (1300) may include an antenna (1340) and may communicate with a counterpart device by transmitting or receiving a signal through the antenna (1340). The wireless communication system through which the wireless communication device (1300) communicates with a counterpart device may be a wireless communication system using a cellular network such as a 5G (5th generation wireless) system, an LTE (Long Term Evolution) system, an LTE-Advanced system, a CDMA (Code Division Multiple Access) system, a GSM (Global System for Mobile Communications) system, as a non-limiting example, or a WLAN (Wireless Local Area Network) system or any other wireless communication system.

[0120] According to one embodiment, the wireless communication device (1300) may include a signal processor (1310), a transceiver (1230), and a transceiver duplexer (1330). The transceiver duplexer (1330) may provide a signal received through an antenna (1340) to the transceiver (1320) as an RF input signal (RFin), and may provide an RF output signal (RFout) received from the transceiver (1320) to the antenna (1340).

[0121] According to an implementation example, the signal processor (1310) may be a baseband processor and may include control logic (1312). The signal processor (1310) may process baseband transmission and reception signals, specifically, generate a baseband signal for the transmission signal path of the transceiver (1320) and process a baseband signal received through the reception signal path of the transceiver (1320).

[0122] The transceiver (1320) may include a transmitter (1322), a receiver (1325), and a frequency synthesis oscillator circuit (1324), and as an example of a low-noise amplifier (LNA) included in the receiver (1325), the low-noise amplifier circuit shown in FIG. 3 is exemplified.

[0123] A transmitter (1322) can generate an RF output signal (RFout) by processing a transmit input signal (TXin) received from a signal processor (1310). As illustrated, the transmitter (1322) may include a variable gain amplifier (VGA), a TX filter, a TX mixer (1323), and a power amplifier (PA) to process the transmit input signal (TXin). A receiver (1325) can generate a receive input signal (RXin) by processing an RF input signal (RFin) and provide it to the signal processor (1310). To process the RF input signal (RFin), the receiver (1325) may include a low-noise amplifier (LNA), an RX mixer (1326), a variable gain amplifier (VGA), and an RX filter. Although an example in FIG. 6 is shown in which control information is provided from the signal processor (1310), embodiments of the present invention are not limited thereto. As an example, control information may be generated inside the transceiver (1320) or from another control circuit outside the transceiver (1320).

[0124]

[0125] FIG. 7 is a block diagram showing a computing system including a low-noise amplifier according to one embodiment of the present disclosure.

[0126] The computing system (1400) may be a fixed computing system, such as a desktop computer, workstation, server, etc., or a portable computing system, such as a laptop computer, etc. Additionally, the computing system (1400) may be a semiconductor device implemented with semiconductors. As illustrated in FIG. 7, the computing system (1400) may include a processor (1410), memory (1420), input / output devices (1430), a storage device (1440), a network interface (1450), and a modem (1460). The processor (1410), memory (1420), input / output devices (1430), storage device (1440), network interface (1450), and modem (1460) may be connected to a bus (1470) and may communicate with each other through the bus (1370).

[0127] The processor (1410) may be referred to as a processing unit and may include at least one core capable of executing any instruction set (e.g., IA-32 (Intel Architecture-32), 64-bit extended IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.), such as a microprocessor, application processor (AP), digital signal processor (DSP), or graphic processing unit (GPU). For example, the processor (1410) may access memory (1420) through a bus (1470) and execute instructions stored in RAM or ROM.

[0128] The memory (1420) may include volatile memory (random access memory: RAM), including DRAM (Dynamic Random Access Memory), or non-volatile memory (read only memory: ROM), including flash memory.

[0129] Input / output devices (1430) may include input devices such as a keyboard, a pointing device, etc., and output devices such as a display device, a printer, etc.

[0130] The storage device (1440) may store data to be processed by the processor (1410) or data processed by the processor (1410). That is, the processor (1410) may generate data by processing the data stored in the storage device (1440), and may also store the generated data in the storage device (1440).

[0131] The network interface (1450) may provide access to a network outside the computing system (1400). For example, the network may include a number of computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of link.

[0132] The modem (1460) can perform wireless or wired communication with an external device. For example, the modem (1460) can perform Ethernet communication, Near Field Communication (NFC), Radio Frequency Identification (RFID) communication, Mobile Telecommunication, Memory Card communication, Universal Serial Bus (USB) communication, etc., but is not limited thereto.

[0133] Additionally, the modem (1460) may include a low-noise amplifier (LNA, 1362) at the front end of the receiving path.

[0134] Depending on the implementation example, the low-noise amplifier (LNA, 1362) may be configured as an independent device within the computing system (1400) or as a device integrated with other circuits of the computing system (1400).

[0135] The examples of the present disclosure disclosed in this specification and drawings are provided merely to facilitate the explanation of the technical content of the present disclosure and to aid in understanding the present disclosure, and are not intended to limit the scope of the present name. It is obvious to those skilled in the art that other variations based on the technical concept of the invention are possible in addition to the examples disclosed herein.

[0136] This achievement is the result of research conducted with funding from the government (Ministry of Science and ICT) and supported by the National Research Foundation of Korea (No. RS-2024-00416319).

[0137] This achievement is the result of research conducted with funding from the government (Ministry of Science and ICT) in 2025 and supported by the Korea Institute of Information and Communications Technology Planning and Evaluation (No.RS-2025-02219277, AI Star Fellowship Support (Daegu Gyeongbuk Institute of Science and Technology)).

[0138] This achievement is the result of research conducted with funding from the government (Ministry of Science and ICT) in 2025 and supported by the National Research Foundation of Korea’s Bio-Medical Technology Development Project (No. RS-2025-02303581).

Claims

1. An input signal source configured to provide an input signal; A matching network configured to perform input impedance matching; A first circuit comprising a first transistor and a second transistor connected in series with each other; and A second circuit is connected in parallel with the first circuit and includes a third transistor and a fifth transistor connected in series with each other, and a fourth transistor and a sixth transistor connected in series with each other. The gate of the third transistor is connected to the gate of the sixth transistor at the first node, and the gate of the fourth transistor is connected to the gate of the fifth transistor at the second node. Low-noise amplifier.

2. In Paragraph 1, The first transistor above is an NMOS transistor, and The second transistor mentioned above is a PMOS transistor, and The drain of the first transistor is connected to the power supply voltage (VDD), and The drain of the second transistor is connected to the ground voltage (GND), and The source of the first transistor and the source of the second transistor are connected at a third node, and The above third node is a node connected to the above matching network, Low-noise amplifier.

3. In Paragraph 1, The third transistor and the fourth transistor are connected to a first LC tank connected to a power supply voltage (VDD), and The above-mentioned fifth transistor and the above-mentioned sixth transistor are connected to a second LC tank connected to a ground voltage (GND), Low-noise amplifier.

4. In Paragraph 1, The drain of the third transistor, the drain of the fourth transistor, the drain of the fifth transistor, and the drain of the sixth transistor are connected at the fourth node, and The above-mentioned fourth node is a node where the output signal is sensed, Low-noise amplifier.

5. In Paragraph 1, The drain of the first transistor is connected to the first node with the first inductor in between, and The drain of the second transistor is connected to the second node with the second inductor in between, Low-noise amplifier.

6. In Paragraph 1, The above third node and the above fourth node are connected with the first resistor in between, Low-noise amplifier.

7. As a method of operation of a low-noise amplifier, A step of generating a first signal by amplifying a received input signal by a first circuit comprising a first NMOS transistor and a second PMOS transistor connected in series with each other; The method includes the step of receiving the first signal and generating a second signal corresponding to an output signal by means of a second circuit comprising a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor connected in parallel with the first circuit. The third PMOS transistor and the fourth PMOS transistor are current bleeding structures, and The third PMOS transistor, the fourth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are of a complementary structure, method.

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