Predictive maintenance artificial intelligence network for early detection of high-speed link eye diagram degradation systems and methods

Abstract

A system and method for identifying a failing on-chip receiver in a hardware platform are provided. On on-chip eye samples are sampled at the on-chip receiver. On-chip eye samples are converted into a first image comprising an eye diagram. Alternatively, a second image with an eye diagram is generated by an eye monitor coupled to the on-chip receiver. An image is selected from either the first image or the second image. An artificial intelligence (AI) network receives the image and determines whether the eye diagram is a normal eye diagram corresponding to a normal on-chip receiver or a failing eye diagram corresponding to a failing on-chip receiver. An alert is generated based on the determination, where the alert indicates a failing on-chip receiver.

Description

Docket No. 70047.512W001 LS24-016WO1PREDICTIVE MAINTENANCE ARTIFICIAL INTELLIGENCE NETWORK FOREARLY DETECTION OF HIGH-SPEED LINK EYE DIAGRAM DEGRADATIONSYSTEMS AND METHODSChee Pin Chan, Tung Lun LooCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of U.S. Provisional Patent Application 63 / 729,907, filed December 9, 2024 and entitled “Predictive Maintenance Artificial Intelligence Network For Early Detection Of High-Speed Link Eye Diagram Degradation Systems And Methods," which is hereby incorporated by reference in its entirety.TECHNICAL FIELD

[0002] The disclosure generally relates to detecting high-speed link eye degradation, and more specifically to using an artificial intelligence system to detect high-speed link eye degradation from images comprising eye diagrams.BACKGROUND

[0003] Server downtime and data loss due to high-speed receiver eye degradation in FPGAs and other hardware devices are becoming increasingly critical issues. These issues often occur in data centers and may cause data center outage and downtime if not caught early. Debugging these issues is challenging due to highly restricted physical and remote access, necessary to avoid disturbances in the data center environment. Data center outages, for example, may affect millions of devices globally and lead to significant disruptions across multiple sectors and services.

[0004] A failing high-speed receiver can also cause disruptions in sectors and services with life- critical applications. High-speed receiver failures in autonomous driving applications and medical procedure devices are particularly egregious and can lead to catastrophic outcomes. For example, an error while a vehicle is in motion or during a surgical procedure may result in fatalities. Therefore,4938-3415-7695 v.l 1Docket No. 70047.512W001 LS24-016WO1 early detection of high-speed receiver failures is essential to ensure the safety and reliability of these critical systems.

[0005] Some common root causes for high-speed receiver eye degradation include suboptimal printed model analog configuration, silicon aging, wear-and-tear of physical connections, mishandling of devices, and power supply glitches. As maintenance can be scheduled to fix these root causes, early detection of eye degradation in the high-speed receiver is crucial to prevent unplanned server downtime and device malfunction.

[0006] Accordingly, the embodiments discussed herein are directed to a solution to early detect high-speed receiver eye degradation, ensuring the reliability and safety of critical systems. In data center environments, once detected, early maintenance can be scheduled, helping maintain continuous operation. In life-critical applications, such as autonomous driving and medical procedures, early detection reduces the likelihood of potential errors and safeguards lives.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 illustrates a block diagram of a programmable logic device (PLD) in accordance with an embodiment.

[0008] FIG. 2 illustrates eye diagrams corresponding to a good and failing high-speed receiver, according to some embodiments.

[0009] FIG. 3 is a block diagram illustrates an eye degradation detection architecture, according to some embodiments.

[0010] FIG. 4 is a block diagram of an artificial intelligence network in the eye degradation detection architecture, according to some embodiments.

[0011] FIG. 5 is a flowchart of a method for detecting eye degradation in a high-speed receiver, according to some embodiments.

[0012] FIG. 6 illustrates diagrams of images comprising eye diagrams with different signal-to- noise ratios, according to some embodiments.

[0013] Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.4938-3415-7695 v.l 2Docket No. 70047.512W001 LS24-016WO1DETAILED DESCRIPTION

[0014] The embodiments are directed to an eye degradation detection architecture that detects high-speed receiver eye degradation in various hardware platforms including CPUs (central processing units), GPUs (graphics processing units), FPGAs (field- programmable gate arrays), and / or Application-Specific Integrated Circuits (ASICs). The eye degradation detection architecture monitors the eye information of a high-speed on-chip receiver using a pretrained predictive maintenance Al model. The eye degradation detection architecture may receive eye diagram information. The eye diagram information may include discrete sample points sampled by on-chip eye monitoring block(s). The discrete sample points may include x and y coordinates and are used to reconstruct real-time eye diagram plots that are converted to eye diagram images. Alternatively, the eye degradation detection architecture may receive eye diagram information that includes eye diagram images.

[0015] The eye degradation detection architecture may include an eye diagram selector, an image scaler, an Al network, and an alert module. The eye diagram selector chooses the source of eye diagram information, such as the discrete sample points from which eye diagram images are reconstructed or the eye diagram images, based on the user configuration. The image scaler receives the eye diagram images and scales them to a resolution that is processed by the Al network. The Al network may be a neural network, such as a convolutional neural network, a ResNet model, or another neural network. The Al network receives the scaled eye diagram images and classifies them as having a normal eye or a failing eye. The alert module receives the output of the Al model and generates an alert based on the classification. For example, when the Al network classifies eye diagram images as having a failing eye, the alert module generates an alert. The alert may be transmitted to a monitoring device as an early indication of the high-speed receive eye degradation.

[0016] Monitoring for signs of eye degradation at the on-chip receiver offers numerous benefits. The eye degradation detection architecture is fully automated and efficient, operating without interrupting live traffic at the data center or other applications. Further, early detection helps prevent data loss and server downtime at the data center by enabling planned maintenance or redundancy planning, ensuring continuous and reliable operation. In life-critical applications, such as autonomous driving and medical procedures, the eye degradation detection architecture is crucial in4938-3415-7695 v.l 3Docket No. 70047.512W001 LS24-016WO1 preventing potentially fatal errors. In telecommunications networks, the eye degradation detection architecture helps maintain signal integrity by minimizing increased bit error rates which can cause dropped calls and poor data quality. Similarly, in financial trading systems, where ultra-low latency and high-speed data links are critical, the eye degradation detection architecture helps reduce the likelihood of delays or errors in transaction data, thereby preventing financial losses. Additionally, in aerospace and defense applications, high-speed data links are vital for communication between various systems and sensors. The eye degradation detection architecture helps reduce the likelihood of critical data being compromised, thereby enhancing mission success and safety.

[0017] FIG. 1 illustrates a block diagram of a programmable logic device (PLD) 100 in accordance with an embodiment of the disclosure. PLD 100 (e.g., a field programmable gate array (FPGA)), a complex programmable logic device (CPLD), a field programmable system on a chip (FPSC), or other type of programmable device) generally includes input / output (I / O) blocks 102 and logic blocks 104 (e.g., also referred to as programmable logic blocks (PLBs). programmable functional units (PFUs), or programmable logic cells (PLCs)).

[0018] I / O blocks 102 provide I / O functionality (e.g., to support one or more TO and / or memory interface standards) for PLD 100, while programmable logic blocks 104 provide logic functionality (e.g., LUT-based logic or logic gate array-based logic) for PLD 100. Additional TO functionality may be provided by serializer / deserializer (SerDes) blocks 150 and physical coding sublayer (PCS) blocks 152. PLD 100 may also include hard intellectual property core (IP) blocks 160 to provide additional functionality (e.g., substantially predetermined functionality provided in hardware which may be configured with less programming than logic blocks 104).

[0019] PLD 100 may also include blocks of memory 106 (e.g., blocks of EEPROM, block SRAM, and / or flash memory), clock-related circuitry 108 (e.g., clock sources, PLL circuits, and / or DLL circuits), and / or various routing resources 180 (e.g., interconnect and appropriate switching logic to provide paths for routing signals throughout PLD 100, such as for clock signals, data signals, or others) as appropriate. In general, the various elements of PLD 100 may be used to perform their intended functions for desired applications, as would be understood by one skilled in the art.

[0020] For example, certain I / O blocks 102 may be used for programming memory 106 or transferring information (e.g., various types of user data and / or control signals) to / from PLD 100.4938-3415-7695 v.l 4Docket No. 70047.512W001 LS24-016WO1Other I / O blocks 102 include a first programming port (which may represent a central processing unit (CPU) port, a peripheral data port, an SPI interface, and / or a sysCONFIG programming port) and / or a second programming port such as a joint test action group (JTAG) port (e.g., by employing standards such as Institute of Electrical and Electronics Engineers (IEEE) 1149.1 or 1532 standards). In various embodiments, I / O blocks 102 may be included to receive configuration data and commands (e.g., over one or more connections 140) to configure PLD 100 for its intended use and to support serial or parallel device configuration and information transfer with SerDes blocks 150, PCS blocks 152, hard IP blocks 160, and / or logic blocks 104 as appropriate.

[0021] It should be understood that the number and placement of the various elements are not limiting and may depend upon the desired application. For example, various elements may not be required for a desired application or design specification (e.g., for the type of programmable device selected).

[0022] Furthermore, it should be understood that the elements are illustrated in block form for clarity and that various elements would typically be distributed throughout PLD 100, such as in and between logic blocks 104, hard IP blocks 160, and routing resources 180 to perform their conventional functions (e.g., storing configuration data that configures PLD 100 or providing interconnect structure within PLD 100). It should also be understood that the various embodiments disclosed herein are not limited to programmable logic devices, such as PLD 100, and may be applied to various other types of programmable devices, as would be understood by one skilled in the art.

[0023] An external system 130 may be used to create a desired user configuration or design of PLD 100 and generate corresponding configuration data to program (e.g., configure) PLD 100. For example, system 130 may provide such configuration data to one or more I / O blocks 102, SerDes blocks 150, and / or other portions of PLD 100. As a result, programmable logic blocks 104, various routing resources, and any other appropriate components of PLD 100 may be configured to operate in accordance with user-specified applications.

[0024] In the illustrated embodiment, system 130 is implemented as a computer system. In this regard, system 130 includes, for example, one or more processors 132 which may be configured to execute instructions, such as software instructions, provided in one or more memories 134 and / or stored in non-transitory form in one or more non-transitory machine-readable mediums 136 (e.g.,4938-3415-7695 v.l 5Docket No. 70047.512W001 LS24-016WO1 which may be internal or external to system 130). For example, in some embodiments, system 130 may run PLD configuration software, such as Lattice Diamond System Planner software available from Lattice Semiconductor Corporation to permit a user to create a desired configuration and generate corresponding configuration data to program PLD 100.

[0025] System 130 also includes, for example, a user interface 135 (e.g., a screen or display) to display information to a user, and one or more user input devices 137 (e.g., a keyboard, mouse, trackball, touchscreen, and / or other device) to receive user commands or design entry to prepare a desired configuration of PLD 100.

[0026] In some instances, PLD 100 may include a high-speed receiver that facilitates high-speed data transmissions. When the high-speed receiver operates normally, the high-speed data transmissions are generally high-speed and error-free. Over time, the high-speed receiver begins to degrade due to suboptimal printed model analog configuration, silicon aging, wear-and-tear of physical connections, mishandling of devices, and power supply glitches. To maintain optimal performance of the high-speed receiver, the data transmissions at the high-speed receiver are monitored through images of eye diagrams. The eye diagrams represent data transmissions and are indicative of a failing high-speed receiver. To monitor eye diagrams, PLD 100 may be coupled to an eye degradation detection architecture 170.

[0027] FIG. 2 is a diagram 200 illustrating eye diagrams that correspond to a good and failing high-speed receiver, according to some embodiments. Eye diagrams may be used to analyze the fidelity of high-speed digital transmissions. Images of eye diagrams may be generated by overlaying multiple instances of a signal’s waveform. The images of the eye diagram may be examined to analyze the fidelity of high-speed digital transmission and to detect patterns that indicate signal degradation. An example image 202 A illustrates a good eye diagram indicating a good high-speed receiver, and an example image 202B illustrates a degraded eye diagram indicating a failing highspeed receiver.

[0028] An eye diagram may include multiple parameters, such as an eye height 204, an eye width 206, a jitter 208, a noise margin 210, and rise and fall times 212. Eye height 204 may be a vertical opening between the top and bottom of the eye opening. Eye height 204 illustrates a separation between the logical 1 (high state) and logical 0 (low state) voltage levels. A larger eye height 204 indicates a stronger, clearer signal, while a smaller eye height 204 suggests noise or4938-3415-7695 v.l 6Docket No. 70047.512W001 LS24-016WO1 interference affecting the signal. Eye width 206 may be a horizontal opening at the center of the eye diagram. Eye width 206 indicates how long the signal stays in a valid state (either high or low) between transitions. A wider eye width 206 represents better timing margins, meaning the highspeed receiver has more tolerance to jitter and timing issues. Jitter 208 represents a horizontal deviation in signal transitions caused by timing errors. An excessive jitter 208 can cause signal overlap and make it difficult to distinguish between logical 0 and 1 states. Noise margin 210 is a distance between the eye edges and the maximum or minimum voltage level. A larger noise margin 210 is preferable because the larger noise margin suggests that the signal can tolerate more noise without error. The rise and fall times 212 are times it takes to transition between logical 0 and 1 states. Faster rise and fall times 212 create sharper, cleaner transitions, reducing the risk of signal misinterpretation.

[0029] Images 202A and 202B illustrate a change in parameters during eye degradation. Specifically, eye height 204 and eye width 206 become smaller, jitter 208 increases, noise margin 210 decreases, and rise and fall times 212 become longer.

[0030] FIG. 3 illustrates a block diagram 300 of an example eye degradation detection architecture, according to some embodiments. The eye degradation detection architecture may detect eye degradation at a high-speed on-chip receiver. The eye degradation detection architecture may operate concurrently and independently across multiple high-speed receiver channels of the on-chip receiver, ensuring that live traffic remains uninterrupted, and link bandwidth is unaffected. The eye degradation detection architecture is also adaptable to be deployed across various hardware platforms and different technological environments, including CPUs, GPUs, FPGAs, and ASICs.

[0031] An example eye degradation detection architecture may include an eye sample-to-image converter 302, an input selector 304, an image scaling module 306, an Al network 308, and an alert module 310.

[0032] Eye degradation detection architecture may handle different types of eye diagram information received as input. The first input may include on-chip eye samples 312 generated by various on-chip eye monitoring blocks in FPGAs, ASICs, etc. Some example eye monitoring blocks may be eye monitors, on-die instruments, eye scans implemented in PCIe drivers, and the like. On- chip eye samples 312 may be multiple discrete sample points with different x and y coordinates. Eye sample-to-image converter 302 may convert the on-chip eye samples 312 into an image by4938-3415-7695 v.l 7Docket No. 70047.512W001 LS24-016WO1 constructing real-time eye diagram plots from the on-chip eye samples 312 and their corresponding x and y coordinates. For example, eye sample-to-image converter 302 may collect on-chip eye samples 312 over a period to generate a real-time eye diagram plot based on the x and y coordinates corresponding to the on-chip eye samples 312. Next, eye sample-to-image converter 302 may convert the plot into an image 314A in an image format, such as jpg. The second input may be image 314B that is already in an image format. Images 314B may be generated by real-time scopes or other eye diagram plotting tools coupled to the on-chip receiver. In this way, eye degradation detection architecture may be configured to receive eye diagram information from various sources, including sources that generate on-chip eye samples 312 and sources that generate images 314B.

[0033] Input selector 304 may be configured to select the source of eye diagram information, such as eye sample-to-image converter 302 that generates images 314A or images 314B from another source. In some instances, input selector 304 may be configured using user configuration or input, be configured at chip start-up, and the like.

[0034] Image scaling module 306 may receive image 314A or 314B and scale image 314A or 314B to a resolution compatible with Al network 308. For example, images 314A, 314B may have different dimensions and those dimensions may be different from the image dimensions that Al network 308 may receive as input. Image scaling module 306 may adjust (increase or decrease) the size of images 314A or 314B to dimensions compatible with Al network 308. For example, if image 314B has dimensions of 720 x 564 pixels and Al network 308 requires images of 64 x 64 pixels, then image scaling module 306 may scale the 720 x 564 pixel image 314B to 64 x 64 pixels while preserving the accuracy of the eye diagram.

[0035] Al network 308 may receive scaled images 314A, 314B and determine whether images 314A, 314B include eye diagram degradation. Al network 308 may classify objects, such as eye diagrams in images 314A and 314B, as depicting either a normal eye diagram (e.g., an eye diagram in image 202A) or a failing eye diagram (e.g., an eye diagram in image 202B). As shown in FIG. 2B, the failing eye diagram may be showing signs of eye degradation. Signs of eye degradation may be based on eye height 204, eye width 206, jitter 208, noise margin 210, and rise and fall times 212 discussed in FIG. 2.

[0036] In some instances, Al network 308 may be a convolutional neural network (CNN), recurrent neural network (RNN), capsule network, generative adversarial network (GAN), and the4938-3415-7695 v.l 8Docket No. 70047.512W001 LS24-016WO1 like that may receive images and classify objects, e.g., eye diagrams, depicted in the image. In some instances, the CNN may be a 7-layer ResNet model that includes convolution, batch normalization, ReLU, pooling, and dropout layers. The structure of Al network 308 is further discussed in detail in FIG. 4. In other instances, Al network 308 may also include various algorithms for processing images 314A and 314B, such as statistical, structural, template matching, and fuzzy-based algorithms.

[0037] Alert module 310 may receive an output of Al network 308. An example output may be a classifier that indicates whether image 314A or 314B includes a normal eye diagram or a failing eye diagram. Upon receiving the classifier, alert module 310 may generate alert 316. Alert 316 may be generated when the classifier indicates that image 314A or 314B include a failing eye diagram. In some instances, alert module 310 may collect a predetermined number of classifiers indicating a failing eye diagram before generating alert 316. Alert 316 may be received and displayed at a computing device (not shown) to indicate a failing eye diagram. In response, the chip and / or on-chip receiver may be scheduled for maintenance.

[0038] Fig. 4 is a simplified diagram illustrating the neural network structure that may be implemented in one or more neural network models in Al network 308, according to some embodiments. Al network 308 may be a neural network model and may include a perceptron neural network, a feed forward neural network, a multilayer perceptron network, a convolutional neural network (CNN), a radial basis function neural network, a recurrent neural network (RNN), an LSTM (Long Short-Term Memory) network, and the like. In some instances, Al network 308 may also be a capsule network, generative adversarial network (GAN). In some instances, the CNN network may be a 7-layer ResNet model.

[0039] The neural network models may comprise a neural network architecture. The example neural network architecture may comprise an input layer 402, one or more hidden layers 404 and an output layer 406. The neural network models may be built as a collection of connected units or nodes, referred to as neurons 408. Each layer 402, 404, or 406 may comprise the same or different number of neurons or nodes 408, with neurons between layers being interconnected according to a specific topology. Each neuron 408 may be associated with an adjustable weight. The neurons 408 may be aggregated into layers 402, 404, 406 such that different layers perform different transformations on the respective input to generate a transformed output, which is an input for the4938-3415-7695 v.l 9Docket No. 70047.512W001 LS24-016WO1 subsequent layer. Further, different layers in neural network models may be combined into their own neural network models, such that an output layer of one neural network model, is an input into the next neural network model, until a final output layer 406 is reached. The number of layers 404 and neurons 408 within each layer may vary depending on the complexity and type of the neural network model.

[0040] Input layer 402 receives input data. The input data may include images, such as images 314A, 314B that depict an eye diagram discussed in FIG. 2. The number of nodes (neurons) in the input layer 402 may be determined by the dimensionality of the input data (e.g., a three-dimensional array having height, width, and color channels of the scaled images 314A, 314B).

[0041] The hidden layers 404 are intermediate layers located between the input and output layers 402, 406 of the neural network models. Although three hidden layers 404 are shown, there may be any number of hidden layers in the neural network model. Generally, neural network models with more layers are more computationally intensive and / or accurate, while neural network models with fewer hidden layers are less computationally intensive and / or accurate. Hidden layers 404 may extract and transform the input data through series of weighted computations and activation functions associated with individual neurons.

[0042] For example, the neural network models may receive images 314A, 314B at input layer 402 and generate output at output layer 406, which may be a classification of the eye diagrams depicted in images 314A, 314B as good eye diagrams or degraded eye diagrams. To perform the transformation, each neuron 408 receives input signals (which may be input to the neural network model or an output of the preceding layer), performs a weighted sum of the inputs according to weights assigned to each connection and then applies an activation function associated with the respective neuron 408 to the result. The output of the neuron is passed to the next layer of neurons or serves as the final output of the network. The activation function may be the same or different across different layers 402, 404, 406 and may be different at neurons 408 within each layer.Example activation functions include but are not limited to Sigmoid, hyperbolic tangent, Rectified Linear Unit (ReLU), Leaky ReLU, Softmax, and / or the like. In this way, input data received at the input layer 402 is transformed by hidden layers 404 into different values indicative of data characteristics corresponding to a task that the neural network models have been trained to perform.4938-3415-7695 v.l 10Docket No. 70047.512W001 LS24-016WO1

[0043] In some embodiments, hidden layers 404 may further be combined in layers and / or blocks. In a non-limiting embodiment, hidden layers 404 may be combined into one or more of convolutional layer(s), pooling layer(s), flattening layer(s), and / or fully connected layer(s). A convolutional layer(s) may detect features in an image frame using one or more filters. As an image frame passes through the filters in the convolution layer(s), the convolutional layer(s) generate feature maps. Each filter may identify a specific feature in the image that corresponds to a feature map. A pooling layer may reduce the dimensions, e.g., height and width of the feature maps while retaining essential features in the feature maps. In some embodiments, convolutional layer(s) and pooling layer(s) may be stacked or interspersed with each other creating a deep neural network that may learn complex features. A flattening layer may follow one or more convolutional layer(s) and pooling layer(s). A flattening layer may flatten the feature maps that are the output of the preceding convolution layer or pooling layer to generate a one-dimensional vector. A fully connected layer includes one or more hidden layers 404 where neuron 408 of a preceding layer is connected to each neuron in the next layer (e.g., as shown in Fig. 4). A fully connected layer may receive the onedimensional vector and combine different features identified from the convolutional layer(s), pooling layer(s) and flattening layer(s) to identify one or more objects in the image frame.

[0044] In some embodiments hidden layers 404 may be combined to form a 7-layer ResNet model. The 7-layer ResNet model may be divided into 7 layers, where the first layer may include a convolutional neural network layer with eight filters, a batch normalization layer, a ReLU layer, and a maxpool layer. The second layer may include a convolutional neural network layer with eight filters, a batch normalization layer, and a ReLU layer. The third layer may include a convolutional neural network layer with sixteen filters, a batch normalization layer, a ReLU layer, and a maxpool layer. A fourth layer may include a convolutional neural network layer with sixteen filters, a batch normalization layer, and a ReLU layer. A fifth layer may include a convolutional neural network layer with sixteen filters, a batch normalization layer, a ReLU layer, and a maxpool layer. A sixth layer may include a convolutional neural network layer with twenty-two filters, a batch normalization layer, and a ReLU layer. A seventh layer may include a convolutional neural network layer with twenty-four filters, a batch normalization layer, a ReLU layer, and a maxpool layer. A dropout layer may follow the seventh layer, and a fully connected layer may follow the dropout layer. The fully connected layer may include three outputs, in some embodiments. Notably, the4938-3415-7695 v.l 11Docket No. 70047.512W001 LS24-016WO1 layers in the above ResNet model are exemplary as other layers and combinations of networks within each layer may also be used to classify images 314A, 314B.

[0045] The batch normalization layer in the 7-layer ResNet model may normalize input into the layer to have a mean of zero and a variance of one. The ReLU layer in the 7-layer ResNet model may be an activation layer that activates the input based values. For example, ReLU layer may pass the input to output if the input is positive or set the input to zero output if the input is not positive. The ReLU layer may be used for the neural network structure to leam patterns included in images. The maxpool layer may be a pooling layer that may be a down-sampling layer that performs a down-sampling operation and reduces spatial dimensions (e.g., height and width) of the input while preserving important information. The maxpool layer may operate as a sliding window on the input, e.g., a 2 x 2 window and generate an output that has a highest value of the input in the sliding window.

[0046] The output layer 406 is the final layer of the neural network structure. It produces the network’s output or prediction based on the computations performed in the preceding layers (e.g., 402, 404). The number of nodes in the output layer depends on the nature of the task being addressed. For example, in a binary classification problem, the output layer may consist of a single node representing the probability of belonging to one class. In this scenario, the output may classify images 314A, 314B as having a normal or failing eye diagram. In a multi-class classification problem, the output layer may have multiple nodes, each representing the probability of belonging to a specific class. In some instances, output layer 406 may use a softmax function that determines probabilities that the eye diagram belongs to different classes, e.g., normal, failing, failed, or to an unknown class.

[0047] Neural network models may also be implemented by hardware, software, and / or a combination thereof. For example, neural network models may comprise a specific neural network structure implemented and run on various hardware platforms, such as but not limited to CPUs (central processing units), GPUs (graphics processing units), FPGAs (field-programmable gate arrays), Application-Specific Integrated Circuits (ASICs), dedicated Al accelerators like TPUs (tensor processing units), and specialized hardware accelerators designed specifically for the neural network computations described herein, and / or the like. Example specific hardware for neural4938-3415-7695 v.l 12Docket No. 70047.512W001 LS24-016WO1 network structures may include, but not limited to Google Edge TPU, Deep Learning Accelerator (DLA), NVIDIA Al-focused GPUs, and / or the like. The hardware may be used to implement the neural network structure is specifically configured based on factors such as the complexity of the neural network, the scale of the tasks (e.g., training time, input data scale, size of training dataset, etc.), and the desired performance.

[0048] Neural network models may be trained by iteratively updating the underlying weights of the neurons 408, bias parameters, and / or coefficients in the activation functions associated with neurons 408. The weights may be updated based on a loss function, such as a mean squared estimation error (MSEE), cross-entropy loss, log-loss, and the like. For example, during training, the training data that includes images with normal, failing, and failed eye diagrams are fed into neural network model over thousands of iterations. The training data flows through the network’s layers 402, 404, 406, with each layer performing computations based on its weights, biases, and activation functions until the output layer 406 produces the output.

[0049] The training data may be labeled with an expected output (e.g., a "ground truth" and a corresponding ground truth label). For example, images with the normal, failing, and failed eye diagrams may be labeled with a classification that is based on different measurements for eye height 204, eye width 206, jitter 208, noise margin 210, and rise and fall times 212 discussed in FIG. 2. The output generated by the output layer 406, e.g., the classifications of the eye diagrams, is compared to the expected output, e.g., the labels in the images from the training data, to compute a loss function that measures the discrepancy between the predicted output and the expected output. In some embodiments, the negative gradient of the loss function may be computed with respect to the weights of each layer individually. This negative gradient is computed one layer at a time, iteratively backward from the last layer 406 to the input layer 402 of the neural network models. These gradients quantify the sensitivity of the network's output to changes in the parameters. The chain rule of calculus is applied to efficiently calculate these gradients by propagating the gradients backward (in a backpropagation network) from the output layer 406 to the input layer 402.

[0050] Parameters of the neural network are updated backwardly from the last layer to the input layer (backpropagating) based on the computed negative gradient using an optimization algorithm to minimize the loss. The backpropagation from the last layer 406 to the input layer 402 may be4938-3415-7695 v.l 13Docket No. 70047.512W001 LS24-016WO1 conducted for a number of training samples in a number of iterative training epochs. In this way, parameters of the neural network models may be gradually updated in a direction to result in a lesser or minimized loss, indicating the neural network has been trained to generate a predicted output value closer to the target output value with improved prediction accuracy. Training may continue until a stopping criterion is met, such as reaching a maximum number of epochs or achieving satisfactory performance on the validation data. In a multiple neural network embodiment, the neural network models may be trained separately and then combined together and trained as a single neural network model.

[0051] Neural network parameters may be trained over multiple stages. For example, initial training (e.g., pre-training) may be performed on one set of training data, and then an additional training stage (e.g., fine-tuning) may be performed using a different set of training data, such as machine-readable code in one or more programming languages. In some embodiments, all, or a portion of parameters of one or more neural-network models being used together may be frozen, such that the “frozen” parameters are not updated during that training phase. This may allow, for example, a smaller subset of the parameters to be trained without the computing cost of updating all the parameters. In some instances, once training is complete, the neural network structure may further be validated on a validation dataset to determine accuracy loss, prior to be installed on one of hardware devices discussed above.

[0052] Therefore, the training process transforms the neural network into an “updated” trained neural network with updated parameters such as weights, activation functions, and biases. The trained neural network thus improves neural network technology for generating executable queries that may be executed by a database, another application interface, and the like to retrieve data.

[0053] Once training is complete, the trained neural network models may enter an inference stage where neural network models may be incorporated into Al system 164 and used to generate responses to various prompts.

[0054] FIG. 5 is a flowchart of an exemplary method 500 for identifying a failing on-chip receiver, according to some embodiments. Notably, method 500 is exemplary and other methods may also be used. The operations 502-512 in method 500 may be implemented using the hardware4938-3415-7695 v.l 14Docket No. 70047.512W001 LS24-016WO1 circuitry discussed in FIGs. 1-4. Note that one or more of the operations may be deleted, combined, or performed in a different order as appropriate.

[0055] At operation 502, on-chip eye samples are received. For example, the eye sample-to- image converter 302 of the eye degradation detection architecture 170 may receive on-chip eye samples 312 sampled from an on-chip receiver located on a hardware platform, such as an FPGA, ASIC, CPU, GPU, and the like.

[0056] At operation 504, images are generated from on-chip eye samples. For example, the eye sample-to-image converter 302 may generate image 314 from on-chip eye samples 312. The on-chip eye samples 312 may generate an eye diagram within image 314A.

[0057] At operation 506, images are received. For example, the eye degradation detection architecture 170 may receive image 314B, which includes eye diagrams from various monitoring devices coupled to the on-chip receiver.

[0058] At operation 508, an image is selected. For example, input selector 304 may select images, such as image 314A or 314B to be processed by Al network 308.

[0059] At operation 510, the selected images are scaled. For example, the image scaling module 306 may receive image 314A or image 314B and scale the dimensions of image 314A or image 314B to dimensions that may be received as input by the Al network 308.

[0060] At operation 512, a classification of an eye diagram in the scaled image is determined. For example, the Al network 308 may be trained to classify the eye diagram in various images. The Al network 308 may receive the scaled image 314A or 314B and classify the eye diagram in the scaled image 314A or 314B as being a good eye diagram or a failing eye diagram. Based on this classification, the corresponding on-chip receiver may also be classified as normal or failing.

[0061] At operation 514, an alert is generated. For example, the alert module 310 may generate an alert when the Al network 308 classifies the scaled image 314A or 314B as including a failing eye diagram. The alert may indicate that the on-chip receiver may require maintenance, should be replaced, and the like.

[0062] FIG. 6 is a diagram 600 illustrating sample images comprising eye diagrams with different signal-to-noise ratios, according to some embodiments. In some instances, various components of the eye degradation detection architecture 170 may be trained using a training dataset and validated using a validation dataset. In particular, the Al network 308 of the eye degradation4938-3415-7695 v.l 15Docket No. 70047.512W001 LS24-016WO1 detection architecture 170 may be trained using a training dataset and validated using a validation dataset prior to being placed in a real-world environment, e.g.. coupled to a hardware platform to detect failing on-chip receivers.

[0063] In some instances, images for a training dataset and validation dataset may be generated using a testing simulator. The testing simulator may be programmed using source code in e.g., Python or another programming language, to generate images with eye diagrams having various signal-to-noise ratios, which may result in different parameters that correspond to eye height 204, the eye width 206, the jitter 208, the noise margin 210, and the rise and fall times 212 of the eye diagram discussed in FIG. 2. Some example images with eye diagrams generated by the test simulator are illustrated in FIG. 6. For example, image 606A may illustrate a normal eye diagram, images 606B and 606C may illustrate failing eye diagrams, and image 606D may illustrate a failed eye diagram. The images, such as images 606A-D, may be labeled as normal, failing, or failed and be included in a training dataset and / or validation dataset. In some instances, the testing simulator may generate several thousand images with eye diagrams and divide a percentage of the generated images (e.g., 80%) to be included in a training dataset and another percentage (e.g., 20%) to be included in a validation dataset.

[0064] In some instances, the images generated using the testing tool, such as images 606A-D, may also be used to test the image scaling module 306. As images 606A-D may have different dimensions, the image scaling module 306 may be tested to reduce or increase the dimensions of images 606A-D to fit the dimensions of input to Al network 308 while preserving the accuracy of the eye diagram in images 606A-D.

[0065] Where applicable, various embodiments provided by the present disclosure can be implemented using hardware, software, or combinations of hardware and software. Also, where applicable, the various hardware components and / or software components set forth herein can be combined into composite components comprising software, hardware, and / or both without departing from the spirit of the present disclosure. Where applicable, the various hardware components and / or software components set forth herein can be separated into sub-components comprising software, hardware, or both without departing from the spirit of the present disclosure. In addition, where applicable, it is contemplated that software components can be implemented as hardware components, and vice versa.4938-3415-7695 v.l 16Docket No. 70047.512W001 LS24-016WO1

[0066] Software in accordance with the present disclosure, such as program code and / or data, can be stored on one or more non-transitory machine-readable mediums. It is also contemplated that software identified herein can be implemented using one or more general purpose or specific purpose computers and / or computer systems, networked and / or otherwise. Where applicable, the ordering of various steps described herein can be changed, combined into composite steps, and / or separated into sub-steps to provide features described herein.

[0067] Embodiments described above illustrate but do not limit the invention. It should also be understood that numerous modifications and variations are possible in accordance with the principles of the present invention. Accordingly, the scope of the invention is defined only by the following claims.4938-3415-7695 v.l 17

Claims

Docket No. 70047.512W001 LS24-016WO1CLAIMSWe claim:

1. A system comprising: a memory; and a processor coupled to the memory and configured to perform operations, the operations comprising to: receive on-chip eye samples generated by a high-speed on-chip receiver; generate an image from the on-chip eye samples, wherein the image comprising an eye diagram; determine, using an artificial intelligence (Al) network, that the eye diagram in the image is a normal eye diagram or a failing eye diagram, wherein the normal eye diagram corresponds to the high-speed on-chip receiver operating normally and the failing eye diagram corresponds to the high-speed on-chip receiver failing; and generating an alert based on the determination.

2. The system of claim 1, wherein the high-speed on-chip receiver is incorporated into a field programmable gate array (FPGA).

3. The system of claim 1, wherein the operations further comprise: scale dimensions of the generated image to dimensions compatible with an input to the Al network.

4. The system of claim 1, wherein the Al network comprises a plurality of layers, wherein at least one layer comprises a convolutional neural network.

5. The system of claim 1, wherein the operations further comprise: generate a training dataset comprising a plurality of images with eye diagrams; label the plurality of images with labels corresponding to images having the normal eye diagram or the failing eye diagram; and train the Al network to classify the plurality of images to match the labels.4938-3415-7695 v.l 18Docket No. 70047.512W001 LS24-016WO16. The system of claim 5, wherein the labels are based on parameters associated with the eye diagram, and wherein the parameters comprise one or more of an eye width, an eye height, a jitter, a noise margin, and a rise and fall time.

7. The system of claim 1, wherein the operations further comprise: receive a second image from a monitoring device coupled to an FPGA; and select whether to process the second image or the generated image with the Al network.

8. A system comprising: a memory; and a processor coupled to the memory and configured to perform operations, the operations comprising: receive eye diagram information generated at a high-speed on-chip receiver of a hardware platform; convert the eye diagram information into an image comprising an eye diagram; determine, using a convolutional neural network comprising multiple layers, that the eye diagram is a failing eye diagram, wherein the failing eye diagram indicates that the highspeed on-chip receiver is failing; and generate an alert indicating that the high-speed on-chip receiver is failing.

9. The system of claim 8, wherein the hardware platform is one of a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), or an Application-Specific Integrated Circuit (ASIC).

10. The system of claim 8, wherein the eye diagram information corresponds to eye-diagram samples having x and y coordinates and the operations further that convert the eye diagram information into the image further comprising: generate the image from multiple eye-diagram samples collected over a period of time, wherein the x and y coordinates of the eye-diagram samples determine locations of the eyediagram samples in the image.4938-3415-7695 v.l 19Docket No. 70047.512W001 LS24-016WO111. The system of claim 8, wherein the operations further comprise: scale dimensions of the image to dimensions compatible with the convolutional neural network.

12. The system of claim 8, wherein the operations further comprise: generate a training dataset comprising a plurality of images with eye diagrams; label the plurality of images with labels corresponding to images having a normal eye or a failing eye; and train the convolutional neural network to classify the plurality of images to match the labels.

13. The system of claim 12, wherein the labels are based on parameters associated with the eye diagram, and wherein the parameters comprise one or more of an eye width, an eye height, a jitter, a noise margin, and a rise and fall time.

14. The system of claim 8, wherein the operations further comprise: receive a second image from a monitoring device coupled to that the hardware platform that includes the high-speed on-chip receiver; and select whether to process the second image or the converted image.

15. A method comprising: receiving an eye diagram information generated at an on-chip receiver; generating a first image from the eye diagram information; receiving a second image from an eye monitoring system coupled to the on-chip receiver; selecting an image from the first image or the second image; determining, using an artificial intelligence network that an eye diagram in the image is a failing eye diagram or a normal eye diagram, wherein the failing eye diagram indicates that the on-chip receiver is failing and the normal eye diagram indicates that the on-chip receiver is not failing; and generating an alert based on the determination.4938-3415-7695 v.l 20Docket No. 70047.512W001 LS24-016WO116. The method of claim 15, wherein the on-chip receiver is incorporated into one or more of a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), or an Application-Specific Integrated Circuit (ASIC).

17. The method of claim 15, wherein the eye diagram information corresponds to eyediagram samples having x and y coordinates and converting the eye diagram information into the first image further comprises: generating the first image from multiple eye-diagram samples collected over a time period, wherein the x and y coordinates of the eye-diagram samples determine locations of the eye -diagram samples in the image.

18. The method of claim 15, further comprising: determining dimensions of an input to the artificial intelligence network; and scaling the image to the dimensions compatible with the input to the artificial intelligence network.

19. The method of claim 15, further comprising: generating a training dataset comprising a plurality of images with eye diagrams; labeling the plurality of images with labels corresponding to the normal eye diagram or the failing eye diagram; and training the artificial intelligence network to classify the plurality of images to match the labels.

20. The method of claim 19, wherein the labels are based on parameters associated with the eye diagram, and wherein the parameters comprise one or more of an eye width, an eye height, a jitter, a noise margin, and a rise and fall time.4938-3415-7695 v.l 21

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