Pixel circuit, driving method, and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit, a driving method, and a display apparatus. The pixel circuit comprises a driving circuit, a light-emitting element, and a control circuit; the driving circuit is separately and electrically connected to a first node and a first electrode of the light-emitting element, and is used for generating, under the control of the potential of the first node, a driving current for driving the light-emitting element; the control circuit is separately and electrically connected to a second electrode of the light-emitting element and N voltage terminals, and is used for controlling, during a light-emitting stage, one of the N voltage terminals to be connected to the second electrode of the light-emitting element, N being an integer greater than 1, and voltage values of voltage signals provided by at least two of the N voltage terminals being different. The present disclosure can reduce power consumption and bright dot defect rate.

Description

Pixel circuits, driving methods, and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a pixel circuit, driving method, and display device. Background Technology

[0002] In related technologies, with the development of AMOLED (Active-matrix organic light-emitting diode) displays, brightness has been continuously improving, currently reaching 1800 nits, and may continue to increase in the future. As brightness increases, the voltage difference between the high voltage value Vdd and the low voltage value Vss needs to be continuously increased, but this leads to problems such as a higher incidence of bright spots, affecting yield and product profitability; in addition, power consumption issues will also become increasingly prominent, leading to increased power consumption. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a pixel circuit, including a driving circuit, a light-emitting element, and a control circuit;

[0004] The driving circuit is electrically connected to the first node and the first electrode of the light-emitting element, respectively, and is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node.

[0005] The control circuit is electrically connected to the second electrode and N voltage terminals of the light-emitting element, respectively, and is used to control one of the N voltage terminals to be connected to the second electrode of the light-emitting element during the light-emitting stage; N is an integer greater than 1.

[0006] The voltage values ​​of the voltage signals provided by at least two of the N voltage terminals are different.

[0007] Optionally, the voltage values ​​of the voltage signals provided by the N voltage terminals are all different.

[0008] Optionally, the first electrode of the light-emitting element is the anode, and the second electrode of the light-emitting element is the cathode; or,

[0009] The first electrode of the light-emitting element is the cathode, and the second electrode of the light-emitting element is the anode.

[0010] Optionally, the control circuit includes N voltage control circuits;

[0011] The nth voltage control circuit includes an nth write module, an nth potential maintenance module, and an nth on / off control module; n is a positive integer less than or equal to N;

[0012] The nth write module is electrically connected to the nth write control terminal, the nth on / off control terminal, and the nth on / off control node, respectively, and is used to write the nth on / off control signal provided by the nth on / off control terminal into the nth on / off control node under the control of the nth write control signal provided by the nth write control terminal.

[0013] The nth potential maintenance module is electrically connected to the nth on / off control node and is used to maintain the potential of the nth on / off control node;

[0014] The nth on / off control module is electrically connected to the nth on / off control node, the nth voltage terminal, and the second electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the nth voltage terminal and the second electrode of the light-emitting element under the control of the potential of the nth on / off control node.

[0015] Optionally, the nth write module includes an nth first transistor, the nth potential maintenance module includes an nth capacitor, and the nth on / off control module includes an nth second transistor;

[0016] The gate of the nth first transistor is electrically connected to the nth write control terminal, the first electrode of the nth first transistor is electrically connected to the nth on / off control terminal, and the second electrode of the nth first transistor is electrically connected to the nth on / off control node.

[0017] The first terminal of the nth capacitor is electrically connected to the nth on / off control node, and the second terminal of the nth capacitor is electrically connected to the DC voltage terminal.

[0018] The gate of the nth second transistor is electrically connected to the nth on / off control node, the first electrode of the nth second transistor is electrically connected to the nth voltage terminal, and the second electrode of the nth second transistor is electrically connected to the second electrode of the light-emitting element.

[0019] Optionally, the first electrode of the light-emitting element is the anode, and the second electrode of the light-emitting element is the cathode; the pixel circuit further includes a data writing circuit, a compensation control circuit, a first initialization circuit, and an energy storage circuit;

[0020] The control terminal of the drive circuit is electrically connected to the first node, the first terminal of the drive circuit is electrically connected to the second node, and the second terminal of the drive circuit is electrically connected to the third node.

[0021] The data writing circuit is electrically connected to the scanning end, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the scanning signal provided by the scanning end;

[0022] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the compensation control signal provided by the compensation control terminal.

[0023] The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first initial control signal provided by the first initial control terminal.

[0024] The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node.

[0025] The pixel circuit described in at least one embodiment of this disclosure further includes a first light-emitting control circuit, a second light-emitting control circuit, and a second initialization circuit;

[0026] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal during the light-emitting stage.

[0027] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the anode of the light-emitting element, respectively, and is used to control the connection between the third node and the anode of the light-emitting element under the control of the light-emitting control signal during the light-emitting stage;

[0028] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the anode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the anode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

[0029] Optionally, the first electrode of the light-emitting element is a cathode, and the second electrode of the light-emitting element is an anode; the pixel circuit further includes a data writing circuit, a compensation control circuit, a first initialization circuit, and an energy storage circuit;

[0030] The control terminal of the drive circuit is electrically connected to the first node, the first terminal of the drive circuit is electrically connected to the second node, and the second terminal of the drive circuit is electrically connected to the third node.

[0031] The data writing circuit is electrically connected to the scanning end, the data line and the third node respectively, and is used to write the data voltage provided by the data line into the third node under the control of the scanning signal provided by the scanning end;

[0032] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the compensation control signal provided by the compensation control terminal.

[0033] The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first initial control signal provided by the first initial control terminal.

[0034] The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node.

[0035] The pixel circuit described in at least one embodiment of this disclosure further includes a first light-emitting control circuit, a second light-emitting control circuit, and a second initialization circuit;

[0036] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the cathode of the light-emitting element, and the second node, respectively, and is used to control the connection between the cathode of the light-emitting element and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal during the light-emitting stage.

[0037] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the low-voltage terminal respectively, and is used to control the connection between the third node and the low-voltage terminal under the control of the light-emitting control signal during the light-emitting stage.

[0038] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the cathode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the cathode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

[0039] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned pixel circuit, the pixel driving method comprising:

[0040] During the light-emitting stage, the control circuit controls one of the N voltage terminals to connect with the second electrode of the light-emitting element;

[0041] The voltage values ​​of the voltage signals provided by at least two of the N voltage terminals are different.

[0042] Optionally, the voltage values ​​of the voltage signals provided by the N voltage terminals are all different.

[0043] In a third aspect, embodiments of this disclosure provide a display device including a plurality of the pixel circuits described above.

[0044] The display device described in at least one embodiment of this disclosure further includes a display control circuit;

[0045] The display grayscale of the pixel circuit is divided into N grayscale ranges; the nth voltage terminal corresponds to the nth grayscale range; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0046] The display control circuit is used to control the control circuit when it is detected that the display grayscale of the pixel circuit is in the nth grayscale range during the current frame display time, so that the control circuit controls the nth voltage terminal to be connected to the second electrode of the light-emitting element during the light-emitting phase included in the current frame display time.

[0047] Optionally, the first electrode of the light-emitting element is the anode, and the second electrode of the light-emitting element is the cathode;

[0048] The minimum display gray level in the m-th gray level range is greater than the maximum display gray level in the n-th gray level range, and the voltage value of the m-th voltage signal provided by the m-th voltage terminal is less than the voltage value of the n-th voltage signal provided by the n-th voltage terminal.

[0049] The m-th voltage terminal corresponds to the m-th grayscale range; m is a positive integer less than or equal to N.

[0050] Optionally, the first electrode of the light-emitting element is a cathode, and the second electrode of the light-emitting element is an anode;

[0051] The minimum display gray level in the m-th gray level range is greater than the maximum display gray level in the n-th gray level range, and the voltage value of the m-th voltage signal provided by the m-th voltage terminal is greater than the voltage value of the n-th voltage signal provided by the n-th voltage terminal.

[0052] The m-th voltage terminal corresponds to the m-th grayscale range; m is a positive integer less than or equal to N.

[0053] The display device described in at least one embodiment of this disclosure further includes a source driver; the source driver stores N grayscale-data voltage correspondence tables;

[0054] The nth gray level-data voltage correspondence table records the correspondence between the display gray level in the nth gray level range and the corresponding analog data voltage. The nth gray level-data voltage correspondence table is calculated based on the voltage value of the nth voltage signal provided by the nth voltage terminal.

[0055] The source driver is used to obtain the analog data voltage corresponding to the current display grayscale from the corresponding grayscale-data voltage correspondence table according to the grayscale range of the current display grayscale of the pixel circuit, and to provide the analog data voltage to the pixel circuit. Attached Figure Description

[0056] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0057] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0058] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0059] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0060] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0061] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0062] Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0063] Figure 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0064] Figure 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0065] Figure 10 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 9;

[0066] Figure 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0067] Figure 12 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11;

[0068] Figure 13 is a schematic diagram of a gamma curve in at least one embodiment of this disclosure;

[0069] Figure 14 is a structural diagram of a display device according to at least one embodiment of the present disclosure;

[0070] Figure 15 is a structural diagram of a display device according to at least one embodiment of the present disclosure;

[0071] Figure 16 is a structural diagram of a display device according to at least one embodiment of the present disclosure;

[0072] Figure 17A is a structural diagram of the display back panel included in the display device;

[0073] Figure 17B is a schematic diagram of the fabrication of a red material layer on the display back panel shown in Figure 17A;

[0074] Figure 17C is a schematic diagram of the fabrication of a green material layer on the display back panel shown in Figure 17B;

[0075] Figure 17D is a schematic diagram of the blue material layer fabricated on the display back panel shown in Figure 17C;

[0076] Figure 18A is a structural diagram of the display back panel included in the display device;

[0077] Figure 18B is a schematic diagram of the red material layer being fabricated on the display back panel shown in Figure 18A;

[0078] Figure 18C is a schematic diagram of the fabrication of a green material layer on the display back panel shown in Figure 18B;

[0079] Figure 18D is a schematic diagram of the blue material layer fabricated on the display back panel shown in Figure 18C. Detailed Implementation

[0080] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0081] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0082] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0083] The pixel circuit described in this embodiment includes a driving circuit, a light-emitting element, and a control circuit;

[0084] The driving circuit is electrically connected to the first node and the first electrode of the light-emitting element, respectively, and is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node.

[0085] The control circuit is electrically connected to the second electrode and N voltage terminals of the light-emitting element, respectively, and is used to control one of the N voltage terminals to be connected to the second electrode of the light-emitting element during the light-emitting stage; N is an integer greater than 1.

[0086] The voltage values ​​of the voltage signals provided by at least two of the N voltage terminals are different.

[0087] When the pixel circuit described in the embodiments of this disclosure is working, the display cycle includes a light-emitting phase;

[0088] During the light-emitting stage, the control circuit controls one of the N voltage terminals to connect with the second electrode of the light-emitting element;

[0089] The voltage values ​​of the voltage signals provided by at least two of the N voltage terminals are different.

[0090] In at least one embodiment of this disclosure, the voltage values ​​of the voltage signals provided by the N voltage terminals are all different, and the voltage value of the voltage signal provided by the nth voltage terminal corresponds to the nth grayscale range.

[0091] When the pixel circuit described in this embodiment is working, the display grayscale of the pixel circuit is divided into N grayscale ranges; the nth voltage terminal corresponds to the nth grayscale range;

[0092] When the display grayscale of the pixel circuit is in the nth grayscale range during the current frame display time, the control circuit controls the connection between the nth voltage terminal and the second electrode of the light-emitting element during the light-emitting phase included in the current frame display time. This controls the higher display grayscale to correspond to the higher voltage across the light-emitting element, and the lower display grayscale to correspond to the lower voltage across the light-emitting element, thereby reducing power consumption and the occurrence rate of bright spots and improving the competitiveness of display products.

[0093] In at least one embodiment of this disclosure, N equals 2 as an example, but this is not a limitation. In practice, N can be any integer greater than 2.

[0094] As shown in Figure 1, the pixel circuit of this embodiment includes a driving circuit 10, a light-emitting element E1, and a control circuit 11; the first electrode of the light-emitting element is the anode, and the second electrode of the light-emitting element is the cathode.

[0095] The driving circuit 10 is electrically connected to the first node N1 and the anode of the light-emitting element E1, respectively, and is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0096] The control circuit 11 is electrically connected to the cathode of the light-emitting element E1, the first voltage terminal V1, and the second high voltage terminal V2, respectively, and is used to control the connection between the first voltage terminal V1 or the second voltage terminal V2 and the cathode of the light-emitting element E1 during the light-emitting stage.

[0097] The first voltage terminal V1 is used to provide a first voltage signal, and the second voltage terminal V2 is used to provide a second voltage signal;

[0098] The voltage value of the first voltage signal is different from the voltage value of the second voltage signal.

[0099] As shown in Figure 2, the pixel circuit of this embodiment includes a driving circuit 10, a light-emitting element E1, and a control circuit 11; the first electrode of the light-emitting element is a cathode, and the second electrode of the light-emitting element is an anode.

[0100] The driving circuit 10 is electrically connected to the first node N1 and the cathode of the light-emitting element E1, respectively, and is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0101] The control circuit 11 is electrically connected to the anode, the first voltage terminal V1, and the second high voltage terminal V2 of the light-emitting element E1, respectively, and is used to control the connection between the first voltage terminal V1 or the second voltage terminal V2 and the anode of the light-emitting element E1 during the light-emitting stage.

[0102] The first voltage terminal V1 is used to provide a first voltage signal, and the second voltage terminal V2 is used to provide a second voltage signal;

[0103] The voltage value of the first voltage signal is different from the voltage value of the second voltage signal.

[0104] Optionally, the first electrode of the light-emitting element is the anode, and the second electrode of the light-emitting element is the cathode; or,

[0105] The first electrode of the light-emitting element is the cathode, and the second electrode of the light-emitting element is the anode.

[0106] In at least one embodiment of this disclosure, the control circuit includes N voltage control circuits;

[0107] The nth voltage control circuit includes an nth write module, an nth potential maintenance module, and an nth on / off control module; n is a positive integer less than or equal to N;

[0108] The nth write module is electrically connected to the nth write control terminal, the nth on / off control terminal, and the nth on / off control node, respectively, and is used to write the nth on / off control signal provided by the nth on / off control terminal into the nth on / off control node under the control of the nth write control signal provided by the nth write control terminal.

[0109] The nth potential maintenance module is electrically connected to the nth on / off control node and is used to maintain the potential of the nth on / off control node;

[0110] The nth on / off control module is electrically connected to the nth on / off control node, the nth voltage terminal, and the second electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the nth voltage terminal and the second electrode of the light-emitting element under the control of the potential of the nth on / off control node.

[0111] In a specific implementation, the control circuit may include N voltage control circuits, and the nth voltage control circuit may include an nth writing module, an nth potential maintenance module, and an nth on / off control module; n is a positive integer less than or equal to N; the nth writing module, under the control of the nth writing control signal, writes the nth on / off control signal into the nth on / off control node; the nth potential maintenance module maintains the potential of the nth on / off control node; the nth on / off control module, under the control of the potential of the nth on / off control node, controls the connection or disconnection between the nth voltage terminal and the second electrode of the light-emitting element.

[0112] As shown in Figure 3, based on at least one embodiment of the driving circuit shown in Figure 2, the control circuit includes a first voltage control circuit and a second voltage control circuit.

[0113] The first voltage control circuit includes a first writing module 21, a first potential maintenance module 22, and a first on / off control module 23;

[0114] The first writing module 21 is electrically connected to the first writing control terminal GW1, the first on / off control terminal ST1 and the first on / off control node NT1 respectively, and is used to write the first on / off control signal provided by the first on / off control terminal ST1 into the first on / off control node NT1 under the control of the first writing control signal provided by the first writing control terminal GW1.

[0115] The first potential maintenance module 22 is electrically connected to the first on / off control node NT1 and is used to maintain the potential of the first on / off control node NT1.

[0116] The first on / off control module 23 is electrically connected to the first on / off control node NT1, the first voltage terminal V1 and the cathode of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the first voltage terminal V1 and the cathode of the light-emitting element E1 under the control of the potential of the first on / off control node NT1.

[0117] The second voltage control circuit includes a second writing module 31, a second potential maintenance module 32, and a second on / off control module 32.

[0118] The second writing module 31 is electrically connected to the second writing control terminal GW2, the second on / off control terminal ST2, and the second on / off control node NT2, respectively, and is used to write the second on / off control signal provided by the second on / off control terminal ST2 into the second on / off control node NT2 under the control of the second writing control signal provided by the second writing control terminal GW2.

[0119] The second potential maintenance module 32 is electrically connected to the second on / off control node NT2 and is used to maintain the potential of the second on / off control node NT2;

[0120] The second on / off control module 33 is electrically connected to the second on / off control node NT2, the second voltage terminal V2, and the cathode of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the second voltage terminal V2 and the cathode of the light-emitting element E1 under the control of the potential of the second on / off control node NT2.

[0121] As shown in Figure 4, based on at least one embodiment of the driving circuit shown in Figure 3, the control circuit includes a first voltage control circuit and a second voltage control circuit.

[0122] The first voltage control circuit includes a first writing module 21, a first potential maintenance module 22, and a first on / off control module 23;

[0123] The first writing module 21 is electrically connected to the first writing control terminal GW1, the first on / off control terminal ST1 and the first on / off control node NT1 respectively, and is used to write the first on / off control signal provided by the first on / off control terminal ST1 into the first on / off control node NT1 under the control of the first writing control signal provided by the first writing control terminal GW1.

[0124] The first potential maintenance module 22 is electrically connected to the first on / off control node NT1 and is used to maintain the potential of the first on / off control node NT1.

[0125] The first on / off control module 23 is electrically connected to the first on / off control node NT1, the first voltage terminal V1 and the anode of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the first voltage terminal V1 and the anode of the light-emitting element E1 under the control of the potential of the first on / off control node NT1.

[0126] The second voltage control circuit includes a second writing module 31, a second potential maintenance module 32, and a second on / off control module 32.

[0127] The second writing module 31 is electrically connected to the second writing control terminal GW2, the second on / off control terminal ST2, and the second on / off control node NT2, respectively, and is used to write the second on / off control signal provided by the second on / off control terminal ST2 into the second on / off control node NT2 under the control of the second writing control signal provided by the second writing control terminal GW2.

[0128] The second potential maintenance module 32 is electrically connected to the second on / off control node NT2 and is used to maintain the potential of the second on / off control node NT2;

[0129] The second on / off control module 33 is electrically connected to the second on / off control node NT2, the second voltage terminal V2, and the anode of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the second voltage terminal V2 and the anode of the light-emitting element E1 under the control of the potential of the second on / off control node NT2.

[0130] Optionally, the nth write module includes an nth first transistor, the nth potential maintenance module includes an nth capacitor, and the nth on / off control module includes an nth second transistor;

[0131] The gate of the nth first transistor is electrically connected to the nth write control terminal, the first electrode of the nth first transistor is electrically connected to the nth on / off control terminal, and the second electrode of the nth first transistor is electrically connected to the nth on / off control node.

[0132] The first terminal of the nth capacitor is electrically connected to the nth on / off control node, and the second terminal of the nth capacitor is electrically connected to the DC voltage terminal.

[0133] The gate of the nth second transistor is electrically connected to the nth on / off control node, the first electrode of the nth second transistor is electrically connected to the nth voltage terminal, and the second electrode of the nth second transistor is electrically connected to the second electrode of the light-emitting element.

[0134] In at least one embodiment of this disclosure, the first electrode of the light-emitting element is the anode, and the second electrode of the light-emitting element is the cathode; the pixel circuit further includes a data writing circuit, a compensation control circuit, a first initialization circuit, and an energy storage circuit;

[0135] The control terminal of the drive circuit is electrically connected to the first node, the first terminal of the drive circuit is electrically connected to the second node, and the second terminal of the drive circuit is electrically connected to the third node.

[0136] The data writing circuit is electrically connected to the scanning end, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the scanning signal provided by the scanning end;

[0137] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the compensation control signal provided by the compensation control terminal.

[0138] The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal, and the first node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first initial control signal provided by the first initial control terminal.

[0139] As shown in Figure 5, based on at least one embodiment of the driving circuit shown in Figure 3, the pixel circuit further includes a data writing circuit 51, a compensation control circuit 52, a first initialization circuit 53, and an energy storage circuit 50.

[0140] The control terminal of the drive circuit 10 is electrically connected to the first node N1, the first terminal of the drive circuit 10 is electrically connected to the second node N2, and the second terminal of the drive circuit 10 is electrically connected to the third node N3.

[0141] The data writing circuit 51 is electrically connected to the scanning terminal SA, the data line DL and the second node N2 respectively, and is used to write the data voltage provided by the data line DL into the second node N2 under the control of the scanning signal provided by the scanning terminal SA.

[0142] The compensation control circuit 52 is electrically connected to the compensation control terminal SC, the first node N1 and the third node N3 respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the compensation control signal provided by the compensation control terminal SC.

[0143] The first initialization circuit 53 is electrically connected to the first initial control terminal SI1, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first initial control signal provided by the first initial control terminal SI1.

[0144] The energy storage circuit 50 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1.

[0145] The pixel circuit described in at least one embodiment of this disclosure further includes a first light-emitting control circuit, a second light-emitting control circuit, and a second initialization circuit;

[0146] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal during the light-emitting stage.

[0147] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the anode of the light-emitting element, respectively, and is used to control the connection between the third node and the anode of the light-emitting element under the control of the light-emitting control signal during the light-emitting stage;

[0148] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the anode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the anode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

[0149] As shown in Figure 6, based on at least one embodiment of the driving circuit shown in Figure 5, the pixel circuit further includes a first light-emitting control circuit 61, a second light-emitting control circuit 62, and a second initialization circuit 63.

[0150] The first light-emitting control circuit 61 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal VDD, and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal VDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM during the light-emitting stage.

[0151] The second light-emitting control circuit 62 is electrically connected to the light-emitting control terminal EM, the third node N3 and the anode of the light-emitting element E1 respectively, and is used to control the connection between the third node N3 and the anode of the light-emitting element E1 under the control of the light-emitting control signal during the light-emitting stage.

[0152] The second initialization circuit 63 is electrically connected to the second initial control terminal SI2, the second initial voltage terminal I2 and the anode of the light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the anode of the light-emitting element E1 under the control of the second initial control signal provided by the second initial control terminal SI2.

[0153] In at least one embodiment of this disclosure, the first electrode of the light-emitting element is a cathode, and the second electrode of the light-emitting element is an anode; the pixel circuit further includes a data writing circuit, a compensation control circuit, a first initialization circuit, and an energy storage circuit;

[0154] The control terminal of the drive circuit is electrically connected to the first node, the first terminal of the drive circuit is electrically connected to the second node, and the second terminal of the drive circuit is electrically connected to the third node.

[0155] The data writing circuit is electrically connected to the scanning end, the data line and the third node respectively, and is used to write the data voltage provided by the data line into the third node under the control of the scanning signal provided by the scanning end;

[0156] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the compensation control signal provided by the compensation control terminal.

[0157] The first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal, and the first node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first initial control signal provided by the first initial control terminal.

[0158] As shown in Figure 7, based on at least one embodiment of the driving circuit shown in Figure 4, the pixel circuit further includes a data writing circuit 51, a compensation control circuit 52, a first initialization circuit 53, and an energy storage circuit 50.

[0159] The control terminal of the drive circuit 10 is electrically connected to the first node N1, the first terminal of the drive circuit 10 is electrically connected to the second node N2, and the second terminal of the drive circuit 10 is electrically connected to the third node N3.

[0160] The data writing circuit 51 is electrically connected to the scanning terminal SA, the data line DL and the third node N3 respectively, and is used to write the data voltage provided by the data line DL into the third node N3 under the control of the scanning signal provided by the scanning terminal SA.

[0161] The compensation control circuit 52 is electrically connected to the compensation control terminal SC, the first node N1 and the second node N2 respectively, and is used to control the connection or disconnection between the first node N1 and the second node N2 under the control of the compensation control signal provided by the compensation control terminal SC.

[0162] The first initialization circuit 53 is electrically connected to the first initial control terminal SI1, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first initial control signal provided by the first initial control terminal SI1.

[0163] The energy storage circuit 50 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1.

[0164] The pixel circuit described in at least one embodiment of this disclosure further includes a first light-emitting control circuit, a second light-emitting control circuit, and a second initialization circuit;

[0165] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the cathode of the light-emitting element, and the second node, respectively, and is used to control the connection between the cathode of the light-emitting element and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal during the light-emitting stage.

[0166] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the low-voltage terminal respectively, and is used to control the connection between the third node and the low-voltage terminal under the control of the light-emitting control signal during the light-emitting stage.

[0167] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the cathode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the cathode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

[0168] As shown in Figure 8, based on at least one embodiment of the driving circuit shown in Figure 7, the pixel circuit further includes a first light-emitting control circuit 61, a second light-emitting control circuit 62, and a second initialization circuit 63.

[0169] The first light-emitting control circuit 61 is electrically connected to the light-emitting control terminal EM, the cathode of the light-emitting element E1 and the second node N2 respectively, and is used to control the connection between the cathode of the light-emitting element E1 and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM during the light-emitting stage.

[0170] The second light-emitting control circuit 62 is electrically connected to the light-emitting control terminal EM, the third node N3, and the low-voltage terminal VGL, respectively, and is used to control the connection between the third node N3 and the low-voltage terminal VGL under the control of the light-emitting control signal during the light-emitting stage.

[0171] The second initialization circuit 63 is electrically connected to the second initial control terminal SI2, the second initial voltage terminal I2 and the cathode of the light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the cathode of the light-emitting element E1 under the control of the second initial control signal provided by the second initial control terminal SI2.

[0172] As shown in Figure 9, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0 and an organic light-emitting element O1.

[0173] The first write module includes a first transistor T11, the first potential maintenance module includes a first capacitor C1, and the first on / off control module includes a first second transistor T12.

[0174] The gate of T11 is electrically connected to the (i-1)th scan terminal SA(i-1), the source of T11 is electrically connected to the first on / off control terminal ST1, and the drain of T11 is electrically connected to the first on / off control node NT1.

[0175] The first terminal of C1 is electrically connected to the first on / off control node NT1, and the second terminal of C1 is electrically connected to the ground terminal GND.

[0176] The gate of T12 is electrically connected to the first on / off control node NT1, the source of T12 is electrically connected to the first low voltage terminal VSS1, and the drain of T12 is electrically connected to the cathode of O1.

[0177] The first voltage terminal is the first low voltage terminal VSS1;

[0178] The second write module includes a second first transistor T21, the second potential maintenance module includes a second capacitor C2, and the second on / off control module includes a second second transistor T22.

[0179] The gate of T21 is electrically connected to the (i-2)th scan terminal SA(i-2), the source of T21 is electrically connected to the second on / off control terminal ST2, and the drain of T21 is electrically connected to the second on / off control node NT2.

[0180] The first terminal of C2 is electrically connected to the second on / off control node NT2, and the second terminal of C2 is electrically connected to the ground terminal GND.

[0181] The gate of T22 is electrically connected to the second on / off control node NT2, the source of T22 is electrically connected to the second low voltage terminal VSS2, and the drain of T22 is electrically connected to the cathode of O1.

[0182] The second voltage terminal is the second low voltage terminal VSS2;

[0183] The energy storage circuit includes a storage capacitor Cst, the data writing circuit includes a third transistor T3, the compensation control circuit includes a fourth transistor T4, the first initialization circuit includes a fifth transistor T5, the first light-emitting control circuit includes a sixth transistor T6, the second light-emitting control circuit includes a seventh transistor T7, and the second initialization circuit includes an eighth transistor T8.

[0184] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0185] The first end of Cst is electrically connected to the first node N1, and the second end of Cst is electrically connected to the high voltage terminal VDD.

[0186] The gate of T3 is electrically connected to the i-th scan terminal SA(i), the source of T3 is electrically connected to DL, and the drain of T3 is electrically connected to N2.

[0187] The gate of T4 is electrically connected to the i-th scan terminal SA(i), the source of T4 is electrically connected to N1, and the drain of T4 is electrically connected to N3.

[0188] The gate of T5 is electrically connected to the (i-1)th scan terminal SA(i-1), the source of T5 is electrically connected to I1, and the drain of T5 is electrically connected to N1.

[0189] The gate of T6 is electrically connected to EM, the source of T6 is electrically connected to VDD, and the drain of T6 is electrically connected to N2.

[0190] The gate of T7 is electrically connected to EM, the source of T7 is electrically connected to N3, and the drain of T7 is electrically connected to the anode of O1.

[0191] The gate of T8 is electrically connected to the (i-1)th scan terminal SA(i-1), the source of T8 is electrically connected to I2, and the drain of T8 is electrically connected to the anode of O1.

[0192] In at least one embodiment of the pixel circuit shown in Figure 9, all transistors are p-type transistors.

[0193] In at least one embodiment of the pixel circuit shown in Figure 9, the scanning end and the compensation control end can be the i-th level scanning end SA(i), the first initial control end, the second initial control end and the first write control end can be the (i-1)-th level scanning end SA(i-1), and the second write control end can be the (i-2)-th level scanning end SA(i-2), where i is an integer greater than 2.

[0194] As shown in Figure 10, when at least one embodiment of the pixel circuit shown in Figure 9 is in operation, the display cycle includes a first control stage S1, a second control stage S2, a writing stage S3, and a light emission stage S4 that are set sequentially.

[0195] In the first control phase S1, SA(i-2) provides a low voltage signal, T21 turns on, ST2 provides a second on / off control signal to NT2, and C2 maintains the potential of NT2;

[0196] In the second control phase S2, SA(i-1) provides a low voltage signal, T11 is turned on, ST1 provides a first on / off control signal to NT1, and C1 maintains the potential of NT1; T5 and T8 are turned on, I1 provides a first initial voltage Vinit1 to N1 so that T0 can be turned on when the write phase S3 begins; I2 provides a second initial voltage Vinit2 to the anode of O1 to remove residual charge on the anode of O1;

[0197] During the write phase S3, SA(i) provides a low voltage signal, T3 and T4 are turned on, DL provides the data voltage Vdata to N2, and N1 and N3 are connected.

[0198] When the write phase S3 begins, T0 is turned on, and Vdata charges Cst through T0 until T0 is turned off. At this time, the potential of N1 is Vdata + Vth, where Vth is the threshold voltage of T0.

[0199] During the light emission phase S4, EM provides a low voltage signal, and T6 and T7 are turned on;

[0200] When the gray level corresponding to Vdata is greater than or equal to 0 gray level but less than or equal to 128 gray level, in the first control stage S1, ST2 provides a low voltage signal to NT2; in the second control stage S2, ST1 provides a high voltage signal to NT1; in the light emission stage S4, the potential of NT2 is low voltage, the potential of NT1 is high voltage, T22 is turned on, T12 is turned off, and VSS2 is connected to the cathode of O1.

[0201] When the gray level corresponding to Vdata is greater than 128 gray levels but less than or equal to 255 gray levels, in the first control stage S1, ST2 provides a high voltage signal to NT2; in the second control stage S2, ST1 provides a low voltage signal to NT1; in the light emission stage S4, the potential of NT1 is low voltage, the potential of NT2 is high voltage, T12 is turned on, T22 is turned off, and VSS1 is connected to the cathode of O1.

[0202] The voltage value Vss2 of the second low voltage signal provided by VSS2 is less than the voltage value Vss1 of the first low voltage signal provided by VSS1. Both Vss2 and Vss1 can be negative. The difference between the voltage value Vdd of the high voltage signal provided by VDD and Vss2 is greater than the difference between Vdd and Vss1. This ensures that the voltage across O1 is greater at high grayscale than at low grayscale, thereby reducing power consumption and the occurrence rate of bright spots, and improving the competitiveness of display products.

[0203] In at least one embodiment of this disclosure, during actual display, the same pixel circuit may display both high and low grayscale levels. Therefore, when programming the Gamma voltage, each pixel circuit must program both the high-grayscale Gamma voltage according to Vss2 and the low-grayscale Gamma voltage according to Vss1. During actual display, based on the grayscale value corresponding to the pixel circuit, T12 or T22 is controlled to conduct, thereby controlling the connection between the cathode of O1 and VSS1 or VSS2.

[0204] As shown in Figure 11, based on at least one embodiment of the pixel circuit shown in Figure 8, the driving circuit includes a driving transistor T0 and an organic light-emitting element O1.

[0205] The first write module includes a first transistor T11, the first potential maintenance module includes a first capacitor C1, and the first on / off control module includes a first second transistor T12.

[0206] The gate of T11 is electrically connected to the (i-1)th scan terminal SA(i-1), the source of T11 is electrically connected to the first on / off control terminal ST1, and the drain of T11 is electrically connected to the first on / off control node NT1.

[0207] The first terminal of C1 is electrically connected to the first on / off control node NT1, and the second terminal of C1 is electrically connected to the ground terminal GND.

[0208] The gate of T12 is electrically connected to the first on / off control node NT1, the source of T12 is electrically connected to the first high voltage terminal VDD1, and the drain of T12 is electrically connected to the anode of O1.

[0209] The first voltage terminal is the first high voltage terminal VDD1;

[0210] The second write module includes a second first transistor T21, the second potential maintenance module includes a second capacitor C2, and the second on / off control module includes a second second transistor T22.

[0211] The gate of T21 is electrically connected to the (i-2)th scan terminal SA(i-2), the source of T21 is electrically connected to the second on / off control terminal ST2, and the drain of T21 is electrically connected to the second on / off control node NT2.

[0212] The first terminal of C2 is electrically connected to the second on / off control node NT2, and the second terminal of C2 is electrically connected to the ground terminal GND.

[0213] The gate of T22 is electrically connected to the second on / off control node NT2, the source of T22 is electrically connected to the second high voltage terminal VDD2, and the drain of T22 is electrically connected to the anode of O1.

[0214] The second voltage terminal is the second high voltage terminal VDD2;

[0215] The energy storage circuit includes a storage capacitor Cst, the data writing circuit includes a third transistor T3, the compensation control circuit includes a fourth transistor T4, the first initialization circuit includes a fifth transistor T5, the first light-emitting control circuit includes a sixth transistor T6, the second light-emitting control circuit includes a seventh transistor T7, and the second initialization circuit includes an eighth transistor T8.

[0216] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0217] The first end of Cst is electrically connected to the first node N1, and the second end of Cst is electrically connected to the low voltage terminal VSS.

[0218] The gate of T3 is electrically connected to the i-th scan terminal SA(i), the source of T3 is electrically connected to DL, and the drain of T3 is electrically connected to N3.

[0219] The gate of T4 is electrically connected to the i-th scan terminal SA(i), the source of T4 is electrically connected to N1, and the drain of T4 is electrically connected to N2.

[0220] The gate of T5 is electrically connected to the (i-1)th scan terminal SA(i-1), the source of T5 is electrically connected to I1, and the drain of T5 is electrically connected to N1.

[0221] The gate of T6 is electrically connected to EM, the source of T6 is electrically connected to the cathode of O1, and the drain of T6 is electrically connected to N2.

[0222] The gate of T7 is electrically connected to EM, the source of T7 is electrically connected to N3, and the drain of T7 is electrically connected to the low voltage terminal VSS.

[0223] The gate of T8 is electrically connected to the (i-1)th scan terminal SA(i-1), the source of T8 is electrically connected to I2, and the drain of T8 is electrically connected to the cathode of O1.

[0224] In at least one embodiment of the pixel circuit shown in Figure 11, all transistors are p-type transistors.

[0225] In at least one embodiment of the pixel circuit shown in Figure 11, the scanning end and the compensation control end can be the i-th level scanning end SA(i), the first initial control end, the second initial control end and the first write control end can be the (i-1)-th level scanning end SA(i-1), and the second write control end can be the (i-2)-th level scanning end SA(i-2), where i is an integer greater than 2.

[0226] As shown in Figure 12, when at least one embodiment of the pixel circuit shown in Figure 11 is in operation, the display cycle includes a first control stage S1, a second control stage S2, a writing stage S3, and a light emission stage S4 that are set sequentially.

[0227] In the first control phase S1, SA(i-2) provides a low voltage signal, T21 turns on, ST2 provides a second on / off control signal to NT2, and C2 maintains the potential of NT2;

[0228] In the second control phase S2, SA(i-1) provides a low voltage signal, T11 is turned on, ST1 provides a first on / off control signal to NT1, and C1 maintains the potential of NT1; T5 and T8 are turned on, I1 provides a first initial voltage Vinit1 to N1 so that T0 can be turned on when the writing phase S3 begins; I2 provides a second initial voltage Vinit2 to the cathode of O1 to clear the residual charge on the cathode of O1;

[0229] During the write phase S3, SA(i) provides a low voltage signal, T3 and T4 are turned on, DL provides the data voltage Vdata to N3, and N1 and N2 are connected.

[0230] When the write phase S3 begins, T0 is turned on, and Vdata charges Cst through T0 until T0 is turned off. At this time, the potential of N1 is Vdata + Vth, where Vth is the threshold voltage of T0.

[0231] During the light emission phase S4, EM provides a low voltage signal, and T6 and T7 are turned on;

[0232] When the gray level corresponding to Vdata is greater than or equal to 0 gray level but less than or equal to 128 gray level, in the first control stage S1, ST2 provides a low voltage signal to NT2; in the second control stage S2, ST1 provides a high voltage signal to NT1; in the light emission stage S4, the potential of NT2 is low voltage, the potential of NT1 is high voltage, T22 is turned on, T12 is turned off, and VDD2 is connected to the anode of O1.

[0233] When the gray level corresponding to Vdata is greater than 128 gray levels but less than or equal to 255 gray levels, in the first control stage S1, ST2 provides a high voltage signal to NT2; in the second control stage S2, ST1 provides a low voltage signal to NT1; in the light emission stage S4, the potential of NT1 is low voltage, the potential of NT2 is high voltage, T12 is turned on, T22 is turned off, and VDD1 is connected to the anode of O1.

[0234] The voltage value Vdd1 of the first high voltage signal provided by VDD1 is greater than the voltage value Vdd2 of the second high voltage signal provided by VDD2. Both Vdd1 and Vdd2 can be positive. The difference between the voltage values ​​Vss of the low voltage signals provided by Vdd1 and VSS is greater than the difference between Vdd2 and Vss. This ensures that the voltage across O1 is greater at high grayscale than at low grayscale, thereby reducing power consumption and the occurrence rate of bright spots, and improving the competitiveness of display products.

[0235] In at least one embodiment of this disclosure, during actual display, the same pixel circuit may display both high and low grayscale levels. Therefore, when programming the Gamma voltage, each pixel circuit must program both the high-grayscale Gamma voltage according to Vss2 and the low-grayscale Gamma voltage according to Vss1. During actual display, based on the grayscale value corresponding to the pixel circuit, T12 or T22 is controlled to conduct, thereby controlling the connection between the anode of O1 and VDD1 or VDD2.

[0236] Figure 13 is a schematic diagram of a gamma curve in at least one embodiment of this disclosure.

[0237] In Figure 13, the horizontal axis represents the displayed grayscale, and the vertical axis represents the displayed brightness, with the unit being nits.

[0238] As shown in Figure 13, the low grayscale Gamma voltage is calculated based on Vss1 from grayscale 0 to grayscale 128, and the high grayscale Gamma voltage is calculated based on Vss2 from grayscale 128 to grayscale 255.

[0239] The driving method described in this embodiment is applied to the pixel circuit described above, and the pixel driving method includes:

[0240] During the light-emitting stage, the control circuit controls one of the N voltage terminals to connect with the second electrode of the light-emitting element;

[0241] The voltage values ​​of the voltage signals provided by at least two of the N voltage terminals are different.

[0242] In at least one embodiment of this disclosure, the voltage values ​​of the voltage signals provided by the N voltage terminals are all different.

[0243] In the driving method described in the embodiments of this disclosure, the display grayscale of the pixel circuit is divided into N grayscale ranges; the nth voltage terminal corresponds to the nth grayscale range;

[0244] When the display grayscale of the pixel circuit is in the nth grayscale range during the current frame display time, the control circuit controls the connection between the nth voltage terminal and the second electrode of the light-emitting element during the light-emitting phase included in the current frame display time. This controls the higher display grayscale to correspond to the higher voltage across the light-emitting element, and the lower display grayscale to correspond to the lower voltage across the light-emitting element, thereby reducing power consumption and the occurrence rate of bright spots and improving the competitiveness of display products.

[0245] The display device described in this disclosure includes a plurality of the pixel circuits described above.

[0246] The display device described in at least one embodiment of this disclosure further includes a display control circuit;

[0247] The display grayscale of the pixel circuit is divided into N grayscale ranges; the nth voltage terminal corresponds to the nth grayscale range; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0248] The display control circuit is used to control the control circuit when it is detected that the display grayscale of the pixel circuit is in the nth grayscale range during the current frame display time, so that the control circuit controls the nth voltage terminal to be connected to the second electrode of the light-emitting element during the light-emitting phase included in the current frame display time.

[0249] As shown in FIG14, the display device according to at least one embodiment of the present disclosure includes a pixel circuit and a display control circuit 140;

[0250] The pixel circuit includes a driving circuit 10, a light-emitting element E1, and a control circuit 11; the first electrode of the light-emitting element is the anode, and the second electrode of the light-emitting element is the cathode.

[0251] The driving circuit 10 is electrically connected to the first node N1 and the anode of the light-emitting element E1, respectively, and is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0252] The control circuit 11 is electrically connected to the cathode of the light-emitting element E1, the first voltage terminal V1, and the second high voltage terminal V2, respectively, and is used to control the connection between the first voltage terminal V1 or the second voltage terminal V2 and the cathode of the light-emitting element E1 during the light-emitting stage.

[0253] The first voltage terminal V1 is used to provide a first voltage signal, and the second voltage terminal V2 is used to provide a second voltage signal;

[0254] The voltage value of the first voltage signal is different from the voltage value of the second voltage signal;

[0255] The display grayscale of the pixel circuit is divided into a first grayscale range and a second display grayscale; the first voltage terminal V1 corresponds to the first grayscale range, and the second voltage terminal V2 corresponds to the second grayscale range.

[0256] The display control circuit 140 is electrically connected to the control circuit 11;

[0257] The display control circuit 140 is used to control the control circuit 11 when it is detected that the display grayscale of the pixel circuit is in the first grayscale range during the current frame display time, so that the control circuit 11 controls the first voltage terminal V1 to be connected to the cathode of the light-emitting element E1 during the light-emitting phase included in the current frame display time.

[0258] The display control circuit 140 is further configured to control the control circuit 11 when it is detected that the display grayscale of the pixel circuit is in the second grayscale range during the current frame display time, so that the control circuit 11 controls the second voltage terminal V2 to be connected to the cathode of the light-emitting element E1 during the light-emitting phase included in the current frame display time.

[0259] As shown in FIG15, the display device according to at least one embodiment of the present disclosure includes a pixel circuit and a display control circuit 140;

[0260] The pixel circuit includes a driving circuit 10, a light-emitting element E1, and a control circuit 11; the first electrode of the light-emitting element is a cathode, and the second electrode of the light-emitting element is an anode;

[0261] The driving circuit 10 is electrically connected to the first node N1 and the cathode of the light-emitting element E1, respectively, and is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0262] The control circuit 11 is electrically connected to the anode, the first voltage terminal V1, and the second high voltage terminal V2 of the light-emitting element E1, respectively, and is used to control the connection between the first voltage terminal V1 or the second voltage terminal V2 and the anode of the light-emitting element E1 during the light-emitting stage.

[0263] The first voltage terminal V1 is used to provide a first voltage signal, and the second voltage terminal V2 is used to provide a second voltage signal;

[0264] The voltage value of the first voltage signal is different from the voltage value of the second voltage signal;

[0265] The display grayscale of the pixel circuit is divided into a first grayscale range and a second display grayscale; the first voltage terminal V1 corresponds to the first grayscale range, and the second voltage terminal V2 corresponds to the second grayscale range.

[0266] The display control circuit 140 is electrically connected to the control circuit 11;

[0267] The display control circuit 140 is used to control the control circuit 11 when it is detected that the display grayscale of the pixel circuit is in the first grayscale range during the current frame display time, so that the control circuit 11 controls the first voltage terminal V1 to be connected to the anode of the light-emitting element E1 during the light-emitting phase included in the current frame display time.

[0268] The display control circuit 140 is further configured to control the control circuit 11 when it is detected that the display grayscale of the pixel circuit is in the second grayscale range during the current frame display time, so that the control circuit 11 controls the second voltage terminal V2 to be connected to the anode of the light-emitting element E1 during the light-emitting phase included in the current frame display time.

[0269] In at least one embodiment of this disclosure, the first electrode of the light-emitting element is the anode, and the second electrode of the light-emitting element is the cathode;

[0270] The minimum display gray level in the m-th gray level range is greater than the maximum display gray level in the n-th gray level range, and the voltage value of the m-th voltage signal provided by the m-th voltage terminal is less than the voltage value of the n-th voltage signal provided by the n-th voltage terminal; in order to control the higher display gray level to correspond to the higher voltage across the light-emitting element, and the lower display gray level to correspond to the lower voltage across the light-emitting element, so as to reduce power consumption and bright spot defect rate and improve the competitiveness of display products.

[0271] The m-th voltage terminal corresponds to the m-th grayscale range; m is a positive integer less than or equal to N.

[0272] In at least one embodiment of this disclosure, the first electrode of the light-emitting element is a cathode, and the second electrode of the light-emitting element is an anode;

[0273] The minimum display gray level in the m-th gray level range is greater than the maximum display gray level in the n-th gray level range, and the voltage value of the m-th voltage signal provided by the m-th voltage terminal is greater than the voltage value of the n-th voltage signal provided by the n-th voltage terminal; in order to control the higher display gray level to correspond to the higher voltage across the light-emitting element, and the lower display gray level to correspond to the lower voltage across the light-emitting element, so as to reduce power consumption and bright spot defect rate and improve the competitiveness of display products.

[0274] The m-th voltage terminal corresponds to the m-th grayscale range; m is a positive integer less than or equal to N.

[0275] The display device described in at least one embodiment of this disclosure further includes a source driver; the source driver stores N grayscale-data voltage correspondence tables;

[0276] The nth gray level-data voltage correspondence table records the correspondence between the display gray level in the nth gray level range and the corresponding analog data voltage. The nth gray level-data voltage correspondence table is calculated based on the voltage value of the nth voltage signal provided by the nth voltage terminal.

[0277] The source driver is used to obtain the analog data voltage corresponding to the current display grayscale from the corresponding grayscale-data voltage correspondence table according to the grayscale range of the current display grayscale of the pixel circuit, and to provide the analog data voltage to the pixel circuit.

[0278] In a specific implementation, the display device may further include a source driver, which stores N grayscale-data voltage correspondence tables. The nth grayscale-data voltage correspondence table is calculated based on the nth voltage signal provided by the nth voltage terminal. When the current display grayscale of the pixel circuit is within the nth grayscale range, the source driver obtains the analog data voltage corresponding to the current display grayscale from the nth grayscale-data voltage correspondence table and provides the analog data voltage to the pixel circuit.

[0279] As shown in FIG16, the display device according to at least one embodiment of the present disclosure includes a pixel circuit P0 and a source driver 160;

[0280] The source driver 160 stores N grayscale-data voltage correspondence tables;

[0281] The nth gray level-data voltage correspondence table records the correspondence between the display gray level in the nth gray level range and the corresponding analog data voltage. The nth gray level-data voltage correspondence table is calculated based on the voltage value of the nth voltage signal provided by the nth voltage terminal.

[0282] The source driver 160 is electrically connected to the pixel circuit P0 via the data line DL. It is used to obtain the analog data voltage corresponding to the current display gray level from the corresponding gray level-data voltage correspondence table according to the gray level range of the current display gray level of the pixel circuit P0, and provide the analog data voltage to the pixel circuit P0 via the data line DL.

[0283] In at least one embodiment of this disclosure, when the light-emitting element is an organic light-emitting diode, and the first electrode of the light-emitting element is the anode and the second electrode of the light-emitting element is the cathode,

[0284] As shown in Figure 17A, the backplate includes an anode layer 170 and metal isolation pillars;

[0285] In Figure 17A, the first metal isolation pillar is labeled M1, the second metal isolation pillar is labeled M2, and the third metal isolation pillar is labeled M3.

[0286] As shown in Figure 17B, a red luminescent material layer is fabricated. A first red luminescent material pattern R1 is placed between M1 and M2, a second red luminescent material pattern is placed between M2 and M3, and a third red luminescent material pattern is placed to the right of M3. Then, a cathode layer and a first CVD (chemical vapor deposition) encapsulation layer are sequentially fabricated on the red luminescent material layer. The second and third red luminescent material patterns, as well as the cathode pattern and CVD encapsulation pattern placed above the second and third red luminescent material patterns, are etched away. An organic layer and / or an inorganic layer (not shown in the figure) can be placed between the cathode layer and the first CVD encapsulation layer.

[0287] In Figure 17B, the first red light-emitting material pattern is labeled R1, the first cathode pattern is labeled Y1, and the first CVD encapsulation layer is labeled CV1.

[0288] Next, a layer of green luminescent material is created;

[0289] In Figure 17C, a first green luminescent material pattern is placed between M2 and M3, and a second green luminescent material pattern is placed to the right of M3;

[0290] Subsequently, a cathode layer and a second CVD encapsulation layer are fabricated on the green luminescent material layer. The second green luminescent material pattern, as well as the cathode pattern and CVD encapsulation pattern disposed above the second green luminescent material pattern, are etched away. An organic layer and / or an inorganic layer (not shown in the figure) may be disposed between the cathode layer and the second CVD encapsulation layer.

[0291] In Figure 17C, the pattern labeled G1 is the first green light-emitting material pattern, the pattern labeled Y2 is the second cathode pattern, and the pattern labeled CV2 is the second CVD encapsulation layer.

[0292] Next, a layer of blue luminescent material is created;

[0293] A cathode layer is fabricated on a blue luminescent material layer, followed by a third CVD encapsulation layer; an organic layer and / or an inorganic layer (not shown in the figure) may be disposed between the cathode layer and the third CVD encapsulation layer;

[0294] In Figure 17D, the first blue luminescent material pattern is labeled B1, the third cathode pattern is labeled Y3, and the third CVD encapsulation layer is labeled CV3.

[0295] Subsequently, an IJP layer (a flexible organic layer) and a fourth CVD encapsulation layer are fabricated sequentially above the third CVD encapsulation layer.

[0296] In at least one embodiment of this disclosure, each metal isolation pillar may be electrically connected to a corresponding cathode pattern.

[0297] In at least one embodiment of this disclosure, when the light-emitting element is an organic light-emitting diode, and the first electrode of the light-emitting element is a cathode and the second electrode of the light-emitting element is an anode,

[0298] As shown in Figure 18A, the backplane includes a cathode layer 180 and a metal isolation pillar;

[0299] In Figure 18A, the first metal isolation pillar is labeled M1, the second metal isolation pillar is labeled M2, and the third metal isolation pillar is labeled M3.

[0300] As shown in Figure 18B, a red luminescent material layer is fabricated. A first red luminescent material pattern R1 is placed between M1 and M2, a second red luminescent material pattern is placed between M2 and M3, and a third red luminescent material pattern is placed to the right of M3. Then, an anode layer and a first CVD (chemical vapor deposition) encapsulation layer are sequentially fabricated on the red luminescent material layer. The second red luminescent material pattern, the third red luminescent material pattern, and the anode pattern and CVD encapsulation pattern placed above the second and third red luminescent material patterns are etched away. An organic layer and / or an inorganic layer (not shown in the figure) can be placed between the anode layer and the first CVD encapsulation layer.

[0301] In Figure 18B, the first red luminescent material pattern is labeled R1, the first anode pattern is labeled A1, and the first CVD encapsulation layer is labeled CV1.

[0302] Next, a layer of green luminescent material is created;

[0303] In Figure 18C, a first green luminescent material pattern is placed between M2 and M3, and a second green luminescent material pattern is placed to the right of M3;

[0304] Next, an anode layer and a second CVD encapsulation layer are fabricated on the green luminescent material layer. The second green luminescent material pattern, as well as the anode pattern and CVD encapsulation pattern disposed above the second green luminescent material pattern, are etched away. An organic layer and / or an inorganic layer (not shown in the figure) may be disposed between the anode layer and the second CVD encapsulation layer.

[0305] In Figure 18C, G1 is the pattern of the first green luminescent material, A2 is the pattern of the second anode, and CV2 is the second CVD encapsulation layer.

[0306] Next, a layer of blue luminescent material is created;

[0307] An anode layer is fabricated on a blue luminescent material layer, followed by a third CVD encapsulation layer; an organic layer and / or an inorganic layer (not shown in the figure) may be disposed between the anode layer and the third CVD encapsulation layer;

[0308] In Figure 18D, the first blue luminescent material pattern is labeled B1, the third anode pattern is labeled A3, and the third CVD encapsulation layer is labeled CV3.

[0309] Subsequently, an IJP layer (a flexible organic layer) and a fourth CVD encapsulation layer are fabricated sequentially above the third CVD encapsulation layer.

[0310] In at least one embodiment of this disclosure, each metal isolation pillar may be electrically connected to a corresponding anode pattern.

[0311] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a driving circuit, a light emitting element and a control circuit; the driving circuit is electrically connected with a first node and a first electrode of the light emitting element respectively, and is configured to generate a driving current for driving the light emitting element under control of an electric potential of the first node; the control circuit is electrically connected with a second electrode of the light emitting element and N voltage terminals respectively, and is configured to control communication between one of the N voltage terminals and the second electrode of the light emitting element in a light emitting stage; N is an integer greater than 1; voltage signals provided by at least two of the N voltage terminals have different voltage values.

2. The pixel circuit of claim 1, wherein, voltage signals provided by the N voltage terminals have different voltage values.

3. The pixel circuit of claim 1, wherein, the first electrode of the light emitting element is an anode, and the second electrode of the light emitting element is a cathode; or the first electrode of the light emitting element is a cathode, and the second electrode of the light emitting element is an anode.

4. The pixel circuit of claim 1, wherein, the control circuit comprises N voltage control circuits; the nth voltage control circuit comprises an nth writing module, an nth potential maintaining module and an nth on-off control module; n is a positive integer less than or equal to N; the nth writing module is electrically connected with an nth writing control terminal, an nth on-off control terminal and an nth on-off control node respectively, and is configured to write an nth on-off control signal provided by the nth on-off control terminal into the nth on-off control node under control of an nth writing control signal provided by the nth writing control terminal; the nth potential maintaining module is electrically connected with the nth on-off control node, and is configured to maintain an electric potential of the nth on-off control node; the nth on-off control module is electrically connected with the nth on-off control node, an nth voltage terminal and the second electrode of the light emitting element respectively, and is configured to control communication or disconnection between the nth voltage terminal and the second electrode of the light emitting element under control of an electric potential of the nth on-off control node.

5. The pixel circuit of claim 4, wherein, the nth writing module comprises an nth first transistor, the nth potential maintaining module comprises an nth capacitor, and the nth on-off control module comprises an nth second transistor; a gate of the nth first transistor is electrically connected with the nth writing control terminal, a first electrode of the nth first transistor is electrically connected with the nth on-off control terminal, and a second electrode of the nth first transistor is electrically connected with the nth on-off control node; a first end of the nth capacitor is electrically connected with the nth on-off control node, and a second end of the nth capacitor is electrically connected with a direct current voltage terminal; a gate of the nth second transistor is electrically connected with the nth on-off control node, a first electrode of the nth second transistor is electrically connected with the nth voltage terminal, and a second electrode of the nth second transistor is electrically connected with the second electrode of the light emitting element.

6. The pixel circuit of any one of claims 1 to 5, wherein, the first electrode of the light emitting element is an anode, and the second electrode of light emitting element is a cathode; the pixel circuit further comprises a data writing circuit, a compensation control circuit, a first initialization circuit and an energy storage circuit; a control terminal of the driving circuit is electrically connected with the first node, a first end of the driving circuit is electrically connected with a second node, and a second end of the driving circuit is electrically connected with a third node. The data writing circuit is electrically connected with a scanning end, a data line and the second node respectively, and is configured to write a data voltage provided by the data line into the second node under control of a scanning signal provided by the scanning end; The compensation control circuit is electrically connected with a compensation control end, the first node and the third node respectively, and is configured to control the first node and the third node to be connected or disconnected under control of a compensation control signal provided by the compensation control end; The first initialization circuit is electrically connected with a first initialization control end, a first initialization voltage end and the first node respectively, and is configured to write a first initialization voltage provided by the first initialization voltage end into the first node under control of a first initialization control signal provided by the first initialization control end; The energy storage circuit is electrically connected with the first node, and is configured to maintain the potential of the first node.

7. The pixel circuit of claim 6, wherein, The pixel circuit further comprises a first light emitting control circuit, a second light emitting control circuit and a second initialization circuit; The first light emitting control circuit is electrically connected with a light emitting control end, a power voltage end and the second node respectively, and is configured to control the power voltage end and the second node to be connected under control of a light emitting control signal provided by the light emitting control end in a light emitting stage; The second light emitting control circuit is electrically connected with the light emitting control end, the third node and an anode of the light emitting element respectively, and is configured to control the third node and the anode of the light emitting element to be connected under control of the light emitting control signal in the light emitting stage; The second initialization circuit is electrically connected with a second initialization control end, a second initialization voltage end and the anode of the light emitting element respectively, and is configured to write a second initialization voltage provided by the second initialization voltage end into the anode of the light emitting element under control of a second initialization control signal provided by the second initialization control end.

8. The pixel circuit of any one of claims 1 to 5, wherein, The first pole of the light emitting element is a cathode, and the second pole of the light emitting element is an anode; the pixel circuit further comprises a data writing circuit, a compensation control circuit, a first initialization circuit and an energy storage circuit; The control end of the driving circuit is electrically connected with the first node, the first end of the driving circuit is electrically connected with the second node, and the second end of the driving circuit is electrically connected with the third node; The data writing circuit is electrically connected with a scanning end, a data line and the third node respectively, and is configured to write a data voltage provided by the data line into the third node under control of a scanning signal provided by the scanning end; The compensation control circuit is electricALLY connected with a compensation control end, the first node and the second node respectively, and is configured to control the first node and the second node to be connected or disconnected under control of a compensation control signal provided by the compensation control end; The first initialization circuit is electricALLY connected with a first initialization control end, a first initialization voltage end and the first node respectively, configured to write a first initialization voltage provided by the first initialization voltage end into the first node under the control of a first initialization control signal provided by the first initialization control end; The energy storage circuit is electricALLY connected with the first node, and is configured to maintain the potential of the first node.

9. The pixel circuit of claim 8, wherein, The first light-emitting control circuit, the second light-emitting control circuit and the second initialization circuit are further included. The first light-emitting control circuit is electrically connected with the light-emitting control terminal, the cathode of the light-emitting element and the second node respectively, and is configured to control the communication between the cathode of the light-emitting element and the second node under the control of a light-emitting control signal provided by the light-emitting control terminal in a light-emitting stage. The second light-emitting control circuit is electrically connected with the light-emitting control terminal, the third node and a low-voltage terminal respectively, and is configured to control the communication between the third node and the low-voltage terminal under the control of the light-emitting control signal in the light-emitting stage. The second initialization circuit is electrically connected with a second initial control terminal, a second initial voltage terminal and the cathode of the light-emitting element respectively, and is configured to write a second initial voltage provided by the second initial voltage terminal into the cathode of the light-emitting element under the control of a second initial control signal provided by the second initial control terminal.

10. A driving method applied to the pixel circuit according to any one of claims 1 to 9, the pixel driving method comprising: in a light-emitting stage, the control circuit controls the communication between one of the N voltage terminals and the second electrode of the light-emitting element; the voltage values of the voltage signals provided by at least two of the N voltage terminals are different.

11. The driving method of claim 10, wherein, The voltage values of the voltage signals provided by the N voltage terminals are different.

12. A display device comprising a plurality of pixel circuits according to any one of claims 1 to 9.

13. The display device of claim 12, wherein, The display control circuit is further included. The display gray scale of the pixel circuit is divided into N gray scale ranges; the nth voltage terminal corresponds to the nth gray scale range; N is an integer greater than 1, and n is a positive integer less than or equal to N; The display control circuit is configured to control the control circuit when it is detected that the display gray scale of the pixel circuit is in the nth gray scale range at a current frame display time, so that the control circuit controls the communication between the nth voltage terminal and the second electrode of the light-emitting element in the light-emitting stage included in the current frame display time.

14. The display device of claim 13, wherein, The first electrode of the light-emitting element is an anode, and the second electrode of the light-emitting element is a cathode; The minimum display gray scale in the mth gray scale range is greater than the maximum display gray scale in the nth gray scale range, and the voltage value of the mth voltage signal provided by the mth voltage terminal is less than the voltage value of the nth voltage signal provided by the nth voltage terminal; The mth voltage terminal corresponds to the mth gray scale range; m is a positive integer less than or equal to N.

15. The display device of claim 13, wherein, The first electrode of the light-emitting element is a cathode, and the second electrode of the light-emitting element is an anode; The minimum display gray scale in the mth gray scale range is greater than the maximum gray scale in the nth gray scale range, and the voltage value of the mth voltage signal is greater than the voltage value of the nth voltage signal provided by the nth voltage terminal; The mth gray scale range corresponds to the mth voltage terminal; m is a positive integer less than or equal to N.

16. A display device as claimed in any one of claims 13 to 15, wherein, The source driver is further included, and N gray scale-data voltage corresponding tables are stored in the source driver. The nth gray scale-data voltage correspondence table records the correspondence between the display gray scale in the nth gray scale range and the corresponding analog data voltage, and is calculated according to the voltage value of the nth voltage signal provided by the nth voltage terminal; The source driver is configured to obtain the analog data voltage corresponding to the current display gray scale of the pixel circuit from the corresponding gray scale-data voltage correspondence table according to the gray scale range in which the current display gray scale is located, and provide the analog data voltage to the pixel circuit.

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