Display panel and driving method therefor

Abstract

Disclosed in the present application are a display panel and a driving method therefor. The display panel comprises a plurality of pixel driving circuits, each pixel driving circuit comprising a switching transistor, a driving transistor, a write control transistor and a compensation transistor, wherein the switching transistor comprises a first electrode connected to a data signal, a second electrode connected to a first node, and a control electrode connected to a first scan control signal; the driving transistor comprises a first electrode connected to the first node, a second electrode connected to a second node, and a control electrode connected to a third node; the write control transistor comprises a first electrode connected to the second node, a second electrode connected to a first electrode of the compensation transistor, and a control electrode connected to a control signal; and the compensation transistor comprises a first electrode connected to the second electrode of the write control transistor, a second electrode connected to the third node, and a control electrode connected to a second scan control signal.

Description

Display panel and its driving method

[0001] This application claims priority to Chinese patent application No. 202411856368.8, filed on December 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, specifically to a display panel and its driving method. Background Technology

[0003] With the development of display technology, users have increasingly higher requirements for the display effect of display panels. Related technologies divide the display panel vertically into multiple display areas by controlling the writing and transmission of scan signals, with each area exhibiting a different pixel refresh rate. Although display areas with higher pixel refresh rates consume more power, display areas with lower pixel refresh rates consume less power, thus improving the display effect while minimizing the overall power consumption of the display panel. Invention Overview

[0004] By controlling the writing and transmission of the scanning signal, only the pixel refresh rate of the display panel in the vertical direction can be adjusted.

[0005] This application provides a display panel and its driving method, which enables the display panel to achieve different pixel refresh rates in different display areas both horizontally and vertically.

[0006] In a first aspect, embodiments of this application provide a display panel, the display panel including a plurality of pixel driving circuits, each pixel driving circuit including a switching transistor, a driving transistor, a write control transistor, and a compensation transistor; wherein, the switching transistor includes a first terminal connected to a data signal, a second terminal connected to a first node, and a control terminal connected to a first scan control signal; the driving transistor includes a first terminal connected to the first node, a second terminal connected to a second node, and a control terminal connected to a third node; the write control transistor includes a first terminal connected to the second node, a second terminal connected to the first terminal of the compensation transistor, and a control terminal connected to a control signal; and the compensation transistor includes a first terminal connected to the second terminal of the write control transistor, a second terminal connected to the third node, and a control terminal connected to a second scan control signal; wherein, the write control transistor is used to control whether the data signal is written to the third node according to the control signal.

[0007] Secondly, embodiments of this application provide a driving method for a display panel, wherein the display panel includes a plurality of pixel driving circuits, each pixel driving circuit including a switching transistor, a driving transistor, a write control transistor, and a compensation transistor; the switching transistor includes a first terminal connected to a data signal, a second terminal connected to a first node, and a control terminal connected to a first scan control signal; the driving transistor includes a first terminal connected to the first node, a second terminal connected to a second node, and a control terminal connected to a third node; the write control transistor includes a first terminal connected to the second node, a second terminal connected to the first terminal of the compensation transistor, and a control terminal connected to a control signal; and the compensation transistor includes a first terminal connected to the second terminal of the write control transistor, a second terminal connected to the third node, and a control terminal connected to a second scan control signal; wherein the driving method includes: the write control transistor controlling whether the data signal is written to the third node according to the control signal. Attached Figure Description

[0008] Figure 1 is a schematic diagram of a pixel driving circuit provided in an embodiment of this application;

[0009] Figure 2 is a schematic diagram of another pixel driving circuit provided in an embodiment of this application;

[0010] Figure 3 is a schematic diagram of a driving timing provided in an embodiment of this application;

[0011] Figure 4 is a schematic diagram of a display panel provided in an embodiment of this application;

[0012] Figure 5 is a schematic diagram of a pixel driving circuit;

[0013] Figure 6 is a schematic diagram of another pixel driving circuit;

[0014] Figure 7 is a schematic diagram of another display panel provided in an embodiment of this application;

[0015] Figure 8 is a flowchart of a display panel driving method provided in an embodiment of this application;

[0016] Figure 9 is a flowchart of another display panel driving method provided in an embodiment of this application;

[0017] Figure 10 is a flowchart of another display panel driving method provided in an embodiment of this application. Embodiments of the present invention

[0018] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0019] Furthermore, in the embodiments of this application, "multiple" refers to two or more. The terms "first" and "second," etc., in the embodiments of this application are used to distinguish different technical features and do not indicate any order, quantity, or importance.

[0020] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0021] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.

[0022] Please refer to Figure 1, which is a schematic diagram of a pixel driving circuit provided in an embodiment of this application. As shown in Figure 1, the pixel driving circuit includes a switching transistor T2, a driving transistor T1, a write control transistor T9, and a compensation transistor T3.

[0023] Switching transistor T2 includes a first terminal connected to the data signal DATA, a second terminal connected to the first node A, and a control terminal connected to the first scan control signal PSCAN. Compensation transistor T3 includes a first terminal connected to the first node A, a second terminal connected to the second node B, and a control terminal connected to the third node Q. Write control transistor T9 includes a first terminal connected to the second node B, a second terminal connected to the first terminal of compensation transistor T3, and a control terminal connected to the control signal Control. Compensation transistor T3 includes a first terminal connected to the second terminal of write control transistor T9, a second terminal connected to the third node Q, and a control terminal connected to the second scan control signal NSCAN_T3.

[0024] The write control transistor T9 is kept either on or off according to the control signal Control. When the write control transistor T9 is on, if the compensation transistor T3 is also on, the channel between the second node B and the third node Q is open, and the data signal DATA can be written to the third node Q. When the write control transistor T9 is off, regardless of whether the compensation transistor T3 is on or off, the channel between the second node B and the third node Q is closed, and the data signal DATA cannot be written to the third node Q. Therefore, the write control transistor T9 can control whether the data signal DATA is written to the third node Q according to the control signal Control.

[0025] In some embodiments, as shown in FIG1, the pixel driving circuit further includes a reset control transistor T10 and a first reset transistor T4.

[0026] The reset control transistor T10 includes a first terminal connected to the first reset signal VI_T4_2, a second terminal connected to the first terminal of the first reset transistor T4, and a control terminal connected to the control signal Control. The first reset transistor T4 includes a first terminal connected to the second terminal of the reset control transistor T10, a second terminal connected to the third node Q, and a control terminal connected to the third scan control signal NSCAN_T4.

[0027] The reset control transistor T10 is kept either on or off according to the control signal Control. When the reset control transistor T10 is on, if the first reset transistor T4 is on, the third node Q can be reset via the first reset signal VI_T4_2. When the reset control transistor T10 is off, regardless of whether the first reset transistor T4 is on or off, the first reset signal VI_T4_2 cannot reach the third node Q, thus preventing the third node Q from being reset. Therefore, the reset control transistor T10 is used to control whether the third node Q is reset according to the control signal Control.

[0028] In some embodiments, the write control transistor T9 and the reset control transistor T10 in a pixel driving circuit are both N-type thin film transistors (NTFTs) or both are P-type thin film transistors (PTFTs). Figure 1 shows an example where the write control transistor T9 and the reset control transistor T10 are N-type thin film transistors.

[0029] Referring to Figure 1, the pixel driving circuit also includes a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a light-emitting device.

[0030] The first light-emitting control transistor T5 includes a first terminal connected to a high-potential signal VDD, a second terminal connected to a first node A, and a control terminal connected to a light-emitting control signal EM1. The second light-emitting control transistor T6 includes a first terminal connected to a second node B, a second terminal connected to a fourth node C, and a control terminal connected to a light-emitting control signal EM1. The light-emitting device includes an anode connected to the fourth node C and a cathode connected to a low-potential signal VSS. During the light-emitting phase, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the current flowing through the driving transistor T1 can pass through the second node B and the fourth node C, thereby driving the light-emitting device to emit light.

[0031] Referring to Figure 1, the pixel driving circuit further includes a second reset transistor T7 and a third reset transistor T8. The second reset transistor T7 includes a first terminal connected to the second reset signal VI_A_3, a second terminal connected to the fourth node C, and a control terminal connected to the fourth scan control signal PSCAN2. The third reset transistor T8 includes a first terminal connected to the third reset signal VI_T8_1, a second terminal connected to the first node A, and a control terminal connected to the fourth scan control signal PSCAN2.

[0032] Referring to Figure 1, the pixel driving circuit further includes a storage capacitor Cst and a boost capacitor Cboost. The storage capacitor Cst includes one end connected to a high-potential signal and the other end connected to the third node Q. The boost capacitor Cboost includes one end connected to the first scan control signal PSCAN and the other end connected to the third node Q.

[0033] Please refer to Figure 2, which is a schematic diagram of a pixel driving circuit provided in an embodiment of this application. The difference between the pixel driving circuit shown in Figure 2 and the pixel driving circuit shown in Figure 1 is that the pixel driving circuit shown in Figure 2 resets the third node Q through the second node B.

[0034] Referring to Figure 2, the pixel driving circuit includes a switching transistor T2, a driving transistor T1, a write control transistor T9, and a compensation transistor T3. The switching transistor T2 includes a first terminal connected to the data signal DATA, a second terminal connected to the first node A, and a control terminal connected to the first scan control signal PSCAN. The compensation transistor T3 includes a first terminal connected to the first node A, a second terminal connected to the second node B, and a control terminal connected to the third node Q. The write control transistor T9 includes a first terminal connected to the second node B, a second terminal connected to the first terminal of the compensation transistor T3, and a control terminal connected to the control signal Control. The compensation transistor T3 includes a first terminal connected to the second terminal of the write control transistor T9, a second terminal connected to the third node Q, and a control terminal connected to the second scan control signal NSCAN_T3. The write control transistor T9 can control whether the data signal DATA is written to the third node Q according to the control signal Control. In some embodiments, the write control transistor T9 can be an N-type thin-film transistor or a P-type thin-film transistor. Figure 2 uses an N-type thin-film transistor as an example for the write control transistor T9.

[0035] Referring to Figure 2, the pixel driving circuit further includes a first reset transistor T4. The first reset transistor T4 includes a first terminal connected to the first reset signal VI_T4_2, a second terminal connected to the second node B, and a control terminal connected to the third scan control signal NSCAN_T4.

[0036] Referring to Figure 2, the pixel driving circuit further includes a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a light-emitting device. The first light-emitting control transistor T5 includes a first terminal connected to a high-potential signal VDD, a second terminal connected to a first node A, and a control terminal connected to a light-emitting control signal EM1. The second light-emitting control transistor T6 includes a first terminal connected to a second node B, a second terminal connected to a fourth node C, and a control terminal connected to the light-emitting control signal EM1. The light-emitting device includes an anode terminal connected to the fourth node C and a cathode terminal connected to a low-potential signal VSS.

[0037] Referring to Figure 2, the pixel driving circuit further includes a second reset transistor T7 and a third reset transistor T8. The second reset transistor T7 includes a first terminal connected to the second reset signal VI_A_3, a second terminal connected to the fourth node C, and a control terminal connected to the fourth scan control signal PSCAN2. The third reset transistor T8 includes a first terminal connected to the third reset signal VI_T8_1, a second terminal connected to the first node A, and a control terminal connected to the fourth scan control signal PSCAN2.

[0038] Referring to Figure 2, the pixel driving circuit also includes a storage capacitor Cst and a boost capacitor Cboost. The storage capacitor Cst includes one end connected to a high-potential signal and the other end connected to the third node Q. The boost capacitor Cboost includes one end connected to the first scan control signal PSCAN and the other end connected to the third node Q.

[0039] In some embodiments, the control electrode may be the gate, the first electrode may be one of the source or the drain, and the second electrode may be the other of the source or the drain.

[0040] It should be understood that in Figures 1 and 2, the switching transistor T2, driving transistor T1, second reset transistor T7, third reset transistor T8, first light-emitting control transistor T5 and second light-emitting control transistor T6 are P-type thin-film transistors, and the compensation transistor T3 and first reset transistor T4 are N-type thin-film transistors. However, this does not constitute a limitation on the embodiments of this application. In practical applications, each transistor can be arbitrarily set to N-type or P-type thin-film transistors in conjunction with the driving timing.

[0041] Please refer to Figure 3, which is a schematic diagram of a driving timing provided in an embodiment of this application. The driving timing shown in Figure 3 is used to drive the corresponding devices in the pixel driving circuits shown in Figures 1 and 2.

[0042] One frame of display time can be divided into a data writing phase and a light emission phase. During the light emission phase, the light emission control signal EM1 is low, and the first light emission control transistor T5 and the second light emission control transistor T6 are turned on. During the data writing phase, the light emission control signal EM1 is high, and the first light emission control transistor T5 and the second light emission control transistor T6 are turned off. When the control signal Control is high and the second scan control signal NSCAN_T3 is high, the channel between the second node B and the third node Q is open, and the data signal DATA can be written to the third node Q. When the control signal Control is low, because the write control transistor T9 is turned off, the channel between the second node B and the third node Q is closed, and the data signal cannot be written to the third node Q.

[0043] This application embodiment can adjust the pixel refresh rate by setting the high-level duration and low-level duration of a control signal, so that data writing is not always performed within a single display frame. For example, referring to FIG3, the first control signal Control1 can be used to ensure that data writing is performed within one display frame and not within the other, thereby reducing the pixel refresh rate by half. As another example, referring to FIG3, the second control signal Control2 can be used to ensure that data writing is performed within one display frame and not within the other two, thereby reducing the pixel refresh rate by two-thirds.

[0044] Based on this, assuming that the write control transistor T9 and the reset control transistor T10 remain on during the first level duration of the control signal Control and remain off during the second level duration of the control signal Control, the larger the ratio of the first level duration to the second level duration of the control signal Control, the higher the pixel refresh rate of the pixel driving circuit. Specifically, if both the write control transistor T9 and the reset control transistor T10 are N-type thin-film transistors, the first level of the control signal is greater than the second level; for example, the first level is high and the second level is low. If both the write control transistor T9 and the reset control transistor T10 are P-type thin-film transistors, the first level of the control signal is less than the second level; for example, the first level is low and the second level is high.

[0045] Please refer to Figure 4, which is a schematic diagram of a display panel provided in an embodiment of this application.

[0046] Referring to FIG4, the display panel 1000 may include a plurality of pixel driving circuits 1100. In this embodiment, the pixel driving circuit 1100 may include a pixel driving circuit 1110, which can be referred to FIG1 or FIG2. For a description of the pixel driving circuit 1110, please refer to the above embodiments, and it will not be repeated here. In some embodiments, the pixel driving circuit 1100 may also include a primary pixel driving circuit 1120, which can be referred to FIG5 or FIG6. The description of each device in the primary pixel driving circuit 1120 and its connection relationship can be referred to the embodiments of FIG1 to FIG3 above, and it will not be repeated here.

[0047] In some embodiments, the display panel 1000 may include at least two display areas 1200, at least one display area 1200 including a pixel driving circuit 1110, and the remaining display areas 1200 may include a raw pixel driving circuit 1120.

[0048] For example, referring to FIG4, the display panel 1000 may include a first display area 1210, a second display area 1220, and a third display area 1230. At least one display area 1200 includes a pixel driving circuit 1110, and the pixel driving circuits 1100 included in a display area 1200 are of the same type. For example, referring to FIG4, the pixel driving circuits in the first display area 1210 are all pixel driving circuits 1110, the pixel driving circuits in the second display area 1220 are all pixel driving circuits 1110, and the pixel driving circuits in the third display area 1230 are all original pixel driving circuits 1120.

[0049] In some embodiments, the display panel includes a first display area and a second display area, both of which include a pixel driving circuit. The control signal connected to the pixel driving circuit in the first display area is a first control signal, and the control signal connected to the pixel driving circuit in the second display area is a second control signal. The first control signal and the second control signal are different control signals.

[0050] In some embodiments, the write control transistor and reset control transistor in the pixel driving circuit remain on during the first level duration of the control signal and remain off during the second level duration of the control signal. If the ratio of the first level duration to the second level duration of the first control signal is greater than the ratio of the first level duration to the second level duration of the second control signal, then the pixel refresh frequency of the first display area is greater than the pixel refresh frequency of the second display area.

[0051] For example, referring to FIG4, the pixel driving circuit 1110 in the first display area 1210 of the display panel 1000 is connected to the first control signal Control1, and the pixel driving circuit 1110 in the second display area 1220 is connected to the second control signal Control2. The first control signal Control1 and the second control signal Control2 are different control signals. For example, based on the first control signal Control1 and the second control signal Control2 shown in FIG3, the pixel refresh rate of the first display area 1210 is reduced by half, and the pixel refresh rate of the second display area 1220 is reduced by two-thirds. For example, referring to FIG7, the pixel refresh rate of the third display area 1230 is 120Hz; the first display area 1210 reduces its pixel refresh rate to 60Hz through the first control signal Control1 shown in FIG3; the second display area 1220 reduces its pixel refresh rate to 40Hz through the second control signal Control2 shown in FIG3.

[0052] In summary, the display panel provided in this application embodiment includes a pixel driving circuit, in which a write control transistor is connected in series next to a compensation transistor. The write control transistor remains on or off according to a control signal. When the write control transistor is on, if the compensation transistor is on, the channel between the second and third nodes is open; when the write control transistor is off, the channel between the second and third nodes is off regardless of whether the compensation transistor is on. Therefore, the write control transistor in the pixel driving circuit of this application embodiment can control whether to perform data writing according to a control signal, that is, whether the data signal is written to the third node, thereby achieving flexible adjustment of the pixel refresh rate. Furthermore, this application embodiment can set the pixel driving circuit in the display area of ​​the display panel where the pixel refresh rate needs to be adjusted, so as to achieve adjustment of the pixel refresh rate of this part of the display area, thereby making different display areas of the display panel present different pixel refresh rates. In addition, by adding a write control transistor to the pixel driving circuit and controlling whether to perform data writing according to a control signal, this application embodiment is not constrained by the vertical direction of the scan signal, and can enable the display panel to achieve the effect of different display areas presenting different pixel refresh rates in both the horizontal and vertical directions.

[0053] Accordingly, embodiments of this application also provide a method for driving a display panel.

[0054] The display panel includes multiple pixel driving circuits. Each pixel driving circuit includes a switching transistor, a driving transistor, a write control transistor, and a compensation transistor. The switching transistor includes a first terminal connected to a data signal, a second terminal connected to a first node, and a control terminal connected to a first scan control signal. The driving transistor includes a first terminal connected to a first node, a second terminal connected to a second node, and a control terminal connected to a third node. The write control transistor includes a first terminal connected to a second node, a second terminal connected to the first terminal of the compensation transistor, and a control terminal connected to a control signal. The compensation transistor includes a first terminal connected to the second terminal of the write control transistor, a second terminal connected to the third node, and a control terminal connected to a second scan control signal.

[0055] Referring to Figure 8, the driving method for the display panel includes step 810.

[0056] Step 810: The write control transistor controls whether the data signal is written to the third node according to the control signal.

[0057] In some embodiments, step 810 includes: the write control transistor remaining on for a first level duration of the control signal to conduct the channel between the second node and the third node when the compensation transistor is on; and the write control transistor remaining off for a second level duration of the control signal to turn off the channel between the second node and the third node. The data signal is written to the third node after flowing through the channel between the second node and the third node.

[0058] In some embodiments, if the write control transistor is an N-type thin-film transistor, the first level of the control signal is greater than the second level; if the write control transistor is a P-type thin-film transistor, the first level of the control signal is less than the second level.

[0059] In some embodiments, each pixel driving circuit further includes a reset control transistor and a first reset transistor. The reset control transistor includes a first terminal connected to a first reset signal, a second terminal connected to the first terminal of the first reset transistor, and a control terminal connected to a control signal. The first reset transistor includes a first terminal connected to the second terminal of the reset control transistor, a second terminal connected to a third node, and a control terminal connected to a third scan control signal.

[0060] Referring to FIG9, the driving method of the display panel further includes step 820.

[0061] Step 820: The reset control transistor controls whether the third node is reset according to the control signal.

[0062] In some embodiments, the write control transistor and the reset control transistor in a pixel driving circuit are both N-type thin-film transistors or both P-type thin-film transistors.

[0063] In some embodiments, step 820 includes: the reset transistor remaining on for a first level duration of the control signal to conduct the channel between the first reset signal and the third node when the first reset transistor is on; and the reset transistor remaining off for a second level duration of the control signal to turn off the channel between the first reset signal and the third node.

[0064] It should be understood that step 820 may be performed before or after step 810, and the order of execution of the steps in Figure 9 does not constitute a limitation of this application.

[0065] In some embodiments, the display panel includes a first display area and a second display area, both of which include pixel driving circuits.

[0066] Referring to FIG10, the driving method of the display panel further includes steps 830 and 840.

[0067] Step 830: Drive the pixel driving circuit in the first display area according to the first control signal;

[0068] Step 840: Drive the pixel driving circuit in the second display area according to the second control signal.

[0069] The first control signal and the second control signal are different control signals.

[0070] It should be understood that steps 830 and 840 can be performed simultaneously, and the execution order of the steps in Figure 10 does not constitute a limitation on this application.

[0071] In some embodiments, the write control transistor remains on for a first level duration of the control signal and remains off for a second level duration of the control signal; wherein, if the ratio of the first level duration to the second level duration of the first control signal is greater than the ratio of the first level duration to the second level duration of the second control signal, then the pixel refresh frequency of the first display area is greater than the pixel refresh frequency of the second display area.

[0072] For details on the specific implementation methods and corresponding beneficial effects of each of the above operations, please refer to the detailed description of the pixel driving circuit, driving timing and display panel above, which will not be repeated here.

[0073] The above provides a detailed description of a display panel and its driving method according to embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, the display panel comprising a plurality of pixel driving circuits, each pixel driving circuit comprising a switching transistor, a driving transistor, a write control transistor, and a compensation transistor; wherein, The switching transistor includes a first electrode that receives a data signal, a second electrode that is connected to a first node, and a control electrode that receives a first scan control signal. The driving transistor includes a first electrode connected to the first node, a second electrode connected to the second node, and a control electrode connected to the third node; The write control transistor includes a first terminal connected to the second node, a second terminal connected to the first terminal of the compensation transistor, and a control terminal that receives control signals. as well as The compensation transistor includes a first terminal connected to the second terminal of the write control transistor, a second terminal connected to the third node, and a control terminal connected to the second scan control signal; The write control transistor is used to control whether the data signal is written to the third node according to the control signal.

2. The display panel according to claim 1, wherein, Each of the pixel driving circuits further includes a first reset transistor; The first reset transistor includes a first electrode connected to a first reset signal, a second electrode connected to the second node, and a control electrode connected to a third scan control signal.

3. The display panel according to claim 1, wherein, Each of the pixel driving circuits further includes a reset control transistor and a first reset transistor; The reset control transistor includes a first terminal connected to a first reset signal, a second terminal connected to the first terminal of the first reset transistor, and a control terminal connected to the control signal. as well as The first reset transistor includes a first terminal connected to the second terminal of the reset control transistor, a second terminal connected to the third node, and a control terminal connected to the third scan control signal; The reset control transistor is used to control whether the third node is reset according to the control signal.

4. The display panel according to claim 3, wherein, In one of the pixel driving circuits, both the write control transistor and the reset control transistor are either N-type thin-film transistors or both are P-type thin-film transistors.

5. The display panel according to claim 1, wherein, Each pixel driving circuit further includes a first light-emitting control transistor, a second light-emitting control transistor, and a light-emitting device; The first light-emitting control transistor includes a first electrode connected to a high-potential signal, a second electrode connected to the first node, and a control electrode connected to a light-emitting control signal; The second light-emitting control transistor includes a first electrode connected to the second node, a second electrode connected to the fourth node, and a control electrode that receives the light-emitting control signal; and The light-emitting device includes an anode connected to the fourth node and a cathode connected to a low-potential signal.

6. The display panel according to claim 1, wherein, Each of the pixel driving circuits further includes a second reset transistor and a third reset transistor; The second reset transistor includes a first terminal connected to a second reset signal, a second terminal connected to the fourth node, and a control terminal connected to a fourth scan control signal; as well as The third reset transistor includes a first electrode connected to a third reset signal, a second electrode connected to the first node, and a control electrode connected to a fourth scan control signal.

7. The display panel according to claim 1, wherein, Each of the pixel driving circuits also includes a storage capacitor; The storage capacitor includes one end connected to a high-potential signal and the other end connected to the third node.

8. The display panel according to claim 1, wherein, Each of the pixel driving circuits also includes a boost capacitor; The boost capacitor includes one end connected to the first scan control signal and the other end connected to the third node.

9. The display panel according to claim 1, wherein, The display panel includes at least two display areas, and at least one of the display areas includes the pixel driving circuit.

10. The display panel according to claim 9, wherein, The display panel includes a first display area and a second display area, and both the first display area and the second display area include the pixel driving circuit. Wherein, the control signal connected to the pixel driving circuit in the first display area is a first control signal, and the control signal connected to the pixel driving circuit in the second display area is a second control signal; the first control signal and the second control signal are different control signals.

11. The display panel according to claim 10, wherein, The write control transistor remains on during the first level duration of the control signal and remains off during the second level duration of the control signal; Wherein, if the ratio of the duration of the first level to the duration of the second level of the first control signal is greater than the ratio of the duration of the first level to the duration of the second level of the second control signal, then the pixel refresh frequency of the first display area is greater than the pixel refresh frequency of the second display area.

12. The display panel according to claim 11, wherein, If the write control transistor is an N-type thin-film transistor, then the first level of the control signal is greater than the second level; and if the write control transistor is a P-type thin-film transistor, then the first level of the control signal is less than the second level.

13. A method for driving a display panel, wherein, The display panel includes multiple pixel driving circuits, each of which includes a switching transistor, a driving transistor, a write control transistor, and a compensation transistor. The switching transistor includes a first terminal for receiving a data signal, a second terminal connected to a first node, and a control terminal for receiving a first scan control signal. The driving transistor includes a first terminal connected to the first node, a second terminal connected to a second node, and a control terminal connected to a third node. The write control transistor includes a first terminal connected to the second node, a second terminal connected to the first terminal of the compensation transistor, and a control terminal for receiving a control signal. The compensation transistor includes a first terminal connected to the second terminal of the write control transistor, a second terminal connected to the third node, and a control terminal connected to the second scan control signal; The driving method includes: The write control transistor controls whether the data signal is written to the third node according to the control signal.

14. The driving method according to claim 13, wherein, The write control transistor controls whether the data signal is written to the third node according to the control signal, including: The write control transistor remains on during the first level duration of the control signal to enable the channel between the second node and the third node when the compensation transistor is on; and The write control transistor remains off during the duration of the second level of the control signal to shut down the channel between the second node and the third node; The data signal is written to the third node after flowing through the channel between the second node and the third node.

15. The driving method according to claim 14, wherein, If the write control transistor is an N-type thin-film transistor, then the first level of the control signal is greater than the second level; and if the write control transistor is a P-type thin-film transistor, then the first level of the control signal is less than the second level.

16. The driving method according to claim 13, wherein, Each pixel driving circuit further includes a reset control transistor and a first reset transistor; the reset control transistor includes a first terminal connected to a first reset signal, a second terminal connected to the first terminal of the first reset transistor, and a control terminal connected to the control signal; the first reset transistor includes a first terminal connected to the second terminal of the reset control transistor, a second terminal connected to the third node, and a control terminal connected to the third scan control signal. The driving method further includes: The reset control transistor controls whether the third node is reset according to the control signal.

17. The driving method according to claim 16, wherein, In one of the pixel driving circuits, both the write control transistor and the reset control transistor are either N-type thin-film transistors or both are P-type thin-film transistors.

18. The driving method according to claim 16, wherein, The reset control transistor controls whether the third node is reset according to the control signal, including: The reset transistor remains on during the first level duration of the control signal, so as to open the channel between the first reset signal and the third node when the first reset transistor is on; and The reset transistor remains off for the duration of the second level of the control signal to shut off the channel between the first reset signal and the third node.

19. The driving method according to claim 13, wherein, The display panel includes a first display area and a second display area, and both the first display area and the second display area include the pixel driving circuit. The driving method further includes: The pixel driving circuit in the first display area is driven according to the first control signal; The pixel driving circuit in the second display area is driven according to the second control signal; Wherein, the first control signal and the second control signal are different control signals.

20. The driving method according to claim 19, wherein, The write control transistor remains on during the first level duration of the control signal and remains off during the second level duration of the control signal; Wherein, if the ratio of the duration of the first level to the duration of the second level of the first control signal is greater than the ratio of the duration of the first level to the duration of the second level of the second control signal, then the pixel refresh frequency of the first display area is greater than the pixel refresh frequency of the second display area.

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