Gate drive circuit and display device

Abstract

Provided in the present application are a gate drive circuit and a display device. The gate drive circuit comprises a plurality of cascaded gate drive stage circuits, each of which comprises a first / second / third output circuit for transmitting a signal of a first / second / third input terminal to a first / second / third output terminal on the basis of a signal of a first / second / third control terminal to form a first / second / third gate signal, wherein at least one of the pulse width and the active potential of any one of the three gate signals is different from that of the other two.

Description

Gate driving circuit and display device

[0001] This application claims priority to Chinese patent application No. 202411901005.1, filed on December 20, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, specifically to gate driving circuits and display devices. Background Technology

[0003] To improve issues such as color shift in display devices, gate drivers need to generate a variety of gate signals to control pixel circuits. In the prior art, each gate driving circuit generally generates one type of gate signal, which requires setting up a variety of gate driving circuits to generate multiple gate signals, resulting in high power consumption of the gate driver. Invention Overview

[0004] Embodiments of this application provide a gate driving circuit and a display device, which are at least used to reduce the power consumption of the gate driver.

[0005] In a first aspect, this application provides a gate driving circuit, comprising a plurality of cascaded gate driving stage circuits, wherein the gate driving stage circuit includes:

[0006] The first output circuit includes a first control terminal, a first input terminal and a first output terminal, and is used to transmit the signal of the first input terminal to the first output terminal according to the signal of the first control terminal to form a first gate signal.

[0007] The second output circuit includes a second control terminal, a second input terminal, and a second output terminal, and is used to transmit the signal from the second input terminal to the second output terminal according to the signal from the second control terminal to form a second gate signal.

[0008] The third output circuit includes a third control terminal, a third input terminal and a third output terminal, and is used to transmit the signal of the third input terminal to the third output terminal according to the signal of the third control terminal to form a third gate signal.

[0009] The control circuit is used to control the signals of the first control terminal, the second control terminal, and the third control terminal according to the frame start signal or the signal of the output terminal of the gate drive stage circuit of the previous i stages, the first clock signal, and the power supply signal, where i is a positive integer;

[0010] Wherein, at least one of the pulse width and effective potential of any one of the first gate signal, the second gate signal, and the third gate signal is different from at least one of the pulse width and effective potential of the other two of the first gate signal, the second gate signal, and the third gate signal.

[0011] Secondly, embodiments of this application provide a display device, comprising a plurality of sub-pixels, a plurality of first gate lines, a plurality of second gate lines, a plurality of third gate lines, and a gate driving circuit as described in any one of claims 1 to 17, wherein the plurality of sub-pixels are arranged into a plurality of sub-pixel groups.

[0012] The first output terminal is electrically connected to the corresponding two first gate lines to drive the corresponding two sub-pixel groups;

[0013] The second output terminal is electrically connected to the two second gate lines corresponding to the two sub-pixel groups;

[0014] The third output terminal is electrically connected to a third gate line corresponding to one of the two sub-pixel groups.

[0015] Thirdly, embodiments of this application also provide another display device, comprising a plurality of sub-pixels, a plurality of first gate lines, a plurality of second gate lines, a plurality of third gate lines, and a gate driving circuit as described in any one of claims 1 to 17, wherein the plurality of sub-pixels are arranged into a plurality of sub-pixel groups.

[0016] The first output terminal is electrically connected to a corresponding first gate line to drive a corresponding sub-pixel group;

[0017] The second output terminal is electrically connected to a second gate line corresponding to one of the sub-pixel groups;

[0018] The third output terminal is electrically connected to a third gate line corresponding to one of the sub-pixel groups.

[0019] Beneficial effects: This application provides a gate driving circuit and a display device, wherein the gate driving circuit includes multiple cascaded gate driving stage circuits. The gate driving stage circuit includes a control circuit, a first output circuit, a second output circuit, and a third output circuit. By configuring the control circuit to control the signals of the control terminals of the three output circuits according to the frame start signal or the signal of the output terminal of the previous i-stage gate driving stage circuit, a first clock signal, and a power supply signal, the three output circuits transmit the signals of their input terminals to the three gate signals of their respective output terminals according to their respective control terminals. At least one of the pulse width and effective potential of any one of them is different from at least one of the pulse width and effective potential of the other two. Thus, while generating multiple gate signals, it is possible to avoid increasing the number of clock signal groups and the number of gate driving stage circuits, thereby saving the power consumption of the gate driving circuit and reducing the bezel size of the display device. Attached Figure Description

[0020] The present application will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for explaining some embodiments of the present application. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0021] Figures 1 and 3 are block diagrams of the gate drive stage circuit provided in the embodiments of the present invention.

[0022] Figures 2 and 4 are circuit diagrams of the gate drive stage circuit provided in the embodiments of the present invention.

[0023] Figure 5 is a waveform diagram of some external signals and node signals in the gate drive stage circuit provided in an embodiment of the present invention.

[0024] Figures 6 to 11 are schematic diagrams of the architecture of the display device provided in the embodiments of the present invention.

[0025] Figure 12 is a circuit diagram of a sub-pixel provided in an embodiment of the present invention.

[0026] Figure 13 is a waveform diagram of a portion of the external signal in a sub-pixel provided in an embodiment of the present invention. Implementation methods of this application

[0027] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application.

[0028] Embodiments of this application provide gate driving circuits, including but not limited to the following embodiments and combinations thereof.

[0029] In some embodiments, as shown in Figures 1 to 11, the gate driving circuit 20 includes a plurality of cascaded gate driving stage circuits 201. The nth stage gate driving stage circuit 201 includes: a first output circuit 3031, including a first control terminal 11, a first input terminal 12, and a first output terminal 13, for transmitting the signal of the first input terminal 12 to the first output terminal 13 according to the signal of the first control terminal 11 to form a first gate signal EM[n]; a second output circuit 3032, including a second control terminal 21, a second input terminal 22, and a second output terminal 23, for transmitting the signal of the second input terminal 22 to the second output terminal 23 according to the signal of the second control terminal 21 to form a second gate signal Nout[n]; and a third output circuit 3033, including a third control terminal 31, a third input terminal 32, and a third output terminal 33, for transmitting the signal of the third input terminal 32 to the third output terminal 33 according to the signal of the third control terminal 31 to form a third gate signal Pout1[n]. The control circuit 40 is configured to control the signals of the first control terminal 11, the second control terminal 21, and the third control terminal 31 based on the frame start signal STV (for the first-stage gate driver circuit 201) or the output of the previous i-th stage gate driver circuit (for the non-stage gate driver circuit 201, the output can be at least one of the above three output terminals or other output terminals), the first clock signal XCK, and the power supply signals (including but not limited to the first voltage signal PVGL, the second voltage signal PVGH, and the third voltage signal NVGL), where i is a positive integer; wherein at least one of the pulse width and effective potential of any one of the first gate signal EM[n], the second gate signal Nout[n], and the third gate signal Pout1[n] is different from at least one of the pulse width and effective potential of the other two of the first gate signal EM[n], the second gate signal Nout[n], and the third gate signal Pout1[n].

[0030] The gate driving circuit 20 described above can be applied to a display device. As shown in Figures 6 and 7, the display device 100 includes a plurality of sub-pixels Pi, a plurality of first gate lines 101, a plurality of second gate lines 102, and a plurality of third gate lines 103. Each of the first gate lines 101, second gate lines 102, and third gate lines 103 is electrically connected between the corresponding first gate driving stage circuit 201 and the corresponding plurality of sub-pixels Pi.

[0031] Within a frame, the multi-level gate driving stage circuit 201 in the gate driving circuit 20 operates sequentially to arrange multiple gate pulses of the same type of gate signal in sequence on the time axis, thereby controlling the corresponding transistors in the multi-row sub-pixels Pi to turn on sequentially, thereby controlling the multi-row sub-pixels Pi to emit light, thus displaying the image of that frame.

[0032] Understandably, in this embodiment, the control circuit 40 in the gate driving circuit 20 is controlled by the output signal of the previous stage, the first clock signal XCK, and the power signal to control the signals of the first control terminal 11, the second control terminal 21, and the third control terminal 31. This allows the first output circuit 3031, the second output circuit 3032, and the third output circuit 3033 to transmit their respective input signals to their respective output terminals according to their respective control signals. This generates a first gate signal EM[n], a second gate signal Nout[n], and a third gate signal Pout1[n] with different pulse widths and phases. This controls the conduction of the corresponding transistors in the sub-pixel Pi. While generating multiple gate signals, this avoids increasing the number of clock signal groups and the number of gate driving stage circuits 201, saving power consumption of the gate driving circuit 20 and reducing the bezel size of the display device.

[0033] In some embodiments, as shown in Figures 1 to 11, the control circuit 40 includes: a shift register circuit 301, at least configured to control the signal of the first node N according to the frame start signal STV or the signal of the output terminal of the gate drive stage circuit 201 of the previous i-th stage, and the first clock signal XCK; wherein, the control circuit 40 is configured to control the signal of the first control terminal 11, the signal of the second control terminal 21, and the signal of the third control terminal 31 according to the signal of the first node N.

[0034] Specifically, the input terminal of the shift register circuit 301 is electrically connected to the frame start line (for transmitting the frame start signal STV) or the output terminal of the previous stage gate driver circuit 201, and the control terminal of the shift register circuit 301 is electrically connected to the first clock line (for transmitting the first clock signal XCK). The shift register circuit 301 controls the signals of the first control terminal 11, the second control terminal 21 and the third control terminal 31 by controlling the signals of the first node N, so that the first output circuit 3031, the second output circuit 3032 and the third output circuit 3033 respectively transmit the signals of their respective input terminals to their respective output terminals according to their respective control signals to generate their respective gate signals.

[0035] For ease of description, the following text will use i=1 and the nth gate drive stage circuit 201 as an example.

[0036] In some embodiments, as shown in Figures 1 to 5, the input terminal of the shift register circuit 301 is electrically connected to the first output terminal of the output terminal of the (n-1)th stage gate drive stage circuit 201. The control circuit 40 further includes a filter circuit 305, electrically connected between the shift register circuit 301 and the second output circuit 3032. The control terminal of the filter circuit 305 is electrically connected to a filter control line for transmitting the filter control signal Con1. The filter circuit 305 is used to control the signal of the second control terminal 21 in response to the filter control signal Con1, so that the second output circuit 3032 generates a second gate signal Nout[n] with a pulse width smaller than that of the first gate signal EM[n].

[0037] Specifically, the shift register circuit 301 is controlled by the first clock signal XCK to transmit the first gate signal EM[n-1] to the first output circuit 3031 and the filter circuit 305. Thereafter, the first output circuit 3031 can generate a corresponding first gate signal EM[n] with a larger pulse width according to the information in the first gate signal EM[n-1], thereby driving the corresponding transistors in the two rows of sub-pixels Pi to work. At the same time, the filter circuit 305 processes the information in the first gate signal EM[n-1] it has obtained according to the filter control signal Con1, thereby controlling the second output circuit 3032 to generate a corresponding second gate signal Nout[n] with a smaller pulse width.

[0038] Understandably, in this embodiment, since a filter circuit 305 is provided between the shift register circuit 301 and the second output circuit 3032, the filter circuit 305 can filter out some components of the information corresponding to the (n-1)th level first gate signal EM[n-1] it acquires according to the filter control signal Con1. As a result, the information component of the (n-1)th level first gate signal EM[n-1] received by the second output circuit 3032 is less than the information component of the (n-1)th level first gate signal EM[n-1] received by the filter circuit 305 and the first output circuit 3031. Consequently, the second gate signal Nout[n] generated by the second output circuit 3032 depends on... The information component of the first gate signal EM[n-1] is less than the information component of the (n-1)th level first gate signal EM[n-1] on which the first gate signal EM[n] generated by the first output circuit 3031 is based. Therefore, the pulse width of the second gate signal Nout[n] is less than the pulse width of the first gate signal EM[n]. Thus, by combining a clock signal with the gate driving stage circuit 201, two gate signals with different pulse widths can be generated. While generating multiple gate signals, it is possible to avoid increasing the number of clock signal groups and the number of gate driving stage circuits 201, thereby saving the power consumption of the gate driving circuit 20 and reducing the bezel size of the display device.

[0039] In some embodiments, as shown in FIGS. 1 to 5, the filtering control signal Con1 is the first gate signals EM[n-k] of the first k levels, where k is a positive integer greater than i, that is, the filtering control line is the first gate line 101 of the (n-k)th level, n≥3, 1<k<n. Since "n-k" is less than "n-1", that is, the effective pulse of the first gate signal EM[n-1] of the (n-1)th level lags behind the effective pulse of the first gate signal EM[n-k] of the (n-k)th level. The end time of the effective pulse of the first gate signal EM[n-k] of the (n-k)th level is between the start time and the end time of the effective pulse of the first gate signal EM[n-1] of the (n-1)th level, so that the filtering circuit 305 is controlled by the end time of the effective pulse of the first gate signal EM[n-k] of the (n-k)th level at a certain time after the start time of the effective pulse of the first gate signal EM[n-1] of the (n-1)th level to transmit the signal of the first node N to the second node K. Before this, the second node K cannot receive the signal of the first node N, so the signal of the second node K is the corresponding invalid potential before this, and the second gate signal Nout[n] is also the corresponding invalid potential before this, and only outputs the corresponding pulse after this (the end time of the effective pulse of the first gate signal EM[n-k] of the (n-k)th level). Therefore, the pulse width of the second gate signal Nout[n] is smaller than the pulse width of the first gate signal EM[n].

[0040] Of course, according to the difference between the pulse width of the second gate signal Nout[n] and the pulse width of the first gate signal EM[n], other signals can also be used as the above filtering control signal. This filtering control signal can be a signal in the gate driving stage circuit 201 of a certain previous stage, or an externally applied signal.

[0041] In some embodiments, as shown in FIGS. 1 to 5, the shift register circuit 301 is configured to respond to the first potential (for example, the corresponding low potential) of the first clock signal XCK, and control the frame start signal STV or the potential of the first gate signal EM[n-1] of the (n-1)th level to act on the first node N; wherein, the filtering circuit 305 is connected to the shift register circuit 301 through the first node N, and is configured to respond to the signal of the first node N and the filtering control signal Con1 to control the signal of the second node K, and the second output circuit 3032 is connected to the filtering circuit 305 through the second node K.

[0042] As discussed above, the shift register circuit 301 of the gate driver stage circuit 201 controls the potential of the frame start signal STV or the first gate signal EM[n-1] of the (n-1)th stage under the first potential of the clock signal to act on the first node N. Then, the first output circuit 3031 generates the first gate signal EM[n] according to the signal of the first node N or the signal of other nodes of the shift register circuit 301. However, for the second output circuit 3032, the filtering circuit 305 needs to process the signal of the first node N according to the filtering control signal Con1 to obtain the signal acting on the second node K. Therefore, the pulse width of the second gate signal Nout[n] generated by the second output circuit 3032 according to the signal of the second node K can be smaller than the pulse width of the first gate signal EM[n].

[0043] In some embodiments, as shown in Figures 2 and 4, the filtering circuit 305 includes a filtering transistor T6, the gate of which is configured to be electrically connected to the control terminal of the filtering circuit 305, one of the source and drain of the filtering transistor T6 being electrically connected to the first node N, and the other of the source and drain of the filtering transistor T6 being electrically connected to the second node K.

[0044] Therefore, in this embodiment, by setting the filtering circuit 305 to include the aforementioned filtering transistor T6, specifically by controlling the conduction period of the filtering transistor T6 through the filtering control signal Con1, the signal of the second node K can only be updated to the current signal of the first node N when the filtering transistor T6 is turned on. That is, at this time, the frame start signal STV or the first gate signal EM[n-1] of the (n-1)th level can sequentially act on the second output circuit 3032 through the first node N and the second node K. During the off period of the filtering transistor T6, the second output circuit 3032 is only controlled by the signal of the first node N that remains the previous signal.

[0045] In some embodiments, as shown in Figures 2 and 3, the shift register circuit 301 is further configured to control the frame start signal or the first gate signal EM[n-1] of the (n-1)th stage to act on the third node O in response to the first potential of the first clock signal; wherein, the first output circuit 3031 is connected to the shift register circuit 301 through the third node O, and is configured to generate the corresponding first gate signal EM[n] in response to the signal of the third node O.

[0046] Understandably, in order to satisfy the difference in the types of transistors in the first output circuit 3031 and the filtering circuit 305, the shift register circuit 301 responds to the first potential of the first clock signal and can control the frame start signal or the (n-1)th level first gate signal EM[n-1] to act on the second node K and the third node O. The first output circuit 3031 can generate the corresponding first gate signal EM[n] according to the signal of the third node O. The filtering circuit 305 can process the signal of the first node N according to the filtering control signal Con1 to obtain the signal of the second node K and generate the corresponding second gate signal Nout[n].

[0047] Furthermore, the phase of the signal at the first node N is opposite to the phase of the signal at the third node O. That is, it can be assumed that the transistor used to control the first gate signal EM[n] in the first output circuit 3031 is of type N or P, and the transistor used to control the signal at the second node K in the filter circuit 305 (for example, the aforementioned filter transistor T6) is of type N or P.

[0048] Specifically, as shown in Figure 3, the shift register circuit 301 may include a shift transistor T1, a first inverting transistor T4, and a second inverting transistor T5; the gate of the shift transistor T1 is loaded with the aforementioned first clock signal XCK, one of the source and drain of the shift transistor T1 is loaded with the frame start signal STV or the (n-1)th level first gate signal EM[n-1], and the other is electrically connected to the third node O; the gates of the first inverting transistor T4 and the second inverting transistor T5 are both electrically connected to the third node O, one of the source and drain of the first inverting transistor T4 is loaded with the second voltage signal PVGH, and the other is electrically connected to one of the source and drain of the second inverting transistor T5, and the other of the source and drain of the second inverting transistor T5 is loaded with the first voltage signal PVGL.

[0049] Among them, the second voltage signal PVGH and the first voltage signal PVGL can both be constant voltage signals, and the amplitude of the former is greater than that of the latter.

[0050] Among them, the shift transistor T1 can transmit the frame start signal STV or the first gate signal EM[n-1] of the (n-1)th stage to the third node O according to the first clock signal XCK to realize the shift. The first inverting transistor T4 and the second inverting transistor T5 can invert the signal of the third node O to obtain the signal of the first node N that is opposite to the phase of the third node O, and finally realize the registration of the frame start signal STV or the first gate signal EM[n-1] of the (n-1)th stage.

[0051] In some embodiments, as shown in FIG3, the first output circuit 3031 includes a first pull-down transistor T2 and a first pull-up transistor T3; the gate of the first pull-down transistor T2 is electrically connected to the third node O, the gate of the first pull-up transistor T3 is electrically connected to the first node N, one of the source and drain of the first pull-down transistor T2 is electrically connected to a first voltage line (for transmitting a first voltage signal PVGL), one of the source and drain of the first pull-up transistor T3 is electrically connected to a second voltage line (for transmitting a second voltage signal PVGH), and the other of the source and drain of the first pull-down transistor T2 and the other of the source and drain of the first pull-up transistor T3 are both electrically connected to the first gate line (for outputting a first gate signal EM[n]). That is, the first control terminal 11 may include the aforementioned first node N and third node O.

[0052] Specifically, in this embodiment, the first pull-down transistor T2 and the first pull-up transistor T3 are controlled by the signals of the third node O and the first node N, respectively, to achieve their respective conduction or cutoff. Taking the phase of the signal of the first node N and the phase of the signal of the third node O as an example, the first pull-down transistor T2 and the first pull-up transistor T3 can both be N-type transistors or P-type transistors, so that the two are alternately turned on, so as to output the first voltage signal PVGL or the second voltage signal PVGH as the effective potential of the first gate signal EM[n] during a specific time period.

[0053] Of course, when the phase of the signal at the first node N is the same as the phase of the signal at the third node O, one of the first pull-down transistor T2 and the first pull-up transistor T3 can be an N-type transistor and the other can be a P-type transistor, which can also make the two conduct alternately.

[0054] Furthermore, as shown in Figure 3, the first output circuit 3031 also includes a first capacitor C1 electrically connected between the first gate line and the third node O. Since the potential of the first clock signal XCK alternates between corresponding high and low potentials, the third node O connected to the source or drain of the shift transistor T1 can turn on the potential jump of the first gate signal EM[n] output by the first gate line when the potential jump of the first clock signal XCK changes. By reasonably setting the types of the first pull-down transistor T2 and the first pull-up transistor T3 and the phase of the first clock signal XCK, the potential jump direction of the first clock signal XCK can be made the same as the potential jump direction of the first gate signal EM[n], thereby accelerating the potential jump of the first gate signal EM[n].

[0055] That is, when the potential of the first clock signal XCK changes in a positive or negative direction to make the shift transistor T1, the signal of the third node O and the signal of the first node N control the first pull-down transistor T2 or the first pull-up transistor T3, so that the first gate signal EM[n] also changes in a positive or negative direction to become the potential of the first voltage signal PVGL or the potential of the second voltage signal PVGH.

[0056] In some embodiments, as shown in Figures 2 and 3, the control circuit 40 further includes a stabilizing circuit 306, electrically connected between the third node O, the first node N (only the first node is illustrated in Figures 2 and 3), and the second node K, for controlling the signal of the second node K in response to the signal of the third node O or the signal of the first node N.

[0057] As discussed above, the second output circuit 3032 is connected to the second node K. Since the potential of the signal of the second node K is transmitted and processed through the signal of the third node O (or the signal of the first node N), in order to improve the reliability of the signal of the second node K, this embodiment sets up a stabilizing circuit 306 connected between the third node O (or the first node N) and the second node K. That is, the stabilizing circuit 306 can control the signal of the second node K according to the signal of the third node O or the signal of the first node N, so that the signal of the second node K is also at the corresponding potential (the same potential as the output controlled by the filtering circuit 305).

[0058] Specifically, as shown in Figure 3, the stabilizing circuit 306 includes: a stabilizing transistor T7, the gate of which is electrically connected to one of the third node O and the first node N (only the first node is used as an example in Figures 2 and 3), the source and drain of which are electrically connected to the second voltage line (for transmitting the second voltage signal PVGH), and the other of which is electrically connected to the second node K.

[0059] That is, the signal of the third node O or the signal of the first node N controls the conduction period of the stabilizing transistor T7. In this path, when the stabilizing transistor T7 is turned on, it transmits the second voltage signal PVGH to the second node K. Since in the other path, the second voltage signal PVGH is also transmitted to the second node K by controlling the second inverting transistor T5 to turn on when the stabilizing transistor T7 is turned on, both paths can control the signal of the second node K to be the second voltage signal PVGH. The stability of the signal of the second node K is improved by the stabilizing transistor T7.

[0060] In some embodiments, as shown in Figures 1 to 5, the third output circuit 3033 is connected to the filter circuit 305 through the second node K. The first terminal of the third output circuit 3033 is electrically connected to the second clock line (referring to the transmission of the second clock signal CK1), that is, the signal of the third input terminal 32 is the second clock signal CK1. The third output circuit 3033 is used to respond to the third potential (e.g., the corresponding low potential) of the signal of the second node K to output the second clock signal CK1 to the corresponding third gate line as the third gate signal Pout1[n].

[0061] The difference between the third output circuit 3033 and the first output circuit 3031 and the second output circuit 3032 is that the third output circuit 3033 requires the participation of the second clock signal CK1 to form a third gate signal Pout1[n] with a pulse width much smaller than the pulse widths of the first gate signal EM[n] and the second gate signal Nout[n].

[0062] Specifically, the third output circuit 3033 may include a third auxiliary transistor T21, a fourth auxiliary transistor T22, a fifth auxiliary transistor T23, a third pull-down transistor T24, a third pull-up transistor T25, and a fourth capacitor C4. The connection relationship of the above devices can be referred to, but is not limited to, the figure 3.

[0063] In some embodiments, as shown in Figures 1 to 5, the control circuit 40 further includes a self-stabilizing circuit 302, which is electrically connected to the filter circuit 305 and the second output circuit 3032 through the second node K, for stabilizing the signal of the second node K according to the signal of the second node K.

[0064] Similarly, to improve the reliability of the signal at the second node K, this embodiment includes a self-stabilizing circuit 302 connected to the second node K. The difference between this self-stabilizing circuit and the aforementioned stabilizing circuit 306 is that the self-stabilizing circuit 302 controls the signal of the second node K itself based on the signal of the second node K, stabilizing the signal of the second node K at a corresponding potential (the same potential controlled by the filtering circuit 305). Its function is similar to positive feedback control of the signal of the second node K, thus improving the stability of the signal of the second node K.

[0065] The self-stabilizing circuit 302 may include a first self-stabilizing transistor T8, a second self-stabilizing transistor T9, a third self-stabilizing transistor T10, a fourth self-stabilizing transistor T11, a fifth self-stabilizing transistor T12, and a sixth self-stabilizing transistor T29. The second output circuit 3032 may include a first auxiliary transistor T15, a second auxiliary transistor T16, a second pull-up transistor T17, and a second pull-down transistor T18. The connection relationship of the above devices can be referred to, but is not limited to, the figure shown in Figure 3.

[0066] In some embodiments, as shown in Figures 1 to 5, the control circuit 40 further includes: a first frequency divider circuit 3041, the control terminal of the first frequency divider circuit 3041 being electrically connected to a first frequency divider control line for transmitting a first frequency divider control signal NLF, the input terminal of the first frequency divider circuit 3041 being electrically connected to the second node K, and the output terminal of the first frequency divider circuit 3041 being electrically connected to the second output circuit 3032 through a fourth node W; wherein, the first frequency divider circuit 3041 is used to control the fourth node W to be electrically connected to the second node K in response to a second potential (e.g., a corresponding low potential) of the first frequency divider control signal NLF.

[0067] In this embodiment, a first frequency divider circuit 3041 controlled by the first frequency divider control signal NLF is set. It can control whether the fourth node W and the second node K are electrically connected at the current time according to the first frequency divider control signal NLF, thereby controlling whether the signal of the second node K can be transmitted and act on the second output circuit 3032, thereby controlling whether the second gate signal Nout[n] generated by the second output circuit 3032 includes the corresponding gate pulse. If it does, the sub-pixel Pi corresponding to at least one row can be turned on; otherwise, the sub-pixel Pi corresponding to at least one row will be turned off.

[0068] Specifically, for the theoretical scanning phase of each row of sub-pixels Pi, the signal of the second node K can be controlled to be transmitted to the second output circuit 3032 based on whether the current amplitude of the first frequency division control signal NLF is the second potential, and then whether the second output circuit 3032 can work to generate the second gate signal Nout[n] including the corresponding gate pulse, thereby determining whether to actually scan the row of sub-pixels Pi.

[0069] Therefore, by setting the amplitude of the first frequency division control signal NLF in different time periods (i.e., the time periods corresponding to different rows of sub-pixels Pi) in multiple frames, it is possible to control whether each row of sub-pixels Pi emits light in multiple frames, thereby realizing the segmented frequency setting of the display device 100. For example, the area corresponding to the sub-pixel Pi that emits light in a larger number of frames (frequency) within a unit time period can be called the high-frequency area, and the area corresponding to the sub-pixel Pi that emits light in a smaller number of frames (frequency) can be called the low-frequency area.

[0070] The first frequency divider circuit 3041 includes a first frequency divider transistor T13, a second frequency divider transistor T14, and a second capacitor C2. The connection relationship of the above-mentioned devices can be referred to, but is not limited to, the figure 3.

[0071] The second control terminal 21 can be the fourth node W, or in some embodiments (not shown), the above frequency division function is not required, so the corresponding first frequency division circuit 3041 can be canceled, and the second node K of the signal controlled by the filter circuit 305 can be directly used as the second control terminal 21.

[0072] In some embodiments, as shown in Figures 1 to 5, the control circuit 40 further includes: a second frequency divider circuit 3042, the control terminal of the second frequency divider circuit 3042 being electrically connected to the second frequency divider control line, the input terminal of the second frequency divider circuit 3042 being electrically connected to the second node K, and the output terminal of the second frequency divider circuit 3042 being electrically connected to the third output circuit 3033 through the sixth node M; wherein, the second frequency divider circuit 3042 is used to control the sixth node M to be electrically connected to the second node K in response to the fourth potential (e.g., the corresponding low potential) of the second frequency divider control signal PLF transmitted by the second frequency divider control line.

[0073] Similarly, in this embodiment, by setting a second frequency divider circuit 3042 controlled by the second frequency divider control signal PLF, it can control whether the sixth node M and the second node K are electrically connected at the current time according to the second frequency divider control signal PLF, thereby controlling whether the signal of the second node K can be transmitted and act on the third output circuit 3033, thereby controlling whether the third gate signal Pout1[n] generated by the third output circuit 3033 includes the corresponding gate pulse. If it does, the sub-pixel Pi corresponding to at least one row can be turned on; otherwise, the sub-pixel Pi corresponding to at least one row will be turned off.

[0074] Similarly, for the theoretical scanning phase of each row of sub-pixels Pi, the actual scanning of that row of sub-pixels Pi can be controlled based on whether the current amplitude of the second frequency division control signal PLF is at the fourth potential.

[0075] Similarly, by setting the amplitude of the second frequency division control signal PLF at different time periods in multiple frames (i.e., the time periods corresponding to different rows of sub-pixels Pi), it is possible to control whether each row of sub-pixels Pi emits light in multiple frames, thereby realizing the frequency division setting of the display device 100.

[0076] The second frequency divider circuit 3042 includes a third frequency divider transistor T19, a fourth frequency divider transistor T20, and a third capacitor C3. The connection relationship of the above-mentioned devices can be referred to, but is not limited to, the figure 3.

[0077] Similarly, the third control terminal 31 can be the sixth node M, or in some embodiments (not shown), the above frequency division function is not required, so the corresponding second frequency division circuit 3042 can be canceled, and the second node K of the signal controlled by the filter circuit 305 can be directly used as the third control terminal 31.

[0078] In some embodiments, when the control circuit 40 includes both a self-stabilizing circuit 302 and a first frequency divider circuit 3041, the self-stabilizing circuit 302 is also connected to the second output circuit 3032 via a fifth node P. The self-stabilizing circuit 302 is used to control the signal of the fifth node P in response to the signal of the second node K. The second output circuit 3032 is used to control the signal of the fourth node W in response to the signal of the fifth node P. The third output circuit 3033 is used to control the signal of the sixth node M in response to the signal of the fifth node P.

[0079] That is, when the first frequency divider circuit 3041 controls the signal of the fourth node W, the self-stabilizing circuit 302 can be set to control the signal of the fifth node P through the signal of the second node K. Then, the second output circuit 3032 controls the signal of the fourth node W according to the signal of the fifth node P, thereby realizing the stabilizing effect of the self-stabilizing circuit 302 on the signal of the fourth node W, and improving the reliability of the second gate signal Nout[n] output by the gate drive stage circuit 201 when dividing the frequency.

[0080] Similarly, by adding the first frequency divider circuit 3041 to control the signal of the sixth node M, the self-stabilizing circuit 302 can also control the signal of the sixth node M through the signal of the second node K. Then, the third output circuit 3033 controls the signal of the sixth node M according to the signal of the fifth node P, thereby realizing the stabilizing effect of the self-stabilizing circuit 302 on the signal of the sixth node M indirectly.

[0081] Specifically, when the signal P(n) of the fifth node P in the nth stage is at the fifth potential (e.g., the corresponding low potential), the first frequency divider transistor T13 transmits the first frequency divider control signal NLF to the fourth node W; otherwise, it does not transmit to the fourth node W. When the first frequency divider control signal NLF is transmitted to the gate of the second frequency divider transistor T14, if the first frequency divider control signal NLF controls the second frequency divider transistor T14 to conduct, then the fourth node W is electrically connected to the second node K. If the first frequency divider control signal NLF controls the second frequency divider transistor T14 to be turned off, then the fourth node W is electrically disconnected from the second node K. Furthermore, through the coupling effect of the second capacitor C2, the potential of the fourth node W also changes with the potential of the first frequency divider control signal NLF, so that the second gate signal Nout[n] output by the second output circuit 3032 no longer has the corresponding gate pulse.

[0082] It is important to note that although both the filter circuit 305 and the first frequency divider circuit 3041 directly or indirectly control whether the fourth node W and the first node N are electrically connected, their operating periods differ. The filter circuit 305 is controlled by a periodic filter control signal Con1. Within each frame, the filter control signal Con1 transmits the signal of the first node N to the second node K through a delay, so that the pulse of the frame start signal STV or the first gate signal EM[n-1] is "clipped" to obtain the pulse of the second node K with a smaller pulse width, and thus the pulse width of the second gate signal Nout[n] is also smaller. The second potential of the first frequency divider control signal NLF is set according to the division of the frequency division area and the frequency magnitude. Its purpose is to control whether the second gate signal Nout[n] generates the corresponding gate pulse during the theoretical scanning phase of the sub-pixel in the current row, thereby determining whether to actually scan the sub-pixel Pi in that row, thus realizing the specific frequency division.

[0083] Similarly, the working principles of the third frequency divider transistor T19, the fourth frequency divider transistor T20, and the third capacitor C3 can also be found in the relevant discussion in the second frequency divider circuit 3042.

[0084] In some embodiments, as shown in Figures 3, 4, 5, and 7, the nth-stage gate drive stage circuit further includes: a fourth output circuit 3034, connected to the filter circuit 305 via the second node K, the first terminal of the fourth output circuit 3034 being electrically connected to the third clock line (for transmitting the third clock signal CK2), the fourth output circuit 3034 being used to respond to the third potential of the signal of the second node K to output the third clock signal CK2 to the corresponding fourth gate line as the corresponding fourth gate signal Pout2[n]; wherein, the third clock signal CK2 is obtained by shifting the second clock signal CK1 along the time axis (the gate pulses of the two are the same), and the fourth gate signal Pout2[n] is obtained by shifting the third gate signal Pout1[n] along the time axis.

[0085] Correspondingly, as shown in Figure 7, the display device 100 also includes multiple fourth gate lines 104, which are electrically connected between the corresponding gate driving stage circuit 201 and the corresponding multiple sub-pixels Pi. Based on the previous description of the two rows of sub-pixels Pi driven by the first gate signal EM[n] and the second gate signal Nout[n], and one row of sub-pixels Pi driven by the third gate signal Pout1[n], it can be considered that the third gate signal Pout1[n] generated by the same gate driving stage circuit 201 is transmitted to the other of the two rows of sub-pixels Pi through a third gate line 103.

[0086] The fourth output circuit 3034 shares the third auxiliary transistor T21 and the fourth auxiliary transistor T22 from the third output circuit 3033. The fourth output circuit 3034 also includes a sixth auxiliary transistor T26, a fourth pull-down transistor T27, a fourth pull-up transistor T28, and a fifth capacitor C5. The connection relationships of these components can be referenced, but are not limited to, those shown in Figure 3. The difference between the fourth output circuit 3034 and the third output circuit 3033 is that the fourth output circuit 3034 generates the fourth gate signal Pout2[n] through a third clock signal CK2, which has a phase difference with the second clock signal CK1. Therefore, the fourth gate signal Pout2[n] also has a corresponding phase difference with the third gate signal Pout1[n], but their gate pulses are the same.

[0087] Based on the above connection relationship and the fact that the first frequency divider circuit 3041 and the second frequency divider circuit 3042 respectively electrically connect the fourth node W and the sixth node M to the second node K, the following explanation is given:

[0088] When the signal at the second node K (which is the same as the signals at the fourth node W and the sixth node M) is at a low potential, the first self-stabilizing transistor T8 is turned off and the second self-stabilizing transistor T9 is turned on. The second voltage signal PVGH is transmitted to the fifth node P, the fifth self-stabilizing transistor T12 is turned on, the third voltage signal NVGL is transmitted to the second node K to maintain or further pull down the low potential of the second node K, the second pull-down transistor T18 is turned off and the second pull-up transistor T17 is turned on, the fourth voltage signal NVGH is transmitted to the second gate line as the second gate signal Nout[n], and the fourth self-stabilizing transistor T9 is turned on. Transistor T11, second auxiliary transistor T16, fourth auxiliary transistor T22, third pull-up transistor T25 and fourth pull-up transistor T28 are turned off to prevent the second voltage signal PVGH from being transmitted to the second node K, the fourth node W and the sixth node M. The signal P[n-2] of the fifth node P of the [n-2]th stage is used to control whether the seventh node Q1 and the eighth node Q2 are electrically connected to the sixth node M, and thus control whether the second clock signal CK1 and the third clock signal CK2 are output as the third gate signal Pout1[n] and the fourth gate signal Pout2[n], respectively.

[0089] Conversely, when the signal at the second node K is at the corresponding high potential, the first self-stabilizing transistor T8 is turned on and the second self-stabilizing transistor T9 is turned off. The first voltage signal PVGL is transmitted to the fifth node P. The fourth self-stabilizing transistor T11, the second auxiliary transistor T16, the fourth auxiliary transistor T22, the third pull-up transistor T25, and the fourth pull-up transistor T28 are turned on. The second voltage signal PVGH is transmitted to the third gate line and the fourth gate line as the third gate signal Pout1[n] and the fourth gate signal Pout2[n], respectively, while the first clock signal XCK is at the corresponding low potential. When the third self-stabilizing transistor T10, the first auxiliary transistor T15, and the third auxiliary transistor T21 are turned on, the second voltage signal PVGH is transmitted to the second node K, the fourth node W, and the sixth node M to maintain or further pull up their high potentials. The second pull-down transistor T18 is turned on and the second pull-up transistor T17 is turned off. The third voltage signal NVGL is transmitted to the second gate line as the second gate signal Nout[n]. At the same time, the fifth self-stabilizing transistor T12 and the second pull-down transistor T18 are turned off to prevent the third voltage signal NVGL from being transmitted to the second node K and the fourth node W.

[0090] Among them, the third voltage signal NVGL and the fourth voltage signal NVGH can both be constant voltage signals, and the amplitude of the former is smaller than that of the latter. Furthermore, there are no limitations on the amplitudes of the third voltage signal NVGL and the first voltage signal PVGL, and there are no limitations on the amplitudes of the fourth voltage signal NVGH and the second voltage signal PVGH.

[0091] For the nth stage gate driver circuit 201, if n is greater than or equal to 3, the signal P[n-2] of the fifth node P of the [n-2]th stage and the first gate signal EM[n-1] of the (n-1)th stage required in the nth stage gate driver circuit 201 can be directly provided by the [n-2]th stage gate driver circuit 201 and the (n-1)th stage gate driver circuit 201, respectively. If n is greater than 0 and less than 3, the above signals can be provided by the virtual gate driver circuit (which does not output gate signals in-plane).

[0092] The types of transistors, the signals loaded by the transistors and capacitors, and their connections can be referenced, but are not limited to, those shown in Figure 3. Based on the types of transistors listed in Figure 3, the corresponding waveforms of the signals and nodes can be referenced in Figure 4. Of course, if the types of transistors are different from those shown in Figure 3, the corresponding waveforms of the signals and nodes will also need to be changed accordingly.

[0093] To better illustrate the working principle of the gate drive stage circuit 201 in this application, the first frequency division control signal NLF and the second frequency division control signal PLF are both at low potentials, and the signal P[n] superimposed on the fifth node P is at the corresponding low potential, so that the second frequency division transistor T14 and the fourth frequency division transistor T20 are turned on. The working process of the nth stage gate drive stage circuit 201 is described as follows.

[0094] After power-on, the power-on control signal Con2 is used to control the sixth self-stabilizing transistor T29 to conduct, so as to transmit the second voltage signal PVGH to the second node K. The second self-stabilizing transistor T9 is turned off, and the first self-stabilizing transistor T8 is turned on, transmitting the first voltage signal PVGL to the fifth node P. This causes the first frequency divider transistor T13 and the third frequency divider transistor T19 to conduct. If the first frequency divider control signal NLF and the second frequency divider control signal PLF are both at their corresponding low potentials, then the second frequency divider transistor T14 and the fourth frequency divider transistor T20 are turned on. Then the signal W(n) of the fourth node W and the signal M(n) of the sixth node M are also at high potentials, causing the second pull-up transistor T17 to be turned off and the second pull-down transistor T20 to be turned off. When 18 is turned on, the low potential output of the third voltage signal NVGL is used as the second gate signal Nout(n). At this time, it can be assumed that the signal P[n-2] of the fifth node P of the [n-2]th stage is also at the corresponding low potential, which makes the fifth auxiliary transistor T23 and the sixth auxiliary transistor T26 turn on. The seventh node Q1 and the eighth node Q2 are at the corresponding high potential, which makes the third pull-down transistor T24 and the fourth pull-down transistor T27 turn off. At the same time, the low potential of the signal P(n) of the first node P makes the third pull-up transistor T25 and the fourth pull-up transistor T28 turn on, so that the second voltage signal PVGH is used as the third gate signal Pout1(n) and the fourth gate signal Pout2(n).

[0095] Time period t1: The first clock signal XCK is at the corresponding high potential, the third clock signal CK2 changes from the corresponding low potential to the corresponding high potential (the second clock signal CK1 is at the corresponding high potential), and the frame start signal STV or the first gate signal EM[n-1] of the (n-1)th stage is at the corresponding high potential. Then the shift transistor T1 is turned off, the signal O[n] of the third node O remains at the previous low potential, the working state of the first inverter transistor T4 and the second inverter transistor T5 remains unchanged, the signal N[n] of the first node N remains at the previous high potential, so that the working state of the first pull-down transistor T2 and the first pull-up transistor T3 also remains unchanged, and the first gate signal EM[n] remains at the previous low potential.

[0096] Simultaneously, the first gate signal EM[n-4] of the [n-4]th stage is at a corresponding high potential, the filter transistor T6 is turned off and the stabilizing transistor T7 is turned on, transmitting the second voltage signal PVGH to the second node K as the signal K[n] of the second node K, and then the second self-stabilizing transistor T9 is turned off, the first self-stabilizing transistor T8 is turned on to transmit the low potential of the first voltage signal PVGL to the fifth node P so that the signal P[n] of the fifth node P is at a low potential (making the first frequency divider transistor T13 and the third frequency divider transistor T19 turn on, and then the second frequency divider transistor T14 and the fourth frequency divider transistor T20 turn on, the signal W[n] of the fourth node W and the signal M[n] of the sixth node M are at the corresponding high potential), and the second pull-down transistor T18 is turned on to output the third voltage signal NVGL as the second gate signal Nout[n], and the fifth self-stabilizing transistor T12 is turned off;

[0097] At the same time, the third self-stabilizing transistor T10 and the fourth self-stabilizing transistor T11 are both turned on, transmitting the second voltage signal PVGH to the second node K as the signal K[n] of the second node K, so as to stabilize the second pull-down transistor T18.

[0098] At the same time, the first auxiliary transistor T15 and the second auxiliary transistor T16 are both turned on, transmitting the second voltage signal PVGH to the fourth node W, while the second pull-up transistor T17 is turned off.

[0099] Simultaneously, the third auxiliary transistor T21 and the fourth auxiliary transistor T22 are both turned on, transmitting the second voltage signal PVGH to the sixth node M. The signal P[n-2] of the fifth node P in the [n-2]th stage is at a low potential, the fifth auxiliary transistor T23 is turned on, the signal Q1[n] of the seventh node Q1 is also at a high potential, the third pull-down transistor T24 is turned off, and since the third pull-up transistor T25 is turned on, the second voltage signal PVGH is output as the second gate signal Pout1[n]. Similarly, the second voltage signal PVGH is output as Pout2[n].

[0100] Time period t2: The first clock signal XCK is at a low potential, the third clock signal CK2 is at a high potential (the second clock signal CK1 changes from a high potential to a low potential), and the frame start signal STV or the first gate signal EM[n-1] is at a high potential. Then the shift transistor T1 is turned on, O[n] becomes at a high potential, the second inverting transistor T5 is turned on and the first inverting transistor T4 is turned off, and the low potential voltage signal PVGL is transmitted to the first node N, so that the first pull-up transistor T3 is turned on. Since the first pull-down transistor T2 is turned off, the second voltage signal PVGH is output as the first gate signal EM[n].

[0101] Meanwhile, EM[n-4] is at the corresponding high potential, the filter transistor T6 is turned off and the stabilizing transistor T7 is turned off, K[n] remains at the previous high potential, so that the working state of the first self-stabilizing transistor T8, the second self-stabilizing transistor T9, and the second pull-down transistor T18 is the same as that of the shift transistor T1, P[n] remains at the previous low potential (the first frequency divider transistor T13, the third frequency divider transistor T19, the second frequency divider transistor T14, and the fourth frequency divider transistor T20 are all turned on), and the third voltage signal NVGL is output as the second gate signal Nout[n], and the fifth self-stabilizing transistor T12 is turned off;

[0102] At the same time, the third self-stabilizing transistor T10 is turned off, the fourth self-stabilizing transistor T11 remains on, and K[n] remains at the previous high potential to stabilize the second pull-down transistor T18.

[0103] At the same time, the first auxiliary transistor T15 is turned off, the second auxiliary transistor T16 remains on, W[n] remains at the previous high potential, and the second pull-up transistor T17 is turned off;

[0104] Meanwhile, the third auxiliary transistor T21 is turned off, the fourth auxiliary transistor T22 remains on, M[n] remains at the previous high potential, and P[n-2] is at the corresponding low potential. The fifth auxiliary transistor T23 is on, and Q1[n] is also at the corresponding high potential. The working states of the third pull-down transistor T24 and the third pull-up transistor T25 are the same as those of the time-shifting transistor T1. Therefore, the second gate signals Pout1[n] and Pout2[n] remain at the previous high potential.

[0105] During time period t3: The potentials of the first clock signal XCK, the third clock signal CK2, and the second clock signal CK1 are all the same as those of the shift transistor T1 during time period. Therefore, the shift transistor T1 is also turned off, O[n] remains at the previous high potential, the operating states of the first inverting transistor T4, the second inverting transistor T5, the first pull-down transistor T2, the first pull-up transistor T3, and the stabilizing transistor T7 are the same as those of the first pull-down transistor T2 during time period. N[n] remains at the previous low potential, and the first gate signal EM[n] remains at the previous high potential.

[0106] Meanwhile, EM[n-4] is the corresponding high potential, the working state of the filter transistor T6 is the same as that of the first pull-down transistor T2 in the same period, K[n] remains at the previous high potential, so that the working states of the first self-stabilizing transistor T8, the second self-stabilizing transistor T9, and the second pull-down transistor T18 are the same as those of the first pull-down transistor T2 in the same period, P[n] remains at the previous low potential (the first frequency divider transistor T13, the third frequency divider transistor T19, the second frequency divider transistor T14, and the fourth frequency divider transistor T20 are all turned on), and the third voltage signal NVGL is output as the second gate signal Nout[n], and the fifth self-stabilizing transistor T12 is turned off;

[0107] At this point, the operating states of the third self-stabilizing transistor T10 and the fourth self-stabilizing transistor T11, the first auxiliary transistor T15 and the second auxiliary transistor T16, the third auxiliary transistor T21 and the fourth auxiliary transistor T22 are the same as those of the time-shifting transistor T1, and K[n], W[n] and M[n] are all at their corresponding high potentials;

[0108] Meanwhile, the potential of P[n-2] is the same as that of the time-shifting transistor T1. The fifth auxiliary transistor T23 is turned on, and Q1[n] is also at the corresponding high potential. The working states of the third pull-down transistor T24 and the third pull-up transistor T25 are also unchanged. Therefore, the second gate signals Pout1[n] and Pout2[n] are both maintained at the previous high potential.

[0109] During time period t4: The potentials of the first clock signal XCK, the third clock signal CK2, and the second clock signal CK1 are the same as those of the first pull-down transistor T2 during time period. Therefore, the shift transistor T1 is also turned on, and O[n] becomes the corresponding high potential (the same as the first pull-up transistor T3 during time period). The operating states of the first inverting transistor T4, the second inverting transistor T5, the first pull-down transistor T2, the first pull-up transistor T3, and the stabilizing transistor T7 are the same as those of the first pull-down transistor T2 during time period. N[n] remains at the previous low potential, and the first gate signal EM[n] remains at the previous high potential.

[0110] Meanwhile, the potential of EM[n-4] is the same as that of the first pull-up transistor T3 in the same time period, so that the working state of the filter transistor T6 is the same as that of the first pull-up transistor T3 in the same time period. K[n] remains at the previous high potential, so that the working states of the first self-stabilizing transistor T8, the second self-stabilizing transistor T9, and the second pull-down transistor T18 also remain unchanged. P[n] remains at the previous low potential (the first frequency divider transistor T13, the third frequency divider transistor T19, the second frequency divider transistor T14, and the fourth frequency divider transistor T20 are all turned on), and the third voltage signal NVGL is output as the second gate signal Nout[n]. The fifth self-stabilizing transistor T12 is turned off.

[0111] At this point, the operating states of the third self-stabilizing transistor T10 and the fourth self-stabilizing transistor T11, the first auxiliary transistor T15 and the second auxiliary transistor T16, the third auxiliary transistor T21 and the fourth auxiliary transistor T22 are the same as those of the first pull-down transistor T2 in the same time period, and K[n], W[n] and M[n] are all at high potentials;

[0112] At the same time, P[n-2] becomes the corresponding high potential, the fifth auxiliary transistor T23 is turned off, Q1[n] remains at the previous high potential, the working state of the third pull-down transistor T24 and the third pull-up transistor T25 remains unchanged, so the second gate signals Pout1[n] and Pout2[n] both remain at the previous high potential;

[0113] During time period t5: The potential status of the first clock signal XCK, the third clock signal CK2, and the second clock signal CK1 is the same as that of the first pull-up transistor T3 during time period. Therefore, the working state of the shift transistor T1 (in the off state), the first inverter transistor T4, the second inverter transistor T5, the first pull-down transistor T2, the first pull-up transistor T3, and the stabilizing transistor T7 is the same as that of the first pull-up transistor T3 during time period. O[n] and the first gate signal EM[n] are both maintained at the previous high potential, and N[n] is maintained at the previous low potential.

[0114] Meanwhile, the potential of EM[n-4] is the same as that of the first inverting transistor T4 in the same time period, so that the working state of the filter transistor T6, the first self-stabilizing transistor T8, the second self-stabilizing transistor T9, and the second pull-down transistor T18 is the same as that of the first inverting transistor T4 in the same time period. K[n] remains at the previous high potential, P[n] and the second gate signal Nout[n] remain at the previous low potential (the first frequency divider transistor T13, the third frequency divider transistor T19, the second frequency divider transistor T14, and the fourth frequency divider transistor T20 are all turned on), and the fifth self-stabilizing transistor T12 is turned off.

[0115] Therefore, the operating states of the third self-stabilizing transistor T10 and the fourth self-stabilizing transistor T11, the first auxiliary transistor T15 and the second auxiliary transistor T16, the third auxiliary transistor T21 and the fourth auxiliary transistor T22 are the same as those of the first pull-up transistor T3 in the same time period, and K[n], W[n] and M[n] are all at high potentials;

[0116] Meanwhile, P[n-2] is the same as in time period t4, and the working states of the fifth auxiliary transistor T23, the third pull-down transistor T24, and the third pull-up transistor T25 are the same as in time period t4. Q1[n], the second gate signal Pout1[n], and Pout2[n] are all maintained at the previous high potential.

[0117] During the above time periods 1 to 5, M[n] is the corresponding high potential, so the second clock signal CK1 and the third clock signal CK2 have no effect.

[0118] During time period t6: the potential status of the first clock signal XCK, the third clock signal CK2, and the second clock signal CK1 becomes the same as that of the first inverting transistor T4 during time period. Then the shift transistor T1 is also turned on, O[n] becomes the corresponding high potential, and the working state of the first inverting transistor T4, the second inverting transistor T5, the first pull-down transistor T2, the first pull-up transistor T3, and the stabilizing transistor T7 is the same as that of the second inverting transistor T5 during time period. The first gate signal EM[n] remains at the previous high potential, and N[n] remains at the previous low potential.

[0119] Simultaneously, EM[n-4] becomes the corresponding low potential, causing filter transistor T6 to turn on, K[n] to become the corresponding low potential, the first self-stabilizing transistor T8 to turn off and the second self-stabilizing transistor T9 to turn on, transmitting the second voltage signal PVGH to the fifth node P so that P[n] is at a high potential (the first frequency divider transistor T13 and the third frequency divider transistor T19 are turned off, the second frequency divider transistor T14 and the fourth frequency divider transistor T20 remain on, W[n] and M[n] become the corresponding low potential so that the second pull-up transistor T17 turns on), the second pull-down transistor T18 is turned off, the fifth self-stabilizing transistor T12 turns on to output the third voltage signal NVGL as K[n], and the second pull-up transistor T17 turns on to output the high-potential voltage signal NVGH as the second gate signal Nout[n];

[0120] Meanwhile, the third self-stabilizing transistor T10, the fourth self-stabilizing transistor T11, the first auxiliary transistor T15, the second auxiliary transistor T16, the third auxiliary transistor T21, and the fourth auxiliary transistor T22 are all turned off to avoid affecting K[n], W[n], and M[n].

[0121] Meanwhile, P[n-2] is the same as time period t5, the fifth auxiliary transistor T23 is turned off, Q1[n] remains at the previous high potential, the third pull-down transistor T24 and the third pull-up transistor T25 are both turned off, the second gate signal Pout1[n] remains at the previous high potential, and similarly, Pout2[n] remains at the previous high potential;

[0122] During time period t7: The potential status of the first clock signal XCK, the third clock signal CK2, and the second clock signal CK1 becomes the same as that of the second inverting transistor T5 during time period. Therefore, the shift transistor T1 is turned off, O[n] remains at a high potential, and the working state of the first inverting transistor T4, the second inverting transistor T5, the first pull-down transistor T2, the first pull-up transistor T3, and the stabilizing transistor T7 is the same as that of the filtering transistor T6 during time period. The first gate signal EM[n] remains at the previous high potential, and N[n] remains at the previous low potential.

[0123] Meanwhile, EM[n-4] is also at the corresponding low potential, so that the working state of the filter transistor T6, the first self-stabilizing transistor T8, the second self-stabilizing transistor T9, the first frequency divider transistor T13, the third frequency divider transistor T19, the second frequency divider transistor T14, the fourth frequency divider transistor T20, the second pull-down transistor T18, the fifth self-stabilizing transistor T12, and the second pull-up transistor T17 is the same as that of the time-period filter transistor T6, K[n], W[n], and M[n] remain at the previous low potential, and P[n] and the second gate signal Nout[n] remain at the previous high potential;

[0124] At the same time, the third self-stabilizing transistor T10 is turned on and the fourth self-stabilizing transistor T11 is turned off, the first auxiliary transistor T15 is turned on and the second auxiliary transistor T16 is turned off, the third auxiliary transistor T21 is turned on and the fourth auxiliary transistor T22 is turned off, so as to avoid affecting K[n], W[n], and M[n].

[0125] Meanwhile, P[n-2] is the same as in time period t6, and the fifth auxiliary transistor T23, the third pull-down transistor T24, and the third pull-up transistor T25 are in the same working state as in time period t6 (all are off), and Q1[n] and the second gate signal Pout1[n] remain at the previous high potential;

[0126] During time period t8: the potential status of the first clock signal XCK, the third clock signal CK2, and the second clock signal CK1 becomes the same as that of the time period filter transistor T6. Then, the shift transistor T1 is turned on, and the working state of the first inverting transistor T4, the second inverting transistor T5, the first pull-down transistor T2, the first pull-up transistor T3, and the stabilizing transistor T7 is the same as that of the time period filter transistor T6. O[n] becomes the corresponding high potential, the first gate signal EM[n] remains at the previous high potential, and N[n] remains at the previous low potential.

[0127] Meanwhile, EM[n-4] is also at the corresponding low potential, so that the working state of the filter transistor T6, the first self-stabilizing transistor T8, the second self-stabilizing transistor T9, the first frequency divider transistor T13, the third frequency divider transistor T19, the second frequency divider transistor T14, the fourth frequency divider transistor T20, the second pull-down transistor T18, the fifth self-stabilizing transistor T12, and the second pull-up transistor T17 is the same as that of the time-stabilizing transistor T7. K[n], W[n], and M[n] remain at the previous low potential, and P[n] and the second gate signal Nout[n] remain at the previous high potential.

[0128] Meanwhile, the third self-stabilizing transistor T10, the fourth self-stabilizing transistor T11, the first auxiliary transistor T15, the second auxiliary transistor T16, the third auxiliary transistor T21, and the fourth auxiliary transistor T22 operate in the same state as time period t6 (all are off) to avoid affecting W[n] and M[n].

[0129] Meanwhile, P[n-2] is the same as time period t7, and the fifth auxiliary transistor T23, the third pull-down transistor T24, and the third pull-up transistor T25 operate in the same state as the time period stabilizing transistor T7 (all are off), and Q1[n] and the second gate signal Pout1[n] remain at the previous high potential;

[0130] During time period t9: the potential status of the first clock signal XCK, the third clock signal CK2, and the second clock signal CK1 becomes the same as during time period t7. Then, the shift transistor T1 is turned off, O[n] and the first gate signal EM[n] remain at the previous high potential, and N[n] remains at the previous low potential.

[0131] At the same time, EM[n-4] is still at the corresponding low potential, K[n], W[n], and M[n] remain at the previous low potential, and P[n] and the second gate signal Nout[n] remain at the previous high potential;

[0132] Meanwhile, the third self-stabilizing transistor T10, the fourth self-stabilizing transistor T11, the first auxiliary transistor T15, the second auxiliary transistor T16, the third auxiliary transistor T21, and the fourth auxiliary transistor T22 operate in the same state as time period t7 (all are off) to avoid affecting W[n] and M[n].

[0133] Meanwhile, P[n-2] is the same as time period t8, and Q1[n] and the second gate signal Pout1[n] remain at the previous high potential;

[0134] During periods 4 to 9, the fifth auxiliary transistor T23 and the sixth auxiliary transistor T26 are cut off, so the second clock signal CK1 and the third clock signal CK2 are ineffective.

[0135] During time period t10: When the potentials of the first clock signal XCK, the third clock signal CK2, and the second clock signal CK1 change to the same as the first self-stabilizing transistor T8, the shift transistor T1 is turned on, O[n] becomes the corresponding high potential, the first gate signal EM[n] remains at the previous high potential, and N[n] remains at the previous low potential;

[0136] At the same time, EM[n-4] is still at the corresponding low potential, K[n], W[n], and M[n] remain at the previous low potential, and P[n] and the second gate signal Nout[n] remain at the previous high potential;

[0137] Meanwhile, the third self-stabilizing transistor T10, the fourth self-stabilizing transistor T11, the first auxiliary transistor T15, the second auxiliary transistor T16, the third auxiliary transistor T21, and the fourth auxiliary transistor T22 operate in the same state as time period t8 (all are off) to avoid affecting W[n] and M[n].

[0138] At the same time, P[n-2] becomes the corresponding low potential, the fifth auxiliary transistor T23 turns on, making Q1[n] become the corresponding low potential, and similarly the sixth auxiliary transistor T26 turns on, making the signal Q2[n] of node Q2 become the corresponding low potential. Then the third pull-down transistor T24 and the fourth pull-down transistor T27 both turn on, and the high-to-low potential in the second clock signal CK1 is transmitted to Pout1[n], and the high potential in the third clock signal CK2 is transmitted to Pout2[n].

[0139] During time period t11: the potential status of the first clock signal XCK, the third clock signal CK2, and the second clock signal CK1 becomes the same as during time period t9. Then the shift transistor T1 is turned off, O[n] and the first gate signal EM[n] remain at the previous high potential, and N[n] remains at the previous low potential.

[0140] At the same time, EM[n-4] is still at the corresponding low potential, K[n], W[n], and M[n] remain at the previous low potential, and P[n] and the second gate signal Nout[n] remain at the previous high potential;

[0141] Meanwhile, the third self-stabilizing transistor T10, the fourth self-stabilizing transistor T11, the first auxiliary transistor T15, the second auxiliary transistor T16, the third auxiliary transistor T21, and the fourth auxiliary transistor T22 operate in the same state as time period t9 (all are off) to avoid affecting W[n] and M[n].

[0142] Meanwhile, P[n-2] is the same as time period t10. The fifth auxiliary transistor T23, the sixth auxiliary transistor T26, the third pull-down transistor T24, and the fourth pull-down transistor T27 operate in the same state as time period t10 (all are turned on). Q1[n] and Q2[n] are both maintained at their corresponding low potentials. The high potential in the second clock signal CK1 is transmitted to Pout1[n], and the potential from low to high in the third clock signal CK2 is transmitted to Pout2[n].

[0143] During time period t12: The potentials of the first clock signal XCK, the third clock signal CK2, and the second clock signal CK1 become the same as during time period t10. Then, the shift transistor T1 is turned on, but the frame start signal STV or the first gate signal EM[n-1] of the (n-1)th stage is at the corresponding low potential, and O[n] becomes at the corresponding low potential, which makes the first pull-down transistor T2, the first inverting transistor T4, and the stabilizing transistor T7 turn on, so that the low potential voltage signal first voltage signal PVGL is output as the first gate signal EM[n] and the second voltage signal PVGH is output as N[n]. Then, the first pull-up transistor T3 is turned off.

[0144] Simultaneously, EM[n-4] is at the corresponding low potential, K[n] becomes the corresponding high potential, and thus the first self-stabilizing transistor T8 is turned on and the second self-stabilizing transistor T9 is turned off, and thus P[n] becomes the corresponding low potential (making the first frequency divider transistor T13 and the third frequency divider transistor T19 turn on, and thus the second frequency divider transistor T14 and the fourth frequency divider transistor T20 turn on, and the signal W[n] of the fourth node W and the signal M[n] of the sixth node M are at the corresponding high potential), and the second pull-down transistor T18 is turned on to output the third voltage signal NVGL as the second gate signal Nout[n], and the fifth self-stabilizing transistor T12 is turned off;

[0145] At the same time, the third self-stabilizing transistor T10, the fourth self-stabilizing transistor T11, the first auxiliary transistor T15, the second auxiliary transistor T16, the third auxiliary transistor T21, and the fourth auxiliary transistor T22 are all turned on (the same as the time shift transistor T1), so K[n], W[n], and M[n] are all at high potentials;

[0146] Meanwhile, P[n-2] is the same as time period t10, the working state of the fifth auxiliary transistor T23 and the sixth auxiliary transistor T26 is the same as time period t10 (both are turned on), Q1[n] and Q2[n] are both turned on, the third pull-down transistor T24 and the fourth pull-down transistor T27 are both turned off, and since the third pull-up transistor T25 and the fourth pull-up transistor T28 are both turned on, the second voltage signal PVGH is output as Pout1[n] and Pout2[n];

[0147] During the aforementioned time periods 10 to 12, the fifth auxiliary transistor T23 and the sixth auxiliary transistor T26 are turned on, and the second clock signal CK1 and the third clock signal CK2 are activated.

[0148] It should be noted that the above analysis is based on the premise that "both the first frequency division control signal NLF and the second frequency division control signal PLF are at their corresponding low potentials," meaning that the frequency of all regions can be equal. However, if at least one of the first frequency division control signal NLF and the second frequency division control signal PLF is at its corresponding high potential, it can be considered that even if at least one of the first frequency division transistor T13 and the third frequency division transistor T19 is turned on, at least one of the corresponding fourth node W and sixth node M is still electrically disconnected from the second node K. This causes the first frequency division circuit 3041 and the second frequency division circuit 3042 in the gate drive stage circuit to be unable to be controlled by the second node K in real time to achieve the output of the gate pulse, thereby enabling the segmented frequency setting within the display area of ​​the display device 100.

[0149] Embodiments of this application also provide a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0150] In some embodiments, as shown in Figures 3 to 4 and Figures 6 to 8, the display device 100 includes the aforementioned plurality of sub-pixels Pi, a plurality of first gate lines 101, a plurality of second gate lines 102, a plurality of third gate lines 103, and any one of the aforementioned first output circuit 3031, second output circuit 3032, and third output circuit 3033. The plurality of sub-pixels Pi are arranged into a plurality of sub-pixel groups (here, a sub-pixel group includes a plurality of sub-pixels Pi in the same row as an example). The first output terminal (outputting a first gate signal EM[n]) is electrically connected to two corresponding first gate lines 101 to drive two corresponding sub-pixel groups. The second output terminal (outputting a second gate signal Nout[n]) is electrically connected to two second gate lines 102 corresponding to two sub-pixel groups. The third output terminal (outputting a third gate signal Pout1[n]) is electrically connected to one of the third gate lines 103 corresponding to one of the two sub-pixel groups.

[0151] That is, the gate driving stage circuit 201 drives multiple sub-pixels Pi in a "one-to-two" manner. Specifically, the first gate signal EM[n] generated by the same gate driving stage circuit 201 is transmitted to the two rows of sub-pixels Pi through two first gate lines 101, the second gate signal Nout[n] generated is transmitted to the two rows of sub-pixels Pi through two second gate lines 102, and the third gate signal Pout1[n] generated is transmitted to one of the two rows of sub-pixels Pi through a third gate line 103.

[0152] Furthermore, considering that the third gate signal Pout1[n] generated by the same gate driving stage circuit 201 can only drive one of the two rows of sub-pixels Pi, in order to drive the other of the two rows of sub-pixels Pi, the display device 100 further includes multiple fourth gate lines 104. The nth stage gate driving stage circuit further includes: a fourth output circuit 3034, electrically connected to the shift register circuit 301, used to generate a fourth gate signal Pout2[n] transmitted to the corresponding fourth output terminal. The fourth gate signal Pout2[n] is obtained by translating the third gate signal Pout1[n] along the time axis. One of the two sub-pixel groups is electrically connected to the third gate line 103, and the other is electrically connected to the fourth gate line 104.

[0153] Specifically, as shown in Figures 12 and 13, the sub-pixel Pi includes: a light-emitting element D; a driving transistor M1 electrically connected to the light-emitting element D; a light-emitting control transistor (e.g., including a first light-emitting control transistor M2 and a second light-emitting control transistor M3) electrically connected to the driving transistor M1, the gate of the light-emitting control transistor being electrically connected to the first gate line (transmitting a first gate signal EM[n]); a compensation transistor M4 electrically connected between the source, drain, and gate of the driving transistor M1, the gate of the compensation transistor M4 being electrically connected to the second gate line (transmitting a second gate signal Nout[n]); and a data writing transistor M5 electrically connected to the other of the source and drain of the driving transistor M1, the gate of the data writing transistor M5 of one of the two sub-pixel groups or the gate of the data writing transistor M5 of both sub-pixel groups being electrically connected to the third gate line 103 or the fourth gate line 104.

[0154] In this process, a high-voltage signal VDD is applied to the source or drain of the unconnected driving transistor M1 of the second light-emitting control transistor M3, and a low-voltage signal VSS is applied to the source or drain of the unconnected driving transistor M1 of the first light-emitting control transistor M2.

[0155] That is, in the "one-to-two" method, the gate of the data writing transistor M5 of one of the two driven sub-pixel groups is electrically connected to the third gate line 103 to load the third gate signal Pout1[n], and the gate of the data writing transistor M5 of the other is electrically connected to the fourth gate line 104 to load the fourth gate signal Pout2[n]. The pulse of the fourth gate signal Pout2[n] can lag behind the pulse of the third gate signal Pout1[n], so that the corresponding two rows of sub-pixels Pi are sequentially written with their corresponding data signals Data.

[0156] In some embodiments, as shown in Figures 7 and 8, based on the above-described "one-to-two" approach, the display device 100 includes multiple fifth gate lines 105, a first gate driving circuit and a second gate driving circuit located on both sides of the multiple sub-pixels Pi respectively; the first gate driving circuit is the aforementioned gate driving stage circuit 201; the second gate driving circuit includes multiple cascaded first gate driving stage circuits 2021, the first gate driving stage circuit 2021 being used to generate a fifth gate signal EM'[n] output to the fifth gate line 105, the fifth gate signal EM'[n] including at least two corresponding pulses within one frame; the fifth gate signal EM'[n] is transmitted to the two fifth gate lines 105 corresponding to the two sub-pixel groups.

[0157] That is, the dual-sided drive composed of gate drive stage circuit 201 and first gate drive stage circuit 2021 both drive multiple sub-pixels Pi in a "one-drives-two" manner. Based on the former's drive, the fifth gate signal EM'[n] generated by the same first gate drive stage circuit 2021 is transmitted to the two rows of sub-pixels Pi through two fifth gate lines 105 respectively.

[0158] It should be noted that since the pulse shape of the fifth gate signal EM'[n] generated by the first gate driving stage circuit 2021 is different from the pulse shape of the first gate signal EM[n], it can be considered that the first gate driving stage circuit 2021 is controlled by the fifth gate signal of a previous stage.

[0159] Specifically, as shown in Figures 12 and 13, the sub-pixel Pi further includes: a first reset transistor M6, electrically connected to the light-emitting element D; a second reset transistor M7, electrically connected to the other of the source and drain of the driving transistor M1; and the gates of the first reset transistor M6 and the second reset transistor M7 are both electrically connected to the fifth gate line 105.

[0160] That is, in the dual-side driving superimposed "one-drive-two" gate driving stage circuit 201 and the first gate driving stage circuit 2021, based on the former's driving, the gates of the first reset transistor M6 and the second reset transistor M7 of the two driven sub-pixel groups are electrically connected to the fifth gate line 105 to load the fifth gate signal EM'[n]. Among them, at least two pulses of the fifth gate signal EM'[n] within a frame can respectively cause the corresponding two rows of sub-pixels Pi to write the corresponding first reset signal Vi1 and the corresponding second reset signal Vi2.

[0161] In some embodiments, as shown in Figures 7 and 8, the display device 100 includes a plurality of sixth gate lines 106; the second gate driving circuit further includes a plurality of cascaded second gate driving stage circuits 2022, the second gate driving stage circuits 2022 being used to generate a sixth gate signal Nout'[n] output to the sixth gate line 106, the sixth gate signal Nout'[n] being obtained by translating the second gate signal Nout[n] along the time axis; the sixth gate signal Nout'[n] being transmitted to the two sixth gate lines 106 corresponding to the two sub-pixel groups.

[0162] That is, in the dual-side drive superposition "one-drive-two", based on the drive mentioned above, the sixth gate signal Nout'[n] generated by the same first gate drive stage circuit 2021 is transmitted to the two rows of sub-pixels Pi through two sixth gate lines 106 respectively.

[0163] Specifically, as shown in Figures 12 and 13, the sub-pixel Pi further includes: a third reset transistor M8, electrically connected to the gate of the driving transistor M1, and the gate of the third reset transistor M8 is electrically connected to the sixth gate line 106.

[0164] That is, in the above-mentioned bilateral driving superposition "one-to-two", the gates of the third reset transistors M8 of the two driven sub-pixel groups are electrically connected to the sixth gate line 106 to load the sixth gate signal Nout'[n]. The pulse of the sixth gate signal Nout'[n] can lead the pulse of the second gate signal Nout[n], so that the corresponding two rows of sub-pixels Pi write the corresponding third reset signal Vi3 before storing the data signal Data.

[0165] In some embodiments, as shown in FIG7, the second gate driving stage circuit 2022 is further configured to generate the third gate signal Pout1[n] output to the third gate line 103 and the fourth gate signal Pout4[n] output to the fourth gate line 104; or, as shown in FIG8, the second gate driving circuit further includes a plurality of cascaded third gate driving stage circuits 2023, the third gate driving stage circuits 2023 being configured to generate the third gate signal Pout1[n] output to the third gate line 103 and the fourth gate signal Pout4[n] output to the fourth gate line 104.

[0166] That is, in the dual-side driving superposition "one-drive-two", based on the driving above, as shown in Figure 7, the second gate driving stage circuit 2022 can also generate the third gate signal Pout1[n] and the fourth gate signal Pout4[n], so as to combine with the third gate signal Pout1[n] and the fourth gate signal Pout4[n] output by the gate driving stage circuit 201 to perform dual-side driving of the data writing transistor M5 of the two rows of sub-pixels Pi, or the third gate signal Pout1[n] and the fourth gate signal Pout4[n] can be generated by the third gate driving stage circuit 2023.

[0167] Embodiments of this application also provide a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0168] In some embodiments, as shown in Figures 1 to 2 and Figures 9 to 11, the difference from the embodiments shown in Figures 3 to 4 and Figures 6 to 8 above is that the first output terminal is electrically connected to a corresponding first gate line 101 to drive a corresponding sub-pixel group; the second output terminal is electrically connected to a second gate line 102 corresponding to a sub-pixel group; and the third output terminal is electrically connected to a third gate line 103 corresponding to one of the sub-pixel groups.

[0169] That is, the gate driving stage circuit 201 drives multiple sub-pixels Pi in a "one-to-one" manner. Specifically, the first gate signal EM[n], the second gate signal Nout[n], and the third gate signal Pout1[n] generated by the same gate driving stage circuit 201 are transmitted to a row of sub-pixels Pi through a first gate line 101, a second gate line 102, and a third gate line 103, respectively.

[0170] Based on the same circuit structure of sub-pixels Pi, the difference from the "one-to-two" approach is that, since each gate driving stage circuit 201 drives only one row of sub-pixels Pi, the data writing transistor M5 of each row of sub-pixels Pi is driven by the third gate signal Pout1[n] generated by the corresponding gate driving stage circuit 201. Furthermore, the pulse of the nth-level third gate signal Pout1[n] lags behind the (n-1)th-level third gate signal Pout1[n-1], so that the (n-1)th row of sub-pixels Pi and the nth row of sub-pixels Pi are sequentially written with the corresponding data signal Data. That is, the gate driving stage circuit 201 does not need to be configured to output the fourth gate signal Pout2[n].

[0171] In some embodiments, in the "one-to-one" method, a corresponding first gate driving circuit and a corresponding second gate driving circuit can also be set. The difference from the "one-to-two" method is that the first gate driving circuit here implements the "one-to-one" method instead of the "one-to-two" method. Correspondingly, the second gate driving circuit also includes a plurality of cascaded first gate driving stage circuits 2021. The first gate driving stage circuit 2021 is used to generate a fifth gate signal EM'[n] output to the fifth gate line 105. The fifth gate signal EM'[n] includes at least two pulses in one frame. However, the fifth gate signal EM'[n] here is only transmitted to one fifth gate line 105 corresponding to one of the sub-pixel groups.

[0172] That is, in the "one-to-one" method, the fifth gate signal EM'[n] generated by the first gate driving stage circuit 2021 of the second gate driving circuit also drives only one row of sub-pixels Pi.

[0173] Specifically, based on the circuit structure of the sub-pixel Pi mentioned above, the difference from the "one-to-two" method is that the gate of the first reset transistor M6 and the gate of the second reset transistor M7 of each row of sub-pixels Pi are electrically connected to one corresponding fifth gate line 105 instead of two.

[0174] In some embodiments, in the "one-to-one" method, the display device 100 also includes multiple sixth gate lines 106, and the second gate driving stage circuit 2022 of the second gate driving circuit is also used to generate the sixth gate signal Nout'[n] output to the sixth gate line 106. The difference from the "one-to-two" method is that the sixth gate signal Nout'[n] here is only transmitted to one sixth gate line 106 corresponding to one of the sub-pixel groups.

[0175] That is, in the "one-to-one" method, the sixth gate signal Nout'[n] generated by the second gate driving stage circuit 2022 of the second gate driving circuit also drives only one row of sub-pixels Pi.

[0176] Specifically, based on the circuit structure of the sub-pixel Pi mentioned above, the difference from the "one-to-two" method is that the gate of the third reset transistor M8 of each row of sub-pixels Pi is electrically connected to one corresponding sixth gate line 106 instead of two.

[0177] Similar to the above "one-drive-two" approach, based on the first gate drive stage circuit 2021 generating and outputting the fifth gate signal EM'[n] and the second gate drive stage circuit 2022 generating and outputting the sixth gate signal Nout'[n], as shown in Figure 10, the third gate signal Pout1[n] can be generated and output by the second gate drive stage circuit 2022, or as shown in Figure 11, it can also be generated and output by adding a third gate drive stage circuit 2023.

[0178] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A gate driving circuit, wherein, This includes multiple cascaded gate drive stage circuits, each gate drive stage circuit comprising: The first output circuit includes a first control terminal, a first input terminal and a first output terminal, and is used to transmit the signal of the first input terminal to the first output terminal according to the signal of the first control terminal to form a first gate signal. The second output circuit includes a second control terminal, a second input terminal, and a second output terminal, and is used to transmit the signal from the second input terminal to the second output terminal according to the signal from the second control terminal to form a second gate signal. The third output circuit includes a third control terminal, a third input terminal and a third output terminal, and is used to transmit the signal of the third input terminal to the third output terminal according to the signal of the third control terminal to form a third gate signal. The control circuit is used to control the signals of the first control terminal, the second control terminal, and the third control terminal according to the frame start signal or the signal of the output terminal of the gate drive stage circuit of the previous i stages, the first clock signal, and the power supply signal, where i is a positive integer; Wherein, at least one of the pulse width and effective potential of any one of the first gate signal, the second gate signal, and the third gate signal is different from at least one of the pulse width and effective potential of the other two of the first gate signal, the second gate signal, and the third gate signal.

2. The gate driving circuit according to claim 1, wherein, The control circuit includes: The shift register circuit is at least used to control the signal of the first node according to the frame start signal or the signal at the output of the gate drive stage circuit of the previous i-th stage, and the first clock signal. The control circuit is used to control the signals of the first control terminal, the second control terminal, and the third control terminal according to the signals of the first node.

3. The gate driving circuit according to claim 2, wherein, The input terminal of the shift register circuit is electrically connected to the first output terminal of the output terminal of the previous i-th stage gate drive stage circuit, and the control circuit further includes: A filtering circuit is electrically connected between the shift register circuit and the second output circuit, and the control terminal of the filtering circuit is electrically connected to a filtering control line for transmitting filtering control signals. The filtering circuit is used to control the signal of the second control terminal in response to the filtering control signal, so that the second output circuit generates a second gate signal with a pulse width smaller than that of the first gate signal.

4. The gate driving circuit according to claim 3, wherein, The filtering control signal is the first gate signal of the first k stages, where k is a positive integer greater than i.

5. The gate driving circuit according to claim 3, wherein, The shift register circuit is used to control the potential of the frame start signal or the first gate signal of the previous i stages to act on the first node in response to the first potential of the first clock signal transmitted by the first clock line. The filtering circuit is connected to the shift register circuit through the first node and is used to control the signal of the second node in response to the signal of the first node and the filtering control signal.

6. The gate driving circuit according to claim 5, wherein, The filtering circuit includes: A filter transistor, wherein the gate of the filter transistor is electrically connected to the control terminal of the filter circuit, one of the source and drain of the filter transistor is electrically connected to the first node, and the other of the source and drain of the filter transistor is electrically connected to the second node.

7. The gate driving circuit according to claim 5, wherein, The shift register circuit is also used to control the potential of the frame start signal or the first gate signal of the previous i stage to act on the third node in response to the first potential of the first clock signal; The first output circuit is connected to the shift register circuit through the third node, and is used to generate the corresponding first gate signal in response to the signal of the third node.

8. The gate driving circuit according to claim 7, wherein, The phase of the signal from the first node is opposite to the phase of the signal from the third node.

9. The gate driving circuit according to claim 7, wherein, The first output circuit includes: A first pull-down transistor, the gate of which is electrically connected to the third node, and one of the source and drain of which is electrically connected to the first voltage line. The first pull-up transistor has its gate electrically connected to the first node, and one of its source and drain is electrically connected to the second voltage line. The other of the source and drain of the first pull-down transistor and the other of the source and drain of the first pull-up transistor are both electrically connected to the first gate line for outputting the first gate signal.

10. The gate driving circuit according to claim 9, wherein, The first output circuit further includes a first capacitor electrically connected between the first gate line and the third node.

11. The gate drive circuit according to claim 7, wherein, The control circuit also includes: A stabilizing circuit, electrically connected between the third node, one of the first nodes, and the second node, is used to control the signal of the second node in response to a signal from the third node or a signal from the first node.

12. The gate driving circuit according to claim 11, wherein, The stabilizing circuit includes: A stable transistor, wherein the gate of the stable transistor is electrically connected to one of the third node and the first node, one of the source and the drain of the stable transistor is electrically connected to a second voltage line, and the other of the source and the drain of the stable transistor is electrically connected to the second node.

13. The gate drive circuit according to claim 5, wherein, The third output circuit is connected to the filtering circuit through the second node. The signal at the third input terminal is the second clock signal. The third output circuit is used to output the second clock signal as the third gate signal in response to the third potential of the signal at the second node.

14. The gate drive circuit according to any one of claims 5 to 13, wherein, The control circuit also includes: The self-stabilizing circuit is electrically connected to at least one of the second output circuit, the third output circuit, and the filtering circuit through the second node, and is used to stabilize the signal of the second node according to the signal of the second node.

15. The gate drive circuit according to any one of claims 5 to 13, wherein, The control circuit also includes: The first frequency divider circuit has its control terminal electrically connected to the first frequency divider control line for transmitting the first frequency divider control signal, its input terminal electrically connected to the second node, and its output terminal electrically connected to the second output circuit through the fourth node. The first frequency divider circuit is used to control the electrical connection between the fourth node and the second node in response to the second potential of the first frequency divider control signal.

16. The gate drive circuit according to claim 15, wherein, The control circuit also includes: The second frequency divider circuit has its control terminal electrically connected to the second frequency divider control signal second frequency divider control line for transmission, its input terminal electrically connected to the second node, and its output terminal electrically connected to the third output circuit through the sixth node. The second frequency divider circuit is used to control the electrical connection between the sixth node and the second node in response to the fourth potential of the second frequency divider control signal.

17. The gate drive circuit according to claim 16, wherein, The control circuit also includes: A self-stabilizing circuit is connected to the second node and connected to at least one of the second output circuit and the third output circuit via the fifth node. The self-stabilizing circuit is used to control the signal of the fifth node in response to the signal of the second node. The second output circuit is used to control the signal of the fourth node in response to the signal of the fifth node. The third output circuit is used to control the signal of the sixth node in response to the signal of the fifth node.

18. The gate drive circuit according to claim 13, 16 or 17, wherein, The gate drive stage circuit further includes: The fourth output circuit is connected to the filter circuit through the second node. The first terminal of the fourth output circuit is electrically connected to the third clock line. The fourth output circuit is used to output the third clock signal transmitted by the third clock line in response to the third potential of the signal of the second node as the corresponding fourth gate signal. The third clock signal is obtained by shifting the second clock signal along the time axis, and the fourth gate signal is obtained by shifting the third gate signal along the time axis.

19. A display device, wherein, It includes multiple sub-pixels, multiple first gate lines, multiple second gate lines, multiple third gate lines, and a gate driving circuit as described in any one of claims 1 to 17, wherein the multiple sub-pixels are arranged into multiple sub-pixel groups. The first output terminal is electrically connected to the corresponding two first gate lines to drive the corresponding two sub-pixel groups; The second output terminal is electrically connected to the two second gate lines corresponding to the two sub-pixel groups; The third output terminal is electrically connected to a third gate line corresponding to one of the two sub-pixel groups.

20. The display device according to claim 19, wherein, The display device further includes multiple fourth gate lines, and the gate driving stage circuit further includes: The fourth output circuit is electrically connected to the shift register circuit and is used to generate a fourth gate signal that is transmitted to the corresponding fourth output terminal. The fourth gate signal is obtained by shifting the third gate signal along the time axis. One of the two sub-pixel groups is electrically connected to the third gate line, and the other is electrically connected to the fourth gate line.

21. The display device according to claim 20, wherein, The sub-pixels include: Light-emitting elements; A driving transistor is electrically connected to the light-emitting element; A light-emitting control transistor is electrically connected to the driving transistor, and the gate of the light-emitting control transistor is electrically connected to the first gate line; A compensation transistor is electrically connected between the source, drain, and gate of the driving transistor, and the gate of the compensation transistor is electrically connected to the second gate line. A data writing transistor is electrically connected to the other of the source and drain of the driving transistor, and the gate of the data writing transistor is electrically connected to the third gate line or the fourth gate line.

22. The display device according to claim 21, wherein, The display device includes multiple fifth gate lines, a first gate driving circuit and a second gate driving circuit located on both sides of the multiple sub-pixels respectively. The first gate driving circuit is the gate driving circuit as described in claim 20; The second gate driving circuit includes a plurality of cascaded first gate driving stage circuits, wherein the first gate driving stage circuit is used to generate a fifth gate signal output to the fifth gate line, and the fifth gate signal includes at least two corresponding pulses within one frame; The fifth gate signal is transmitted to the two fifth gate lines corresponding to the two sub-pixel groups.

23. The display device according to claim 22, wherein, The sub-pixel also includes: The first reset transistor is electrically connected to the light-emitting element; The second reset transistor is electrically connected to the other of the source and drain of the driving transistor, and the gates of the first reset transistor and the second reset transistor are both electrically connected to the fifth gate line.

24. The display device according to any one of claims 21 to 23, wherein, The display device includes multiple sixth gate lines; The second gate driving circuit further includes a plurality of cascaded second gate driving stage circuits, the second gate driving stage circuits being used to generate a sixth gate signal output to the sixth gate line, the sixth gate signal being obtained by translating the second gate signal along the time axis; The sixth gate signal is transmitted to the two sixth gate lines corresponding to the two sub-pixel groups.

25. The display device according to claim 24, wherein, The second gate drive stage circuit is also used to generate the third gate signal output to the third gate line and the fourth gate signal output to the fourth gate line.

26. The display device according to claim 24, wherein, The second gate driving circuit further includes a plurality of cascaded third gate driving stage circuits, wherein the third gate driving stage circuits are used to generate the third gate signal output to the third gate line and the fourth gate signal output to the fourth gate line.

27. The display device according to claim 24, wherein, The sub-pixel also includes: The third reset transistor is electrically connected to the gate of the driving transistor, and the gate of the third reset transistor is electrically connected to the sixth gate line.

28. A display device, wherein, It includes multiple sub-pixels, multiple first gate lines, multiple second gate lines, multiple third gate lines, and a gate driving circuit as described in any one of claims 1 to 17, wherein the multiple sub-pixels are arranged into multiple sub-pixel groups. The first output terminal is electrically connected to a corresponding first gate line to drive a corresponding sub-pixel group; The second output terminal is electrically connected to a second gate line corresponding to one of the sub-pixel groups; The third output terminal is electrically connected to a third gate line corresponding to one of the sub-pixel groups.

29. The display device according to claim 28, wherein, The sub-pixels include: Light-emitting elements; A driving transistor is electrically connected to the light-emitting element; A light-emitting control transistor is electrically connected to the driving transistor, and the gate of the light-emitting control transistor is electrically connected to the first gate line; A compensation transistor is electrically connected between the source, drain, and gate of the driving transistor, and the gate of the compensation transistor is electrically connected to the second gate line. A data writing transistor is electrically connected to the other of the source and drain of the driving transistor, and the gate of the data writing transistor is electrically connected to the third gate line.

30. The display device according to claim 29, wherein, The display device includes multiple fifth gate lines, a first gate driving circuit and a second gate driving circuit located on both sides of the multiple sub-pixels respectively. The first gate driving circuit is the gate driving circuit as described in claim 28; The second gate driving circuit includes a plurality of cascaded first gate driving stage circuits, wherein the first gate driving stage circuit is used to generate a fifth gate signal output to the fifth gate line, and the fifth gate signal includes at least two corresponding pulses within one frame; The fifth gate signal is transmitted to a fifth gate line corresponding to a sub-pixel group.

31. The display device according to claim 30, wherein, The sub-pixel also includes: The first reset transistor is electrically connected to the light-emitting element; The second reset transistor is electrically connected to the other of the source and drain of the driving transistor, and the gates of the first reset transistor and the second reset transistor are both electrically connected to the fifth gate line.

32. The display device according to any one of claims 29 to 31, wherein, The display device includes multiple sixth gate lines; The second gate driving circuit further includes a plurality of cascaded second gate driving stage circuits, the second gate driving stage circuits being used to generate a sixth gate signal output to the sixth gate line, the sixth gate signal being obtained by translating the second gate signal along the time axis; The sixth gate signal is transmitted to a sixth gate line corresponding to a sub-pixel group.

33. The display device according to claim 32, wherein, The second gate drive stage circuit is also used to generate the third gate signal output to the third gate line.

34. The display device according to claim 32, wherein, The second gate driving circuit further includes a plurality of cascaded third gate driving stage circuits, the third gate driving stage circuits being used to generate the third gate signal output to the third gate line.

35. The display device according to claim 32, wherein, The sub-pixel also includes: The third reset transistor is electrically connected to the gate of the driving transistor, and the gate of the third reset transistor is electrically connected to the sixth gate line.

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