Chip, chip manufacturing method, packaging substrate, and packaged chip

Abstract

The present application provides a chip, a chip manufacturing method, a packaging substrate, and a packaged chip. The chip comprises a substrate and a deep trench capacitor; the substrate has a first surface and a second surface that are opposite to each other; the deep trench capacitor comprises a plurality of deep trenches; the plurality of deep trenches are spaced apart and embedded into the first surface; a partial region of the first surface and the inner walls of the plurality of deep trenches are provided with sub-capacitor structures formed by N+1 electrode layers and N capacitor dielectric layers, N being a positive integer; a groove passing through at least two electrode layers and at least one capacitor dielectric layer is present in a thickness direction of the substrate, the groove is located between two adjacent deep trenches, the groove separates the at least two electrode layers and the at least one capacitor dielectric layer, and at least one electrode layer on one side of the groove is connected to any electrode layer on the other side of the groove by means of a conductive path. By physically separating a weak layer, the present application can effectively avoid a short circuit, and improve the voltage withstand capability of the separated weak layer, thereby improving the reliability and stability of an entire device.

Description

A chip, a chip manufacturing method, a packaging substrate, and a packaged chip.

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411904988.4, filed on December 20, 2024, with the invention entitled "A chip, a chip manufacturing method, a packaging substrate and a packaged chip", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor manufacturing, and in particular to a chip, a chip manufacturing method, a packaging substrate, and a packaged chip. Background Technology

[0004] With advancements in semiconductor process technology, especially the widespread adoption of FinFET (Fin Field-Effect Transistor) technology, the demand for drive strength per unit area has increased significantly, requiring higher current density and faster current change rates. These changes place higher demands on the stability of the power supply voltage, necessitating more effective methods to control parasitic resistance and inductance to reduce noise and optimize power integrity (PI).

[0005] Against this backdrop, high-capacitance-density deep trench capacitors (DTCs) have become key components in modern chip design and packaging technologies due to their excellent energy storage, filtering, and decoupling capabilities. Compared with traditional multilayer ceramic capacitors (MLCCs), deep trench capacitors exhibit significant advantages in achieving device miniaturization, supporting multi-port and multi-power-domain operation, and improving integration. Existing deep trench capacitor structures typically consist of multiple cells arranged in alternating patterns of trench / fin, pillar / trench, or via / trench, with the deep trench filled with single-sided electrodes and dielectric material.

[0006] However, existing deep-groove capacitor technology has some limitations. As the number of thin film layers inside the capacitor increases, the aspect ratio within the deep trench continuously improves, leading to inconsistencies in the quality and electrical performance of each film layer. This inconsistency may affect the reliability and performance of the final product. Furthermore, since all capacitor cells and layers are connected in parallel, a defect in one layer or cell (such as a short circuit or open circuit) can affect the entire power domain, causing the entire deep-groove capacitor to fail and disrupting the normal operation of the entire circuit.

[0007] In view of this, a new chip is needed to overcome the shortcomings of the existing structure and improve the reliability of deep trench capacitors and the device yield. Summary of the Invention

[0008] This application provides a chip, a chip manufacturing method, a packaging substrate, and a packaged chip. By designing and optimizing the internal structural layout of deep trench capacitors, the robustness and redundancy of deep trench capacitors in the face of local faults in weak layers are improved, thereby improving the reliability of deep trench capacitors and the yield of devices.

[0009] In a first aspect, this application provides a chip, comprising: a substrate and a deep trench capacitor. The substrate has a first surface and a second surface opposite to each other. The deep trench capacitor comprises: a plurality of deep trenches, the plurality of deep trenches being embedded in the first surface at intervals. A sub-capacitor structure formed by N+1 electrode layers and N capacitor dielectric layers is disposed on a portion of the first surface and the inner wall of the plurality of deep trenches, where N is a positive integer. A groove is present in the thickness direction of the substrate, penetrating at least two electrode layers and at least one capacitor dielectric layer. The groove is located between two adjacent deep trenches. The groove disconnects at least two electrode layers and at least one dielectric layer. At least one electrode layer on the disconnected side is connected to any electrode layer on the disconnected side through a conductive path.

[0010] In the above design, a groove extends through at least two electrode layers and at least one capacitor dielectric layer in the thickness direction of the substrate. This groove is located between two adjacent deep trenches. The main purpose of the groove is to physically disconnect weak layers with slightly inferior quality or electrical performance. If these layers are not disconnected, short circuits may form on them, affecting the overall performance of the deep trench capacitor. By physically disconnecting these layers, short circuits can be effectively avoided, and the withstand voltage of the disconnected weak layers can be improved, thereby enhancing the reliability and stability of the entire device.

[0011] Furthermore, in order to convert the disconnected capacitors into a series connection after the original parallel connection is broken, this application uses a conductive path to connect the disconnected electrodes in series, so that these electrode capacitors are changed from a parallel connection to a partially series and parallel connection, thereby maximizing the capacitance.

[0012] In one possible implementation, the groove divides a sub-capacitor into two separate sub-capacitors. At least one electrode layer on the disconnected side is connected to any electrode layer on the disconnected side via a conductive path, thus connecting the two separate sub-capacitors in series. In the above design, the electrode layers on the disconnected side are connected to the electrode layers on the disconnected side via a conductive path, thereby connecting the two separate sub-capacitors in series. In this way, the original weak layer is broken, and the two series-connected separate sub-capacitors share the voltage that would originally be borne by a single capacitor, reducing the risk of failure of the entire deep groove capacitor.

[0013] As one possible implementation, it further includes: a redistribution layer, the redistribution layer being opposite to the first surface, the redistribution layer including a first interconnect and a second interconnect, the redistribution layer including at least one first contact hole and at least one second contact hole, a first power supply terminal being connected to the first contact hole via the first interconnect, a second power supply terminal being connected to the second contact hole via the second interconnect, a first electrode layer on the disconnected side being connected to a second electrode layer on the disconnected side via a conductive path, a first contact hole being connected to a third electrode layer that is not disconnected, a first contact hole being connected to a fourth electrode layer that is disconnected, a second contact hole being connected to an electrode layer that is not disconnected except for the third electrode layer, and a second contact hole being connected to an electrode layer that is disconnected except for the first electrode layer, the second electrode layer, and the fourth electrode layer.

[0014] In the above design, after the capacitor located in the weak layer is disconnected by the groove, the two disconnected electrode layers are connected through a conductive path, thereby forming two series-connected separator capacitors. The total voltage between the first power supply terminal and the second power supply terminal will be distributed between the two series-connected separator capacitors, reducing the voltage pressure on a single capacitor and improving the withstand voltage performance. Meanwhile, the other electrodes that are not disconnected and the electrode layers that are not connected by conductive paths are connected to the first contact hole and the second contact hole respectively, thereby forming a new parallel capacitor relationship. Through reasonable redistribution layer design, the overall capacitance value can be increased without increasing the additional volume, thereby increasing the capacitance density per unit area.

[0015] In one possible implementation, the first contact hole is connected to a non-adjacent, unbroken electrode layer, and the first contact hole is connected to a non-adjacent, broken electrode layer.

[0016] By avoiding the first contact hole from being connected to an adjacent electrode layer (whether disconnected or not), the loss of capacitance density can be effectively prevented.

[0017] In one possible implementation, the second contact hole is connected to a non-adjacent, unbroken electrode layer, and the second contact hole is connected to a non-adjacent, broken electrode layer.

[0018] By avoiding the second contact hole from being connected to an adjacent electrode layer (whether disconnected or not), the loss of capacitance density can be effectively prevented.

[0019] In one possible implementation, a portion of the first surface and the inner walls of the multiple deep trenches specifically include a fifth electrode layer, a sixth electrode layer, and a first capacitor dielectric layer. The fifth electrode layer, the sixth electrode layer, and the first capacitor dielectric layer constitute a first sub-capacitor. A groove penetrating the fifth electrode layer, the sixth electrode layer, and the first capacitor dielectric layer exists in the thickness direction of the substrate. The fifth electrode layer on one side of the disconnection is connected to the fifth electrode layer on the other side of the disconnection through a conductive path. A first contact hole is connected to the sixth electrode layer on one side of the disconnection, and a second contact hole is connected to the sixth electrode layer on the other side of the disconnection.

[0020] In the above design, the original conduction loop is: first power supply terminal - sixth electrode layer - fifth electrode layer - second power supply terminal. The sixth electrode layer and the fifth electrode layer form the first sub-capacitor. The conduction loop after the groove penetrates the fifth and sixth electrode layers is: first power supply terminal - disconnect one side of the sixth electrode layer - disconnect one side of the fifth electrode layer - disconnect the other side of the fifth electrode layer - disconnect the other side of the sixth electrode layer - second power supply terminal, forming a structure where the first and second separator sub-capacitors are connected in series. This not only solves the problem of weak layers caused by the manufacturing process in deep trench capacitors, but also significantly improves the withstand voltage performance of the weak dielectric layers in deep trench capacitors. It avoids the problem of the entire deep trench capacitor failing due to the failure of a single layer or point, thus improving the device yield. Through this design, even if there are quality problems or poor electrical performance in a specific area, it will not affect the function of the entire capacitor, thereby improving the reliability and stability of the system.

[0021] In one possible implementation, a portion of the first surface and the inner walls of the multiple deep trenches specifically include a seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor; the eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor; and the ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. A groove penetrating the seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer exists in the thickness direction of the substrate. The seventh electrode layer on one side of the disconnection is connected to the seventh electrode layer on the other side of the disconnection via a conductive path. A first contact hole is connected to the eighth and tenth electrode layers on the disconnection side, and a second contact hole is connected to the eighth and ninth electrode layers on the other side of the disconnection.

[0022] In the above design, by physically disconnecting electrode layers with slightly inferior quality or electrical performance, potential short circuits are prevented, ensuring electrical isolation and thus improving overall reliability. Simultaneously, the resulting series-connected separator capacitor structure not only solves the problem of weak layers caused by the manufacturing process in deep-groove capacitors but also significantly improves the withstand voltage performance of weak dielectric layers in deep-groove capacitors. This avoids the problem of the entire deep-groove capacitor failing due to the failure of a single layer or point, thereby improving device yield.

[0023] In one possible implementation, a portion of the first surface and the inner walls of the multiple deep trenches specifically include a seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor; the eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor; and the ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. A groove penetrating the seventh electrode layer, the eighth electrode layer, the ninth electrode layer, the tenth electrode layer, the second capacitor dielectric layer, the third capacitor dielectric layer, and the fourth capacitor dielectric layer exists in the thickness direction of the substrate. The seventh electrode layer on one side of the disconnection is connected to the seventh electrode layer on the other side of the disconnection through a conductive path. A first contact hole is connected to the eighth electrode layer on one side of the disconnection, the tenth electrode layer on one side of the disconnection, and the ninth electrode layer on the other side of the disconnection. A second contact hole is connected to the ninth electrode layer on one side of the disconnection, the eighth electrode layer on the other side of the disconnection, and the tenth electrode layer on the other side of the disconnection.

[0024] In the above design, by physically disconnecting electrode layers with slightly inferior quality or electrical performance, potential short circuits are prevented, ensuring electrical isolation and thus improving overall reliability. Simultaneously, the resulting series-connected separator capacitor structure not only solves the problem of weak layers caused by the manufacturing process in deep-groove capacitors but also significantly improves the withstand voltage performance of weak dielectric layers in deep-groove capacitors. This avoids the problem of the entire deep-groove capacitor failing due to the failure of a single layer or point, thereby improving device yield.

[0025] In one possible implementation, a portion of the first surface and the inner walls of the multiple deep trenches specifically include a seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor; the eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor; and the ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. A groove penetrating the seventh electrode layer, the eighth electrode layer, the ninth electrode layer, the tenth electrode layer, the second capacitor dielectric layer, the third capacitor dielectric layer, and the fourth capacitor dielectric layer exists in the thickness direction of the substrate. The seventh electrode layer on one side of the disconnection is connected to the ninth electrode layer on the other side of the disconnection through a conductive path. A first contact hole is connected to the eighth electrode layer on one side of the disconnection, the tenth electrode layer on one side of the disconnection, and the seventh electrode layer on the other side of the disconnection. A second contact hole is connected to the ninth electrode layer on one side of the disconnection, the eighth electrode layer on the other side of the disconnection, and the tenth electrode layer on the other side of the disconnection.

[0026] In the above design, by physically disconnecting electrode layers with slightly inferior quality or electrical performance, potential short circuits are prevented, ensuring electrical isolation and thus improving overall reliability. Simultaneously, the resulting series-connected separator capacitor structure not only solves the problem of weak layers caused by the manufacturing process in deep-groove capacitors but also significantly improves the withstand voltage performance of weak dielectric layers in deep-groove capacitors. This avoids the problem of the entire deep-groove capacitor failing due to the failure of a single layer or point, thereby improving device yield.

[0027] In one possible implementation, at least one first contact hole is filled with a first interconnecting material, and at least one second contact hole is filled with a second interconnecting material to form a second interconnecting material. The first interconnecting material and the second interconnecting material are strip structures arranged at intervals.

[0028] By connecting the first interconnect and the second interconnect to each electrode layer respectively, new capacitive connections are formed, thereby increasing the overall capacitance value without increasing the volume, and thus increasing the capacitance density per unit area. The strip-shaped structure of the first and second interconnects increases the contact area between each interconnect and the electrode layer, reducing contact resistance and thus reducing energy loss and signal delay during signal transmission. The strip structure also better disperses stress, reducing the risk of breakage due to thermal expansion or mechanical stress.

[0029] In a second aspect, this application discloses a method for fabricating a chip, the method comprising: providing a substrate having opposing first and second surfaces; forming a plurality of deep trenches spaced apart on the first surface of the substrate; alternately depositing electrode material and dielectric material on a portion of the first surface and the inner walls of the plurality of deep trenches to form a sub-capacitor structure consisting of N+1 electrode layers and N capacitor dielectric layers, where N is a positive integer; etching at least one sub-capacitor to form a groove penetrating at least two electrode layers and at least one capacitor dielectric layer in the thickness direction of the substrate, the groove consisting of at least two electrode layers and at least one dielectric layer; and connecting at least one electrode layer on one disconnected side to any electrode layer on the other disconnected side via a conductive path.

[0030] In the above-described fabrication method, a groove is formed in the thickness direction of the substrate, penetrating at least two electrode layers and at least one capacitor dielectric layer. This groove is located between two adjacent deep grooves. The main purpose of the groove is to physically disconnect weak layers with slightly inferior quality or electrical performance. By physically disconnecting these layers, short circuits can be effectively avoided, and the withstand voltage of the disconnected weak layers can be improved, thereby enhancing the reliability and stability of the entire device. Furthermore, to achieve the transformation of the disconnected capacitors from a parallel connection to a series connection after the partial disconnection, this application uses a conductive path to connect the disconnected electrodes in series. This transforms the parallel connection of these electrode capacitors into a partially series-plus-parallel connection, thereby maximizing capacitance.

[0031] As one possible implementation, after providing a substrate, the method further includes: forming an organic material layer on a first surface, forming a plurality of deep trenches spaced apart on the first surface of the substrate, including: photolithographically etching a pattern at positions corresponding to the plurality of deep trenches on the organic material layer, etching the plurality of deep trenches on the organic material layer according to the pattern, and removing the organic material layer.

[0032] As one possible implementation, after alternately depositing electrode materials and dielectric materials on a portion of the first surface and the inner walls of multiple deep trenches, the method further includes: forming an organic material layer on the side of the capacitor structure opposite to the first surface; etching at least one sub-capacitor to form a groove penetrating the two electrode layers and the capacitor dielectric layer in the thickness direction of the substrate; including: photolithographically etching a pattern at the position corresponding to the groove on the organic material layer; etching the groove on the organic material layer and the capacitor structure according to the pattern; and removing the organic material layer.

[0033] As one possible implementation, the organic material layer includes one or more of a spin coating layer, a bottom anti-reflective layer, and a photoresist layer.

[0034] In one possible implementation, the method further includes: forming a composite thin film layer on the side of the capacitor structure opposite to the first surface; etching to form at least one first contact hole penetrating the composite thin film layer and connected to at least one electrode layer; etching to form at least one second contact hole penetrating the composite thin film layer and connected to at least one electrode layer; connecting a first power supply terminal to the first contact hole via a first interconnect line; connecting a second power supply terminal to the second contact hole via a second interconnect line; filling the at least one first contact hole with conductive material to form a first interconnect; and filling the at least one second contact hole with conductive material to form a second interconnect.

[0035] As one possible implementation method, the conductive material is tungsten.

[0036] In one possible implementation, the first electrode layer on the disconnected side is connected to the second electrode layer on the disconnected side via a conductive path, the first contact hole is connected to the undisconnected third electrode layer, the first contact hole is connected to the disconnected fourth electrode layer, the second contact hole is connected to the undisconnected electrode layers other than the third electrode layer, and the second contact hole is connected to the disconnected electrode layers other than the first, second, and fourth electrode layers.

[0037] In one possible implementation, electrode layer material and dielectric material are alternately deposited on a portion of the first surface and the inner walls of multiple deep trenches. A fifth electrode layer, a sixth electrode layer, and a first capacitor dielectric layer are formed on a portion of the first surface and the inner walls of multiple deep trenches. The fifth electrode layer, the sixth electrode layer, and the first capacitor dielectric layer constitute a first sub-capacitor. The first sub-capacitor is etched to form a groove that penetrates the fifth electrode layer, the first capacitor dielectric layer, and the sixth electrode layer in the thickness direction of the substrate. The fifth electrode layer on one side of the disconnection is connected to the fifth electrode layer on the other side of the disconnection through a conductive path. A first contact hole is connected to the sixth electrode layer on the disconnection side, and a second contact hole is connected to the sixth electrode layer on the other side of the disconnection.

[0038] In one possible implementation, electrode layer materials and dielectric materials are alternately deposited on a portion of the first surface and the inner walls of multiple deep trenches. A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are formed on a portion of the first surface and the inner walls of multiple deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor; the eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor; and the ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The second sub-capacitor is etched to form a groove penetrating the seventh electrode layer, the second capacitor dielectric layer, and the eighth electrode layer in the thickness direction of the substrate. The seventh electrode layer on one side of the disconnection is connected to the seventh electrode layer on the other side of the disconnection through a conductive path. A first contact hole is connected to the eighth and tenth electrode layers on the disconnected side, and a second contact hole is connected to the eighth and ninth electrode layers on the other side of the disconnection.

[0039] In one possible implementation, electrode layer materials and dielectric materials are alternately deposited on a portion of the first surface and the inner walls of multiple deep trenches. A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are formed on the portion of the first surface and the inner walls of the multiple deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor; the eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor; and the ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The second, third, and fourth sub-capacitors are etched to form a groove that penetrates the seventh electrode layer, the second capacitor dielectric layer, the eighth electrode layer, the third capacitor dielectric layer, the ninth electrode layer, the fourth capacitor dielectric layer, and the tenth electrode layer in the thickness direction of the substrate. The seventh electrode layer on one side of the disconnection is connected to the seventh electrode layer on the other side of the disconnection through a conductive path. The first contact hole is connected to the eighth electrode layer on one side of the disconnection, the tenth electrode layer on one side of the disconnection, and the ninth electrode layer on the other side of the disconnection. The second contact hole is connected to the ninth electrode layer on one side of the disconnection, the eighth electrode layer on the other side of the disconnection, and the tenth electrode layer on the other side of the disconnection.

[0040] In one possible implementation, electrode layer materials and dielectric materials are alternately deposited on a portion of the first surface and the inner walls of multiple deep trenches. A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are formed on the portion of the first surface and the inner walls of the multiple deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor; the eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor; and the ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The second, third, and fourth sub-capacitors are etched to form a groove that penetrates the seventh electrode layer, the second capacitor dielectric layer, the eighth electrode layer, the third capacitor dielectric layer, the ninth electrode layer, the fourth capacitor dielectric layer, and the tenth electrode layer in the thickness direction of the substrate. The seventh electrode layer on one side of the disconnection is connected to the ninth electrode layer on the other side of the disconnection through a conductive path. The first contact hole is connected to the eighth electrode layer on one side of the disconnection, the tenth electrode layer on one side of the disconnection, and the seventh electrode layer on the other side of the disconnection. The second contact hole is connected to the ninth electrode layer on one side of the disconnection, the eighth electrode layer on the other side of the disconnection, and the tenth electrode layer on the other side of the disconnection.

[0041] Thirdly, this application provides a packaging substrate, including a substrate body, the substrate body including a deep trench capacitor, the substrate body having opposing first and second surfaces, the deep trench capacitor including: a plurality of deep trenches, spaced apart and embedded in the first surface of the substrate body, N+1 electrode layers and N capacitor dielectric layers are disposed on a portion of the first surface and the inner walls of the plurality of deep trenches to form a capacitor structure, where N is a positive integer, a groove penetrating at least two electrode layers and at least one capacitor dielectric layer in the thickness direction of the substrate body, the groove disconnecting at least two electrode layers and at least one capacitor dielectric layer, at least one electrode layer on the disconnected side being connected to any electrode layer on the disconnected other side through a conductive path.

[0042] In the above design, a groove penetrating at least two electrode layers and at least one capacitor dielectric layer exists in the thickness direction of the substrate body. This groove is located between two adjacent deep grooves. By physically disconnecting these layers, short circuits can be effectively avoided, and the withstand voltage of the weaker layers after disconnection can be improved, thereby enhancing the reliability and stability of the entire device. Furthermore, to transform the originally parallel-connected capacitors into a series connection after disconnection, this application uses conductive paths to connect the disconnected electrodes in series. This transforms the parallel connection of these electrode capacitors into a partially series-plus-parallel connection, thereby maximizing capacitance.

[0043] Fourthly, this application provides a method for fabricating a packaging substrate. The method includes: providing a substrate body having opposing first and second surfaces; forming a plurality of deep trenches spaced apart on the first surface of the substrate body; alternately depositing electrode materials and dielectric materials on a portion of the first surface and the inner walls of the plurality of deep trenches to form a sub-capacitor structure consisting of N+1 electrode layers and N capacitor dielectric layers, where N is a positive integer; etching at least one sub-capacitor to form a groove penetrating at least two electrode layers and at least one capacitor dielectric layer in the thickness direction of the substrate body; the groove penetrating at least two electrode layers and at least one capacitor dielectric layer; and connecting at least one electrode layer on one side of the disconnection to any electrode layer on the other side of the disconnection via a conductive path.

[0044] In the above-described fabrication method, a groove is formed in the thickness direction of the substrate body, penetrating at least two electrode layers and at least one capacitor dielectric layer. This groove is located between two adjacent deep grooves. The main purpose of the groove is to physically disconnect weak layers with slightly inferior quality or electrical performance. By physically disconnecting these layers, short circuits can be effectively avoided, and the withstand voltage of the disconnected weak layers can be improved, thereby enhancing the reliability and stability of the entire device. Furthermore, to achieve the transformation of the disconnected capacitors into a series connection after the original parallel connection is broken, this application uses a conductive path to connect the disconnected electrodes in series. This transforms the parallel connection of these electrode capacitors into a partially series-plus-parallel connection, thereby maximizing capacitance.

[0045] Fifthly, this application provides a packaged chip, including a chip and a packaging substrate described in any of the claims in the third aspect above, wherein the chip is packaged on the packaging substrate. Since the packaging substrate can physically disconnect weak layers, it can effectively prevent short circuits and improve the withstand voltage of the disconnected weak layers, thereby improving the reliability and stability of the entire device. Therefore, the packaged chip including the aforementioned packaging substrate also has better reliability and stability.

[0046] Sixthly, this application provides an electronic device, including: a circuit board and a chip as described in any of the first aspects or a packaged chip as described in any of the fifth aspects, wherein the chip or packaged chip is disposed on the circuit board. Since the chip or packaged chip in the above-mentioned electronic device can effectively prevent short circuits by physically disconnecting weak layers, and improve the withstand voltage of the disconnected weak layers, thereby improving the reliability and stability of the entire device, the electronic device including the above-mentioned chip or packaged chip also has better performance and reliability. Attached Figure Description

[0047] Figure 1A illustrates an application scenario diagram of a chip to which this application applies.

[0048] Figure 1B illustrates an application scenario diagram of a chip provided in this application.

[0049] Figure 2A is a schematic diagram of an existing deep trench capacitor structure.

[0050] Figure 2B is a schematic diagram of an existing deep trench capacitor structure.

[0051] Figure 3 is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0052] Figure 4 is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0053] Figure 5 is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0054] Figure 6A is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0055] Figure 6B illustrates a schematic diagram of the process of changing the capacitor connection from parallel to partially series.

[0056] Figure 6C is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0057] Figure 6D illustrates another process of changing the capacitors from parallel to partially series connection.

[0058] Figure 6E is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0059] Figure 6F illustrates another process of changing the capacitors from parallel to partially series connection.

[0060] Figure 7A is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0061] Figure 7B is a top view of a chip provided in an embodiment of this application;

[0062] Figure 7C illustrates a schematic diagram of the process of changing the capacitor connection from parallel to partially series.

[0063] Figure 8A is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0064] Figure 8B is a top view of a chip provided in an embodiment of this application;

[0065] Figure 8C illustrates a schematic diagram of the process of changing the capacitors from parallel connection to partial series connection.

[0066] Figure 9A is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0067] Figure 9B is a top view of a chip provided in an embodiment of this application;

[0068] Figure 9C illustrates a schematic diagram of the process of changing the capacitor connection from parallel to partially series.

[0069] Figures 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, and 33 are schematic diagrams of a chip fabrication process. Detailed Implementation

[0070] The following section introduces the possible application scenarios of this application.

[0071] In one possible application scenario, the deep-groove capacitor in this application can be integrated into a memory, such as random access memory (RAM), which can be DRAM or static random access memory (SRAM). In some examples, the deep-groove capacitor can be a system-on-chip (SOC) chip. The device can be a device with only read and write functions, such as the device shown in Figure 1A, where the deep-groove capacitor can be applied to a disk, hard drive, or memory. Alternatively, the device can also be a device with read and write functions as well as other functions, such as the terminal device shown in Figure 1B, which can include, but is not limited to, smartphones, desktop computers, wearable devices (such as smart helmets or smartwatches), in-vehicle devices, laptops, and laptop computers.

[0072] It should be understood that the possible application scenarios given above are merely examples. The deep trench capacitor provided in this application can also be applied to other possible scenarios, and is not limited to those exemplified above. For example, it can also be applied to sensors, and furthermore, it can be applied to integrated circuits (ICs).

[0073] The deep-groove capacitors involved in this application can be used to manufacture independent integrated passive devices (IPDs). In advanced multi-chip modules or system-in-package (SiP) systems, by directly embedding the deep-groove capacitors into the silicon interposer, overall performance can be improved while reducing size and weight. In fan-out panel-level packaging (FOP) technology, the deep-groove capacitors of this application can be integrated into the package substrate as a key component. This helps improve the electrical performance of the product while simplifying layout design.

[0074] Embedding deep trench capacitors within printed circuit boards (PCBs) or other types of substrates creates a "buried capacitor" structure. This method saves surface space and improves power supply decoupling at high frequencies. Furthermore, the deep trench capacitors of this application can be applied to a wider range of fields, such as sensors and integrated circuits (ICs). For example, in sensors, they can be used to enhance the stability of analog front-ends.

[0075] The preceding text introduced the possible application scenarios of this application. The following section provides explanations of some terms used in this application. It should be noted that these explanations are for the convenience of those skilled in the art and do not constitute a limitation on the scope of protection claimed in this application.

[0076] I. Contact Hole (CT)

[0077] Contact holes can be considered as structures used to connect front-end devices and back-end metals in the back-end (BONL) process of semiconductor device manufacturing. Semiconductor device manufacturing processes are divided into front-end (FONL) processes and BONL processes. FONL processes refer to the fabrication of wafers and active devices in semiconductor devices, while BONL processes refer to the fabrication of metal layer structures.

[0078] II. The damascene process is a key process in modern semiconductor manufacturing used to form metal interconnects, especially widely used in copper interconnect technology. It involves filling material into pre-formed grooves or holes and then polishing them smooth.

[0079] III. The redistribution layer (RDL) is an important component of advanced packaging technology. RDL is mainly used to change or redistribute the positions of pads on the chip, so that internal circuit pads that were originally irregular or unsuitable for direct connection to external pins can be adapted to positions suitable for subsequent interconnection. This technology is widely used in advanced packaging processes such as multi-chip modules, system-in-package, and fan-out packaging.

[0080] IV. Chemical mechanical polishing (CMP) is a key process in semiconductor manufacturing used to planarize wafer surfaces. CMP combines chemical reactions and mechanical friction to achieve selective removal and planarization of various materials. This technology can be applied in multilayer interconnect structures, shallow trench isolation, damascene processes, and advanced packaging.

[0081] V. Physical vapor deposition (PVD) is a surface engineering technique used to form thin films on the surface of a substrate or workpiece. It is widely used in semiconductor manufacturing, optical components, decorative coatings, and many other fields. The basic principle of PVD technology is to transform the source material from a solid or liquid state into a gaseous state, and then re-condense it into a solid thin film on the substrate.

[0082] VI. Chemical vapor deposition (CVD) is a process technology used to deposit thin films on substrates. It involves introducing one or more volatile precursor gases into a reaction chamber, where these gases undergo a chemical reaction under specific conditions to form a solid material thin film on the substrate surface. CVD technology is widely used in semiconductor manufacturing, micro-electro-mechanical systems (MEMS), and optical devices, and can deposit various types of thin films, including metals, oxides, nitrides, and carbides.

[0083] 7. Photoresist strip (PVC) is a critical step in semiconductor manufacturing processes. It is used to remove residual photoresist from the surface after pattern transfer and etching are completed. This process ensures that subsequent processing steps can be performed without photoresist interference.

[0084] As described in the background art, in semiconductor manufacturing and microelectronics engineering, defects, weak points, or potential problem areas may exist in one or more layers of material in a multilayer structure. These problem areas may lead to degraded device performance, reduced reliability, or even complete failure.

[0085] When filling deep trenches with multiple layers of electrode and dielectric materials, the aspect ratio gradually increases with the number of layers, leading to differences in the quality and electrical properties of each layer. Referring to Figure 2A, which is a schematic diagram of a conventional deep trench capacitor structure, in a deep trench 24 on a substrate 310 or similar material, the deep trench capacitor consists of multiple electrode layers 22 and multiple capacitor dielectric layers 21 formed by alternating deposition of electrode and dielectric materials. When the depth of the deep trench 24 is much greater than its width (i.e., a high aspect ratio), the deposition process faces greater challenges. Under the same conditions, as the number of layers increases, the deposition of subsequent layers will be affected by the previous layers, leading to a decrease in material uniformity and density.

[0086] Therefore, even under the same deposition conditions, the material quality or electrical properties of different layers can vary. These differences are mainly due to the increased complexity of the deposition process caused by the high aspect ratio structure, which leads to a decrease in film uniformity and density, thereby affecting the physical and electrical properties of each layer.

[0087] For layers with slightly inferior quality or electrical performance, these often become defects in the final device yield. Defects refer to weak layers caused by process limitations, resulting in poor reliability and low withstand voltage. Specifically, weak layers may fail to withstand high voltages and break down, thus affecting the stability and reliability of the entire deep trench capacitor structure.

[0088] Referring to Figure 2B, which is a schematic diagram of a conventional deep trench capacitor structure, the left side of Figure 2B shows the equivalent capacitance of the deep trench capacitor, illustrating three capacitors (capacitor 1, capacitor 2, and capacitor 3) connected in parallel. The right side of Figure 2B shows a case where capacitor 1 has broken down and short-circuited. When a layer of capacitors in a deep trench capacitor short-circuits due to a defect, that layer of capacitors fails, and the current flows directly through the short-circuit path, bypassing the normal capacitors. This short circuit leads to an abnormal current distribution throughout the deep trench capacitor. Because the resistance of the short-circuit path is very low, most of the current flows through the short-circuit path instead of passing through the normal capacitors, even if these normal capacitors themselves are not short-circuited.

[0089] To address the reliability degradation caused by weak layers due to process defects in multilayer deep trench capacitors, and the problem that failure of a single layer or point can lead to the failure of the entire deep trench capacitor and thus affect the normal operation of the entire circuit system, this application addresses these issues by designing and optimizing the internal structural layout of the deep trench capacitor. This optimization not only improves the robustness and redundancy of the deep trench capacitor in the face of local failures in weak layers, but also ensures that the deep trench capacitor can maintain its functional integrity even when there are weak layers caused by process defects.

[0090] In view of this, this application provides a chip that addresses the problem of weak layers in multilayer deep trench capacitors by disconnecting the weak layers, thereby effectively improving the voltage withstand performance of the weak layers.

[0091] Under normal circumstances, multiple capacitors in a deep trench capacitor are connected in parallel. If the electrode layer or dielectric layer corresponding to a certain capacitor layer is weak, it may break down first under higher voltage, causing the entire deep trench capacitor to fail. To solve this problem, the electrode layer of the weak layer is disconnected, effectively introducing a breakpoint at that location, changing the current path and voltage distribution inside the capacitor. This transforms the partially disconnected electrode capacitors from a traditional parallel connection to a series connection. According to the principle of capacitor series connection, the total voltage is distributed among the series capacitors. Therefore, even if the original electrode layer or dielectric layer is weak, it no longer needs to bear the entire operating voltage; instead, the voltage load is shared by the two disconnected electrode layers.

[0092] Through the above improvements, the withstand voltage performance of the weak layer is significantly enhanced, reducing the pressure borne by the weak layer, lowering the risk of breakdown, and thus improving the overall reliability and lifespan of the deep trench capacitor. In particular, it solves the reliability degradation problem caused by process-induced weak layers; even if a weak layer or point is found, it will not lead to the failure of the entire deep trench capacitor.

[0093] Furthermore, stress accumulates in the multilayer structure of deep-groove capacitors, and weak layers easily become areas of stress concentration. By disconnecting the weak layers, this stress can be released, preventing further damage caused by stress and thus further improving the stability and reliability of deep-groove capacitors.

[0094] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0095] Figure 3 is a schematic diagram of a chip structure provided in an embodiment of this application. As shown in Figure 3, in this example, the chip includes a substrate 310 and deep trench capacitors embedded in the substrate 310. The substrate 310 has opposing first surfaces 311 and second surfaces 312. The deep trench capacitor includes a plurality of deep trenches 321, which are spaced apart and embedded in the first surface 311.

[0096] Multiple deep trenches 321 are embedded within the substrate 310. This can be understood as the deep trench capacitor being partially or completely buried within the substrate 310, with one surface exposed on one side of the substrate 310. This surface is referred to as the first surface 311, and the side opposite to the first surface 311 can be referred to as the second surface 312. It is understood that electrode layers 331 and capacitor dielectric layers 332 are stacked within the first surface 311 and the deep trenches 321. Therefore, the first surface 311 can also be understood as the surface of the substrate 310 in the stacking direction, and the second surface 312 can also be understood as the surface of the substrate 310 in the opposite stacking direction.

[0097] Furthermore, the stacked electrode layer 331 and capacitor dielectric layer 332 structure on the inner walls of the first surface 311 and the deep trenches 321 is specifically described as a sub-capacitor structure formed by alternately stacked N+1 layers of electrode layers 331 and N layers of capacitor dielectric layers 332 on a portion of the first surface 311 and the inner walls of the multiple deep trenches 321. In addition, in some possible structures, a liner is also included on a portion of the first surface 311 and the inner walls of the multiple deep trenches 321. The liner is used to prevent metal atoms from diffusing into the substrate 310 or other sensitive areas, avoiding short circuits or changes in device characteristics, and to block impurities in the substrate 310 from diffusing upwards into the electrode layer 331, maintaining the purity of the electrode layer 331.

[0098] The deep trench 321 specifically refers to the high aspect ratio structure of the first surface 311 embedded in the substrate 310. In order to improve the capacitance density of the deep trench capacitor, the aspect ratio of the deep trench 321 in the deep trench capacitor is usually required to be greater than 30:1. The aspect ratio refers to the ratio between the width and depth of the deep trench. Such a large aspect ratio enables each deep trench 321 to significantly increase the effective surface area of ​​the deep trench capacitor, thereby greatly increasing the capacitance value of the deep trench capacitor per unit area.

[0099] The sidewalls of the deep trench 321 can also be inclined, and the inclination angle can be determined by those skilled in the art based on experience, or verified by bottom etching experiments. In this way, when depositing the electrode layer 331 and the capacitor dielectric layer 332, the deposited material can fill along the inclined sidewalls to effectively ensure deposition quality. It should be understood that, provided the process allows, the deep trench 321 can also be vertical; no specific limitation is made.

[0100] In this embodiment of the application, the substrate 310 may be made of one or more of the following materials: single crystal silicon, silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), or indium nitride (InN).

[0101] The electrode layer 331 of a deep trench capacitor is typically made of highly doped polycrystalline silicon or metal (such as tungsten or aluminum) to ensure good conductivity and compatibility with semiconductor processes. The capacitor dielectric layer 332 is often made of silicon dioxide (SiO2), silicon nitride (Si3N4), or high dielectric constant materials such as hafnium oxide (HfO2) or aluminum oxide (Al2O3). These materials can provide excellent insulation performance and high dielectric constant, which helps to improve the capacitance and stability of the deep trench capacitor.

[0102] It should be noted that the above description of the material, thickness, width or length of each electrode layer 331 and capacitor dielectric layer 332 in the deep trench capacitor is only an exemplary description. In actual operation, the specific implementation of each layer can be set according to the actual storage requirements. The embodiments of this application do not limit each layer to having the above features.

[0103] Among them, N are stacked alternately. + One electrode layer 331 and N capacitor dielectric layers 332 mean that the electrode layer 331 has one more layer than the capacitor dielectric layer 332. When N is 1, as shown in Figure 3, it includes two electrode layers 331 and one capacitor dielectric layer 332. When N is 2, as shown in Figure 3, it includes three electrode layers 331 and two capacitor dielectric layers 332. When N is 3, as shown in Figure 3, it includes four electrode layers 331 and three capacitor dielectric layers 332.

[0104] It should be understood that the structure shown in Figure 3 includes at least two electrode layers 331 and at least one capacitor dielectric layer 332. The at least two electrode layers 331 and at least one capacitor dielectric layer 332 can be stacked alternately in the order of electrode layer 331, capacitor dielectric layer 332, electrode layer 331, capacitor dielectric layer 332, electrode layer 331… These will not be listed here. In one possible design, the liner, at least two electrode layers 331, and at least one capacitor dielectric layer 332 can be deposited on a portion of the first surface 311 and the inner walls of multiple deep trenches 321 using layer deposition (LD) technology. Through deposition technology, it can be ensured that the thickness and composition of each material layer (such as the liner, electrode layer, and dielectric layer) are highly consistent on the first surface 311 and the inner walls of the deep trenches 321. The deposition process can form a smooth, defect-free interface, enhance the bonding force between layers, and reduce the risk of delamination, etc.

[0105] A groove 340 is present in the thickness direction of the substrate 310, penetrating at least two electrode layers 331 and at least one capacitor dielectric layer 332. This groove 340 is located between two adjacent deep trenches 321. The main purpose of the groove 340 is to physically disconnect electrode layers 331 with slightly inferior quality or electrical performance. If these layers are not disconnected, short circuits may form on them, affecting the overall performance of the deep trench capacitor. By physically disconnecting these layers, short circuits can be effectively avoided, ensuring electrical isolation between each electrode layer 331 and the capacitor dielectric layer 332, thereby improving the reliability and stability of the entire chip.

[0106] The groove 340 is a shallow trench or gap located between two adjacent deep grooves 321. Its main purpose is to physically disconnect a specific electrode layer 331 and a capacitor dielectric layer 332, rather than to increase the capacitance value of the deep groove capacitor. The groove 340 is designed to completely disconnect the specific electrode layer 331 and capacitor dielectric layer 332, rather than partially disconnecting them. That is, the portion of each layer penetrated by the groove 340 will form a clear electrical isolation band. Depending on the specific application requirements, the groove 340 can penetrate at least two electrode layers 331 and at least one capacitor dielectric layer 332, and can even be extended to three or four electrode layers 331 and the multiple layers of capacitor dielectric layers 332 in between, depending on the specific weak layer and the connection method.

[0107] The groove 340 can be formed into the required groove structure using various microfabrication techniques, such as dry etching, wet etching, or laser cutting. Selecting a suitable etching process ensures that the shape, size, and depth of the groove meet design requirements without affecting the integrity of the surrounding structure. Compared to the deep groove 321, the depth and width of the groove 340 are relatively smaller. The depth of the groove 340 can penetrate at least two electrode layers and at least one capacitor dielectric layer, ensuring that these layers are physically completely separated. The groove 340 can be adjusted relatively flexibly. Optionally, the minimum width of the groove 340 is limited by the manufacturing process capabilities (such as photolithography resolution), while the maximum width is affected by space utilization, the capacitance value of the deep groove capacitor, and the overall design layout.

[0108] The groove 340 starts from the electrode layer 331 and the capacitor dielectric layer 332 in a direction away from the first surface 311 and penetrates vertically downwards for a predetermined number of layers. This vertical penetration method ensures that the materials in each layer are effectively separated. In addition, depending on specific design requirements, the groove 340 can also be selectively processed in the middle layer between the electrode layer 331 and the capacitor dielectric layer 332, without having to start from the top or bottom layer.

[0109] The groove 340 can be designed as an inclined or stepped through-path to accommodate complex three-dimensional structures or specific process requirements, enabling finer control. The groove 340 can be a regular shape, such as rectangular, circular, or other geometric shapes. In some cases, the groove 340 can be designed as an irregular shape to accommodate more complex device layouts or special electrical isolation requirements.

[0110] The groove 340 is positioned between two adjacent deep grooves 321 and is precisely positioned using high-precision photolithography and etching technology to ensure that it does not interfere with the effective working area of ​​the deep groove capacitor. This design simplifies the etching process and makes the processing more direct and convenient.

[0111] By introducing grooves 340 to disconnect at least two electrode layers 331 and at least one dielectric layer 332, areas where process defects may exist can be effectively isolated. This not only prevents these defects from causing short circuits or other electrical faults, but also ensures that differences in quality or electrical performance between different layers do not affect the overall performance of the deep trench capacitor. This structure solves the problem of weak layers caused by the process in multilayer deep trench capacitors, thereby improving the yield of deep trench capacitors.

[0112] The introduction of groove 340 effectively creates a breakpoint at the weak layer location, altering the current path and voltage distribution within the deep-groove capacitor. The previously parallel-connected capacitors are now disconnected, transforming into a series connection. Based on the principle of series connection in deep-groove capacitors, the total voltage is distributed among the series capacitors. Therefore, even if the original electrode layer 331 or capacitor dielectric layer 332 is weak, it no longer needs to bear the entire operating voltage; instead, it shares the voltage load with the other undisconnected layers. This reduces the risk of the weak layer breaking down due to excessive voltage.

[0113] To convert the originally parallel capacitors into a series connection after disconnecting the latter, the disconnected electrodes need to be connected in series. This transforms the parallel connection into a partially series-parallel connection, thereby maximizing capacitance density (i.e., capacitance per unit area).

[0114] Referring again to Figure 3, at least one electrode layer 331 on the disconnected side is connected to any electrode layer 331 on the disconnected side via a conductive path 350.

[0115] In this application, in order to transform the originally parallel-connected capacitors into a partially series-parallel connection after partial disconnection, a specific conductive path 350 needs to be introduced between the disconnected electrodes. Specifically, at least one electrode layer 331 on the disconnected side is connected to any electrode layer 331 on the other disconnected side through the conductive path 350. This connection method makes these sub-capacitors no longer completely parallel, but form a structure combining partial series and parallel connections. The conductive path 350 can be made of metal wires, conductive polymers, or any other suitable conductive material to ensure good electrical conductivity and mechanical stability.

[0116] In this application, in order to transform the originally parallel-connected sub-capacitors into a partially series-parallel connection after partial disconnection, a redistribution layer process can be used to design the conductive path 350. Specifically, at least one electrode layer 331 on the disconnected side is connected to any electrode layer 331 on the other disconnected side through the conductive path 350 formed by the redistribution layer. This connection method makes these capacitors no longer completely parallel, but form a structure that combines partial series and parallel connections.

[0117] The redistribution layer is typically made of copper, aluminum, or other highly conductive metals to ensure good electrical conductivity and mechanical stability. Using photolithography, fine wiring can be achieved in a very small space, ensuring that the conductive path 350 can accurately connect to the target electrode layer without affecting other functional areas.

[0118] By appropriately designing the conductive path 350 to connect the electrode layers 331 in series, the overall capacitance value can be maintained without increasing the volume, thereby increasing the capacitance density per unit area. A series connection is formed between the electrode layer 331 disconnected on one side and the corresponding electrode layer 331 disconnected on the other side. According to the principle of capacitor series connection, the total voltage is distributed among these series capacitors, reducing the voltage pressure on individual capacitor layers. The electrode layers 331 that are not disconnected are connected in parallel, maintaining the original parallel capacitor characteristics. Simultaneously, some of the series capacitors also work together with these parallel capacitors, thus forming a partially series-plus-parallel connection.

[0119] Referring to Figure 4, which is a schematic diagram of a chip structure according to an embodiment of this application, the left side of Figure 4 shows the equivalent capacitance of the deep trench capacitor, illustrating how the groove 340 divides the original capacitor 1 into two independent sub-capacitors 1 and 2. Through the design of the groove 340, capacitor 1 is divided into two sub-capacitors. The electrode layer on one side is disconnected, and the electrode layer on the other side is disconnected, connected via a conductive path 350, thus connecting sub-capacitors 1 and 2 in series. The right side of Figure 4 shows sub-capacitors 1 and 2 connected in series. This disconnects the original weak layer, and the series-connected sub-capacitors 1 and 2 are then connected in parallel with capacitors 2 and 3. The voltage that should have been borne by capacitor 1 is distributed among the series-connected sub-capacitors 1 and 2, reducing the risk of failure of the entire deep trench capacitor.

[0120] In one possible implementation, please continue to refer to Figure 5, which is a schematic diagram of the structure of a chip provided in an embodiment of this application. In order to further improve the electrical performance and manufacturing flexibility of the deep trench capacitor, this application also includes a redistribution layer 360, which is located on the opposite side of the first surface 311 of the substrate 310.

[0121] The redistribution layer 360 includes a first interconnect 361 and a second interconnect 362. The first interconnect 361 and the second interconnect 362 in the redistribution layer 360 are made of highly conductive materials, such as copper (Cu), aluminum (Al), or other alloys, possessing good conductivity and mechanical stability, effectively reducing resistance and signal transmission loss. The first interconnect 361 and the second interconnect 362 can be formed using processing techniques such as photolithography, electroplating, or sputtering, ensuring precise control over their width, thickness, and position to meet high-performance requirements.

[0122] To further improve the quality and reliability of the interconnects, the first interconnect 361 and the second interconnect 362 can be fabricated using a damascus process. The main steps of the damascus process include: first, etching trenches of a predetermined shape and size into the insulating material; depositing a thin barrier layer (such as tantalum nitride, TaN) inside and on the surface of the trenches to prevent metal diffusion into the insulating layer; filling the trenches with metal (such as copper) through chemical vapor deposition or physical vapor deposition; and finally, chemical mechanical polishing to remove excess metal, planarizing the surface and ensuring the precise positioning and height consistency of the interconnects.

[0123] The redistribution layer 360 also includes at least one first contact hole 365 and at least one second contact hole 366, wherein at least one first contact hole 365 is filled with conductive material to form a first interconnect 363, and at least one second contact hole 366 is filled with conductive material to form a second interconnect 364.

[0124] Electrical connections between different layers are achieved by filling contact holes with conductive materials. Commonly used interconnect materials include tungsten (W), copper (Cu), or aluminum (Al), which possess excellent electrical conductivity and thermal stability. The first interconnect 363 and the second interconnect 364 are formed through processes such as chemical vapor deposition and physical vapor deposition, ensuring complete filling of the contact holes with interconnects.

[0125] The first power supply terminal 371 is connected to the first contact hole 365 (first interconnect 363) via the first interconnect line 361, and the second power supply terminal 372 is connected to the second contact hole 366 (second interconnect 364) via the second interconnect line 362.

[0126] The first contact hole 365 and the second contact hole 366 are used to connect each layer to the power supply terminal. The diameter and depth of the first contact hole 365 and the second contact hole 366 need to be optimized according to specific application requirements to ensure the filling and reliable connection of the interconnects. The shape of the first contact hole 365 and the second contact hole 366 can be circular, square or other geometric shapes, depending on the process conditions and design requirements.

[0127] The first contact hole 365 and the second contact hole 366 can be inclined holes, with the hole walls inclined along the stacking direction (i.e., the vertical direction shown in the figure) of the stacked structure of the electrode layer 331 and the capacitor dielectric layer 332. Generally, inclined holes are easier to fabricate because during the etching process, the number of etching ions decreases as the etching progresses downwards, resulting in a smaller hole diameter closer to the bottom, making it easier to form an inclined hole that is wider at the top and narrower at the bottom. However, in other implementations, if the process can be guaranteed, the first contact hole 365 and the second contact hole 366 can also be vertical holes instead of inclined holes; this application does not specifically limit this.

[0128] When the first power supply terminal 371 is connected to the power supply voltage and the second power supply terminal 372 is connected to ground, supplying power to the deep-sink capacitor means providing the deep-sink capacitor with the power supply voltage. When the second power supply terminal 372 is connected to the power supply voltage and the first power supply terminal 371 is connected to ground, supplying power to the deep-sink capacitor means providing the deep-sink capacitor with a negative power supply voltage.

[0129] Understandably, the electrode layer 331 connected to the first interconnect 363 is connected to the first power supply terminal 371 via the first interconnect line 361, and the electrode layer 331 connected to the second interconnect 364 is connected to the second power supply terminal 372 via the second interconnect line 362. If the first power supply terminal 371 is connected to a power supply voltage and the second power supply terminal 372 is connected to ground, it is equivalent to applying a power supply voltage to the electrode layer 331 connected to the first interconnect 363 and applying a ground voltage to the electrode layer 331 connected to the second interconnect 364.

[0130] To clearly explain the connection relationship between the various electrode layers 331 and to illustrate the structure formed by these electrode layers 331 through interconnects, the following further describes the connection relationship between the first interconnect 363 and the second interconnect 364 and each electrode layer 331.

[0131] Referring to Figure 5, which is a schematic diagram of a chip structure provided in an embodiment of this application, the first electrode layer on one side of the groove 340 is used to represent any one of the disconnected electrode layers, and the second electrode layer on the other side is used to represent any one of the disconnected electrode layers on the other side of the groove 340.

[0132] Any disconnected electrode layer located on one side of the groove 340 can be connected to any disconnected electrode layer on the other side of the groove 340 via a conductive path 350, thereby achieving an electrical connection between the disconnected electrode layers. This connection method ensures that the disconnected electrode layers are no longer completely isolated, but rather form a series structure through the conductive path 350.

[0133] In this application, an unbroken third electrode layer is used to represent any electrode layer that is not disconnected by the groove, and a broken fourth electrode layer 384 is used to represent any electrode layer that is disconnected by the groove, except for those connected by the conductive path 350. When the first interconnect 363 is connected to the unbroken third electrode layer and to the broken fourth electrode layer 384, it is equivalent to applying a power supply voltage to the third electrode layer and the fourth electrode layer connected to the first interconnect 363.

[0134] The term "undisconnected electrode layers other than the third electrode layer" specifically refers to all other undisconnected electrode layers besides the aforementioned undisconnected third electrode layer. The term "disconnected electrode layers other than the first, second, and fourth electrode layers" refers to all other disconnected electrode layers besides the aforementioned three types of electrode layers.

[0135] The second interconnect 364 is connected to the unbroken electrode layers except the third electrode layer. After being connected to the disconnected electrode layers except the first, second, and fourth electrode layers, it is equivalent to applying a ground voltage to each electrode layer connected to the second interconnect 364.

[0136] Through the design of the interconnects and conductive paths described above, the multiple capacitors that were originally connected in parallel now form a structure that combines partial series and parallel connections.

[0137] After the capacitor located in the weak layer is disconnected through the groove 340, the two disconnected electrode layers 331 are connected through the conductive path 350, thereby forming two series-connected separator capacitors. The total voltage between the first power supply terminal 371 and the second power supply terminal 372 will be distributed between the two series-connected separator capacitors, reducing the voltage pressure on a single capacitor and improving the withstand voltage performance. Other electrodes that are not disconnected and electrode layers 331 that are not connected by conductive paths are connected to the first interconnect 363 and the second interconnect 364 respectively, thereby forming a new parallel capacitor relationship. Through the reasonable redistribution layer 360 design, the overall capacitance value can be increased without increasing the additional volume, thereby increasing the capacitance density per unit area.

[0138] In this application, the redistribution layer 360 connects multiple electrode layers through specific interconnects and conductive paths, forming a structure that combines partial series and parallel connections. Since adjacent electrode layers are connected to the same interconnect, which is equivalent to applying the same polarity to the two electrode layers of a capacitor, a non-adjacent connection method is used to prevent capacitance loss and ensure the overall performance of the capacitor.

[0139] The first interconnect 363 is connected to a non-adjacent undisconnected electrode layer, meaning that the first interconnect 363 will not be directly connected to an adjacent undisconnected electrode layer, but will instead be connected by skipping one or more electrode layers. The first interconnect 363 is also connected to a non-adjacent disconnected electrode layer 331. Similarly, this connection method ensures that the first interconnect 363 will not be directly connected to an adjacent disconnected electrode layer 331, but will instead be connected by skipping one or more electrode layers 331.

[0140] The second interconnect 364 is connected to a non-adjacent, undisconnected electrode layer 331. Similar to the first interconnect 363, the second interconnect 364 is not directly connected to an adjacent undisconnected electrode layer 331, but is connected by spacing one or more electrode layers 331 between them. The second interconnect 364 is also connected to a non-adjacent, disconnected electrode layer 331, ensuring that the second interconnect 364 is not directly connected to an adjacent disconnected electrode layer 331, but is connected by spacing one or more electrode layers 331 between them.

[0141] By using the above-mentioned non-adjacent connection design, the first interconnect 363 and the second interconnect 364 are prevented from being connected to adjacent electrode layers (whether disconnected or not), which can effectively prevent the loss of capacitance density.

[0142] In the following embodiments, several different types of deep trench capacitor structures will be described in detail, and their performance and reliability will be optimized through various designs. For example, electrode layers 331 and capacitor dielectric layers 332 with different numbers of layers, and grooves 340 at different positions, divide the original capacitor into multiple independent sub-capacitors, realizing a partially series and parallel connection method, thereby optimizing voltage distribution and improving withstand voltage performance. Through the different connection methods of the first interconnect 363 and the second interconnect 364 in the redistribution layer 360, capacitance loss is prevented and the stability and reliability of the deep trench capacitor are enhanced.

[0143] Example 1

[0144] In one example, referring to FIG6A, FIG6A is a schematic diagram of the structure of a chip provided in an embodiment of the present application. A portion of the first surface 311 and the inner wall of the multiple deep trenches 321 specifically include a fifth electrode layer 601, a sixth electrode layer 602 and a first capacitor dielectric layer 603. The fifth electrode layer 601, the sixth electrode layer 602 and the first capacitor dielectric layer 603 constitute a first sub-capacitor.

[0145] A groove 340 is provided in the thickness direction of the substrate 310, penetrating the fifth electrode layer 601, the sixth electrode layer 602 and the first capacitor dielectric layer 603. The fifth electrode layer 601 on one side of the disconnection is connected to the fifth electrode layer 601 on the other side of the disconnection through a conductive path 350. The first interconnect 363 is connected to the sixth electrode layer 602 on the disconnection side, and the second interconnect 364 is connected to the sixth electrode layer 603 on the other side of the disconnection.

[0146] In Figure 6A, a portion of the first surface 311 and the inner walls of the multiple deep trenches 321 include a fifth electrode layer 601, a sixth electrode layer 602, and a first capacitor dielectric layer 603. These layers together constitute the first sub-capacitor. The fifth electrode layer 601 serves as one electrode of the first sub-capacitor, and the sixth electrode layer 602 serves as the other electrode of the first sub-capacitor, located between the two electrodes to store charge and isolate the two electrodes.

[0147] A groove 340 is present in the thickness direction of the substrate 310, penetrating the fifth electrode layer 601, the sixth electrode layer 602, and the first capacitor dielectric layer 603. This groove divides the original first sub-capacitor into two independent parts, thereby realizing a series connection.

[0148] The specific connection relationships are as follows:

[0149] The fifth electrode layer 601 on one side is disconnected and the fifth electrode layer 601 on the other side is disconnected, which is connected through the conductive path 350, so that the disconnected fifth electrode layers form a series connection, reducing the voltage pressure borne by the fifth electrode layer 601 and the sixth electrode layer 602.

[0150] The first interconnect 363 is connected to the disconnected sixth electrode layer 602, and the second interconnect 364 is connected to the sixth electrode layer 602 on the other side of the disconnection, thereby forming a series connection between the first separator capacitor 610 and the second separator capacitor 611.

[0151] After the first separator capacitor 610 and the second separator capacitor 611 are connected in series, the total voltage will be distributed between the first separator capacitor 610 and the second separator capacitor 611, which reduces the voltage pressure on a single first capacitor and improves the withstand voltage performance of the fifth electrode layer 601 and the sixth electrode layer 602.

[0152] Even if the fifth electrode layer 601 or the sixth electrode layer 602 has a weak process or a fault, the fifth electrode layer 601 and the sixth electrode layer 602 are disconnected by the groove 340, which reduces the voltage pressure on the fifth electrode layer 601 and the sixth electrode layer 602 and improves the stability and yield of the deep trench capacitor.

[0153] Figure 6B illustrates a schematic diagram of the process of changing the capacitors from parallel connection to partial series connection.

[0154] The first interconnect is connected to the first power supply terminal 371, which is equivalent to applying a power supply voltage to one side of the sixth electrode layer after it is disconnected by the groove 340. The second interconnect is connected to the second power supply terminal 372, which is equivalent to applying a ground voltage to the other side of the sixth electrode layer after it is disconnected by the groove 340.

[0155] Thus, the original conduction loop is first power supply terminal 371 - sixth electrode layer - fifth electrode layer - second power supply terminal 372, where the sixth electrode layer and the fifth electrode layer form the first sub-capacitor 604. The conduction loop after the groove 340 passes through the fifth electrode layer and the sixth electrode layer is first power supply terminal 371 - disconnect the sixth electrode layer on one side - disconnect the fifth electrode layer on one side - disconnect the fifth electrode layer on the other side - disconnect the sixth electrode layer on the other side - second power supply terminal 372, forming a structure in which the first separator sub-capacitor 610 and the second separator sub-capacitor 611 are connected in series. In this way, not only is the problem of weak layers caused by the process in deep trench capacitors solved, but the withstand voltage performance of the weak dielectric layer in deep trench capacitors is also significantly improved. This avoids the problem that the failure of a certain layer or a certain point will cause the entire deep trench capacitor to fail and not work properly, thus improving the device yield.

[0156] In another example, referring to Figure 6C, which is a schematic diagram of a chip structure provided in an embodiment of this application, the specific connection relationships are as follows:

[0157] The sixth electrode layer 602 on one side is disconnected and the sixth electrode layer 602 on the other side is disconnected. They are connected through a conductive path 350, so that the disconnected sixth electrode layers form a series connection, which reduces the voltage pressure on the fifth electrode layer 601 and the sixth electrode layer 602.

[0158] The first interconnect 363 is connected to the disconnected fifth electrode layer 601, and the second interconnect 364 is connected to the fifth electrode layer 601 on the other side of the disconnection, thereby forming a series connection between the first separator capacitor 610 and the second separator capacitor 611.

[0159] After the first separator capacitor 610 and the second separator capacitor 611 are connected in series, the total voltage will be distributed between the first separator capacitor 610 and the second separator capacitor 611, which reduces the voltage pressure on the individual first capacitor 604 and improves the voltage withstand performance of the fifth electrode layer 601 and the sixth electrode layer 602.

[0160] Even if the fifth electrode layer 601 or the sixth electrode layer 602 has a weak process or a fault, the fifth electrode layer 601 and the sixth electrode layer 602 are disconnected by the groove 340, which reduces the voltage pressure on the fifth electrode layer 601 and the sixth electrode layer 602 and improves the stability and yield of the deep trench capacitor.

[0161] Figure 6D illustrates another process of changing the capacitors from parallel to partially series connection.

[0162] The first interconnect is connected to the first power supply terminal 371, which is equivalent to applying a power supply voltage to one side of the fifth electrode layer after it is disconnected by the groove 340. The second interconnect is connected to the second power supply terminal 372, which is equivalent to applying a ground voltage to the other side of the fifth electrode layer after it is disconnected by the groove 340.

[0163] Thus, the original conduction loop is first power supply terminal 371 - sixth electrode layer - fifth electrode layer - second power supply terminal 372, where the sixth electrode layer and the fifth electrode layer form the first sub-capacitor 604. The conduction loop after the groove 340 passes through the fifth electrode layer and the sixth electrode layer is first power supply terminal 371 - disconnect the fifth electrode layer on one side - disconnect the sixth electrode layer on one side - disconnect the sixth electrode layer on the other side - disconnect the fifth electrode layer on the other side - second power supply terminal 372, forming a structure in which the first separator sub-capacitor 610 and the second separator sub-capacitor 611 are connected in series. In this way, not only is the problem of weak layers caused by the process in deep trench capacitors solved, but the withstand voltage performance of the weak dielectric layer in deep trench capacitors is also significantly improved. This avoids the problem of the entire deep trench capacitor failing and not working properly due to the failure of a certain layer or a certain point, thus improving the device yield.

[0164] In another example, referring to Figure 6E, which is a schematic diagram of a chip structure provided in an embodiment of this application, the specific connection relationships are as follows:

[0165] The fifth electrode layer 601 on one side is disconnected and the sixth electrode layer 602 on the other side is disconnected, which is connected through a conductive path 350, so that the fifth electrode layer 601 on one side is disconnected and the sixth electrode layer 602 on the other side are connected in series, thereby reducing the voltage pressure borne by the fifth electrode layer 601 and the sixth electrode layer 602.

[0166] The first interconnect 363 is connected to the sixth electrode layer 602 on the disconnected side, and the second interconnect 364 is connected to the fifth electrode layer 601 on the other disconnected side, thereby forming a series connection between the first separator capacitor 610 and the second separator capacitor 611.

[0167] After the first separator capacitor 610 and the second separator capacitor 611 are connected in series, the total voltage will be distributed between the first separator capacitor 610 and the second separator capacitor 611, which reduces the voltage pressure on the individual first capacitor 604 and improves the voltage withstand performance of the fifth electrode layer 601 and the sixth electrode layer 602.

[0168] Even if the fifth electrode layer 601 or the sixth electrode layer 602 has a weak process or a fault, the fifth electrode layer 601 and the sixth electrode layer 602 are disconnected by the groove 340, which reduces the voltage pressure on the fifth electrode layer 601 and the sixth electrode layer 602 and improves the stability and yield of the deep trench capacitor.

[0169] Figure 6F illustrates another process of changing the capacitors from parallel to partially series connection.

[0170] The first interconnect is connected to the first power supply terminal 371, which is equivalent to applying a power supply voltage to one side of the sixth electrode layer after it is disconnected by the groove 340. The second interconnect is connected to the second power supply terminal 372, which is equivalent to applying a ground voltage to the other side of the fifth electrode layer after it is disconnected by the groove 340.

[0171] Thus, the original conduction loop is first power supply terminal 371 - sixth electrode layer - fifth electrode layer - second power supply terminal 372, where the sixth electrode layer and the fifth electrode layer form the first sub-capacitor 604. The conduction loop after the groove 340 passes through the fifth electrode layer and the sixth electrode layer is first power supply terminal 371 - disconnect one side of the sixth electrode layer - disconnect one side of the fifth electrode layer - disconnect the other side of the sixth electrode layer - disconnect the other side of the fifth electrode layer - second power supply terminal 372, forming a structure in which the first separator sub-capacitor 610 and the second separator sub-capacitor 611 are connected in series. In this way, not only is the problem of weak layers caused by the process in deep trench capacitors solved, but the withstand voltage performance of the weak dielectric layer in deep trench capacitors is also significantly improved. This avoids the problem of the entire deep trench capacitor failing due to the failure of a certain layer or a certain point, thus improving the device yield.

[0172] The above embodiments are merely illustrative examples, intended to demonstrate possible applications of different designs and connection methods. The specific connection methods of the interconnecting components (such as the first and second interconnecting components) are not intended to limit this application. This application covers, but is not limited to, these examples; other reasonable connection methods and design schemes are equally applicable to the spirit and scope of this application. Therefore, further details are omitted here.

[0173]

Example 2

[0174] In one example, referring to FIG7A, FIG7A is a schematic diagram of the structure of a chip provided in an embodiment of the present application. A portion of the first surface 311 and the inner walls of the multiple deep trenches 321 specifically include a seventh electrode layer 701, an eighth electrode layer 702, a ninth electrode layer 703, a tenth electrode layer 704, a second capacitor dielectric layer 705, a third capacitor dielectric layer 706, and a fourth capacitor dielectric layer 707. The seventh electrode layer 701, the eighth electrode layer 702, and the second capacitor dielectric layer 705 constitute a second sub-capacitor 710, the eighth electrode layer 702, the ninth electrode layer 703, and the third capacitor dielectric layer 706 constitute a third sub-capacitor 711, and the ninth electrode layer 703, the tenth electrode layer 704, and the fourth capacitor dielectric layer 707 constitute a fourth sub-capacitor 712.

[0175] A groove 340 is present in the thickness direction of the substrate 310, penetrating the seventh electrode layer 701, the eighth electrode layer 702, and the second capacitor dielectric layer 705. This groove divides the original capacitor into multiple independent sub-capacitors, thereby realizing a partially series-plus-parallel connection.

[0176] The specific connection relationships are as follows:

[0177] The seventh electrode layer 701 on one side is disconnected and the seventh electrode layer 701 on the other side is disconnected, which is connected through the conductive path 350, so that the disconnected seventh electrode layers 701 form a series connection, reducing the voltage pressure borne by the seventh electrode layer 701 and the eighth electrode layer 702.

[0178] The first interconnect 363 is connected to the eighth electrode layer 702 and the tenth electrode layer 704 on the disconnected side, and the second interconnect 364 is connected to the eighth electrode layer 702 and the ninth electrode layer 703 on the other disconnected side. This causes the third separator capacitor 720 and the fourth separator capacitor 721 to form a series connection.

[0179] After the third sub-capacitor 720 and the fourth sub-capacitor 721 are connected in series, the total voltage will be distributed between the third sub-capacitor 720 and the fourth sub-capacitor 721, which reduces the voltage pressure on the individual second sub-capacitor 710 and improves the withstand voltage performance of the seventh electrode layer 701 and the eighth electrode layer 702.

[0180] Even if the seventh electrode layer 701 or the eighth electrode layer 702 has a weak process or a fault, the seventh electrode layer 701 and the eighth electrode layer 702 are disconnected by the groove 340, which reduces the voltage pressure on the seventh electrode layer 701 and the eighth electrode layer 702 and improves the stability and yield of the deep trench capacitor.

[0181] The structure of the deep trench capacitor involved in the above embodiment 2 is shown in Figure 7B, which is a top view of a chip provided in this application embodiment. This application uses four electrode layers 331 and three capacitor dielectric layers as an example. The square holes in Figure 7B are contact holes connected to each electrode layer. Different contact holes, whose positions are clearly marked in Figure 7B, are connected to different electrode layers. To implement the design principle of the above embodiment, the seventh electrode layer and the eighth electrode layer are each disconnected by a groove 340. The seventh electrode layer is led out through contact holes and interconnected through conductive paths 350. Conductive paths 350 serve as a bridge between the electrodes on both sides of the disconnected seventh electrode layer. The remaining eighth, ninth, and tenth electrode layers are also connected through contact holes to the first interconnect and the second interconnect, respectively, and are interconnected through the first interconnect and the second interconnect. The first interconnect is connected to the first power supply terminal 371, and the second interconnect is connected to the second power supply terminal 372.

[0182] Figure 7C illustrates a schematic diagram of the process of changing the capacitors from parallel connection to partial series connection.

[0183] The first interconnect is connected to the first power supply terminal 371, which is equivalent to applying a power supply voltage to one side of the eighth electrode layer and the tenth electrode layer after being disconnected by the groove 340. The second interconnect is connected to the second power supply terminal 372, which is equivalent to applying a power supply voltage and a ground voltage to the other side of the eighth electrode layer and the ninth electrode layer after being disconnected by the groove 340.

[0184] Thus, the original conduction circuits are respectively: first power supply terminal 371 - tenth electrode layer - ninth electrode layer - second power supply terminal 372, first power supply terminal 371 - ninth electrode layer - eighth electrode layer - second power supply terminal 372, and first power supply terminal 371 - eighth electrode layer - seventh electrode layer - second power supply terminal 372.

[0185] The conductive circuits through the groove 340, passing through the seventh and eighth electrode layers, are respectively: first power supply terminal 371 - tenth electrode layer - ninth electrode layer - second power supply terminal 372, first power supply terminal 371 - ninth electrode layer - one side of the disconnected eighth electrode layer - second power supply terminal 372, and first power supply terminal 371 - one side of the disconnected eighth electrode layer - one side of the disconnected seventh electrode layer - the other side of the disconnected seventh electrode layer - the other side of the disconnected eighth electrode layer - second power supply terminal 372, forming a structure in which the first separator capacitor 710 and the second separator capacitor 711 are connected in series.

[0186] In this way, not only is the problem of weak layers (the seventh and eighth electrode layers) in deep trench capacitors caused by the process solved, but the withstand voltage performance of the weak dielectric layer in deep trench capacitors is also significantly improved. This avoids the problem of the entire deep trench capacitor failing and not working properly due to the failure of a certain layer or a certain point, and improves the device yield.

[0187] It should be noted that in the structure of this application, since the other sides of the ninth electrode layer and the eighth electrode layer are connected by the second interconnect 364, there is a certain loss of capacitance dielectric between the other sides of the ninth electrode layer and the eighth electrode layer.

[0188]

Example 3

[0189] In one example, referring to FIG8A, FIG8A is a schematic diagram of the structure of a chip provided in an embodiment of the present application. A portion of the first surface 311 and the inner walls of multiple deep trenches 321 specifically include a seventh electrode layer 701, an eighth electrode layer 702, a ninth electrode layer 703, a tenth electrode layer 704, a second capacitor dielectric layer 705, a third capacitor dielectric layer 706, and a fourth capacitor dielectric layer 707. The seventh electrode layer 701, the eighth electrode layer 702, and the second capacitor dielectric layer 705 constitute a second sub-capacitor 710, the eighth electrode layer 702, the ninth electrode layer 703, and the third capacitor dielectric layer 706 constitute a third sub-capacitor 711, and the ninth electrode layer 703, the tenth electrode layer 704, and the fourth capacitor dielectric layer 707 constitute a fourth sub-capacitor 712.

[0190] A groove 340 is present in the thickness direction of the substrate, penetrating the seventh electrode layer 701, the eighth electrode layer 702, the ninth electrode layer 703, the tenth electrode layer 704, the second capacitor dielectric layer 705, the third capacitor dielectric layer 706, and the fourth capacitor dielectric layer 707. This groove divides the original capacitor into multiple independent sub-capacitors, thereby realizing a partially series-plus-parallel connection.

[0191] The specific connection relationships are as follows:

[0192] The seventh electrode layer 701 on one side is disconnected and the seventh electrode layer 701 on the other side is disconnected, which is connected through the conductive path 350, so that the disconnected seventh electrode layers 701 form a series connection, reducing the voltage pressure borne by the seventh electrode layer 701 and the eighth electrode layer 702.

[0193] The first interconnect 363 is connected to the eighth electrode layer 702 on the disconnected side, the tenth electrode layer 704 on the disconnected side, and the ninth electrode layer 703 on the other side. The second interconnect 364 is connected to the ninth electrode layer 703 on the disconnected side, the eighth electrode layer 702 on the other side, and the tenth electrode layer 704 on the other side.

[0194] After the third sub-capacitor 720 and the fourth sub-capacitor 721 are connected in series, the total voltage will be distributed between the third sub-capacitor 720 and the fourth sub-capacitor 721, which reduces the voltage pressure on the individual second sub-capacitor 710 and improves the withstand voltage performance of the seventh electrode layer 701 and the eighth electrode layer 702.

[0195] Even if the seventh electrode layer 701, the eighth electrode layer 702, the ninth electrode layer 703, and the tenth electrode layer 704 have process weaknesses or faults, the seventh electrode layer 701, the eighth electrode layer 702, the ninth electrode layer 703, and the tenth electrode layer 704 can be disconnected through the groove 340, which reduces the voltage pressure on the seventh electrode layer 701, the eighth electrode layer 702, the ninth electrode layer 703, and the tenth electrode layer 704, and improves the stability and yield of the deep trench capacitor.

[0196] The structure of the deep trench capacitor involved in the above embodiment three is shown in the top view of Figure 8B. Figure 8B is a top view of a chip provided in this application embodiment three, with four electrode layers 331 and three capacitor dielectric layers as examples. The square holes in Figure 8B are contact holes connected to each electrode layer. Different contact holes, whose positions are clearly marked in Figure 8B, are connected to different electrode layers. To implement the design principle of the above embodiment, the seventh electrode layer 701, the eighth electrode layer 702, the ninth electrode layer 703, and the tenth electrode layer 704 are each disconnected by a groove 340. The seventh electrode layer 701 is led out through contact holes and interconnected through conductive paths 350. The conductive paths 350 serve as a bridge between the electrodes on both sides of the disconnected seventh electrode layer 701. The remaining eighth electrode layer 702, ninth electrode layer 703, and tenth electrode layer 704 are also connected through contact holes via the first interconnect 363 and the second interconnect 364, respectively, and are interconnected through the first interconnect 363 and the second interconnect 364. The first interconnect 363 is connected to the first power supply terminal 371, and the second interconnect 364 is connected to the second power supply terminal 372.

[0197] Figure 8C illustrates a schematic diagram of the process of changing the capacitors from parallel connection to partial series connection.

[0198] The first interconnect is connected to the first power supply terminal 371, which is equivalent to applying a power supply voltage on one side of the disconnected eighth electrode layer, one side of the disconnected tenth electrode layer, and the other side of the disconnected ninth electrode layer. The second interconnect is connected to the second power supply terminal 372, which is equivalent to applying a ground voltage on the other side of the disconnected eighth electrode layer, the other side of the disconnected tenth electrode layer, and one side of the disconnected ninth electrode layer.

[0199] Thus, the original conductive loops are respectively: first power supply terminal 371 - tenth electrode layer - ninth electrode layer - second power supply terminal 372, first power supply terminal 371 - ninth electrode layer - eighth electrode layer - second power supply terminal 372, and first power supply terminal 371 - eighth electrode layer - seventh electrode layer - second power supply terminal 372; the conductive loops after the groove 340 passes through the seventh electrode layer, eighth electrode layer, ninth electrode layer, and tenth electrode layer are respectively: first power supply terminal 371 - both sides of the disconnected tenth electrode layer - both sides of the disconnected ninth electrode layer - second power supply terminal 372 (first power supply terminal 371 - one side of the disconnected tenth electrode layer - one side of the disconnected ninth electrode layer - second power supply terminal 372 and first power supply terminal 371 - the other side of the disconnected tenth electrode layer - disconnected The first power supply terminal 371 is connected to the second power supply terminal 372 on the other side of the ninth electrode layer, and to the second power supply terminal 372 on both sides of the disconnected ninth electrode layer and the second power supply terminal 372 on both sides of the disconnected eighth electrode layer. The first power supply terminal 371 is connected to the second power supply terminal 372 on one side of the disconnected ninth electrode layer and the second power supply terminal 372 on the other side of the disconnected ninth electrode layer and the second power supply terminal 372 on the other side of the disconnected eighth electrode layer. The first power supply terminal 371 is connected to the second power supply terminal 372 on one side of the disconnected eighth electrode layer and the second power supply terminal 372 on the other side of the disconnected seventh electrode layer and the second power supply terminal 372 on the other side of the disconnected eighth electrode layer.

[0200] In this way, not only is the problem of weak layers caused by the process in deep trench capacitors solved, but the withstand voltage performance of the weak dielectric layer in deep trench capacitors is also significantly improved. This avoids the problem of the entire deep trench capacitor failing and not working properly due to the failure of a certain layer or a certain point, thereby improving the device yield.

[0201] Compared to the structure of Embodiment 2, the structure of this application has no loss of capacitance dielectric between the other sides of the ninth electrode layer and the eighth electrode layer because the other sides of the ninth electrode layer and the eighth electrode layer are respectively connected to different interconnects.

[0202]

Example 4

[0203] To change the parallel connection of the corresponding separator sub-capacitors of different electrode layers to a series connection, in one example, referring to Figure 9A, which is a schematic diagram of the structure of a chip provided in an embodiment of this application, a portion of the first surface 311 and the inner walls of multiple deep trenches 321 specifically include a seventh electrode layer 701, an eighth electrode layer 702, a ninth electrode layer 703, a tenth electrode layer 704, a second capacitor dielectric layer 705, a third capacitor dielectric layer 706, and a fourth capacitor dielectric layer 707. The seventh electrode layer 701, the eighth electrode layer 702, and the second capacitor dielectric layer 705 constitute the second sub-capacitor 710, the eighth electrode layer 702, the ninth electrode layer 703, and the third capacitor dielectric layer 706 constitute the third sub-capacitor 711, and the ninth electrode layer 703, the tenth electrode layer 704, and the fourth capacitor dielectric layer 707 constitute the fourth sub-capacitor 712.

[0204] A groove 340 is present in the thickness direction of the substrate, penetrating the seventh electrode layer 701, the eighth electrode layer 702, the ninth electrode layer 703, the tenth electrode layer 704, the second capacitor dielectric layer 705, the third capacitor dielectric layer 706, and the fourth capacitor dielectric layer 707. The specific connection relationship is as follows:

[0205] The seventh electrode layer 701 on one side is disconnected and the ninth electrode layer 703 on the other side is disconnected, which is connected through a conductive path 350, so that the seventh electrode layer 7014 on one side is disconnected and the ninth electrode layer 703 on the other side is connected in series.

[0206] The first interconnect 363 is connected to the eighth electrode layer 702 on the disconnected side, the tenth electrode layer 704 on the disconnected side, and the seventh electrode layer 701 on the other side. The second interconnect 364 is connected to the ninth electrode layer 703 on the disconnected side, the eighth electrode layer 702 on the other side, and the tenth electrode layer 704 on the other side.

[0207] After the third separator capacitor 720 and the fifth separator capacitor 722 are connected in series, the total voltage will be distributed between the third separator capacitor 720 and the fifth separator capacitor 722, which reduces the voltage pressure on the sub-capacitors and improves the withstand voltage performance of the seventh electrode layer 701, the eighth electrode layer 702, the ninth electrode layer 703 and the tenth electrode layer 704.

[0208] Even if the seventh electrode layer 701, the eighth electrode layer 702, the ninth electrode layer 703, and the tenth electrode layer 704 all have process weaknesses or faults, the seventh electrode layer 701, the eighth electrode layer 702, the ninth electrode layer 703, and the tenth electrode layer 704 are disconnected by the groove 340, which reduces the voltage pressure on the seventh electrode layer 701, the eighth electrode layer 702, the ninth electrode layer 703, and the tenth electrode layer 704, and improves the stability and yield of the deep trench capacitor.

[0209] The structure of the deep trench capacitor involved in the above embodiment four is shown in Figure 9B, which is a top view of a chip provided in this application embodiment. This application uses four electrode layers 331 and three capacitor dielectric layers 332 as examples. The square holes in Figure 9B are contact holes connected to each electrode layer. Different contact holes, whose positions are clearly marked in Figure 9B, are connected to different electrode layers. To implement the design principle of the above embodiment, the seventh electrode layer 701, the eighth electrode layer 702, the ninth electrode layer 703, and the tenth electrode layer 704 are each disconnected by a groove 340. The seventh electrode layer 701 is led out through contact holes and interconnected through conductive path 350. Conductive path 350 serves as a bridge between the electrodes on both sides of the seventh electrode layer 701. The remaining eighth electrode layer 702, ninth electrode layer 703, and tenth electrode layer 704 are also connected through contact holes via first interconnect 363 and second interconnect 364 respectively, and are interconnected through first interconnect 363 and second interconnect 364. Among them, first interconnect 363 is connected to first power supply terminal 371, and second interconnect 364 is connected to second power supply terminal 372.

[0210] Figure 9C illustrates a schematic diagram of the process of changing the capacitors from parallel connection to partial series connection.

[0211] The first interconnect is connected to the first power supply terminal 371, which is equivalent to applying a power supply voltage on one side of the disconnected eighth electrode layer, one side of the disconnected tenth electrode layer, and the other side of the disconnected seventh electrode layer. The second interconnect is connected to the second power supply terminal 372, which is equivalent to applying a ground voltage on the other side of the disconnected eighth electrode layer, the other side of the disconnected ninth electrode layer, and one side of the disconnected eighth electrode layer.

[0212] Thus, the original conductive loops are: first power supply terminal 371 - tenth electrode layer - ninth electrode layer - second power supply terminal 372, first power supply terminal 371 - ninth electrode layer - eighth electrode layer - second power supply terminal 372, and first power supply terminal 371 - eighth electrode layer - seventh electrode layer - second power supply terminal 372. The conductive loops after the groove 340 passes through the seventh, eighth, ninth, and tenth electrode layers are: first power supply terminal 371 - one side of the disconnected tenth electrode layer - one side of the disconnected ninth electrode layer - second power supply terminal 372, and first power supply terminal 371 - one side of the disconnected eighth electrode layer. One side of the disconnected ninth electrode layer - second power supply terminal 372, first power supply terminal 371 - the other side of the disconnected ninth electrode layer - the other side of the disconnected eighth electrode layer - second power supply terminal 372, first power supply terminal 371 - the other side of the disconnected seventh electrode layer - the other side of the disconnected eighth electrode layer - second power supply terminal 372, first power supply terminal 371 - one side of the disconnected eighth electrode layer - one side of the disconnected seventh electrode layer - the other side of the disconnected ninth electrode layer - the other side of the disconnected eighth electrode layer - second power supply terminal, thereby forming a structure in which the first separator capacitor 710 and the third separator capacitor 712 are connected in series.

[0213] In this way, not only is the problem of weak layers caused by the process in deep trench capacitors solved, but the withstand voltage performance of the weak dielectric layer in deep trench capacitors is also significantly improved. This avoids the problem of the entire deep trench capacitor failing and not working properly due to the failure of a certain layer or a certain point, thereby improving the device yield.

[0214] Compared to the structure of Embodiment 2, the structure of this application has no loss of capacitance dielectric between the other sides of the eighth electrode layer and the ninth electrode layer because the other sides of the ninth electrode layer are connected to different interconnects.

[0215] The above embodiments are merely illustrative examples, intended to demonstrate possible applications of different designs and connection methods. The specific connection methods of the interconnecting components (such as the first and second interconnecting components) are not intended to limit this application. This application covers, but is not limited to, these examples; other reasonable connection methods and design schemes are equally applicable to the spirit and scope of this application. Therefore, further details are omitted here.

[0216] Based on the chip shown in the above embodiments, this application also provides a chip fabrication method. Figures 10-33 exemplarily illustrate a chip fabrication process provided by this application (taking the structure of Embodiment 3 as an example). The fabrication process includes:

[0217] Step 1: Provide a substrate to obtain the structure shown in Figure 10.

[0218] Step 2: An organic material layer is formed on the first surface of the substrate, and a pattern is photolithographically etched at the positions corresponding to the multiple deep trenches on the organic material layer to obtain the structure shown in Figure 11.

[0219] Step 3: Multiple deep trenches are formed on the substrate by etching, and the remaining organic material layer is removed to obtain the structure shown in Figure 12. The deep trenches formed by etching can be vertical trenches or inclined trenches as shown in Figure 12, and there is no specific limitation.

[0220] Step four: Electrode materials and dielectric materials are alternately deposited on a portion of the first surface and the inner walls of multiple deep trenches to form a sub-capacitor structure with four electrode layers and three dielectric layers (seventh electrode layer 701, eighth electrode layer 702, ninth electrode layer 703, tenth electrode layer 704, second dielectric layer 705, third dielectric layer 706, and fourth dielectric layer 707). An organic material layer is formed on the side of the capacitor structure opposite to the first surface (which can be understood as forming an organic material layer on the seventh electrode layer 701), resulting in the structure shown in Figure 13.

[0221] Step 5: A pattern is photolithographically etched on the organic material layer at the position corresponding to the seventh electrode layer 701 in the groove 340. The seventh electrode layer 701 is then etched according to the pattern to obtain the structure shown in Figure 14.

[0222] Step 6: A pattern is photolithographically etched on the organic material layer at the position corresponding to the eighth electrode layer 702 in the groove 340. The pattern is then etched on the eighth electrode layer 702 to obtain the structure shown in Figure 15.

[0223] Step 7: A pattern is photolithographically etched on the groove 340 on the organic material layer at the position corresponding to the ninth electrode layer 703, and then etched on the ninth electrode layer 701 according to the pattern to obtain the structure shown in Figure 16.

[0224] Step 8: A pattern is photolithographically etched on the organic material layer at the position corresponding to the tenth electrode layer 704 in the groove 340. The pattern is then etched on the tenth electrode layer 704 to obtain the structure shown in Figure 17.

[0225] Step 9: Deposit a composite thin film layer on the side of the capacitor structure opposite to the first surface to obtain the structure shown in Figure 18.

[0226] Step 10: To facilitate the design of subsequent contact holes and interconnects, the surface of the composite thin film layer is polished to a flat surface using chemical mechanical polishing technology, resulting in the structure shown in Figure 19.

[0227] Step 11: Etch to form contact holes that penetrate the composite thin film layer and connect to each electrode layer, obtaining the structure shown in Figure 20.

[0228] Step 12: A tungsten filling process using chemical vapor deposition is used to fill the contact holes that connect to each electrode layer (i.e., tungsten material is deposited in the contact holes to form interconnects). The contact holes are connected by the tungsten on the surface, resulting in the structure shown in Figure 21.

[0229] Step 13: Since the electrode layers are connected through the tungsten layer on the surface after being filled by the tungsten process, chemical mechanical polishing is required to remove the W on the surface in order to disconnect the electrode layers from each other and obtain the structure shown in Figure 22.

[0230] To ensure reliable connections between electrode plates and maintain high performance and reliability even at very small feature sizes, the aforementioned disconnected electrode layers can be reconnected using a damascus process.

[0231] Step fourteen: Deposit silicon nitride on the side of the capacitor structure opposite to the first surface to form a silicon nitride deposition layer, and obtain the structure shown in Figure 23.

[0232] Step 15: Deposit a composite thin film layer on the silicon nitride deposition layer. Next, perform trench photolithography. Coat the composite thin film layer with photoresist, and transfer the design pattern onto the photoresist using a pre-set mask and exposure equipment. After exposure, develop the photoresist to remove unexposed portions, exposing the areas where trenches need to be formed. The surface of the composite thin film layer then reveals the composite thin film layer protected by the remaining photoresist and the exposed areas to be etched.

[0233] Finally, the trench etching step is performed. Using reactive ion etching technology, the exposed composite thin film layer is etched away, and the required trench structure is formed according to the pattern defined by photolithography. All residual photoresist is removed to obtain a composite thin film layer with a trench structure, resulting in the structure shown in Figure 24.

[0234] Step sixteen: After completing the trench etching, perform the photoresist stripping step. The surface of the silicon nitride deposited layer is still covered with photoresist used to design the pattern. In order to proceed to the next step, this residual photoresist must be completely removed. The above structure is placed in the stripping equipment, and specific chemical solutions, such as organic solvents or plasma ashing technology, are used to remove all the remaining photoresist.

[0235] Then, electrochemical copper plating is performed on the trench structure to fill the trenches and form the desired metal interconnects. Specifically,

[0236] A thin seed layer (SL) is deposited on the surface of the trench structure, typically achieved through physical vapor deposition (PVD) or chemical vapor deposition (CVD). The seed layer provides a conductive surface, allowing for uniform current distribution and ensuring the effectiveness of the electroplating process. The structure with the seed layer is then immersed in an electrolyte containing copper ions, and a direct current is applied. Under the influence of the current, copper ions are reduced to metallic copper on the surface of the seed layer and deposited, gradually filling the trench until it is completely filled.

[0237] Finally, the trenches are filled with copper layers to form metal interconnects (i.e., the first interconnect and the second interconnect), resulting in the structure shown in Figure 25.

[0238] Step 17: Since the surface of the trench structure is covered with an excess of copper material, it is removed by chemical mechanical polishing, leaving only the metal lines that exist in the trench, resulting in the structure shown in Figure 26.

[0239] Step 18: To provide a uniform and continuous metal layer for subsequent patterning and etching steps, and to form a new layer of metal interconnects, silicon nitride is deposited again on the side of the capacitor structure opposite to the first surface to form a silicon nitride deposition layer, resulting in the structure shown in Figure 27.

[0240] Step 19: A composite thin film layer, a silicon nitride deposition layer, and another composite thin film layer are deposited sequentially on the silicon nitride deposition layer to obtain the structure shown in Figure 28.

[0241] Step 20: Coat a layer of photoresist onto the composite thin film layer, and transfer the design pattern onto the photoresist using a pre-set mask and exposure equipment. After exposure, develop the photoresist to remove the unexposed areas, exposing the areas where trenches and contact holes need to be formed. The surface of the composite thin film layer then shows the area protected by the remaining photoresist and the exposed areas to be etched. Perform the trench etching step. Using reactive ion etching technology, etch away the exposed composite thin film layer, form the required trench structure according to the photolithographically defined pattern, remove all residual photoresist, and obtain a composite thin film layer with trench and contact hole structures, resulting in the structure shown in Figure 29.

[0242] Step 21: Perform photoresist stripping. The silicon nitride deposited layer surface is still covered with photoresist for pattern design. Then, electrochemical copper plating is performed in the trench structure to fill the trench and form the required metal interconnects (i.e., the first interconnect and the second interconnect), resulting in the structure shown in Figure 30.

[0243] Step 22: Deposit silicon nitride again on the side of the capacitor structure opposite to the first surface to obtain the structure shown in Figure 31.

[0244] Step 23: Using physical vapor deposition or chemical vapor deposition techniques, and employing silicon nitride (Si3N4), silicon carbide (SiC), or other suitable materials as capping layers, the capping layers provide additional protection, enhance the stability of the interconnect structure and its resistance to electromigration, to obtain the structure shown in Figure 32.

[0245] Step 24: Uniformly coat a layer of photoresist onto the surface of the capping layer. This photoresist layer will serve as a mask during the etching process. Using a predefined mask and precision exposure equipment, transfer the designed pattern onto the photoresist. Develop the photoresist to remove unexposed areas, exposing the areas to be etched. At this point, the capping layer surface shows an area protected by the remaining photoresist and the exposed area to be etched. Place the structure with the photoresist pattern into the etching equipment to obtain contact holes for connecting the two power terminals. Finally, remove all residual photoresist to obtain the structure shown in Figure 33.

[0246] It should be noted that those skilled in the art should understand that, in the chip fabrication method involved in this application, unless otherwise specified or required by specific process conditions, the steps in the above-mentioned fabrication method can be appropriately adjusted and rearranged according to the actual production environment, equipment characteristics, and material properties.

[0247] Furthermore, the relevant structures and implementation methods in Embodiments 1, 2, and 4 above are also applicable to this preparation method, and will not be repeated in this application.

[0248] Based on the same concept, this application also provides a packaging substrate, including a substrate body, the substrate body including a deep trench capacitor, the substrate body having opposing first and second surfaces, the deep trench capacitor including: a plurality of deep trenches spaced apart and embedded in the first surface of the substrate body, and N being disposed on a portion of the first surface and the inner walls of the plurality of deep trenches. + A capacitor structure is formed by one electrode layer and N capacitor dielectric layers, where N is a positive integer. A groove penetrates at least two electrode layers and at least one capacitor dielectric layer in the thickness direction of the substrate body. The groove disconnects at least two electrode layers and at least one capacitor dielectric layer. At least one electrode layer on the disconnected side is connected to any electrode layer on the disconnected side through a conductive path.

[0249] The types of substrates mentioned above include, but are not limited to, organic substrates, ceramic substrates, silicon substrates, etc. It should be understood that the packaging substrate in this embodiment is basically the same as the chip structure containing deep trench capacitors described in the above embodiments. For specific similarities, please refer to the description of the foregoing embodiments. Repeated parts will not be repeated.

[0250] Because there are grooves penetrating at least two electrode layers and at least one capacitor dielectric layer in the thickness direction of the substrate body, and these grooves are located between two adjacent deep grooves, short circuits can be effectively avoided by physically disconnecting these layers, improving the withstand voltage of the weak layer after disconnection, thereby improving the reliability and stability of the entire device. Furthermore, in order to convert the originally parallel-connected capacitors into a series connection after disconnection, this application uses conductive paths to connect the disconnected electrodes in series, changing the parallel connection of these electrode capacitors to a partially series-plus-parallel connection, thereby maximizing capacitance.

[0251] Based on the same concept, this application also provides a method for fabricating a packaging substrate. The method includes: providing a substrate body having opposing first and second surfaces; forming a plurality of deep trenches spaced apart on the first surface of the substrate body; alternately depositing electrode materials and dielectric materials on a portion of the first surface and the inner walls of the plurality of deep trenches to form a sub-capacitor structure consisting of N+1 electrode layers and N capacitor dielectric layers, where N is a positive integer; etching at least one sub-capacitor to form a groove penetrating at least two electrode layers and at least one capacitor dielectric layer in the thickness direction of the substrate body; the groove penetrating at least two electrode layers and at least one capacitor dielectric layer; and connecting at least one electrode layer on one side of the disconnection to any electrode layer on the other side of the disconnection through a conductive path.

[0252] Because a groove is formed in the thickness direction of the substrate body, penetrating at least two electrode layers and at least one capacitor dielectric layer, and this groove is located between two adjacent deep grooves, physically disconnecting these layers can effectively prevent short circuits and improve the withstand voltage of the weak layer after disconnection, thereby improving the reliability and stability of the entire device. Furthermore, to achieve the transformation of the disconnected capacitors into a series connection after the original parallel connection is broken, this application uses a conductive path to connect the disconnected electrodes in series, changing the parallel connection of these electrode capacitors to a partially series-plus-parallel connection, thereby maximizing capacitance.

[0253] It should be understood that the preparation method in this embodiment is basically the same as the preparation method described in Figures 10-33 of the foregoing embodiments. Please refer to the description of the foregoing embodiments. Repeated parts will not be described again.

[0254] Based on the same concept, this application also provides a packaged chip, including the packaging substrate and chip of the aforementioned embodiments, with the chip packaged on the packaging substrate. The packaged chip includes, but is not limited to, device modules, memory circuits, logic circuits, power devices, etc., which will not be listed here. Exemplarily, the packaged chip may include a packaging substrate and one or more chips, with the chip packaged on the packaging substrate. Exemplarily, when there are multiple chips, the multiple chips can be packaged in, but not limited to, a three-dimensional manner. Since the aforementioned packaging substrate can physically disconnect weak layers, it can effectively avoid short circuits, improve the withstand voltage of the disconnected weak layers, and thus improve the reliability and stability of the entire device. Therefore, the packaged chip including the aforementioned packaging substrate also has good reliability and stability. Furthermore, the principle by which this packaged chip solves the problem is similar to that of the aforementioned chip; therefore, the implementation of this packaged chip can refer to the implementation of the aforementioned chip, and repeated details will not be elaborated further.

[0255] This application also provides an electronic device, including a circuit board and the chip or packaged chip involved in the above embodiments, wherein the chip or packaged chip is disposed on the circuit board. Since the above-mentioned chip can effectively avoid short circuits by physically disconnecting weak layers, and improve the withstand voltage of the disconnected weak layers, thereby improving the reliability and stability of the entire device, the electronic device including the above-mentioned chip or packaged chip also has better performance and reliability. Furthermore, the principle by which this electronic device solves the problem is similar to that of the aforementioned chip; therefore, the implementation of this electronic device can refer to the implementation of the aforementioned chip, and repeated details will not be elaborated further.

[0256] For example, the electronic device includes, but is not limited to: smartphones, smartwatches, tablets, virtual reality (VR) devices, augmented reality (AR) devices, in-vehicle devices, desktop computers, personal computers, handheld computers, or personal digital assistants.

[0257] Although some possible embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the embodiments of this application as well as all changes and modifications falling within the scope of this application.

[0258] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A chip, characterized by include: Substrate and deep trench capacitors; The substrate has opposing first and second surfaces; The deep trench capacitor includes: a plurality of deep trenches, which are embedded at intervals into the first surface. A sub-capacitor structure formed by N+1 electrode layers and N capacitor dielectric layers is disposed on a portion of the first surface and the inner wall of the plurality of deep trenches, where N is a positive integer. A groove is present in the thickness direction of the substrate, penetrating at least two electrode layers and at least one capacitor dielectric layer. The groove is located between two adjacent deep trenches and disconnects the at least two electrode layers and the at least one capacitor dielectric layer. At least one of the electrode layers on one side is disconnected and connected to any one of the electrode layers on the other side via a conductive path.

2. The chip according to claim 1, characterized in that, The groove divides one sub-capacitor into two separate sub-capacitors; At least one of the electrode layers on one side is disconnected and any one of the electrode layers on the other side is disconnected, so that the two separator capacitors are connected in series.

3. The chip according to claim 1 or 2, characterized in that Also includes: A redistribution layer is opposite to the first surface. The redistribution layer includes a first interconnect and a second interconnect. The redistribution layer includes at least one first contact hole and at least one second contact hole. A first power supply terminal is connected to the first contact hole through the first interconnect, and a second power supply terminal is connected to the second contact hole through the second interconnect. The first electrode layer on one side is disconnected and the second electrode layer on the other side is disconnected, connected through the conductive path; The first contact hole is connected to the unbroken third electrode layer, and the first contact hole is connected to the disconnected fourth electrode layer; The second contact hole is connected to the unbroken electrode layers except for the third electrode layer, and the second contact hole is connected to the disconnected electrode layers except for the first electrode layer, the second electrode layer and the fourth electrode layer.

4. The chip of claim 3, wherein The first contact hole is connected to a non-adjacent, unbroken electrode layer, and the first contact hole is connected to a non-adjacent, broken electrode layer.

5. The chip of claim 3, wherein The second contact hole is connected to a non-adjacent, unbroken electrode layer, and the second contact hole is connected to a non-adjacent, disconnected electrode layer.

6. The chip according to any of claims 3 to 5, characterized in that A fifth electrode layer, a sixth electrode layer, and a first capacitor dielectric layer are specifically disposed on a portion of the first surface and on the inner wall of the plurality of deep trenches. The fifth electrode layer, the sixth electrode layer, and the first capacitor dielectric layer constitute a first sub-capacitor. The substrate has a groove that penetrates the fifth electrode layer, the sixth electrode layer, and the first capacitor dielectric layer in the thickness direction, and the fifth electrode layer on one side of the disconnection is connected to the fifth electrode layer on the other side of the disconnection through the conductive path; The first contact hole is connected to the sixth electrode layer on the disconnected side, and the second contact hole is connected to the sixth electrode layer on the disconnected other side.

7. The chip according to any of claims 3 to 5, characterized in that A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are specifically disposed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor. The eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor. The ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The substrate has a groove that penetrates the seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer in the thickness direction, and the seventh electrode layer on one side of the disconnection is connected to the seventh electrode layer on the other side of the disconnection through the conductive path; The first contact hole is connected to the eighth electrode layer and the tenth electrode layer on the disconnected side, and the second contact hole is connected to the eighth electrode layer and the ninth electrode layer on the other disconnected side.

8. The chip according to any one of claims 3 to 5, wherein A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are specifically disposed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor. The eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor. The ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The substrate has a groove extending through the seventh electrode layer, the eighth electrode layer, the ninth electrode layer, the tenth electrode layer, the second capacitor dielectric layer, the third capacitor dielectric layer, and the fourth capacitor dielectric layer in the thickness direction. The seventh electrode layer on one side is disconnected and the seventh electrode layer on the other side is disconnected through the conductive path. The first contact hole is connected to the eighth electrode layer on the disconnected side, the tenth electrode layer on the disconnected side, and the ninth electrode layer on the other disconnected side. The second contact hole is connected to the ninth electrode layer on the disconnected side, the eighth electrode layer on the other disconnected side, and the tenth electrode layer on the other disconnected side.

9. The chip according to any one of claims 3 to 5, wherein A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are specifically disposed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor. The eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor. The ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The substrate has a groove extending through the seventh electrode layer, the eighth electrode layer, the ninth electrode layer, the tenth electrode layer, the second capacitor dielectric layer, the third capacitor dielectric layer, and the fourth capacitor dielectric layer in the thickness direction. The seventh electrode layer on one side is disconnected and the ninth electrode layer on the other side is disconnected through the conductive path. The first contact hole is connected to the eighth electrode layer on the disconnected side, the tenth electrode layer on the disconnected side, and the seventh electrode layer on the other disconnected side. The second contact hole is connected to the ninth electrode layer on the disconnected side, the eighth electrode layer on the other disconnected side, and the tenth electrode layer on the other disconnected side.

10. The chip according to any of claims 3 to 9, characterized in that At least one of the first contact holes is filled with conductive material to form a first interconnect, and at least one of the second contact holes is filled with the conductive material to form a second interconnect. The first interconnect and the second interconnect are strip structures arranged at intervals.

11. A method of producing a chip, characterized by, include: A substrate is provided, the substrate having opposing first and second surfaces; A plurality of deep grooves spaced apart are formed on the first surface of the substrate; Electrode materials and dielectric materials are alternately deposited on a portion of the first surface and on the inner walls of the plurality of deep trenches to form a sub-capacitor structure consisting of N+1 electrode layers and N capacitor dielectric layers, where N is a positive integer. At least one of the sub-capacitors is etched to form a groove that penetrates at least two electrode layers and at least one capacitor dielectric layer in the thickness direction of the substrate, the groove penetrating the at least two electrode layers and the at least one capacitor dielectric layer; At least one of the electrode layers on the disconnected side is connected to any one of the electrode layers on the disconnected side via a conductive path.

12. The method according to claim 11, characterized in that, After providing the substrate, it also includes: An organic material layer is formed on the first surface; The plurality of deep trenches spaced apart are formed on the first surface of the substrate, including: Patterns are photolithographically etched at the locations corresponding to the plurality of deep trenches on the organic material layer; The plurality of deep grooves are etched into the organic material layer according to the pattern described; Remove the organic material layer.

13. The method according to claim 11, characterized in that, After alternately depositing the electrode material and the dielectric material on a portion of the first surface and the inner walls of the plurality of deep trenches, the process further includes: An organic material layer is formed on the side of the sub-capacitor structure opposite to the first surface; Etching at least one of the sub-capacitors to form a groove penetrating the two electrode layers and the capacitor dielectric layer in the thickness direction of the substrate, including: A pattern is photolithographically etched at the location corresponding to the groove on the organic material layer; The grooves are etched into the organic material layer and the capacitor structure according to the pattern described above. Remove the organic material layer.

14. The method according to claim 12 or 13, characterized in that, The organic material layer includes one or more of a spin coating layer, a bottom anti-reflective layer, and a photoresist layer.

15. The method of claim 11, wherein, The method further includes: A composite thin film layer is formed on the side of the capacitor structure opposite to the first surface; Etching forms at least one first contact hole that penetrates the composite thin film layer and is conductive to at least one electrode layer; etching forms at least one second contact hole that penetrates the composite thin film layer and is conductive to at least one electrode layer. A first power supply terminal is connected to the first contact hole via the first interconnect line, and a second power supply terminal is connected to the second contact hole via the second interconnect line. Conductive material is filled into the at least one first contact hole to form a first interconnect, and conductive material is filled into the at least one second contact hole to form a second interconnect.

16. The method of claim 15, wherein, The conductive material is tungsten.

17. The method according to claim 15 or 16, characterized in that, The first electrode layer on one side is disconnected and the second electrode layer on the other side is disconnected, connected through the conductive path; The first contact hole is connected to the unbroken third electrode layer, and the first contact hole is connected to the disconnected fourth electrode layer; The second contact hole is connected to the unbroken electrode layers except for the third electrode layer, and the second contact hole is connected to the disconnected electrode layers except for the first electrode layer, the second electrode layer and the fourth electrode layer.

18. The method of claim 15 or 16, wherein, The electrode layer material and the dielectric material are alternately deposited on a portion of the first surface and on the inner walls of the plurality of deep trenches. A fifth electrode layer, a sixth electrode layer and a first capacitor dielectric layer are formed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The fifth electrode layer, the sixth electrode layer and the first capacitor dielectric layer constitute a first sub-capacitor. The first sub-capacitor is etched to form a groove that penetrates the fifth electrode layer, the first capacitor dielectric layer, and the sixth electrode layer in the thickness direction of the substrate; The fifth electrode layer on one side is disconnected and the fifth electrode layer on the other side is disconnected, connected through the conductive path; The first contact hole is connected to the sixth electrode layer on the disconnected side, and the second contact hole is connected to the sixth electrode layer on the disconnected other side.

19. The method of claim 15 or 16, wherein, The electrode layer material and the dielectric material are alternately deposited on a portion of the first surface and on the inner walls of the plurality of deep trenches. A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are formed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor. The eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor. The ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The second sub-capacitor is etched to form the groove that penetrates the seventh electrode layer, the second capacitor dielectric layer, and the eighth electrode layer in the thickness direction of the substrate; The seventh electrode layer on one side is disconnected and the seventh electrode layer on the other side is disconnected, connected through the conductive path; The first contact hole is connected to the eighth electrode layer and the tenth electrode layer on the disconnected side, and the second contact hole is connected to the eighth electrode layer and the ninth electrode layer on the other disconnected side.

20. The method of claim 15 or 16, wherein, The electrode layer material and the dielectric material are alternately deposited on a portion of the first surface and on the inner walls of the plurality of deep trenches. A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are formed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor. The eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor. The ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The second sub-capacitor, the third sub-capacitor, and the fourth sub-capacitor are etched to form the groove that penetrates the seventh electrode layer, the second capacitor dielectric layer, the eighth electrode layer, the third capacitor dielectric layer, the ninth electrode layer, the fourth capacitor dielectric layer, and the tenth electrode layer in the thickness direction of the substrate; The seventh electrode layer on one side is disconnected and the seventh electrode layer on the other side is disconnected, connected through the conductive path; The first contact hole is connected to the eighth electrode layer on the disconnected side, the tenth electrode layer on the disconnected side, and the ninth electrode layer on the other disconnected side. The second contact hole is connected to the ninth electrode layer on the disconnected side, the eighth electrode layer on the other disconnected side, and the tenth electrode layer on the other disconnected side.

21. The method of claim 15 or 16, wherein, The electrode layer material and the dielectric material are alternately deposited on a portion of the first surface and on the inner walls of the plurality of deep trenches. A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are formed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor. The eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor. The ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The second sub-capacitor, the third sub-capacitor, and the fourth sub-capacitor are etched to form the groove that penetrates the seventh electrode layer, the second capacitor dielectric layer, the eighth electrode layer, the third capacitor dielectric layer, the ninth electrode layer, the fourth capacitor dielectric layer, and the tenth electrode layer in the thickness direction of the substrate; The seventh electrode layer on one side is disconnected and the ninth electrode layer on the other side is disconnected, connected through the conductive path; The first contact hole is connected to the eighth electrode layer on the disconnected side, the tenth electrode layer on the disconnected side, and the seventh electrode layer on the other disconnected side. The second contact hole is connected to the ninth electrode layer on the disconnected side, the eighth electrode layer on the other disconnected side, and the tenth electrode layer on the other disconnected side.

22. A package substrate, comprising: Includes a substrate body, the substrate body including a deep trench capacitor; The substrate body has a first surface and a second surface that are opposite to each other; The deep trench capacitor includes: Multiple deep trenches are embedded at intervals into the first surface of the substrate body. N+1 electrode layers and N capacitor dielectric layers are disposed on a portion of the first surface and the inner walls of the multiple deep trenches to form a capacitor structure, where N is a positive integer. A groove extends through at least two electrode layers and at least one capacitor dielectric layer in the thickness direction of the substrate body, and the groove disconnects the at least two electrode layers and the at least one capacitor dielectric layer; At least one of the electrode layers on one side is disconnected and connected to any one of the electrode layers on the other side via a conductive path.

23. The package substrate of claim 22, wherein, The groove divides one sub-capacitor into two separate sub-capacitors; At least one of the electrode layers on one side is disconnected and any one of the electrode layers on the other side is disconnected, so that the two separator capacitors are connected in series.

24. The package substrate of claim 22 or 23, wherein, Also includes: A redistribution layer is opposite to the first surface. The redistribution layer includes a first interconnect and a second interconnect. The redistribution layer includes at least one first contact hole and at least one second contact hole. A first power supply terminal is connected to the first contact hole through the first interconnect, and a second power supply terminal is connected to the second contact hole through the second interconnect. The first electrode layer on one side is disconnected and the second electrode layer on the other side is disconnected, connected through the conductive path; The first contact hole is connected to the unbroken third electrode layer, and the first contact hole is connected to the disconnected fourth electrode layer; The second contact hole is connected to the unbroken electrode layers except for the third electrode layer, and the second contact hole is connected to the disconnected electrode layers except for the first electrode layer, the second electrode layer and the fourth electrode layer.

25. The package substrate of claim 24, wherein, The first contact hole is connected to a non-adjacent, unbroken electrode layer, and the first contact hole is connected to a non-adjacent, broken electrode layer.

26. The package substrate of claim 24, wherein, The second contact hole is connected to a non-adjacent, unbroken electrode layer, and the second contact hole is connected to a non-adjacent, disconnected electrode layer.

27. The package substrate of any one of claims 24-26, wherein, A fifth electrode layer, a sixth electrode layer, and a first capacitor dielectric layer are specifically disposed on a portion of the first surface and on the inner wall of the plurality of deep trenches. The fifth electrode layer, the sixth electrode layer, and the first capacitor dielectric layer constitute a first sub-capacitor. The substrate body has a groove that penetrates the fifth electrode layer, the sixth electrode layer and the first capacitor dielectric layer in the thickness direction, and the fifth electrode layer on one side of the disconnection is connected to the fifth electrode layer on the other side of the disconnection through the conductive path; The first contact hole is connected to the sixth electrode layer on the disconnected side, and the second contact hole is connected to the sixth electrode layer on the disconnected other side.

28. The package substrate of any one of claims 24-26, wherein, A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are specifically disposed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor. The eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor. The ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The substrate body has a groove that penetrates the seventh electrode layer, the eighth electrode layer and the second capacitor dielectric layer in the thickness direction, and the seventh electrode layer on one side of the disconnection is connected to the seventh electrode layer on the other side of the disconnection through the conductive path; The first contact hole is connected to the eighth electrode layer and the tenth electrode layer on the disconnected side, and the second contact hole is connected to the eighth electrode layer and the ninth electrode layer on the other disconnected side.

29. The package substrate of any one of claims 24-26, wherein, A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are specifically disposed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor. The eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor. The ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The substrate body has a groove in the thickness direction that penetrates the seventh electrode layer, the eighth electrode layer, the ninth electrode layer, the tenth electrode layer, the second capacitor dielectric layer, the third capacitor dielectric layer and the fourth capacitor dielectric layer, and the seventh electrode layer on one side of the disconnection is connected to the seventh electrode layer on the other side of the disconnection through the conductive path; The first contact hole is connected to the eighth electrode layer on the disconnected side, the tenth electrode layer on the disconnected side, and the ninth electrode layer on the other disconnected side. The second contact hole is connected to the ninth electrode layer on the disconnected side, the eighth electrode layer on the other disconnected side, and the tenth electrode layer on the other disconnected side.

30. The package substrate of any one of claims 24-26, wherein, A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are specifically disposed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor. The eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor. The ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The substrate body has a groove in the thickness direction that penetrates the seventh electrode layer, the eighth electrode layer, the ninth electrode layer, the tenth electrode layer, the second capacitor dielectric layer, the third capacitor dielectric layer and the fourth capacitor dielectric layer, and the seventh electrode layer on one side of the disconnection is connected to the ninth electrode layer on the other side of the disconnection through the conductive path; The first contact hole is connected to the eighth electrode layer on the disconnected side, the tenth electrode layer on the disconnected side, and the seventh electrode layer on the other disconnected side. The second contact hole is connected to the ninth electrode layer on the disconnected side, the eighth electrode layer on the other disconnected side, and the tenth electrode layer on the other disconnected side.

31. The package substrate of any one of claims 24-30, wherein, At least one of the first contact holes is filled with conductive material to form a first interconnect, and at least one of the second contact holes is filled with the conductive material to form a second interconnect. The first interconnect and the second interconnect are strip structures arranged at intervals.

32. A method of fabricating a package substrate, comprising: include: A substrate body is provided, the substrate body having opposing first and second surfaces; A plurality of deep grooves are formed at intervals on the first surface of the substrate body; Electrode materials and dielectric materials are alternately deposited on a portion of the first surface and on the inner walls of the plurality of deep trenches to form a sub-capacitor structure consisting of N+1 electrode layers and N capacitor dielectric layers, where N is a positive integer. At least one of the sub-capacitors is etched to form a groove that penetrates at least two electrode layers and at least one capacitor dielectric layer in the thickness direction of the substrate body, the groove penetrating the at least two electrode layers and the at least one capacitor dielectric layer; At least one of the electrode layers on the disconnected side is connected to any one of the electrode layers on the disconnected side via a conductive path.

33. The method according to claim 32, characterized in that, After providing the substrate body, it also includes: An organic material layer is formed on the first surface; The plurality of deep grooves spaced apart are formed on the first surface of the substrate body, including: Patterns are photolithographically etched at the locations corresponding to the plurality of deep trenches on the organic material layer; The plurality of deep grooves are etched into the organic material layer according to the pattern described; Remove the organic material layer.

34. The method according to claim 32, characterized in that, After alternately depositing the electrode material and the dielectric material on a portion of the first surface and the inner walls of the plurality of deep trenches, the process further includes: An organic material layer is formed on the side of the sub-capacitor structure opposite to the first surface; Etching at least one of the sub-capacitors to form a groove penetrating the two electrode layers and the capacitor dielectric layer in the thickness direction of the substrate body includes: A pattern is photolithographically etched at the location corresponding to the groove on the organic material layer; The grooves are etched into the organic material layer and the capacitor structure according to the pattern described above. Remove the organic material layer.

35. The method of claim 33 or 34, wherein, The organic material layer includes one or more of a spin coating layer, a bottom anti-reflective layer, and a photoresist layer.

36. The method of claim 32, wherein, The method further includes: A composite thin film layer is formed on the side of the capacitor structure opposite to the first surface; Etching forms at least one first contact hole that penetrates the composite thin film layer and is conductive to at least one electrode layer; etching forms at least one second contact hole that penetrates the composite thin film layer and is conductive to at least one electrode layer. A first power supply terminal is connected to the first contact hole via the first interconnect line, and a second power supply terminal is connected to the second contact hole via the second interconnect line. Conductive material is filled into the at least one first contact hole to form a first interconnect, and conductive material is filled into the at least one second contact hole to form a second interconnect.

37. The method of claim 36, wherein, The conductive material is tungsten.

38. The method of claim 36 or 37, wherein, The first electrode layer on one side is disconnected and the second electrode layer on the other side is disconnected, connected through the conductive path; The first contact hole is connected to the unbroken third electrode layer, and the first contact hole is connected to the disconnected fourth electrode layer; The second contact hole is connected to the unbroken electrode layers except for the third electrode layer, and the second contact hole is connected to the disconnected electrode layers except for the first electrode layer, the second electrode layer and the fourth electrode layer.

39. The method of claim 36 or 37, wherein, The electrode layer material and the dielectric material are alternately deposited on a portion of the first surface and on the inner walls of the plurality of deep trenches. A fifth electrode layer, a sixth electrode layer and a first capacitor dielectric layer are formed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The fifth electrode layer, the sixth electrode layer and the first capacitor dielectric layer constitute a first sub-capacitor. The first sub-capacitor is etched to form a groove that penetrates the fifth electrode layer, the first capacitor dielectric layer, and the sixth electrode layer in the thickness direction of the substrate body; The fifth electrode layer on one side is disconnected and the fifth electrode layer on the other side is disconnected, connected through the conductive path; The first contact hole is connected to the sixth electrode layer on the disconnected side, and the second contact hole is connected to the sixth electrode layer on the disconnected other side.

40. The method of claim 36 or 37, wherein, The electrode layer material and the dielectric material are alternately deposited on a portion of the first surface and on the inner walls of the plurality of deep trenches. A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are formed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor. The eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor. The ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The second sub-capacitor is etched to form the groove that penetrates the seventh electrode layer, the second capacitor dielectric layer, and the eighth electrode layer in the thickness direction of the substrate body; The seventh electrode layer on one side is disconnected and the seventh electrode layer on the other side is disconnected, connected through the conductive path; The first contact hole is connected to the eighth electrode layer and the tenth electrode layer on the disconnected side, and the second contact hole is connected to the eighth electrode layer and the ninth electrode layer on the other disconnected side.

41. The method of claim 36 or 37, wherein, The electrode layer material and the dielectric material are alternately deposited on a portion of the first surface and on the inner walls of the plurality of deep trenches. A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are formed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor. The eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor. The ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The second sub-capacitor, the third sub-capacitor, and the fourth sub-capacitor are etched to form the groove that penetrates the seventh electrode layer, the second capacitor dielectric layer, the eighth electrode layer, the third capacitor dielectric layer, the ninth electrode layer, the fourth capacitor dielectric layer, and the tenth electrode layer in the thickness direction of the substrate body; The seventh electrode layer on one side is disconnected and the seventh electrode layer on the other side is disconnected, connected through the conductive path; The first contact hole is connected to the eighth electrode layer on the disconnected side, the tenth electrode layer on the disconnected side, and the ninth electrode layer on the other disconnected side. The second contact hole is connected to the ninth electrode layer on the disconnected side, the eighth electrode layer on the other disconnected side, and the tenth electrode layer on the other disconnected side.

42. The method of claim 36 or 37, wherein, The electrode layer material and the dielectric material are alternately deposited on a portion of the first surface and on the inner walls of the plurality of deep trenches. A seventh electrode layer, an eighth electrode layer, a ninth electrode layer, a tenth electrode layer, a second capacitor dielectric layer, a third capacitor dielectric layer, and a fourth capacitor dielectric layer are formed on a portion of the first surface and on the inner walls of the plurality of deep trenches. The seventh electrode layer, the eighth electrode layer, and the second capacitor dielectric layer constitute a second sub-capacitor. The eighth electrode layer, the ninth electrode layer, and the third capacitor dielectric layer constitute a third sub-capacitor. The ninth electrode layer, the tenth electrode layer, and the fourth capacitor dielectric layer constitute a fourth sub-capacitor. The second sub-capacitor, the third sub-capacitor, and the fourth sub-capacitor are etched to form the groove that penetrates the seventh electrode layer, the second capacitor dielectric layer, the eighth electrode layer, the third capacitor dielectric layer, the ninth electrode layer, the fourth capacitor dielectric layer, and the tenth electrode layer in the thickness direction of the substrate body; The seventh electrode layer on one side is disconnected and the ninth electrode layer on the other side is disconnected, connected through the conductive path; The first contact hole is connected to the eighth electrode layer on the disconnected side, the tenth electrode layer on the disconnected side, and the seventh electrode layer on the other disconnected side. The second contact hole is connected to the ninth electrode layer on the disconnected side, the eighth electrode layer on the other disconnected side, and the tenth electrode layer on the other disconnected side.

43. A packaged chip, comprising: It includes a chip and a packaging substrate as described in any one of claims 22-31, wherein the chip is packaged on the packaging substrate.

44. An electronic device, comprising: include: A circuit board and a chip as claimed in any one of the claims 1-10 or a packaged chip as claimed in claim 43, the chip or the packaged chip being arranged on the circuit board.

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