DDR phy for preventing error in DQS gating signal generation due to noise on data strobe line

Abstract

Disclosed is an SoC comprising: a DQS controller for generating a DQS gating signal for masking a data strobe signal provided by a memory; and a blocking signal generator for outputting a blocking pulse that is generated from a point in time when the DQS gating signal transitions from a first level to a second level to start masking the data strobe signal and lasts for a predetermined time. The blocking pulse is configured to be provided as a reset signal to the DQS controller. The DQS controller is configured not to transition the DQS gating signal from the second level to the first level during a time period in which at least some components of the DQS controller are reset by the blocking pulse.

Description

DDR PHY that prevents DQS gating signal generation errors caused by data strobe line noise

[0001] The present invention relates to a technology for an SoC including a memory controller to generate a DQS gating signal to read data from memory, and in particular, to a technology for blocking the phenomenon in which the generation of an incorrect DQS gating signal is initiated by noise in a DQS channel.

[0002] The SoC (System on Chip) can be connected to multiple memories through a shared DQ channel and DQS (data strobe signal) channel.

[0003] While any one of the above SoC and the plurality of memories occupies the DQ channel and the DQS channel, the terminals of the other remaining devices connected to the DQ channel and the DQS channel may be set to a floating state.

[0004] In one embodiment, the SoC may transmit a read command to the first memory to read data from the first memory among the plurality of memories. After a predetermined delay time has elapsed from the time the read command is transmitted, the first memory may occupy the DQ channel and the DQS channel. Then, the DQ (read data) read from the first memory may be transmitted to the SoC through the DQ channel, and the DQS may be transmitted to the SoC through the DQS channel. The DQS is a pulse train signal indicating the reference timing for the SoC to acquire the DQ.

[0005] While the first memory occupies the DQ channel and DQS channel for the transmission of the DQ and DQS, the terminals of the remaining memories, excluding the SoC and the first memory connected to the DQ channel and DQS channel, may be set to a floating state.

[0006] The DQS output from the terminal of the first memory is a pulse train signal in the form of a square wave. When the pulse period of the pulse train signal is short, the shape of the DQS detected at the terminal of the SoC may have a distorted shape from a square wave. Therefore, the SoC can restore the shape of the DQS detected at the terminal of the SoC into a square wave shape.

[0007] When the first memory terminates the transmission of the DQ and DQS and terminates the occupation of the DQ channel and DQS channel, the DQ channel and DQS channel become high impedance. That is, in a state where there is no device occupying the DQ channel and DQS channel among the SoC and the plurality of memories, the DQ channel and DQS channel can maintain a high impedance state.

[0008] Therefore, immediately after the first memory finishes transmitting the DQS, it is necessary to block the signal flowing into the SoC from the DQS channel.

[0009] To this end, the SoC may block the DQS channel itself immediately after the transmission of the DQS is terminated, and to this end, it may generate and use an internal signal, a DQS gating signal. The DQS gating signal is configured to allow the reception of a signal from the DQS channel only during a time interval from a predetermined start time delayed from the time the SoC transmits a read command to the memory, until the end time when the memory terminates the transmission of the DQS corresponding to the read command.

[0010] According to the prior art, the SoC generates an internal DQS clock (=internal DQS) corresponding to the DQS using an internal clock. The acquisition timing of the DQ transmitted along with the DQS is determined by the internal DQS clock. At this time, the DQS and the internal DQS clock must be synchronized and aligned with each other. However, since the internal clock of the SoC and the DQS generated by the memory are signals generated independently of each other, it is necessary to execute a process referred to as a so-called training process to synchronize and align the internal DQS clock generated using the internal clock with the DQS. The training process must be performed during a time interval when the DQ channel and the DQS channel are not occupied for data reading / writing. In other words, there is a problem in that the training process cannot be performed during a time interval when the SoC and the multiple memories occupy the DQ channel and the DQS channel for data reading / writing. In addition, even if the internal DQS clock is synchronized with the DQS by the above training process, there is a problem that the training process must be repeated because timing drift caused by temperature or supply voltage drift may occur.

[0011] Therefore, other techniques that do not utilize the internal clock of the SoC to generate an internal DQS clock corresponding to the above DQS may also be considered.

[0012] Meanwhile, in DDR memory systems, when the Data Strobe (DQS) channel is in a high-impedance (high-Z) state, noise can be introduced into the DQS line and transmitted to the SoC's DQS receiver. This can cause errors in the internal DQS clock generation, leading to timing issues with read data transmitted through the Data (DQ) channel. In particular, when the first memory device terminates the use of the DQ and DQS channels, the I / O terminals of that memory switch to a high-impedance state. Significant noise may occur during the short period immediately following this transition, and this noise can be transmitted to the memory controller's DQS receiver, degrading the integrity of data transmission. To prevent this problem, the DQS line can be designed to be insensitive to noise when in a high-impedance state. For example, an appropriate termination resistor can be added to the DQS line.

[0013] Alternatively, unnecessary signals can be blocked by utilizing DQS gating technology. However, this requires the assumption that the DQS gating signal is generated without errors; depending on the specific embodiment for generating the DQS gating signal, there is a problem in that the generation of the DQS gating signal may start incorrectly due to the noise, and it is necessary to resolve this problem.

[0014] The present invention aims to provide a technology that blocks the phenomenon in which the generation of an incorrect DQS gating signal is initiated by noise in a DQS channel.

[0015] According to one aspect of the present invention, an SoC may be provided comprising: a DQS control unit (12) that generates a DQS gating signal (1241) that masks a data strobe signal (1103) provided by a memory; and a blocking signal generation unit (15) that outputs a blocking pulse (501) that is generated from the point in time when the DQS gating signal is switched from a first level to a second level and continues for a predetermined time to start masking the data strobe signal, wherein the blocking pulse is provided to the DQS control unit as a reset signal, and the DQS control unit is configured not to switch the DQS gating signal from the second level to the first level during the time interval in which at least some components of the DQS control unit are reset by the blocking pulse.

[0016] At this time, the blocking signal generating unit may include: a delay unit (151) that outputs a delay signal (1502) that delays the DQS gating signal by the predetermined time; an inverter (152) that outputs an inverted signal that inverts the DQS gating signal; and an AND gate (153) that receives the delay signal and the inverted signal and outputs a blocking signal including the blocking pulse.

[0017] At this time, the SoC may further include: a memory controller (20) that provides a read command (2001) to be transmitted to the memory by the SoC; a DQS receiver (11) that provides the data strobe signal and the inverted data strobe signal received respectively from a first DQS channel and a second DQS channel connecting the SoC and the memory; a read command confirmation unit (13); and a DQS clock driver (14) that generates an internal DQS clock (1401). The DQS controller may include a DQS counter unit (122) that generates a read gate signal (1231) for masking the data strobe signal and provides a predetermined BL completion signal (1221) and a read completion signal (1222) indicating the end time of the gating pulse of the read gate signal. And the read command confirmation unit may be configured to generate a subsequent read signal (1301) based on the BL completion signal and the read command. And the DQS counter unit (122) may be configured to generate the BL completion signal by counting the inverted data strobe signal, and to generate the read completion signal using the inverted data strobe signal and the subsequent read signal. And the internal DQS clock (1401) may have the same level as the data strobe signal during the time interval when the read gate signal (1231) is at a first level, and may have a predetermined different level during the time interval when the read gate signal is at a second level. And data may be read using the internal DQS clock (1401) from the DQ received from the DQ channel connecting the SoC and the memory. And the blocking pulse may be provided as a reset signal for the DQS counter unit.

[0018] According to another aspect of the present invention, an SoC may be provided comprising: a DQS control unit (12) that generates a DQS gating signal (1241) that masks a data strobe signal (1103) provided by a memory; a blocking signal generation unit (15) that outputs a blocking signal (1501) including a blocking pulse (501) that is generated from the point in time when the DQS gating signal is switched from a first level to a second level and continues for a predetermined time to start masking the data strobe signal; and a strobe blocking unit (16) configured to block the input of the data strobe signal to the DQS control unit while the blocking pulse is output, so that the DQS gating signal is not switched from the second level to the first level while the blocking pulse is output.

[0019] At this time, the blocking signal generating unit may include: a delay unit (151) that outputs a delay signal (1502) that delays the DQS gating signal by the predetermined time; an inverter (152) that outputs an inverted signal that inverts the DQS gating signal; and an AND gate (153) that receives the delay signal and the inverted signal and outputs a blocking signal including the blocking pulse.

[0020] At this time, the strobe blocking unit may include a second inverter (163) that outputs a second inverted signal obtained by inverting the blocking signal; and a first AND gate (161) that receives the second inverted signal and the data strobe signal. The data strobe signal is not input to the DQS control unit, and instead of the data strobe signal, the output signal of the first AND gate may be input to the DQS control unit.

[0021] At this time, the SoC may further include a DQS receiver (11) that provides the data strobe signal and the inverted data strobe signal received respectively from a first DQS channel and a second DQS channel connecting the SoC and the memory. The strobe blocker may further include a second AND gate (162) that receives the second inverted signal and the inverted data strobe signal. The inverted data strobe signal is not input to the DQS controller, and instead of the inverted data strobe signal, the output signal of the second AND gate may be input to the DQS controller.

[0022] At this time, the SoC may further include: a memory controller (20) that provides a read command (2001) to be transmitted to the memory by the SoC; a DQS receiver (11) that provides the data strobe signal and the inverted data strobe signal received respectively from a first DQS channel and a second DQS channel connecting the SoC and the memory; a read command confirmation unit (13); and a DQS clock driver (14) that generates an internal DQS clock (1401). At this time, the DQS controller may include a DQS counter unit (122) that generates a read gate signal (1231) for masking the data strobe signal and provides a predetermined BL completion signal (1221) and a read completion signal (1222) indicating the end time of the gating pulse of the read gate signal. And the read command confirmation unit may be configured to generate a subsequent read signal (1301) based on the BL completion signal and the read command. And the DQS counter unit (122) may be configured to generate the BL completion signal by counting the inverted data strobe signal, and to generate the read completion signal using the inverted data strobe signal and the subsequent read signal. And the internal DQS clock (1401) may have the same level as the data strobe signal during the time interval when the read gate signal (1231) is at a first level, and may have a predetermined different level during the time interval when the read gate signal is at a second level. And data may be read using the internal DQS clock (1401) from the DQ received from the DQ channel connecting the SoC and the memory. And while the above blocking pulse is output, the above inverted data strobe signal may be blocked from being input to the DQS counter.

[0023] At this time, the SoC may further include a second inverter (163) that outputs a second inverted signal in which the cutoff signal is inverted; and a second AND gate (162) that receives the second inverted signal and the inverted data strobe signal. At this time, the inverted data strobe signal is not input to the DQS counter, and instead of the inverted data strobe signal, the output signal of the second AND gate may be input to the DQS counter.

[0024] According to one aspect of the present invention, an SoC (1) communicating with a memory may be provided. The SoC includes: a DDR PHY (10); and a memory controller (20) that provides a read command (ReadCmd) (2001) to be transmitted to the memory by the SoC. The DDR PHY (10) includes: a DQS receiver (11) that provides a data strobe signal and an inverted data strobe signal received from a first DQS channel and a second DQS channel, respectively, connecting the SoC and the memory; and a DQS control unit (122) that generates a read gate signal (1231) for masking the data strobe signal and provides a predetermined BL completion signal (BL_done) (1221) and a read completion signal (ReadDone) (1222) indicating the end time of the gating pulse of the read gate signal. It includes a read command confirmation unit (13) that generates a next read signal (NextRead) (1301) based on the BL completion signal and the read command; and a DQS clock driving unit (14) that generates an internal DQS clock (1401). The DQS counter unit (122) is configured to generate the BL completion signal by counting the inverted data strobe signal, and to generate the read completion signal using the inverted data strobe signal and the next read signal. The internal DQS clock (1401) has the same level as the data strobe signal during the time interval when the read gate signal (1231) is at a first level, and has a predetermined different level during the time interval when the read gate signal is at a second level. Data is to be read from the DQ received from the DQ channel connecting the SoC and the memory using the internal DQS clock (1401).

[0025] At this time, the DQS receiver is configured to further provide an inverted data strobe signal received from a second DQS channel connecting the SoC and the memory, and the DQS controller may be configured to generate the readout gate signal using the data strobe signal and the inverted data strobe signal.

[0026] At this time, the DQS receiver is configured to further provide an inverted data strobe signal received from a second DQS channel connecting the SoC and the memory, and the end time of the gating pulse of the read gate signal can be determined by the value obtained by counting the pulses of the inverted data strobe signal.

[0027] At this time, the DQS counter unit includes a second count (BL Cnt) that counts pulses of the inverted data strobe signal, and the DQS counter unit may be configured to generate a pulse of the BL completion signal when the countdown of the second count is completed.

[0028] At this time, the read command may be transmitted to a memory that generates the data strobe signal by the memory controller. The read command confirmation unit may be configured to set the subsequent read signal to a first level before receiving the data strobe signal if the read command includes a command to read two or more sets of data having a predetermined length, and to set the subsequent read signal to a second level before receiving the data strobe signal if the read command includes a command to read only one set of data having a predetermined length. Furthermore, the read command confirmation unit may be configured to change the subsequent read signal to a second level if, when the subsequent read signal is at the first level, the generation of the pulse of the BL completion signal is confirmed, there is only one set of data to be read continuously remaining at the time the pulse of the BL completion signal is confirmed, and to maintain the subsequent read signal at the first level if there are two or more sets of data to be read continuously remaining at the time the pulse of the BL completion signal is confirmed.

[0029] At this time, the DQS counter unit may be configured not to generate a pulse of the read completion signal when the subsequent read signal is at the first level at the time when the countdown of the second count is completed, and to generate a pulse of the read completion signal when the subsequent read signal is at the second level at the time of completion.

[0030] At this time, the pulse of the readout completion signal may be generated at the time when the countdown of the second count is completed, or at the time when the post-amble clock of the inverted data strobe signal ends.

[0031] At this time, the DQS counter unit may be configured to initialize the second count to a predetermined second value before receiving the data strobe signal, and may be configured to initialize the second count to the second value when the countdown of the second count is completed.

[0032] At this time, the DQS counter unit may be configured to count down the second count for every rising edge or falling edge of the inverted data strobe signal after the preamble clock of the data strobe signal has ended.

[0033] At this time, the DDR PHY (10) may further include: a read start unit (121) that generates and outputs a read start signal (ReadStart) (1211) based on the inverted data strobe signal; and a DQS gating signal generation unit (123) that generates the read gate signal based on the read start signal and the read completion signal. The read start unit is configured to generate a pulse of the read start signal for every rising edge of the inverted data strobe signal, and the DQS gating signal generation unit may be configured to synchronize the falling edge of the read gate signal with the time of occurrence of the pulse of the read completion signal.

[0034] At this time, the DQS gating signal generation unit may be configured to synchronize the rising edge of the read gate signal with any one of the pulses of the read start signal.

[0035] According to the present invention, a technique can be provided to block the phenomenon in which the generation of an incorrect DQS gating signal is initiated by noise in the DQS channel.

[0036] Figure 1 is a diagram illustrating the configuration of a functional part for data reading of an SoC and the signals used for data reading of memory.

[0037] Figure 2 shows an example of the timing diagrams of DQSt, DQSc, and DQ.

[0038] FIG. 3a is a timing diagram showing the timing relationship between the DQS gating signal generated according to a preferred embodiment and DQSt, DQSc, and DQ.

[0039] FIG. 3b illustrates a situation where noise is introduced into the DQSt channel and DQSc channel connected to the DQS receiver of the DDR PHY immediately after the post-amble clock ends, and the DQS receiver incorrectly recognizes the noise as a legitimate DQSt channel signal and / or DQSc channel signal.

[0040] FIG. 4 shows a generation circuit of an internal DQS clock provided according to one embodiment.

[0041] FIG. 5 shows a generation circuit of an internal DQS clock provided according to one embodiment of the present invention.

[0042] Figure 6 shows the timing diagram of each signal of the circuit presented in Figure 5.

[0043] FIG. 7 shows a generation circuit of an internal DQS clock provided according to another embodiment of the present invention.

[0044] FIG. 8 shows an example of the configuration of a blocking signal generating unit and a strobe blocking unit provided according to an embodiment of the present invention presented in FIG. 5.

[0045] Figure 9 shows the timing diagram of each signal presented in Figure 8.

[0046] FIG. 10 shows the structure of a DDR PHY provided according to one embodiment of the present invention.

[0047] FIG. 11 illustrates a method for generating a read start signal (ReadStart) using DQSt and DQSc, provided according to an embodiment of the present invention.

[0048] Figure 12 is a timing diagram of the signals output by each component of the DDR PHY presented in Figure 10.

[0049] FIG. 13 is a timing diagram showing how the DQS gating signal generation unit of FIG. 10 changes the level of the read-on gate signal.

[0050] FIG. 14 is a timing diagram showing how the DQS clock driver of FIG. 10 generates an internal DQS clock (DQSi_ck).

[0051] FIG. 15 is a timing diagram illustrating the method for generating the extended DQS gating signal presented in FIG. 14.

[0052] FIG. 16 is a timing diagram showing how the DQS clock driver of FIG. 10 generates an internal DQS clock (DQSi_ck).

[0053] FIG. 17 is a timing diagram illustrating the timing of reading DQ in an SoC provided according to one embodiment of the present invention.

[0054] FIG. 18 shows a generation circuit of an internal DQS clock provided according to one embodiment of the present invention.

[0055] The circuit of Fig. 19 is the circuit of Fig. 10 with the addition of a blocking signal generator, a second AND gate, and an inverter.

[0056] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be implemented in various other forms. The terms used in this specification are intended to aid in understanding the embodiments and are not intended to limit the scope of the present invention. Furthermore, singular forms used below include plural forms unless the phrases clearly indicate otherwise.

[0057] Figure 1 is a diagram illustrating the configuration of a functional part for data reading of an SoC and the signals used for data reading of memory.

[0058] The SoC (1) and multiple memories (4, 5) may be part of a computing device that operates independently.

[0059] The SoC (1) can be connected to one or more memories (4, 5) and multiple channels. The multiple channels may include a DQSt channel, a DQSc channel, and a DQ channel.

[0060] In this specification, the DQSt channel, DQSc channel, and DQ channel may be referred to as the DQSt channel signal, DQSc channel signal, and DQ channel signal, respectively, or as the DQSt signal, DQSc signal, and DQ signal, or simply as DQSt, DQSc, and DQ.

[0061] The DQSt channel (Data Strobe True Channel) is a signal used for data synchronization that provides a reference signal for matching data transmission timing. It is activated when data is transmitted to help ensure accurate reading and writing of data. It is transmitted as a unidirectional signal and is typically used in conjunction with the Data Signal (DQ). The DQSt channel is a True signal and serves as the base signal for DQS.

[0062] The DQSc channel (Data Strobe Complement Channel) serves as a complementary signal to DQSt, forming a differential signal to provide a transmission environment robust against noise. The DQSc channel transmits a signal with opposite phase to the DQSt channel and operates in conjunction with DQSt to enhance data timing accuracy through differential signals and reduce the impact of external interference (noise).

[0063] The Data Queue Channel (DQ) is the line through which actual data is transmitted. It serves as a physical pathway for data read and write operations and is used to exchange data between the DRAM module and the memory controller. Multiple DQ lines can be configured in parallel to increase data transmission speed.

[0064] In this specification, the DQSt channel may be referred to as the DQS channel, and the DQSc channel may be referred to as the inverted DQS channel.

[0065] The SoC (1) may include a DDR PHY (10), a memory controller (20), and other major functional parts (30). When the memory controller (20) transmits a ReadCmd command to the DDR PHY (10), the DDR PHY (10) transmits the ReadCmd command to the memory indicated by the ReadCmd command through a predetermined communication channel, receives and processes the DQSt, DQSc, and DQ transmitted by the memory in response, and provides the processed result to the memory controller (20).

[0066] The memory may be, for example, a DRAM. Each of the memory (4, 5) may include a DQS transmitter (40). The DQS transmitter (40) may transmit DQSt, DQSc, and DQ in response to a read command received by the memory to which it belongs. While one of the memory (ex: 4) occupies the DQSt channel, DQSc channel, and DQ channel, the terminals connected to the DQSt channel, DQSc channel, and DQ channel among the remaining other memory (ex: 5) and the terminals of the SoC (1) may be configured to remain in a floating state.

[0067] The above floating state may mean a state in which the terminal is not connected to a clear potential (voltage or logic state). Characteristically, the terminal may be in a floating state, unconnected to anything, and may be considered a high-impedance (high-Z) state in the circuit. This means that the terminal does not transmit or receive signals or conduct current.

[0068] Figure 2 shows an example of the timing diagrams of DQSt, DQSc, and DQ.

[0069] Immediately after SoC (1) sends a read command to memory, the DQSt channel, DQSc channel, and DQ channel may be in a high impedance (Hi-Z) state.

[0070] The memory may occupy the DQSt channel and the DQSc channel and output signals DQSt (1101) and DQSc (1102) to the DQSt channel and the DQSc channel, respectively. DQSt (1101) and DQSc (1102) are each pulse trains, and their voltage levels are complementary to each other. DQSt (1101) and DQSc (1102) may each consist of a preamble clock (71) having a predetermined number of pulses, a read clock (72) having a predetermined number of pulses, and a postamble clock (73) having a predetermined number of pulses. When the postamble clock (73) ends, the memory ceases to occupy the DQSt channel and the DQSc channel, and as a result, the DQSt channel and the DQSc channel return to a high impedance state (Hi-Z).

[0071] In the detailed description and related drawings of the present specification below, the preamble clock (71), the read clock (72), and the postamble clock (73) are exemplified as having lengths of 4tCK, BL16, and 2.5tCK, respectively, but the present invention is not limited to these values. For example, according to an embodiment, the preamble clock (71) may have a length of 1tCK, 2tCK, 3tCK, 4tCK, or a different length. Also, according to an embodiment, the postamble clock (73) may have a length of 0.5tCK, 1.5tCK, 2.5tCK, 4.5tCK, or a different length. Also, according to an embodiment, the read clock (72) may have a length of BL16, BL32, or a different length.

[0072] At the time when the preamble clock (71) ends, the memory may occupy the DQ channel and output the DQ. The memory may provide the DQ synchronized with the read clock. When the time interval during which a predetermined number of data is transmitted by the DQ ends, the memory stops occupying the DQ channel, and as a result, the DQ channel returns to a high impedance state.

[0073] FIG. 3a is a timing diagram showing the timing relationship between the DQS gating signal generated according to a preferred embodiment and DQSt, DQSc, and DQ.

[0074] The DQS gating signal (1241) changes to an enabled state when the preamble clock (71) starts and changes to a disabled state when the postamble clock (73) ends. In this specification, the enabled state may be referred to as a gate open state, and the disabled state may be referred to as a gate blocked state.

[0075] When the post-ampl clock (73) ends, DQSt and DQSc become high impedance (Hi-Z).

[0076] FIG. 3b illustrates a situation where noise is introduced into the DQSt channel and DQSc channel connected to the DQS receiver of the DDR PHY immediately after the post-amble clock ends, and the DQS receiver incorrectly recognizes the noise as a legitimate DQSt channel signal and / or DQSc channel signal.

[0077] Reference numeral 1100f in FIG. 3b represents noise introduced into the DQSt channel and the DQSc channel. In reality, the form of the noise may differ from the patterns of the DQSt signal and the DQSc signal, but there is a problem in that the DQS receiver of the DDR PHY may incorrectly recognize the noise as the DQSt signal and / or the DQSc signal. Reflecting this point, and to aid in understanding the present invention, the appearance of reference numeral 1100f in FIG. 3b is depicted as having the same pattern as the DQSt signal and the DQSc signal, rather than as an atypical form of noise.

[0078] When the post-amble clock (73) ends, the DQS gating signal (1241) is changed to a disabled state. However, if a noise signal (1100f) occurs immediately after the end of the post-amble clock (73), the DQS receiver of the DDR PHY may recognize the noise signal (1100f) as a new pre-amble clock (71). In this case, the DDR PHY may generate an incorrect DQS gating signal (1241f) once again immediately after the end of the post-amble clock (73), which can be understood as an incorrect operation method.

[0079] The present invention aims to solve this problem. Specifically, it aims to solve the problem of an incorrect DQS gating signal (1241f) being generated due to a noise signal (1100f) occurring in the DQSt channel or DQSc channel immediately after the end of the post-amble clock (73).

[0080] FIG. 4 shows a generation circuit of an internal DQS clock provided according to one embodiment.

[0081] The DDR PHY (10) may include a DQS receiver (11), a DQS controller (12), and a DQS clock driver (DQS CLK DRV) (14).

[0082] The DDR PHY (10) can receive DQSt and DQSc to generate an internal DQS clock (DQSi_ck) (1401). The internal DQS clock (1401) is a clock that determines the timing for acquiring DQ. The internal DQS clock (1401) is synchronized and aligned with DQSt and DQSc.

[0083] The DQS receiver (11) receives DQSt and DQSc and uses them to generate and output DQS_out (1103) and DQS_ck (1104). The DQS receiver (11) can generate DQS_out (1103) and DQS_ck (1104) by amplifying and restoring them into a square wave using a high-speed signal comparator that compares DQSt and / or DQSc with a reference voltage inside the DQS receiver (11).

[0084] Since DQS_out (1103) is generated by correcting the distorted shape of DQSt (1101) as it passes through the DQSt channel, DQS_out (1103) is essentially identical to DQSt (1101).

[0085] In one embodiment, DQS_out (1103) is a signal that is output by converting DQSt (1101) into digital at the DQS receiver (11). Or in another modified embodiment, DQS_out (1103) is a signal that is output by converting into digital at the DQS receiver (11) a signal having a value obtained by subtracting the level of DQSc (1102) from the level of DQSt (1101). For convenience of explanation below, the case where DQS_out (1103) is a signal that is output by converting DQSt (1101) into digital at the DQS receiver (11) will be assumed and described.

[0086] DQS_ck (1104) is a signal that is output by converting DQSc (1102) into digital at the DQS receiver (11).

[0087] DQS_out (1103) is input to the DQS control unit (12) and the DQS clock drive unit (14).

[0088] DQS_ck (1104) is input to the DQS control unit (12).

[0089] The DQS clock driver (14) generates an internal DQS clock (1401) by masking the waveform of DQS_out (1103) with a DQS gating signal (ReadRange) (1241). That is, the internal DQS clock (1401) has a second level during the time interval when the DQS gating signal (1241) is at a second level (low level), and has the same level as DQS_out (1103) during the time interval when the DQS gating signal (1241) is at a first level (high level). The internal DQS clock (1401) provides a reference timing for acquiring the DQ.

[0090] Hereinafter, the first level of the DQS gating signal (1241) may be referred to as the pass level of the DQS gating signal (1241), and the second level of the DQS gating signal (1241) may be referred to as the cut level of the DQS gating signal (1241).

[0091] In this specification, the DQS gating signal (1241) may also be referred to as the second readout gate signal (1241).

[0092] The specific method or specific circuit for generating the DQS gating signal (1241) of the DQS control unit (12) may not be limited to a specific one.

[0093] However, the principle by which the DQS control unit (12) generates the DQS gating signal (1241) is based on the following premise. That is, the DQS gating signal (1241) is configured to have a pass level from the start of the pattern only when it is confirmed that the DQS_out (1103) and DQS_ck (1104) input to the DQS control unit (12) are not in an unknown state but are a pattern of a predefined preamble clock (71) (i.e., the DQS gating signal (1241) is changed to an enabled state). After that, when the DQS_out (1103) and DQS_ck (1104) end with a pattern of a postamble clock (73), the DQS gating signal (1241) is switched to a cut-off level (i.e., the DQS gating signal (1241) is changed to a disabled state). After that, while DQS_out (1103) and DQS_ck (1104) remain at unknown values, the DQS gating signal (1241) is not switched back to a pass level (i.e., the DQS gating signal (1241) remains in a disabled state).

[0094] When using the circuit structure shown in FIG. 4, as shown in FIG. 3b, a problem may occur in which an incorrect DQS gating signal (1241f) is generated due to a noise signal (1100f) that occurs in the DQSt channel or DQSc channel during a predetermined time interval immediately after the end of the post-amble clock (73).

[0095] FIG. 5 shows a generation circuit of an internal DQS clock (1401) provided according to one embodiment of the present invention.

[0096] Figure 6 shows the timing diagram of each signal of the circuit presented in Figure 5.

[0097] The circuit of Fig. 5 is intended to solve the problem of generating the incorrect DQS gating signal (1241f), which cannot be solved by the circuit of Fig. 4 alone.

[0098] The following explanation will be provided with reference to FIGS. 5 and FIGS. 6.

[0099] The DDR PHY (10) shown in FIG. 5 is the DDR PHY (10) shown in FIG. 4 with the addition of a blocking signal generation unit (15) and a strobe blocking unit (16). Therefore, the explanation of the input / output relationship of the DQS receiver (11), DQS controller (12), and DQS clock driver (14) shown in FIG. 5 can be replaced with the explanation in FIG. 4. Below, the explanation will focus on the blocking signal generation unit (15) and the strobe blocking unit (16).

[0100] The purpose of the blocking signal generation unit (15) is to receive a DQS gating signal (1241) as input, and to generate and output a blocking signal (1501) having a blocking pulse (501) that persists for a predetermined time interval from the point when the DQS gating signal (1241) is switched from the pass level (gate open level) to the blocking level (gate blocking level).

[0101] The signal level of the blocking signal (1501) during the time interval in which the blocking pulse (501) occurs in the blocking signal (1501) may be referred to as the blocking level, and the signal level of the blocking signal (1501) during other time intervals may be referred to as the pass level.

[0102] The above predetermined time interval may be, for example, a time interval that includes the duration of noise generated when the memory device terminates the use of the DQS channel as described above and switches the corresponding I / O terminal of the memory device to a high impedance state. The point in time when the I / O terminal of the memory device switches to a high impedance state may be, for example, immediately after the end of the post-amble clock (73) shown in FIG. 6.

[0103] The purpose of the strobe blocking unit (16) is to transmit the DQS_out (1103) and DQS_ck (1104) output by the DQS receiver (11) to the DQS control unit (12) as is during the time interval when the blocking signal (1501) is at the passing level, and, conversely, not to transmit the DQS_out (1103) and DQS_ck (1104) output by the DQS receiver (11) to the DQS control unit (12) during the time interval when the blocking signal (1501) is at the blocking level.

[0104] That is, the strobe blocking unit (16) may include two input terminals that receive DQS_out (1103) and DQS_ck (1104). The strobe blocking unit (16) may include a first output terminal that outputs DQS_out.f (1105), which is an output signal corresponding to DQS_out (1103), and a second output terminal that outputs DQS_ck.f (1106), which is an output signal corresponding to DQS_ck (1104).

[0105] DQS_out.f(1105) has the same value as DQS_out(1103) when the blocking signal (1501) is at the pass level, and has a predetermined fixed value when the blocking signal (1501) is at the blocking level.

[0106] DQS_ck.f (1106) has the same value as DQS_ck (1104) when the blocking signal (1501) is at the pass level, and has a predetermined fixed value when the blocking signal (1501) is at the blocking level.

[0107] At this time, the principle by which the DQS control unit (12) generates the DQS gating signal (1241) is based on the following premise. That is, the DQS gating signal (1241) is configured to switch to a pass level from the start of the pattern only when it is confirmed that the DQS_out.f (1105) and DQS_ck.f (1106) input to the DQS control unit (12) are patterns of a predefined preamble clock (71). That is, the DQS gating signal (1241) changes to an enable state, i.e., a gate open state. After that, when the DQS_out.f (1105) and DQS_ck.f (1106) end with a pattern of a postamble clock (73), the DQS gating signal (1241) switches to a blocking level. That is, the DQS gating signal (1241) changes to a disable state, i.e., a gate blocking state. After that, when DQS_out.f (1105) and DQS_ck.f (1106) are maintained at an unknown value or a specific fixed level, the DQS gating signal (1241) is not switched back to the pass level. That is, the DQS gating signal (1241) continues to remain in a disabled state, i.e., a gate-blocked state.

[0108] Accordingly, in the time interval when the blocking signal (1501) is at the blocking level, that is, in the time interval when the blocking pulse (501) of the blocking signal (1501) is generated, the DQS_out.f (1105) and DQS_ck.f (1106) do not have a pattern of the predefined preamble clock (71) and have a specific fixed level, so the DQS control unit (12) does not start generating the DQS gating signal (1241). That is, as shown in FIG. 6, in the time interval when the blocking pulse (501) is generated, the DQS gating signal (1241) does not change to an enabled state and continues to maintain a disabled state.

[0109] FIG. 7 shows a generation circuit of an internal DQS clock (1401) provided according to another embodiment of the present invention.

[0110] The DDR PHY (10) shown in FIG. 7 is the DDR PHY (10) shown in FIG. 4 with a blocking signal generation unit (15) added. Therefore, the explanation of the input / output relationship of the DQS receiver (11), DQS controller (12), and DQS clock driver (14) shown in FIG. 7 can be replaced with the explanation in FIG. 4.

[0111] The blocking signal generating unit (15) shown in FIG. 7 may be the same as the blocking signal generating unit (15) shown in FIG. 5.

[0112] However, in the DDR PHY (10) of FIG. 5, the blocking signal (1501) is input to the strobe blocking unit (16), but in the DDR PHY (10) of FIG. 7, the blocking signal (1501) is input to the reset terminal of the DQS control unit (12).

[0113] The DQSt, DASc, DQS gating signals (1241), and blocking signal (1501) presented in FIG. 7 can also follow the timing diagram of FIG. 6.

[0114] That is, the DDR PHY (10) shown in FIG. 7 is a modified other embodiment that achieves the same purpose as the DDR PHY (10) shown in FIG. 5.

[0115] At this time, the principle by which the DQS control unit (12) generates the DQS gating signal (1241) is the same as the principle by which the DQS control unit (12) generates the DQS gating signal (1241) described in FIG. 4.

[0116] However, the DQS control unit (12) shown in FIG. 7 may be configured so that the DQS gating signal (1241) is disabled during the time interval when a reset pulse signal is input to the reset terminal of the DQS control unit (12).

[0117] At this time, during the time interval when the blocking signal (1501) is at the blocking level, that is, during the time interval when the blocking pulse (501) of the blocking signal (1501) is generated, the blocking signal (1501) acts as a reset pulse signal input to the reset terminal of the DQS control unit (12). Accordingly, during the time interval when the blocking pulse (501) of the blocking signal (1501) is generated, the DQS gating signal (1241) has a disabled state.

[0118] In the embodiment of the present invention shown in FIGS. 5 and 7, the duration of the time interval during which the blocking pulse (501) is generated can be designed to be longer than the noise generation time interval, which is the time interval during which noise generated when the memory device terminates the use of the DQS channel and switches the corresponding I / O terminal of the memory device to a high impedance state as described above. Additionally, the duration of the time interval during which the blocking pulse (501) is generated can be designed to be shorter than the minimum time difference between two consecutive pairs of DQSt (1101) (DQSc (1102)) input to the DDR PHY (10). Therefore, it is possible to receive both DQSt (1101) and DQSc (1102) input to the DDR PHY (10) without missing any of them, while excluding the influence of noise.

[0119] In one embodiment, the noise occurrence time interval may refer to a finite time interval until the transient response, which is generated by parasitic components of the output buffer, package, and board wiring, coupling with adjacent signal lines, etc., when the I / O driver of the memory device switches to a high-impedance state, is attenuated within an acceptable voltage range. The time interval can be pre-calculated by signal integrity simulation or actual measurement for the corresponding DQS line. The transient noise generated by the Hi-Z transition is a transient response attenuated by parasitic components (L, C, R) of the memory I / O output driver, and generally can be maintained for only a short time within a few nanoseconds. This value is sufficiently shorter than the lengths of the DQS preamble and postamble defined in the JEDEC standard and the minimum time interval between consecutive DQS clock pulses, and can be inferred from IBIS-based signal integrity (SI) simulation or actual measurement results.

[0120] FIG. 8 shows an example of the configuration of a blocking signal generating unit (15) and a strobe blocking unit (16) provided according to an embodiment of the present invention presented in FIG. 5.

[0121] Figure 9 shows the timing diagram of each signal presented in Figure 8.

[0122] The following explanation will be provided with reference to FIGS. 8 and FIGS. 9.

[0123] The blocking signal generating unit (15) may include a delay unit (151), an inverter (152), and an AND gate (153).

[0124] The delay unit (151) can delay the DQS gating signal (1241) by a pre-designed delay time (D1) and output it. The output signal (Delay window) of the delay unit (151) is represented by reference number 1502. The delay time (D1) is the same as the duration of the blocking pulse (501) described above and is a pre-designed time length.

[0125] The two input terminals of the AND gate (153) can receive a DQS gating signal (1241) inverted by the inverter (152) and a delay signal (1502).

[0126] The AND gate (153) outputs a blocking signal (1501), and the blocking signal (1501) may have a blocking pulse (501) that lasts for the delay time (D1) from the time when the DQS gating signal (1241) switches from the enabled state to the disabled state.

[0127] The strobe blocking unit (16) may include a first AND gate (161), a second AND gate (162), and an inverter (163). The two input terminals of the first AND gate (161) receive DQS_out (1103) and a blocking signal (1501) inverted by the inverter (163). The two input terminals of the second AND gate (162) receive DQS_ck (1104) and a blocking signal (1501) inverted by the inverter (163). As a result, during the time interval when there is no blocking pulse (501) in the blocking signal (1501), DQS_out.f (1105) and DQS_ck.f (1106) have the same value as DQS_out (1103) and DQS_ck (1104), respectively.

[0128] In contrast, during the time interval when the blocking pulse (501) exists in the blocking signal (1501), DQS_out.f (1105) and DQS_ck.f (1106) each have low level values ​​regardless of the values ​​of DQS_out (1103) and DQS_ck (1104). Therefore, as shown in reference number 1100f of FIG. 9, even if noise occurs in DQSt (1101) and DQSc (1102) during the time interval when the blocking pulse (501) exists in the blocking signal (1501), the noise is not transmitted to the DQS control unit (12). As a result, the DQS control unit (12) has the effect of not generating an incorrect DQS gating signal (1241) due to the noise.

[0129] In FIG. 8, the signal input to the DQS clock driver (14) is exemplified as DQS_out.f (1105), but in other embodiments, the signal input to the DQS clock driver (14) may be DQS_out (1103).

[0130] In FIG. 8, the strobe blocking unit (16) is illustrated as being a separate part from the DQS control unit (12), but in other embodiments, the DQS control unit (12) may include the strobe blocking unit (16).

[0131] In one embodiment, the blocking signal generating unit (15) illustrated in FIG. 7 may also have the same internal configuration as the blocking signal generating unit (15) presented in FIG. 8.

[0132] <DDR PHY의 일 실시예에 대한 본 발명의 적용 사례>

[0133] FIG. 10 shows the structure of a DDR PHY provided according to one embodiment of the present invention.

[0134] The above DDR PHY (10) may include a DQS receiver (11), a DQS controller (12), a Read Command Checker (13), and a DQS clock driver (14).

[0135] The DQS receiver (11), DQS controller (12), and DQS clock driver (14) may each have the same structure as described in FIG. 4.

[0136] The read command confirmation unit (13) can determine the value of a subsequent read signal (1301) based on the BL completion signal (1221) provided by the DQS counter (122) of the DQS control unit (12) and the read command (2001) provided by the memory controller (20), and provide it to the DQS counter unit (122) of the DQS control unit (12).

[0137] The DQS control unit (12) can generate a read gate signal (ReadOn) (1231) based on DQS_out (1103), DQS_ck (1104), and subsequent read signal (1301).

[0138] The DQS clock driver (14) generates and outputs an internal DQS clock (1401) based on DQS_out (1103) and a DQS gating signal (1241).

[0139] At this time, the DQS receiver (11) may not use the local clock inside the DDR PHY (10) to generate DQS_out (1103) and DQS_ck (1104).

[0140] The above DQS control unit (12) may include a Read Start unit (121), a DQS counter unit (122), and a DQS gating signal generation unit (123).

[0141] The readout start unit (121) generates and outputs a readout start signal (1211) using DQS_out (1103) and DQS_ck (1104).

[0142] The DQS counter unit (122) generates and outputs a read completion signal (1222) and a BL completion signal (1221) using DQS_ck (1104) and a follow-up read signal (1301).

[0143] The DQS gating signal generation unit (123) generates and outputs a read gate signal (1231) using a read start signal (1211) and a read complete signal (1222).

[0144] A DQS gating signal extension unit (124) is further included between the DQS clock driving unit (14) and the DQS gating signal generating unit (123).

[0145] The DQS gating signal expansion unit (124) generates an expanded DQS gating signal (1241) based on the readout gate signal (1231). In this specification, the DQS gating signal may also be referred to as a second readout gate signal.

[0146] In one embodiment of the present invention, DQS_out (1103) is a square wave shape restored from the shape of DQSt (1101), so DQS_out (1103) can be regarded as DQSt. Additionally, DQS_ck (1104) is a square wave shape restored from the shape of DQSc (1102), so DQS_ck (1104) can be regarded as DQSc.

[0147] FIG. 11 illustrates a method for generating a read start signal (ReadStart) using DQSt and DQSc, provided according to an embodiment of the present invention.

[0148] At the time the memory begins to output DQSt (1101) and DQSc (1102), both DQSt (1101) and DQSc (1102) have a second level value. Then, as DQSc (1102) changes to the first level before DQSt (1101), DQSt (1101) and DQSc (1102) have complementary level values.

[0149] The first level and the second level may each be a high level and a low level. Alternatively, the first level and the second level may each be a low level and a high level. The present specification describes an example in which the first level and the second level are each a high level and a low level.

[0150] The readout starter (121) is configured to generate a pulse of the readout start signal (1211) by recognizing the point in time when DQSt (1101) has a second level and DQSc (1102) has a first level. The readout starter (121) generates a pulse of the readout start signal (1211) whenever a rising edge is detected in DQSc (1102).

[0151] In this specification, generating a pulse of a signal may mean temporarily raising the value of the signal, which had a second level value, to a first level to generate a pulse-shaped level change.

[0152] In one embodiment, the readout start signal (1211) may be generated in the form of a pulse train (1211_p) composed of pulses with a relatively long duration of the first level.

[0153] In another embodiment, the readout start signal (1211) may be generated in the form of a pulse train (1211_sp) composed of pulses with a relatively short duration of the first level.

[0154] Figure 12 is a timing diagram of the signals output by each component of the DDR PHY presented in Figure 10.

[0155] In FIG. 12, reference numeral IV represents the initial value, HZ represents the high impedance, Pr.Cnt represents the preamble count, and BL Cnt represents the BL count.

[0156] In FIG. 12, the reference numeral DQS_Cnt refers to Pr. Cnt and BL Cnt, which are count variables used inside the DQS counter unit (122).

[0157] After SoC (1) sends a read command to memory, while the DQS counter unit (122) waits for reception of DQSc (1102), SoC (1) can set the preamble count to the first initial value and the BL count to the second initial value.

[0158] The first initial value may be a value corresponding to the number of pulses constituting the preamble clock of DQSt (1101) and DQSc (1102). The second initial value may be a value corresponding to the number of pulses constituting the read clock constituting a set of data having a predetermined length.

[0159] In one embodiment, the number of pulses constituting the preamble clock may be a fixed value according to a defined pattern of the DQS preamble output by the memory, and the SoC may know this value in advance and set it as an initial value.

[0160] At the first rising edge point after DQSc (1102) begins to occur, the preamble count may be set to a predetermined first initial value.

[0161] Afterwards, whenever a pulse of DQSc (1102) occurs, that is, at every rising edge of DQSc (1102), the value of the preamble count can be decreased by 1.

[0162] SoC(1) can determine that when the value of the preamble count becomes 0, the preamble clock ends and the read clock begins.

[0163] Afterwards, whenever a pulse of DQSc (1102) occurs, that is, at every rising edge of DQSc (1102), the value of the BL count can be decreased by 1.

[0164] When the value of the above BL count becomes 0, the DQS counter unit (122) can generate a pulse of the BL completion signal (1221).

[0165] When the value of the subsequent readout signal (1301) is at the second level at the time the pulse of the BL completion signal (1221) is generated, the DQS counter unit (122) can generate a pulse of the readout completion signal (ReadDone) (1222).

[0166] In contrast, if the value of the subsequent readout signal (1301) is at the first level at the time when the pulse of the BL completion signal (1221) is generated, the DQS counter unit (122) may not generate the pulse of the readout completion signal (1222).

[0167] SoC (1) can determine that the read clock ends and the post-amble clock starts when the subsequent read signal (1301) is at the second level at the time when the value of the BL count becomes 0.

[0168] For example, referring to the example in FIG. 12, since the subsequent readout signal (1301) is at the second level at the first time point (t1) and the fourth time point (t4) when the pulse of the BL completion signal (1221) occurs, the pulse of the readout completion signal (1222) occurs at the first time point (t1) and the fourth time point (t4). In contrast, since the subsequent readout signal (1301) is at the first level at the third time point (t3) when the pulse of the BL completion signal (1221) occurs, the pulse of the readout completion signal (1222) does not occur at the third time point (t2).

[0169] Here, the fact that the value of the subsequent readout signal (1301) is at the first level means that, in addition to one set of data having a predetermined length (e.g., BL16) being read out at the time when the subsequent readout signal (1301) is at the first level, there is another set of data that is scheduled to be transmitted continuously. That is, even if all of the above set of data is read out, it means that the other set of data and the readout clocks for reading it are immediately transmitted continuously.

[0170] In contrast, the fact that the value of the subsequent readout signal (1301) is at the second level indicates that when the subsequent readout signal (1301) is at the second level, a set of data having a predetermined length (e.g., BL16) is read out and all of it is read out, there is no other set of data that is continuously transmitted after the set of data. That is, it means that when all of the set of data having the predetermined length (e.g., BL16) is read out, the postamble clock is transmitted immediately.

[0171] The value of the subsequent reading signal (1301) can be determined by the reading command confirmation unit (13) based on the BL completion signal (1221) and the reading command (2001).

[0172] Before the memory transmits the preamble clock of DQSc (1102), the SoC (1) transmits a read command (2001) generated by the memory controller (20) to the memory. At this time, the read command (2001) may include a command to read a set of data having a predetermined length (e.g., BL16) N times consecutively (N=1, 2, 3, ...). In accordance with the command, the memory may transmit DQSt, which consists of a preamble clock, a read clock, and a postamble clock. At this time, the time length of the read clock may be equal to the time length required for the memory to read the set of data N times consecutively. Here, N may be referred to as the number of consecutive reads.

[0173] At this time, the read command verification unit (13) can verify the continuous read count N by analyzing the read command (2001) transmitted to the memory. Next, the read command verification unit (13) can set the third count managed by the read command verification unit (13) to N before the DQSt (1101) for the read command (2001) is received.

[0174] For example, the read command confirmation unit (13) can set the subsequent read signal (1301) to a second level when the third count has a value of '1', and set the subsequent read signal (1301) to a first level when the third count is greater than '1'.

[0175] If the third count is 2 or more at the time the pulse of the BL completion signal (1221) occurs, the read command confirmation unit (13) can decrease the third count by 1.

[0176] In one embodiment, when the third count is 1 at the time the pulse of the BL completion signal (1221) occurs, the read command confirmation unit (13) may maintain the value of the third count at 1 or decrease it by 1 to make it 0.

[0177] The example in FIG. 12 shows a situation where the SoC (1) issues a read command (2001) immediately before the second time point (t2), and N=2. At this time, since N=2, a data set having a length of, for example, BL16 can be transmitted twice in succession. Since N=2, the value of the third count is set to 2 at the second time point (t2). And since the third count has a value greater than 1 at the second time point (t2), the subsequent read signal (1301) is set to the first level. And at the third time point (t3), the read command confirmation unit (13) can confirm that a pulse of the BL completion signal (1221) has been generated, so the value of the third count can be decreased by 1. Therefore, at the third time point (t3), the value of the third count changes from 2 to 1. As a result, immediately after the third time point (t3), the value of the third count is 1, so the subsequent readout signal (1301) is set to the second level. At this time, since the subsequent readout signal (1301) is at the first level at the third time point (t3), the pulse of the readout completion signal (1222) is not generated despite the generation of the pulse of the BL completion signal (1221). Next, at the fourth time point (t4), the readout command confirmation unit (13) can confirm that the pulse of the BL completion signal (1221) has been generated, but since the value of the third count is 1, the value of the third count can be maintained at 1 without decreasing it, or it can be decreased by 1. And at the fourth time point (t4), since the subsequent readout signal (1301) is at the second level, the pulse of the readout completion signal (1222) is generated by the pulse of the BL completion signal (1221).

[0178] It can be seen that the pulse of the readout completion signal (1222) is a signal synchronized with the edge of the last DQSt before the post-amble clock occurs.

[0179] FIG. 13 is a timing diagram showing how the DQS gating signal generation unit of FIG. 10 changes the level of the read-on gate signal.

[0180] The readout gate signal (1231) may have a first level (high level) only during a portion of the time interval in which DQSt (1101) occurs, and a second level during the remaining interval.

[0181] The falling edge of the read gate signal (1231) may be synchronized with the time of occurrence of the pulse of the read completion signal (1222).

[0182] The rising edge of the readout gate signal (1231) can be synchronized with any one of the pulses of the readout start signal (1211).

[0183] In the graph indicated by reference number 1231_1 in FIG. 13, the rising edge of the read gate signal (1231) is synchronized with the pulse of the first read start signal (1211) that occurred after the time when DQSt (1101) occurred.

[0184] In another graph indicated by reference number 1231_2 in FIG. 13, the rising edge of the read gate signal (1231) is synchronized with the pulse of the read start signal (1211) that occurs just before the read clock starts.

[0185] In this specification, the portion of the section from the rising edge to the falling edge of the readout gate signal (1231) may be referred to as a 'gating pulse,' and the readout gate signal may be referred to as a 'DQS gating signal' or a 'DQS masking signal.'

[0186] FIG. 14 is a timing diagram showing how the DQS clock driver of FIG. 10 generates an internal DQS clock (DQSi_ck).

[0187] The DQS clock driver (14) generates an internal DQS clock (1401) by masking the waveform of DQS_out (1103) with a read gate signal (1231). That is, the internal DQS clock (1401) has a second level during the time interval when the read gate signal (1231) is at a second level (low level), and has the same level as DQS_out (1103) during the time interval when the read gate signal (1231) is at a first level (high level). The internal DQS clock (1401) provides a reference timing for acquiring the DQ.

[0188] In this specification, the portion of the extended DQS gating signal (1241) from the rising edge to the falling edge may be referred to as a gating pulse.

[0189] FIG. 15 is a timing diagram illustrating the method for generating the extended DQS gating signal presented in FIG. 14.

[0190] The DQS gating signal extension unit (124) synchronizes the rising edge of the DQS gating signal (1241) with the rising edge of the readout gate signal (1231).

[0191] However, the DQS gating signal extension unit (124) causes the falling edge of the DQS gating signal (1241) to occur after the falling edge of the readout gate signal (1231). The DQS gating signal extension unit (124) can synchronize the falling edge of the DQS gating signal (1241) with the rising edge of the last pulse of DQSc (1102).

[0192] FIG. 16 is a timing diagram showing how the DQS clock driver (14) of FIG. 10 generates an internal DQS clock (DQSi_ck).

[0193] The DQS clock driver (14) generates an internal DQS clock (1401) by masking the waveform of DQS_out (1103) with a DQS gating signal (1241). That is, the internal DQS clock (1401) has a second level during the time interval when the DQS gating signal (1241) is at a second level (e.g., low level), and has the same level as DQS_out (1103) during the time interval when the DQS gating signal (1241) is at a first level (e.g., high level). The internal DQS clock (1401) provides a reference timing for acquiring the DQ. The second level may be referred to as a closing level, and the first level may be referred to as an open level.

[0194] FIG. 17 is a timing diagram illustrating the timing of reading DQ in an SoC provided according to one embodiment of the present invention.

[0195] As described above, the read timing of DQ is determined by the internal DQS clock (1401) generated by the read gate signal (1231) masking DQSt (1101).

[0196] Up to now, an embodiment of the DDR PHY (10) presented in FIG. 10 has been described using FIG. 10 to FIG. 17. However, even according to the embodiment of the DDR PHY (10) presented in FIG. 10, the problem described in FIG. 3b is not resolved. To solve this problem, a blocking signal generating unit (15) provided according to an embodiment of the present invention presented in FIG. 5 and FIG. 7 can be applied to the DDR PHY (10) presented in FIG. 10.

[0197] FIG. 18 shows a generation circuit of an internal DQS clock (1401) provided according to one embodiment of the present invention.

[0198] The circuit of Fig. 18 is the circuit of Fig. 10 with a blocking signal generating unit (15) added.

[0199] The DQS gating signal (1241) is input to the blocking signal generation unit (15).

[0200] The blocking signal (1501), which is the output signal of the blocking signal generating unit (15), is input to the reset terminal (Reset) of the DQS counter (122).

[0201] The DQS counter (122) stops operating during the time interval when a reset pulse signal is input to its reset terminal.

[0202] At this time, during the time interval when the blocking signal (1501) is at the blocking level, that is, during the time interval when the blocking pulse (501) of the blocking signal (1501) is generated, the blocking signal (1501) acts as a reset pulse signal input to the reset terminal of the DQS counter (122). As a result, during the time interval when the blocking pulse (501) of the blocking signal (1501) is generated, the DQS gating signal (1241) has a disabled state.

[0203] The circuit of Fig. 19 is the circuit of Fig. 10 with the addition of a blocking signal generating unit (15), a second AND gate (162), and an inverter (163).

[0204] The DQS gating signal (1241) is input to the blocking signal generation unit (15).

[0205] The second AND gate (162) receives the blocking signal (1501) inverted by DQS_ck (1104) and the inverter (163) and provides the generated signal to the DQS counter (122).

[0206] The two input terminals of the second AND gate (162) are input to DQS_ck (1104) and the cutoff signal (1501) inverted by the inverter (163). As a result, during the time interval when there is no cutoff pulse (501) in the cutoff signal (1501), DQS_ck.f (1106) has the same value as DQS_ck (1104).

[0207] In contrast, during the time interval when the blocking pulse (501) exists in the blocking signal (1501), DQS_ck.f (1106) has a low level value regardless of the value of DQS_ck (1104). Therefore, as shown in reference number 1100f of FIG. 9, even if noise occurs in DQSc (1102) during the time interval when the blocking pulse (501) exists in the blocking signal (1501), the noise is not transmitted to the DQS counter (122).

[0208] As a result, the DQS gating signal (1241) has a disabled state during the time interval when the blocking pulse (501) of the blocking signal (1501) is generated.

[0209] In FIGS. 18 and 19, the blocking signal generation unit (15) is shown as a separate module from the DQS control unit (12). However, depending on the embodiment, the blocking signal generation unit (15) may be included in the DQS control unit (12).

[0210] Using the embodiments of the present invention described above, those skilled in the art will be able to easily make various changes and modifications within the scope of the essential characteristics of the present invention. The content of each claim of the patent claims may be combined with other claims that are not related by reference within the scope of what can be understood from this specification.

[0211] [Acknowledgements] This invention is based on the research results of the project “Development of Memory Controller PHY IP for Next-Generation Data Center and Automotive DDR5 Memory Interface” (Project No. 20025970), which was conducted as part of the national R&D project “Technology Development for Global K-Fabless Creation and Strategic Product Creation - Global Star Fabless 30 Technology Development Support,” supported by the Ministry of Trade, Industry and Energy and carried out by the Korea Institute of Industrial Technology Planning and Evaluation as the implementing agency. This research was conducted by OpenEdge Technology Co., Ltd. from May 1, 2023, to December 31, 2025.

Claims

1. A DQS control unit (12) that generates a DQS gating signal (1241) that masks a data strobe signal (1103) provided by memory; and A blocking signal generating unit (15) that outputs a blocking pulse (501) generated from the point at which the DQS gating signal switches from a first level to a second level and continues for a predetermined time to start masking the data strobe signal; Includes, The above blocking pulse is provided to the DQS control unit as a reset signal, and The above DQS control unit is configured not to switch the DQS gating signal from the second level to the first level during the time interval in which the DQS control unit is reset by the blocking pulse. SoC.

2. In Paragraph 1, The above blocking signal generating unit is, A delay unit (151) that outputs a delay signal (1502) that delays the above DQS gating signal by the above predetermined time; An inverter (152) that outputs an inverted signal obtained by inverting the above DQS gating signal; and An AND gate (153) that receives the above delay signal and the above inversion signal and outputs a blocking signal including the above blocking pulse; including, SoC.

3. In Paragraph 1, A memory controller (20) that provides a read command (2001) to be transmitted to the memory by the above SoC; A DQS receiver (11) that provides the data strobe signal and the inverted data strobe signal received respectively from the first DQS channel and the second DQS channel connecting the SoC and the memory; Reading command confirmation unit (13); and A DQS clock driver (14) that generates an internal DQS clock (1401); Includes more, The above DQS control unit includes a DQS counter unit (122) that generates a read gate signal (1231) for masking the data strobe signal and provides a predetermined BL completion signal (1221) and a read completion signal (1222) indicating the end time of the gating pulse of the read gate signal. The above read command confirmation unit is configured to generate a subsequent read signal (1301) based on the BL completion signal and the read command, and The above DQS counter unit (122) is configured to generate the BL completion signal by counting the inverted data strobe signal, and to generate the readout completion signal using the inverted data strobe signal and the subsequent readout signal. The internal DQS clock (1401) has the same level as the data strobe signal during the time interval when the read gate signal (1231) is at a first level, and has a predetermined different level during the time interval when the read gate signal is at a second level. Data is read from the DQ received from the DQ channel connecting the above SoC and the above memory using the internal DQS clock (1401), and The above blocking pulse is characterized by being provided as a reset signal for the DQS counter unit. SoC.

4. In claim 1, the blocking pulse is generated by triggering the switching of the DQS gating signal from the first level to the second level, SoC.

5. A DQS control unit (12) that generates a DQS gating signal (1241) that masks a data strobe signal (1103) provided by memory; A blocking signal generating unit (15) that outputs a blocking signal (1501) including a blocking pulse (501) generated from the point in time when the DQS gating signal switches from a first level to a second level and continues for a predetermined time to start masking the data strobe signal; and A strobe blocker (16) configured to block the input of the data strobe signal to the DQS control unit while the blocking pulse is output, so that the DQS gating signal does not switch from the second level to the first level while the blocking pulse is output. including, SoC.

6. In Paragraph 5, The above blocking signal generating unit is, A delay unit (151) that outputs a delay signal (1502) that delays the above DQS gating signal by the above predetermined time; An inverter (152) that outputs an inverted signal obtained by inverting the above DQS gating signal; and An AND gate (153) that receives the above delay signal and the above inversion signal and outputs a blocking signal including the above blocking pulse; including, SoC.

7. In Paragraph 5, The above strobe blocking unit is, A second inverter (163) that outputs a second inverted signal in which the above-mentioned blocking signal is inverted; and A first AND gate (161) that receives the second inversion signal and the data strobe signal; Includes, Characterized in that the data strobe signal is not input to the DQS control unit, and instead of the data strobe signal, the output signal of the first AND gate is input to the DQS control unit. SoC.

8. In Paragraph 7, It further includes a DQS receiver (11) that provides the data strobe signal and the inverted data strobe signal received respectively from the first DQS channel and the second DQS channel connecting the SoC and the memory, and The above strobe blocking unit further includes a second AND gate (162) that receives the second inverted signal and the inverted data strobe signal, and The above inverted data strobe signal is not input to the DQS control unit, and instead of the inverted data strobe signal, the output signal of the second AND gate is input to the DQS control unit. SoC.

9. In Paragraph 5, A memory controller (20) that provides a read command (2001) to be transmitted to the memory by the above SoC; A DQS receiver (11) that provides the data strobe signal and the inverted data strobe signal received respectively from the first DQS channel and the second DQS channel connecting the SoC and the memory; Reading command confirmation unit (13); and A DQS clock driver (14) that generates an internal DQS clock (1401); Includes more, The above DQS control unit includes a DQS counter unit (122) that generates a read gate signal (1231) for masking the data strobe signal and provides a predetermined BL completion signal (1221) and a read completion signal (1222) indicating the end time of the gating pulse of the read gate signal. The above read command confirmation unit is configured to generate a subsequent read signal (1301) based on the BL completion signal and the read command, and The above DQS counter unit (122) is configured to generate the BL completion signal by counting the inverted data strobe signal, and to generate the readout completion signal using the inverted data strobe signal and the subsequent readout signal. The internal DQS clock (1401) has the same level as the data strobe signal during the time interval when the read gate signal (1231) is at a first level, and has a predetermined different level during the time interval when the read gate signal is at a second level. Data is read from the DQ received from the DQ channel connecting the above SoC and the above memory using the internal DQS clock (1401), and The inverted data strobe signal is configured to be blocked from being input to the DQS counter unit while the above blocking pulse is output, SoC.

10. In Paragraph 9, A second inverter (163) that outputs a second inverted signal in which the above-mentioned blocking signal is inverted; and It further includes a second AND gate (162) that receives the second inversion signal and the inversion data strobe signal, and Characterized in that the inverted data strobe signal is not input to the DQS counter, and instead of the inverted data strobe signal, the output signal of the second AND gate is input to the DQS counter. SoC.

11. In paragraph 5, the blocking pulse is generated by triggering the transition of the DQS gating signal from the first level to the second level, SoC.

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