Multiplexed stack identifiers for multi-die stacked memory

Abstract

A memory device comprises a base die and three or more memory dies arranged in a vertical stack above the base die. The memory device further comprises two sets of connections per external channel between the three or more memory dies and the base die, wherein multiplexing circuitry on the base die manages concurrent access to two of the three or more memory dies via the two sets of connections.

Description

Attorney Docket No.: 27170.1095 (L1048PCT)MULTIPLEXED STACK IDENTIFIERS FOR MULTI-DIE STACKED MEMORYBACKGROUND

[0001] Many computer systems use certain types of memory devices, such as dynamic random access memory' (DRAM) devices, as system memory' to temporarily store an operating system, critical applications, and data. With widespread use of multi-core processors, particularly, in servers and workstations, higher capacity and faster memory devices are needed to catch up with the computing power of these processors, thereby reducing the processor-memory' performance gap and allowing the applications to use the full processing speed of modern processors.

[0002] High bandwidth memory (HBM) is an advanced type of DRAM designed to deliver high bandwidth and power efficiency in a compact form factor for high-performance computing applications. Unlike traditional DRAM modules, HBM uses a 3D-stacked architecture where multiple DRAM dies are vertically stacked and interconnected using through-silicon vias (TSVs), which significantly reduces the physical footprint and improves data transfer speeds. HBM achieves this high bandwidth by incorporating multiple channels per die, such as 8 or more channels per die, to allow simultaneous data access across numerous pathways. The memory stacks are placedin close proximity to the processor (e.g., GPU, CPU, or Al accelerator) via an interposer, minimizing latency and enhancing energy efficiency. Due to these superior performance characteristics, HBM is widely used in applications like graphics processing, AI / ML workloads, and supercomputing, where massive data throughput and low power consumption are critical.

[0003] Future generations of HBM are expected to further increase the bandwidth to match the requirements of these computing applications. Increasing the bandwidth has associated tradeoffs, however, including increasing the number of input / output (I / O) pins on the memory device, which increases the DRAM package size and the number of pins required on the host system-on-chip (SoC), and increasing the I / O data rate and the complexity of the signaling protocol, which increases the power utilization.SUMMARY

[0004] The following is a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the disclosure. This summary is not an extensive overview of the disclosure. It is intended to neither identify key or critical elements of the disclosure, nor delineate any scope of the particular implementations of the disclosure or anyAttorney Docket No.: 27170.1095 (L1048PCT)scope of the claims. Its sole purpose is to present some concepts of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

[0005] In some aspects of the present disclosure, a memory device includes a base die and three or more memory dies (e.g., dynamic random access memory (DRAM) devices) arranged in a vertical stack above the base die. The three or more memory dies can be arranged into a plurality of stack identifier (ID) groups, each having a respective stack ID. The memory device further includes two sets of connections per host channel (e.g., through-silicon vias (TSVs)) between the three or more memory dies and the base die and multiplexing circuitry on the base die manages concurrent access to two of the three or more memory dies via the two sets of connections. The concurrent access to two of the three or more memory dies can be in response to two independent memory access commands. Each of the plurality of stack ID groups may be coupled to at least one of the two sets of connections and each of the two sets of connections is coupled to a respective subset of the plurality of stack ID groups.

[0006] In order to manage the concurrent access to two of the three or more memory dies via the two sets of connections, the multiplexing circuitry is to interleave first data read from a first memory die in a first stack ID group and received via a first set of connections with second data read from a second memory die in a second stack ID group and received via a second set of connections. The first set of connections and the second set of connections can be identified in view of a prior access operation performed on the memory device.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0008] FIG. 1 is a block diagram illustrating a computing system with a memory device including multiple stacked memory dies, according to an embodiment.

[0009] FIG. 2 is a block diagram illustrating a memory die stack configured for use with multiplexed stack identifiers, according to an embodiment.

[0010] FIG. 3 is a block diagram illustrating a memory die stack configured for use with multiplexed stack identifiers, according to an embodiment.

[0011] FIG. 4 is a block diagram illustrating a memory die stack with separate address and data connections and configured for use with multiplexed stack identifiers, according to an embodiment.Attorney Docket No.: 27170.1095 (L1048PCT)

[0012] FIG. 5 is a block diagram illustrating multiplexing circuitry' in a memory die stack configured for use with multiplexed stack identifiers, according to an embodiment.

[0013] FIG. 6 is a timing diagram illustrating operation of multi-die stacked memory using multiplexed stack identifiers, according to an embodiment.

[0014] FIG. 7 is a flow diagram illustrating a method of performing a data access operation in multi-die stacked memory using multiplexed stack identifiers, according to an embodiment.DETAILED DESCRIPTION

[0015] The following description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a good understanding of several embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that at least some embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known components or methods are not describedin detail or are presentedin simple block diagram format in order to avoid unnecessarily obscuring the present disclosure. Thus, the specific details set forth are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the scope of the present disclosure.

[0016] Aspects of the present disclosure include multiplexed stack identifiers for multi-die stacked memory, such as high bandwidth memory (HBM). As described above, a HBM module, or any multi-die stacked memory, can include a number of memory dies, which can be stacked vertically above a base die including various peripheral circuitry associated with operation of the memory module. The memory dies in the stack can be logically arranged into groups, where each group is identified by a corresponding unique stack identifier (stack ID). The number of stack ID groups and the number of memory dies within each group may be based on the number of external memory channels coupling the memory module to a memory controller and a number of internal channels per die. For example, if a memory module has 32 external memory channels, and each memory die has 8 internal channels per die, then the memory dies in the stack can be grouped into sets of 4 memory dies associated with each stack ID. Thus, in a 8 -die stack, there can be 2 stack IDs, and in a 12-die stack, there can be 3 stack IDs, for example. The stack IDs allow for logical addressing and accessibility of the memory dies within each respective group, where data and address busses are routed from the base die to the different memory channels within each stack ID group. In this manner, the bandwidth of the memory module can be increased byAttorney Docket No.: 27170.1095 (L1048PCT)providing access to additional resources (i.e., the memory channels within the different stack ID groups) that would not normally be accessible concurrently due to the fixed number of external memory channels in the memory module.

[0017] In order to allow for concurrent routing of separate data from a single channel to different stack ID groups, there would normally be a separate set of through silicon vias (TSVs) running through the stack from each stack ID group to the base die. In other words, there would be one set of TSVs per channel for each stack ID used in the memory module. Thus, as the number of memory dies in the HBM stack and the number of stack IDs increases, so does the number of sets of TSVs. An increased TSV count, however, takes up more space in the memory module, potentially reducing the overall storage capacity, and is more error prone, potentially hurting performance in the memory module.

[0018] Accordingly, embodiments of the present disclosure use multiplexed stack IDs to permit the use of a given number of stack ID groups in a memory die stack with a lesser number of sets of TSVs used to access the memory dies in the stack. For example, a memory module with a 12 die stack can utilize 3 stack IDs, but only 2 sets of TSVs, where the data and address signals are multiplexed across the 2 sets of TSVs to enable interleaved access to the memory channels in any 2 of the 3 stack ID groups in succession. This approach enables increased bandwidth in the memory module without requiring change to the stacked memory array core architecture. The number of TSVs is also fixed, regardless of the stack height, which saves resources and improves performance. Finally, the core operating frequency of the DRAM memory devices in the stacked memory array does not need to increase, despite the resulting increase (e.g., doubling) of the VO bandwidth in the memory module.Additional details with respect to the multiplexed stack IDs for multi-die stacked memory are provided below with respect to FIGs 1-6.

[0019] FIG. 1 is a block diagram illustrating a computing system 100 with a memory device 130 including multiple stacked memory dies, according to an embodiment. As illustrated, the memory device 130 includes a stack of memory dies 132, 134, 136, 138, arranged together in a single package. Each of memory dies 132, 134, 136, 138 can include an array of memory cells, such as DRAM or some other memory type, as well as associated circuitry and control logic. Depending on the embodiment, memory device 130 can have some other number of memory dies and / or some other type of memory.

[0020] Each of memory' dies 132, 134, 136, 138 may include a memory' core (e.g., memory array), a number of low-resistance metal layers, and an interface for communication with the memory controller 120. In one embodiment, the memory' die stack is coupled to aAttorney Docket No.: 27170.1095 (L1048PCT)packaging substrate that holds integrated circuit (IC) terminals via which the memory dies communicate with other devices, such as memory controller 120. The functionality of memory' controller 120 may be disposed on a separate Input / Output (170) die along with transmitter / receiver circuits that interface to the DRAM memory device 130. Such an I / O die may include other types of I / O interfaces, as well as one or more chiplet interfaces that communicate with one or more respective CPU chiplet dies. The I / O die and CPU chiplet dies may be co-packaged together and coupled to one-another via a silicon interposer. In one embodiment, the memory dies 132, 1.34, 136, 1.38 in the stack are physically separated from one another by non-conducting layers (e.g., a Silicon substrate). In one embodiment, the memory' dies 132, 134, 136, 138 in the stack are interconnected via a number of respective interconnections, such as through-silicon vias (TSVs), as will be described in more detail below7. Furthermore, in some embodiments, the memory controller 120 could be packaged together with the memory7device 130.

[0021] In one embodiment, memory device 130 communicates with a memory controller 120 via a memory bus 122. In one embodiment, the memory controller 120 includes logic circuitry7that controls memory access operations, such as read, write, and refresh operations, performed on memory device 130. The read and write operation s may be performed in response to requests received from a processor 110, or other host system, over bus 112. In one embodiment, computing system 100 includes one or more additional memory devices 130 also coupled to memory controller 120, via memory bus 122 or a different memory bus In one embodiment, the memory bus 122 includes a data bus and a command / address bus, each comprising a number of data and command / address lines, respectively. The command portion of the command / address bus conveys instructions such as read, write, and refresh commands issued by the memory controller 120. The address portion of the command / address bus may comprise a number of address lines carrying signals that identify the location of data in the memory7device 130.

[0022] In one embodiment, memory device 130 further includes multiplexing circuitry 140 which manages concurrent access to a subset of the memory dies 132, 134, 136, 138 via the respective sets of connections (e.g., TSVs). For example, the multiplexing circuitry 140 can interleave first data read from a first memory die in a first stack ID group and received via a first set of connections with second data read from a second memory die in a second stack ID group and received via a second set of connections. The first set of connections and the second set of connections can be identified in view of a prior access operation performed on the memory device. For example, control logic in the memoryAttorney Docket No.: 27170.1095 (L1048PCT)device can route data from a given memory die onto a respective set of connections that was not most recently used to perform a memory access operation on that same memory die. Once interleaved together, the data can be output (e.g., to memory controller 120) at approximately twice the data rate than if the data was read out from the respective memory die separately.

[0023] FIG. 2 is a block diagram illustrating a memory die stack 200 configured for use with multiplexed stack identifiers, according to an embodiment. In the illustrated embodiment, the stack 200 includes 12 memory dies, which are representative of any of memory dies 132-138. It should be understood that this is merely one example, and that in other embodiments, memory die stack 200 can include some other number of memory dies. The stack 200 is formed vertically above base die 202, which can include peripheral circuitry associated with operation of the memory device, including signal drivers, sense circuitry, data buffers, etc. In one embodiment, the base die 202 further includes multiplexing circuitry 140.

[0024] In one embodiment, each die has a number of internal channels (e.g., 8 internal channels). These internal channels may correspond to a subset of the external memory' channels coupling the memory device to an external device, such as memory' controller 120. For example, if there are 32 external memory' channels, one die may correspond the first 8 channels (i.e., channels 7-0), another die may correspond to the next 8 channels (i.e., channels 15-8), a third die may correspond to the next 8 channels (i.e., channels 23-16), and a fourth die may correspond to the remaining 8 channels (i.e., channels 31-24). Given that all of the external memory channels are then associated with only 4 memory dies, the memory device can utilize stack identifiers (IDs) to provide access to the additional memory dies in the stack 200 to increase the bandwidth of the memory device and provide more storage capacity.

[0025] In one embodiment, each set of four memory dies are logically grouped together and assigned a shared stack ID (i.e., SID0, SID1, SID2). Since each stack ID group includes 4 memory dies, a respective die in each stack ID group can be associated with each set of 8 external memory channels. In this manner, a memory access operation from one of the external memory channels can be directed to the respective memory die in any of the 3 stack ID groups by routing the correspon ding signals using the associated stack ID. In order to allow for concurrent routing of separate data from a single channel to the different stack ID groups, there would normally be a separate set of through silicon vias (TSVs) running from the base die 202 for each stackID used in the stack 200. By utilizing multiplexing circuitry 140 on the base die 202, however, a lesser number of sets of TSVs can be used.Attorney Docket No.: 27170.1095 (L1048PCT)

[0026] In the illustrated embodiment, there are only 2 sets of TSVs 210 and 220 used to route data and address signals from a single channel (e.g., channel 0) to the memory dies associated with any of stack IDS SID0, SID1, orSID2. Each set of TSVs 210 and 220, which may each include two or more individual TSVs, can be electronically coupled to a different subset of the stack ID groups. For example, as illustrated in FIG. 2, TSV set 210 is coupled to the memory dies in SID0 and in SID 1, while TSV set 220 is coupled to the memory dies in SID1 and SID2. It should be noted, that while FIG.2 illustrates the TSV sets 210 and 220 as being coupled to one memory die within the corresponding stack ID groups, it should be understood that there can be two corresponding TSV sets (not shown) for each remaining channel, and which thus may be coupled to different memory dies within the corresponding stack ID groups. With this configuration, multiplexing circuitry 140 can alternately transfer data from the memory dies on any two of the three stack ID groups in successive operations and interleave the retrieved data for output at a faster data rate than could be achieved when retrieving the data from two stack ID groups consecutively. For example, the multiplexing circuitry could (i) retrieve and interleave data from SID0 using TSV set 210 with data retrieved from SID1 using TSV set 220, (ii) retrieve and interleave data from SID0 using TSV set 210 with data retrieved from SID2 using TSV set 220, or (iii) retrieve and interleave data from SID1 using TSV set 210 with data retrieved from SID2 using TSV set 220. In other embodiments, the sets of TSVs may be connected to memory dies in the stack ID groups in a different configuration, which may alter the manner in which the data and address signals are transmitted.

[0027] FIG. 3 is a block diagram illustrating a memory die stack 300 configured for use with multiplexed stack identifiers, according to an embodiment. In the illustrated embodiment, the stack 300 includes 16 memory dies, which are representative of any of memory dies 132-138. It should be understood that this is merely one example, and that in other embodiments, memory' die stack 300 can include some other number of memory dies. The stack 300 is formed verti cally above base die 302, which can include peripheral circuitry associated with operation of the memory' device, including signal drivers, sense circuitry, data buffers, etc. In one embodiment, the base die 302 further includes multiplexing circuitry 140.

[0028] In one embodiment, each die has a number of internal channels (e.g., 8 internal channels). These internal channels may correspond to a subset of the external memory' channels coupling the memory device to an external device, such as memoiy controller 120. For example, if there are 32 external memory channels, one die may correspond the first 8 channels (i,e., channels 7-0), another die may correspond to the next 8Attorney Docket No.: 27170.1095 (L1048PCT)channels (i.e., channels 15-8), a third die may correspond to the next 8 channels (i.e., channels 23-16), and a fourth die may correspond to the remaining 8 channels (i.e., channels 31 -24). Given that all of the external memory channels are then associated with only 4 memory dies, the memory device can utilize stack identifiers (IDs) to provide access to the additional memory dies in the stack 200 to increase the bandwidth of the memory device and provide more storage capacity.

[0029] In one embodiment, each set of four memory dies are logically grouped together and assigned a shared stack ID (i.e., SIDO, SID1, SID2, SID3). Since each stack ID group includes 4 memory dies, a respective die in each stack ID group can be associated with each set of 8 external memory channels. In this manner, a memory access operation from one of the externa] memory channels can be directed to the respective memory die in any of the 4 stack ID groups by routing the corresponding signals using the associated stack ID. In order to allow for concurrent routing of separate data from a single channel to the different stack ID groups, there would normally be a separate set of through silicon vias (TSVs) running from the base die 302 for each stackID used in the stack 300. By utilizing multiplexing circuitry 140 on the base die 302, however, a lesser number of sets of TSVs can be used.

[0030] In the illustrated embodiment, there are only 2 sets of TSVs 310 and 320 used to route data and address signals from a single channel (e.g., channel 0) to the memory dies associated with any of stack IDS SIDO, SID1, SID2, orSID3. Each set of TSVs 310 and 320, which may each include two or more individual TSVs, can be electronically coupled to a different subset of the stack ID groups. For example, as illustrated in FIG. 3, TSV set 310 is coupled to the memory dies in SIDO, in SID1, and in SID2, while TSV set 320 is coupled to the memory dies in SID1, SID2, and SID3. It should be noted, that while FIG. 3 illustrates the TSV sets 310 and 320 as being coupled to one memory die within the corresponding stack ID groups, it should be understood that there can be two corresponding TSV sets (not shown) for each remaining channel and which thus may be coupled to different memory dies within the corresponding stack ID groups. With this configuration, multiplexing circuitry 140 can alternately transfer data from the memory dies on any two of the four stack ID groups in successive operations and interleave the retrieved data for output at a faster data rate than could be achieved when retrieving the data from two stack ID groups consecutively. For example, the multiplexing circuitry could (i) retrieve and interleave data from SIDO using TSV set 310 with data retrieved from SID1 using TSV set 320, (ii) retrieve and interleave data from SIDO using TSV set 310 with data retrieved from SID2 using TSV set 320, (iii) retrieve and interleave data from SIDO using TSV set 310 with data retrieved from SID3Attorney Docket No.: 27170.1095 (L1048PCT)using TSV set 320, (iv) retrieve and interleave data from SID1 using TSV set 310 with data retrieved from SID2 using TSV set 320, (v) retrieve and interleave data from SID1 using TSV set 310 with data retrieved from SID3 using TSV set 320, or (vi) retrieve and interleave data from SID2 using TSV set 310 with data retrieved from SID3 using TSV set 320. In other embodiments, the sets of TSVs may be connected to memory dies in the stack ID groups in a different configuration, which may alter the manner in which the data and address signals are transmitted.

[0031] FIG. 4 is a block diagram illustrating a memory die stack with separate address and data connections and configured for use with multiplexed stack identifiers, according to an embodiment. In the illustrated embodiment, the stack 400 includes 16 memory dies, which are representative of any of memory dies 132-138 It should be understood that this is merely one example, and that in other embodiments, memory die stack 400 can include some other number of memory dies. The stack 300 is formed vertically above base die 402, which can include peripheral circuitry associated with operation of the memory device, including signal drivers, sense circuitry, data buffers, etc In one embodiment, the base die 402 further includes multiplexing circuitry 140.

[0032] In one embodiment, each set of four memory dies in the stack 400 are logically grouped together and assigned a shared stack ID (i.e., SID0, SID1, SID2, SID3). Since each stack ID group includes 4 memory dies, a respective die in each stack ID group can be associated with each set of 8 external memory channels. In this manner, a memory access operation from one of the external memory channels can be directed to the respective memory die in any of the 4 stack ID groups by routing the corresponding signals using the associated stack ID.

[0033] In the illustrated embodiment, there are 4 sets of TSVs 410, 420, 430, and 440 used to route data and address signals from a single channel (e.g., channel 0) to the memory dies associated with any of stack IDS SID0, SID1, SID2, or SID3. Each set of TSVs 410, 420, 430, and 440, which may each include two or more individual TSVs, can be electronically coupled to a different subset of the stack ID groups. For example, as illustrated in FIG. 4, TSV sets 410 and 430 are coupled to the memory dies in SID0, in SID1, and in SID2, while TSV sets 420 and 440 are coupled to the memory dies in SID1, SID2, and SID3. It should be noted, that while FIG. 4 illustrates the TSV sets 310 and 320 as being coupled to one memory die within the corresponding stack ID groups, it should be understood that there can be four corresponding TSV sets (not shown) for each remaining channel, and which thus may be coupled to different memory dies within the corresponding stack ID groups. In thisAttorney Docket No.: 27170.1095 (L1048PCT)embodiment, the command / address (CA) signals maybe be sent to / from base die 402 on different TSV sets than the data (DQ) signals for a given channel. For example, data signals may be sent via TSV sets 410 and 420, while command / address signals are sent via TSV sets 430 and 440. The multiplexing circuitry 140 may thus separately multiplex signals sent via TSV sets 410 and 420 and multiplex signals sent via TSV sets 430 and 440 in order to reduce CA bandwidth limitations. For example, commands and address information can be sent concurrently to different SID groups using the TSV sets 430 and 440. This can be enabled on the host side with twice the CA bandwidth by doubling the number of I / O pins or doubling the CA transfer rate. In another embodiment, commands and address information can be broadcast to 2 SID groups using TSV sets 430 and 440 in order to effectively double the CA bandwidth.

[0034] FIG. 5 is a block diagram illustrating multiplexing circuitry in a memory die stack configured for use with multiplexed stack identifiers, according to an embodiment. As described above with respect to FIG. 2, the memory dies in a memory stack can be arranged into a number of stack ID groups (e.g., SID0, SID1, SID2). Those stack ID groups are represented on the right side of this architecture 500, and it can be understood that each stack ID group may include some number of memory' dies (e.g., four memory dies) based on the number of channels. While architecture 500 is based on a 12-die memory? stack, it should be understood appropriate modification could be made for a memory' stack including some other number of memory' dies. In order to perform a memory access operation, such as a read operation for purposes of illustration, corresponding to a given memory channel on the respective memory? dies in each of the stack ID groups, stack ID multiplexing implemented by multiplexing circuit 140 can be utilized. The architecture 500 illustrates one memory die corresponding to a given channel in each of three stack ID groups. TSV sets 510 and 520 allow for separate data to be read concurrently (i.e., at least partially overlapping in time) from two of those memory dies and corresponding to the same channel. While 256 bits of data may be read from a memory die at a time (e.g., at a rate 400 MHz), multiple bank groups within each die allows a data rate increase (e.g., to 800 MHz). The access delay associated with performing a read operation is largely attributable to setup time and other overhead operations associated with using shared resources, and so by using multiple bank groups within a given die, the throughput can be improved by overlapping accesses to separate resources.

[0035] As shown in the architecture 500, one memory? die corresponding to a given channel in each of the stack ID groups is selectively coupled to one or more of the TSV setsAttorney Docket No.: 27170.1095 (L1048PCT)510 and 520. For example, the memory dies of SIDO and SID1 are coupled to TSV set 510 and the memory dies of SID1 and SID2 are coupled to TSV set 520 TSV enable circuitry 512 and 522 controls the coupling and, in the case where a single TSV set is coupled to the memory dies in more than one stack ID group, ensures that data and address signals are only sent to or received from the memory die in one of those stack ID groups at a time. Thus, as part of successive memory access operations, 256 bits can be read from the memory dies in each of two different stack ID groups and transferred in two data streams to the base die 502 via TSV sets 510 and 520 concurrently (i.e., at least partially overlapping in time). Within the memory dies of each stack ID group, an internal multiplexer selectively controls access to the different bank groups. At base die 502, multiplexing circuit 140 (e.g., including a multiplexer) can alternately sample the two data streams and interleave the data (e.g. forming 512 bits) at the output. For example, each SID provides 256 bits at 800 MHz (i.e., 25.6 GB / s) and the multiplexing circuit 140 interleaves the data to provide 512 bits at 800 MHz (i.e., 51.2 GB / s). Physical layer (PHY) component 536 can serialize the output data (e.g., into 32 bit chunks) which can be sent to a requestor, such as a memory controller, at faster data transfer rate (e.g., 12.8 Gbps).

[0036] FIG. 6 is a timing diagram 600 illustrating operation of multi-die stacked memory using multiplexed stack identifiers, according to an embodiment. In one embodiment, there is a shared command / address (CA) bus 610 on which multiple independent command directed to different stack IDs are received, according to clock signal 620. For example, two activate (ACT) commands can be received in succession (e.g., from memory controller 120), which are directed to memory dies in SIDO and SID1, respectively. Once the memory dies are activated, individual read (RD) commands directed to the memory dies in SIDO and SID1 may be received in succession. For example, if the read command directed to SIDO is received first, followed by the read command directed to SID1, control logic in the memory device can begin execution of the first read command on a first memory die in SIDO and subsequently begin execution of the second read command on a second memory die in SID1. That data can be read out concurrently from the memory dies on respective DQ buses 630, which may correspond to the separate sets of TSVs described herein. For example, the data may be read at least partially overlapping in time, but offset by one cycle of clock signal 620, as illustrated. In another embodiment, separate CA busses can be used as illustrated in FIG. 4, or the commands and address information can be broadcast to multiple stack ID groups to maximize the overlapping potential of the DQ bus.Attorney Docket No.: 27170.1095 (L1048PCT)

[0037] As described above with respect to FIG. 5, the separate data streams can be interleaved at multiplexing circuitry 140 on the base die 502. This is illustrated in timing diagram 600 of FIG. 6 by data stream 640. As shown, data stream 640 can include alternating portions of data from the individual data streams read from SID0 and SID1. By interleaving the data in this manner, the data output speed can be increased, as indicated by clock signal 650. In one embodiment, data stream 640 represents the serialized output stream from PHY component 536, as shown in FIG. 5. Although timing diagram 600 illustrates read operations, it should be understood that similar techniques can be utilized to perform other types of memory access operations including write operations, for example.

[0038] FIG. 7 is a flow diagram illustrating a method of performing a data access operation in multi-die stacked memory using multiplexed stack identifiers, according to an embodiment. The method 700 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device to perform hardware simulation), or a combination thereof. In one embodiment, the method 700 is performed by control logic of memory controller 102. In another embodiment, the method 400 is performed by a control logic within memory device 130, such as by control logic on the base die that controls operation of multiplexing circuitry 140.

[0039] At block 710, the processing logic receives a request to access data stored at a memory device, such as memory device 130. In one embodiment, the request is sent by a host system and received by memory controller 120. Depending on the embodiment, the request can include a read request to read data stored on the memory device or a write request to program data to the memory device. In one embodiment, the request identifies particular data stored in a multi-die memory stack, such as one of stacks 200, 300, or 400, which may include one or more chunks of data. For example, the requested data may be associated with a given channel.

[0040] At block 720, the processing logic routes the request to respective memory dies in different stack ID groups. As described above, the multi-die memory stack can include a number of memory dies, which can be arranged into stack ID groups. For example, there may be three stack ID groups, each including four memory dies. Each memory channel is associated with a respective die in each of the stack ID groups. Accordingly, in the case of a read request, the requested data associated with a given channel may be spread across those respective dies in the separate stack ID groups. Thus, in some embodiments, commands andAttorney Docket No.: 27170.1095 (L1048PCT)address information, including the memory access request, can be sent concurrently to the different stack ID groups using the TSV sets 430 and 440.

[0041] At block 730, the processing logic reads separate data from the respective memory dies in different stack ID groups concurrently using two sets of connections. For example, TSV sets 510 and 520 allow for separate data corresponding to the same channel to be read concurrently (i.e., at least partially overlapping in time) from two of the three memory' dies in the multi-die stack.

[0042] At block 740, the processing logic interleaves the separate data for output to the requestor. For example, multiplexing circuitry 140 can alternately sample the two data streams from TSV sets 510 and 520 and interleave the data (e.g. forming 512 bits) at the output. For example, each SID provides 256 bits at 800 MHz (i.e., 25.6 GB / s) and the multiplexing circuit 140 interleaves the data to provide 512 bits at 800 MHz (i.e., 51.2 GB / s). A physical layer (PHY) component 536 can serialize the output data (e.g., into 32 bit chunks) which can be sent to the requestor, such as memory controller 120.

[0043] Although the operations of the methods herein are shown and described in a particular order, the order of the operations of each method may be altered so that certain operations may be performed in an inverse order or so that certain operation may be performed, at least in part, concurrently with other operations. In certain implementations, instructions or sub-operations of distinct operations may be in an intermittent and / or alternating manner.

[0044] It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other implementations will be apparent to those skilled in the art upon reading and understanding the above description. The scope of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0045] In the above description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the aspects of the present disclosure may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present disclosure.

[0046] Some portions of the detailed descriptions above are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work toAttorney Docket No.: 27170.1095 (L1048PCT)others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0047] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as “receiving,” “determining,” “selecting,” “storing,” “setting,” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

[0048] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus maybe specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0049] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear as set forth in the description. In addition, aspects of the present disclosure are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.Attorney Docket No.: 27170.1095 (L1048PCT)

[0050] Aspects of the present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any procedure for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.).

Claims

Attorney Docket No.: 27170.1095 (L1048PCT)CLAIMSWhat is claimed is:

1. A memory device comprising:a base die;three or more memory dies arranged in a vertical stack above the base die; and two sets of connections between the three or more memory dies and the base die, wherein multiplexing circuitry on the base die manages concurrent access to two of the three or more memory dies via the two sets of connections.

2. The memory device of claim 1, wherein the three or more memory dies are arranged into a plurality of stack identifier (ID) groups, each having a respective stack ID.

3. The memory device of claim 2, wherein each of the plurality of stack ID groups is coupled to at least one of the two sets of connections.

4. The memory device of claim 2, wherein each of the two sets of connections is coupled to a respective subset of the plurality of stack ID groups.

5. The memory device of claim 2, wherein to manage the concurrent access to two of the three or more memory dies via the two sets of connections, the multiplexing circuitry is to interleave first data read from a first memory die in a first stack ID group and received via a first set of connections with second data read from a second memory die in a second stack ID group and received via a second set of connections.

6. The memory device of claim 5, where the first set of connections and the second set of connections are identified in view of a prior access operation performed on the memory device.

7. The memory device of claim 1, wherein the concurrent access to two of the three or more memory dies is in response to two independent memory access commands.

8. The memory device of claim 1, wherein the three or more memory dies comprise dynamic random access memory (DRAM) devices.Attorney Docket No.: 27170.1095 (L1048PCT)9. The memory device of claim 1, wherein the two sets of connections comprise through-silicon vias (TSVs).

10. A memory device comprising:a base die;a plurality of memory dies disposed in a vertical stack above the base die and logically arranged into a plurality of stack identifier (ID) groups, each having a respective stack ID; anda plurality of sets of connections between the plurality of memory dies and the base die, wherein multiplexing circuitry on the base die manages concurrent access to a subset of the plurality of memory dies via the plurality of sets of connections.

11. The memory device of claim 10, wherein a number of the sets of connections is less than a number of the stack ID groups.

12. The memory device of claim 10, wherein to manage the concurrent access to the subset of the plurality of memory dies via the plurality of sets of connections, the multiplexing circuitry is to interleave first data read from a first memory die in a first stack ID group and received via a first set of connections with second data read from a second memory die in a second stack ID group and received via a second set of connections.

13. The memory device of claim 12, where the first set of connections and the second set of connections are identified in view of a prior access operation performed on the memory device.

14. The memory device of claim 10, wherein the concurrent access to the subset of the plurality of memory dies is in response to two independent memory access commands.

15. A memory device comprising:three or more memory dies arranged in a vertical stack; andtwo sets of connections coupled to the three or more memory dies, the two sets of connections to provide concurrent access to two of the three or more memory dies via the two sets of connections.Attorney Docket No.: 27170.1095 (L1048PCT)16. The memory device of claim 15, wherein the three or more memory dies are arranged into a plurality of stack identifier (ID) groups, each having a respective stack ID.

17. The memory device of claim 16, wherein to provide the concurrent access to two of the three or more memory dies via the two sets of connections, multiplexing circuitry is to interleave first data read from a first memory die in a first stack ID group and received via a first set of connections with second data read from a second memory die in a second stack ID group and received via a second set of connections.

18. The memory device of claim 17, where the first set of connections and the second set of connections are identified in view of a prior access operation performed on the memory device.

19. The memory device of claim 15, wherein the concurrent access to two of the three or more memory dies is in response to two independent memory access commands.

20. The memory device of claim 15, wherein the three or more memory dies comprise dynamic random access memory (DRAM) devices.

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