Boron passivation for gate oxide in transistors

Abstract

Disclosed herein is a method to create a transistor such as a boron-passivated interface in a silicon carbide power metal oxide semiconductor field effect transistors (MOSFET). The method includes passivating a top interface of a substrate, such as a silicon carbide substrate, with a diborane treatment, depositing an oxide cap layer on the boron-passivated interface, performing a nitridation of the oxide cap layer, and depositing a gate oxide layer on the nitrided cap layer. In another aspect, a boron-passivated interface in a transistor is described.

Description

Docket No. 1508.44023514WOBORON PASSIVATION FOR GATE OXIDE IN TRANSISTORSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to previously filed United States Provisional Patent Application Serial Number 63 / 734,477, filed December 16, 2024, entitled “Boron Passivation for Gate Oxide in Transistors,” which is hereby incorporated by reference in its entirety.FIELD OF THE DISCLOSURE

[0002] The embodiments of the present disclosure relate to methods and systems to fabricate transistors.BACKGROUND

[0003] A power metal oxide semiconductor field effect transistor (MOSFET) is a specific type of transistor designed to handle significant power levels. Compared to other power semiconductor devices, a MOSFET's main advantages are high switching speed and good efficiency at low voltages. A MOSFET electrically isolates a gate from the source. Transistors such as MOSFETs typically have a substrate that may be fabricated from silicon, silicon carbide (SiC), or other materials. The SiC MOSFETs isolate the gate with a layer of SiC to allow high switching speeds. Because the SiC power MOSFET has less on-resistance than a Si MOSFET, the SiC power MOSFET can operate over a wide range of blocking voltage with lower conduction and switching loss.

[0004] There remains a need in the art for processes that provide high n-channel mobility in transistors, such as SiC power MOSFETs, and further reduce on-resistance while preventing threshold voltage (Vth) instability.Docket No. 1508.44023514WOBRIEF SUMMARY

[0005] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter. This Summary is not intended as an aid in determining the scope of the claimed subject matter. This Summary is merely exemplary of the numerous and varied embodiments. Mention of one or more representative features of a given embodiment is likewise exemplary. Such an embodiment can typically exist with or without the feature(s) mentioned; likewise, those features can be applied to other embodiments of the presently disclosed subject matter, whether listed in this summary or not. To avoid excessive repetition, this Summary does not list or suggest all possible combinations of such features.

[0006] In one aspect, a method to create a boron-passivated interface in a transistor, such as a power metal oxide semiconductor field effect transistors (MOSFET), is described. The method includes passivating a top interface of a semiconductor substrate, such as a silicon carbide (SiC) substrate, with a diborane treatment. The method includes depositing an oxide cap layer on the boron- passivated interface, performing a nitridation of the oxide cap layer, and depositing a gate oxide (GOx) layer on the nitrided cap layer. The method may also include performing a post-oxidation annealing of the transistor.

[0007] In another aspect, the nitridation is performed by a decoupled plasma nitridation. In another aspect, the method may also include performing a surface pretreatment of the top interface of the SiC substrate. In another aspect, the diborane treatment is performed by one or more of a sub- atmospheric chemical vapor deposition (SACVD) process or an atmospheric pressure chemical vapor deposition (ATM CVD) process. In another aspect, the diborane treatment deposits a thin layer of boron that is 1-3 nm thick.Docket No. 1508.44023514WO

[0008] In another aspect, depositing an oxide cap layer is performed using one or more of a SACVD process, a tetraethyl orthosilicated (TEOS) deposition process, a low pressure chemical vapor deposition (LPCVD), a silicon dioxide (SiO2) deposition process, or an atomic layer deposition (ALD) process. In another aspect, depositing a GOx layer on the nitrided cap layer is performed using one or more of a SACVD process, a LPCVD process, or an ALD process.

[0009] In another aspect, the nitridation further includes a post-nitridation annealing. In another aspect, the nitridation further includes a rapid thermal processing. In another aspect, the surface pretreatment is an in-situ H2 cleaning to remove residual native oxides. In another aspect, a temperature range for the diborane treatment is between 400 and 1200 degrees C.

[0010] In one aspect, a SiC power MOSFET includes a SiC substrate, a thin layer of boron creating a boron-passivated interface on a top surface of the SiC substrate, a nitrided oxide cap layer on the boron-passivated interface, and GOx layer on the nitrided cap layer. In another aspect, the thin layer of boron is 1-3 nm thick. In another aspect, the nitrided oxide cap layer is 30 to 50 angstroms thick. In another aspect, the nitrided oxide cap layer is configured to prevent boron diffusion into the GOx layer.

[0011] Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0012] To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure number in which that element is first introduced. The accompanying drawings illustrate exemplary approaches of the disclosure, including the practical application of the principles thereof, as follows:

[0013] FIG. l is a block flow diagram of a method to provide a boron passivation interface for aGOx in a MOSFET in accordance with one embodiment.Docket No. 1508.44023514WO

[0014] FIG. 2 illustrates a MOSFET with a boron passivated interface in accordance with one embodiment.

[0015] FIG. 3 shows a schematic of an example apparatus / system according to implementations of the disclosure.DETAILED DESCRIPTION

[0016] Processes in accordance with the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, where various embodiments are shown. The processes may be embodied in many different forms and are not to be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so the disclosure will be thorough and complete, and will fully convey the scope of the methods to those skilled in the art.

[0017] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the presently disclosed subject matter. While the following terms are believed to be well understood by one of ordinary skill in the art, the following definitions are set forth to facilitate explanation of the presently disclosed subject matter.

[0018] All technical and scientific terms used herein, unless otherwise defined below, are intended to have the same meaning as commonly understood by one of ordinary skill in the art. References to techniques employed herein are intended to refer to the techniques as commonly understood in the art, including variations on those techniques or substitutions of equivalent techniques that would be apparent to one of skill in the art. While the following terms are believed to be well understood by one of ordinary skill in the art, the following definitions are set forth to facilitate explanation of the presently disclosed subject matter.

[0019] In describing the presently disclosed subject matter, it will be understood that a number of techniques and steps are disclosed. Each of these has individual benefit and each can also be used inDocket No. 1508.44023514WO conjunction with one or more, or in some cases all, of the other disclosed techniques. Accordingly, for the sake of clarity, this description will refrain from repeating every possible combination of the individual steps in an unnecessary fashion. Nevertheless, the specification and claims should be read with the understanding that such combinations are entirely within the scope of the technology and the claims.

[0020] A silicon carbide (SiC) power MOSFET is constructed using a boron-passivated interface between the SiC substrate and the Gate Oxide (GOx). The technologies described herein allow the boron layer to include a deposition of 1-3 nm of pure boron. An integrated oxynitride capping layer over the boron layer prevents boron diffusion from the interface into the GOx layer during high temperature post-oxidation annealing (POA).

[0021] FIG. 1 is a block flow diagram of a method 100 to provide a boron passivation interface for a GOx in a MOSFET in accordance with one embodiment. Although the example method 100 depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the method 100. In other examples, different components of an example device or system that implements the method 100 may perform functions at substantially the same time or in a specific sequence.

[0022] In block 102, the method 100 performs a surface pretreatment of a SiC substrate. The surface pretreatment may be an in-situ Fb cleaning to remove residual native oxides. For example, a pretreatment such as an in-situ H2 plasma cleaning is a process that removes impurities and contaminants from surfaces using an energetic plasma. This process is typically used to clean the surfaces of substrates before deposition or other processes are performed. Any other suitable cleaning or surface preparation process may be performed to prepare the substrate for the deposition. For example, an ex-situ surface preparation may be used in certain example processes.Docket No. 1508.44023514WO

[0023] In some examples, the pretreatment of the surface may include a nitridation pretreatment.The nitridation can be performed using any of a variety of processes including, but not limited to, a thermal or plasma deposition and / or doping / treatment. In some embodiments, for example, the nitridation pre-treatment can achieved by a plasma nitridation treatment using N2 at temperatures within a range between room temperature (e.g., between about 15 °C and about 25 °C) and about 400 °C or higher. In other embodiments, the nitridation pre-treatment can be achieved using a rapid thermal nitridation treatment using ammonia (NH3), such as at temperatures up to about 1100 °C or higher (e.g., at temperatures up to about 1350 °C).

[0024] In block 104, the method 100 includes passivating the SiC interface with a diborane treatment on the oxide-free SiC interface. Conventional techniques and processes have indicated that boron inclusion at the SiC / GOx interface enhances n-channel mobility. This process is referred to as boron-passivation or b-passivation. In certain examples, the boron-passivation increases n-channel mobility by a factor of 3 to 6 times that of systems using conventional interface oxidation / nitridation processes.

[0025] In conventional SiC power MOSFETs, different types of passivation or no passivation is used. In one conventional MOSFET, a furnace oxide is deposited onto a SiC substrate via furnace oxidation. This furnace oxidation may be followed by a nitric oxide (NO) post-oxidation annealing (POA) process. In another example, the SiC substrate may be pretreated with H2 and then have an in- situ N2 passivation via rapid thermal anneal (RTA) process or a decoupled plasma nitridation (DPN) process. The GOx is then deposited by a process such as low pressure chemical vapor deposition (LPCVD) SiO2 or a SiO2 atomic layer deposition (ALD) process. The MOSFET may then receive oxide densification via furnace POA in N2 or another type of annealing process.

[0026] Other conventional systems use boron to passivate the interface. In conventional boron- passivation systems, the boron is deposited at the SiC interface by thermal treatments in a furnaceDocket No. 1508.44023514WO with planar diffusion after GOx formation. This process may be referred to as post oxidationAnnealing (POA). In POA, boron atoms diffuse from an external source through the GOx and accumulate at the SiC interface. However, some amount of boron is incorporated throughout the GOx layer. This dispersion of the boron is unsuitable for most commercial devices because the boron incorporated in the GOx layer causes threshold voltage (Vth) instability and problems with oxide reliability. This process is unsuitable for most commercial devices because of the increase in the Vth instability.

[0027] In other conventional systems, a thin Boron Diffusion Layer (BDL) has been formed by spin coating a boron-containing solution. The BDL may be formed at the SiC Interface before the GOx formation occurs. However, the layer of pure boron may diffuse from the interface into the GOx during the high temperature POA process. Because of this diffusion, these conventional processes are not suitable for the fabrication flows of SiC power MOSFETs.

[0028] Because of these inherent issues, the method 100 first provides a boron passivation via diborane treatment on the oxide-free SiC interface or by any other suitable deposition process. The thin BDL of the method 100 may be less than 10 nm, such as 1-3 nm. In other examples, different layer depths of pure boron may be used, such as 0.5-3nm, l-5nm, 3-5nm, 1-lOnm, or 3-10nm.

[0029] The boron-passivated interface is illustrated in greater detail in FIG. 2. FIG. 2 illustrates a MOSFET 200 with a boron-passivated interface 204 in accordance with one embodiment.

[0030] In the illustration, the MOSFET 200 has a SiC substrate 202. The boron-passivated interface 204 is at a top surface of the SiC substrate 202.

[0031] The boron-passivated interface 204 may be deposited by any suitable diborane treatment. For example, the boron may be deposited by a sub-atmospheric chemical vapor deposition (SACVD) process or an atmospheric pressure chemical vapor deposition (ATM CVD) process. Chemical vapor deposition (CVD) is generally a method to deposit nanostructures or nanomaterials in solid form ontoDocket No. 1508.44023514WO a specific target or sample using vapor or gases in an inert atmosphere at controlled temperature and pressure. CVD processes are typically used in the semiconductor industry to produce thin films, such as the thin layer of boron for the interface. CVD provides processes that allow for the deposition of metallic, ceramic, and semiconducting thin films by depositing a solid onto a heated surface by a chemical reaction from the vapor or gas phase. Typically a gas, such as hydrogen or argon is used as a carrier gas. In other examples, such as processes using Diborane, Nitrogen can also be used as a carrier gas.

[0032] A SACVD process is configured to perform a CVD operation at pressures that are below atmospheric pressure, while ATM CVD operates at atmospheric pressures. A temperature range for the diborane treatment may be 400-1200°C, and a pressure range may be 40Torr-ATM.

[0033] Returning to FIG. 1, in block 106, the method 100 includes depositing an undoped silicate glass (USG) oxide cap layer on the SiC interface.

[0034] The USG oxide deposition for the oxide cap layer may be performed by any suitable process. For example, the oxide may be deposited by a SACVD process, a tetraethyl orthosilicated (TEOS) deposition process, a low pressure chemical vapor deposition (LPCVD), a silicon dioxide (SiO2) deposition process, or an atomic layer deposition (ALD) process.

[0035] In an example, the oxide cap layer may be 30 to 50 angstroms. In other examples different thicknesses may be used, such as 20 to 40 angstroms, 20 to 60 angstroms, or 40 to 60 angstroms.

[0036] In block 108, the method 100 includes performing a nitridation of the oxide cap layer at block 108. The nitridation of the oxide cap layer may be performed using a decoupled plasma nitridation (DPN) process. Typically, DPN is implemented using inductive coupling plasma to generate ions with lower kinetic energy for minimizing the carrier mobility degradation.Docket No. 1508.44023514WO

[0037] The DPN process may be followed by a post-nitridation annealing (PNA) process.Following the DPN with a PNA process improves the nitrogen distribution in the nitrided oxide cap layer and enhances the diffusion barrier properties. In another example, the DPN process may be followed by rapid thermal annealing (RTA) of the nitrided oxide cap layer 206. In RTA, the method 100 heats the nitrided oxide cap layer to high temperatures, such as 1,000 degrees C for a short period of time, such as 3 to 60 seconds.

[0038] In FIG. 2, the nitrided oxide cap layer 206 is illustrated covering the boron-passivated interface 204. The nitrided oxide cap layer 206 is between the GOx layer 208 and the boron- passivated interface 204.

[0039] Returning to FIG. 1, in block 110, the method 100 includes the depositing of a GOx layer 208 layer. The GOx layer 208 may be deposited by any suitable deposition process, such as SACVD, LPCVD, or ALD.

[0040] In an example, the GOx layer 208 may be 350 to 400 angstroms. In other examples different thicknesses may be used, such as 300 to 350 angstroms, 400 to 500 angstroms, or 300 to 500 angstroms.

[0041] In block 112, the method 100 includes performing post-oxidation annealing (POA). The POA provides oxide densification in the MOSFET 200. Different POA settings, such as the temperature, duration, and gas flow rates, may be used depending on the type and design of the GOx. For example, the process may perform the POA in N2 or use any other type of annealing, such as ultra-high temperature annealing or RTA. Without the nitrided oxide cap layer described herein, the boron in the boron-passivated interface 204 may diffuse into the Gox layer 208 during the POA process.

[0042] As illustrated in FIG. 2, the GOx layer 208 is deposited on top of the nitrided oxide cap layer 206.Docket No. 1508.44023514WO

[0043] The method 100, as described in FIG. 1, utilizes two separate technologies to achieve the effective boron-passivation. First, the pure boron layer was formed by CVD as previously described for applications such as radiation and electron detectors on silicon. This method of boron deposition is combined with a process for decoupled DPN and PNA for boron diffusion suppression in dielectrics. Together these processes allow deposition of a 1-3 nm of pure boron at the SiC interface. The integration of the oxynitride capping layer on top of the pure boron layer prevents boron diffusion from the interface into the GOx layer during the high temperature POA. This allows for high n- channel mobility in SiC power MOSFETs 200 while preventing Vth instability.

[0044] FIG. 3 shows a schematic of an example apparatus / system 300 according to implementations of the disclosure. In some implementations, the system 300 may be a cluster tool operable to perform processes necessary to form the MOSFET 200 described herein. Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc., located in Santa Clara, California. It is contemplated that other processing systems (including those from other manufacturers) may be adapted to benefit from aspects described herein.

[0045] As shown, the system 300 may include at least one central transfer station / chamber 302 and one or more robots 304 within the transfer station / chamber 302, wherein the robot 304 is operable to move a robot blade and a wafer to and from each of a plurality of processing chambers 310A - 310N connected with, or positioned adjacent to, the transfer station / chamber 302. In some implementations, the processing chambers 310A - 310N may support ion implantation, material deposition, material etching, thermal processing, and others. The particular arrangement of process chambers and components can be varied depending on the cluster tool and should not be taken as limiting the scope of the disclosure. In another example, one or more of the chambers may includeDocket No. 1508.44023514WO multiple process regions within a same chamber, which permits a common supply of gases, common pressure control, and common process gas exhaust / pumping. Modular design of the system enables rapid conversion from one configuration to any other.

[0046] In some implementations, processing chamber 310A may be a deposition chamber operable to deposit one or more layers or features of the stack of layers on a SiC substrate 202 of the MOSFET 200. For example, the processing chamber 310A may include a material deposition tool operable to form the boron-passivation interface 204. The material deposition tool may be still further operable to form the GOx layer 208 layer, a nitrided oxide cap layer 206, or any other suitable layer. Although non-limiting, the deposition chamber may include one or more of an atomic layer deposition chamber, a plasma enhanced atomic layer deposition chamber, a chemical vapor deposition chamber, a plasma enhanced chemical vapor deposition chamber, or a physical deposition. The deposition chamber may further be an epitaxial growth deposition chamber or any suitable deposition chamber, such as SACVD, LPCVD, or ALD.

[0047] In some implementations, processing chamber 310B may be an etch chamber operable to form one or more trenches. In some implementations, processing chamber 310B may be used for wet and / or dry etch processes.

[0048] In some implementations, processing chamber 310C may be operable to perform a nitridation process on the MOSFET 200, while processing chamber 310D may be operable to perform one or more thermal processes, such as an annealing or a rapid thermal processing.

[0049] A system controller 320 is in communication with the robot 304, the transfer station / chamber 302, and the plurality of processing chambers 310A - 310N. The system controller 320 can be any suitable component that can control the processing chambers 310A - 310N and robot(s) 304, as well as the processes occurring within the process chambers 310A - 310N. ForDocket No. 1508.44023514WO example, the system controller 320 can be a computer including a central processor 322, memory 324, suitable circuits / logic / instructions, and storage.

[0050] Processes or instructions may generally be stored in the memory 324 of the system controller 320 as a software routine that, when executed by the processor 322, causes the processing chambers 310A - 310N to perform processes of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown) that is remotely located from the hardware being controlled by the processor 322. Some or all of the method(s) of the present disclosure may also be performed in hardware. As such, the process may be implemented in software and executed using a computer system, in hardware as, e.g., an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routine, when executed by the processor 322, transforms the general-purpose computer into a specific purpose computer (controller) that controls the chamber operation such that the processes are performed.

[0051] For the sake of convenience and clarity, terms such as “top,” “bottom,” “upper,” “lower,” “vertical,” ‘horizontal,” “lateral,” and “longitudinal” will be used herein to describe the relative placement and orientation of components and their constituent parts as appearing in the figures. The terminology will include the words specifically mentioned, derivatives thereof, and words of similar import.

[0052] As used herein, an element or operation recited in the singular and proceeded with the word “a” or “an” is to be understood as including plural elements or operations, until such exclusion is explicitly recited. Furthermore, references to "one implementation" of the present disclosure are not intended as limiting. Additional implementations may also incorporate the recited features.

[0053] Furthermore, the terms “substantial” or “substantially,” as well as the terms “approximate” or “approximately,” can be used interchangeably in some implementations, and can be described usingDocket No. 1508.44023514WO any relative measures acceptable by one of ordinary skill in the art. For example, these terms can serve as a comparison to a reference parameter, to indicate a deviation capable of providing the intended function. Although nondimiting, the deviation from the reference parameter can be, for example, in an amount of less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, and so on.

[0054] Still furthermore, one of ordinary skill will understand when an element such as a layer, region, or substrate is referred to as being formed on, deposited on, or disposed “on,” “over” or “atop” another element, the element can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on,” “directly over” or “directly atop” another element, no intervening elements are present.

[0055] The present disclosure is not to be limited in scope by the specific implementations described herein. Indeed, other various implementations of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other implementations and modifications are intended to fall within the scope of the present disclosure. Furthermore, the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose. Those of ordinary skill in the art will recognize the usefulness is not limited thereto and the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Thus, the claims set forth below are to be construed in view of the full breadth and spirit of the present disclosure as described herein.

Claims

1. Docket No. 1508.44023514WOCLAIMSWhat is claimed is:

1. A method to fabricate a transistor, comprising: passivating a top interface of a semiconductor substrate with boron; depositing an oxide cap layer on the boron-passivated interface; performing a nitridation of the oxide cap layer; and depositing a gate oxide layer on the nitrided oxide cap layer.

2. The method of claim 1, further comprising performing a post-oxidation annealing of the transistor after the depositing of the gate oxide layer.

3. The method of claim 1, wherein the nitridation is performed by a decoupled plasma nitridation.

4. The method of claim 3, wherein the nitridation further comprises a post-nitridation annealing.

5. The method of claim 3, wherein the nitridation further comprises a rapid thermal processing.

6. The method of claim 1, further comprising performing a surface pretreatment of the top interface of the semiconductor substrate before the passivating with boron.

7. The method of claim 6, wherein the surface pretreatment is an in-situ H2 cleaning to remove residual native oxides.

8. The method of claim 6, wherein the surface pretreatment is a nitridation of the top interface of the semiconductor substrate.

9. The method of claim 1, wherein passivating the top interface with the boron is performed by depositing the boron using one or more of a sub-atmospheric chemical vapor deposition process or an atmospheric pressure chemical vapor deposition process.Docket No. 1508.44023514WO10. The method of claim 9, wherein the semiconductor substrate is a silicon carbide substrate.

11. The method of claim 1, wherein passivating the top interface with the boron comprises depositing a thin layer of boron that is 1-3 nm thick.

12. The method of claim 1, wherein depositing the oxide cap layer is performed using one or more of a sub-atmospheric chemical vapor deposition process, a tetraethyl orthosilicated deposition process, a low pressure chemical vapor deposition, a silicon dioxide deposition process, or an atomic layer deposition process.

13. The method of claim 1, wherein depositing the gate oxide layer on the nitrided oxide cap layer is performed using one or more of a sub-atmospheric chemical vapor deposition process, a low pressure chemical vapor deposition process, or an atomic layer deposition process.

14. The method of claim 1, wherein the transistor is a power metal oxide semiconductor field effect transistor.

15. A transistor, comprising: a semiconductor substrate; a boron-passivated interface on a top surface of the semiconductor substrate; a nitrided oxide cap layer on the boron-passivated interface; and a gate oxide layer on the nitrided oxide cap layer.

16. The transistor of claim 15, wherein the boron-passivated interface comprises a layer of boron that is 1-3 nm thick.

17. The transistor of claim 15, wherein the nitrided oxide cap layer is 30 to 50 angstroms thick.

18. The transistor of claim 15, wherein the nitrided oxide cap layer is configured to prevent boron diffusion into the gate oxide layer.Docket No. 1508.44023514WO19. A method to fabricate a transistor, comprising: passivating a top interface of a semiconductor substrate with a diborane treatment; depositing a nitrided oxide cap layer on the boron-passivated interface; depositing a gate oxide layer on the nitrided oxide cap layer; and performing a post-oxidation annealing of the transistor.

20. The method of claim 19, wherein depositing the nitrided oxide cap layer further comprises: depositing an oxide cap layer on the boron-passivated interface; performing a nitridation of the oxide cap layer.

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