Sensor assembly and driving method therefor, and display substrate

Abstract

A sensor assembly and a driving method therefor, and a display substrate. The sensor assembly comprises: a piezoelectric transducer (20) and a signal processing circuit (10). The signal processing circuit (10) comprises: a voltage-stabilizing sub-circuit, which is configured to store the voltage difference between a signal of a constant voltage signal terminal (AP) and a signal of a first node (N1); a reading sub-circuit, which is configured to provide, under the control of a signal of a first control signal terminal (Gate1), a signal of a second node (N2) to a signal reading terminal (Read); and a node control sub-circuit, which is configured to provide a signal of a bias voltage terminal (BIAS) to a third node (N3) and provide a signal of the third node (N3) to the first node (N1) under the control of signals of a second control signal terminal (Gate2) and a third control signal terminal (Gate3). The piezoelectric transducer (20) is configured to transmit an ultrasonic wave under the control of a signal of a transmission signal terminal (Tx), convert an ultrasonic wave signal reflected by a fingerprint to be recognized into an electrical signal, and transmit the electrical signal to the third node (N3).

Description

Sensor components and their driving methods, display substrates Technical Field

[0001] This article relates to the field of fingerprint recognition technology, specifically to a sensor component and its driving method, and a display substrate. Background Technology

[0002] In recent years, with the development of technology, electronic products with biometric identification functions have gradually entered people's lives and work. Fingerprints are unique and unchanging features that distinguish individuals from one another; they consist of ridges and valleys on the surface of the skin at the fingertips. Because of their uniqueness and immutability, fingerprints can be used for personal identification, making fingerprint recognition technology highly valued.

[0003] Currently, fingerprint recognition is mainly implemented using optical, capacitive, and ultrasonic imaging technologies. Among them, recognition achieved through ultrasonic sensors is more secure due to its 3D characteristics, offering a better user experience and design, and is relatively low in cost, making it a popular research direction for major manufacturers. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a sensor assembly and its driving method, as well as a display substrate.

[0006] In a first aspect, this disclosure provides a sensor assembly, including: a piezoelectric transducer and a signal processing circuit, wherein the signal processing circuit includes: a driving sub-circuit, a reading sub-circuit, a node control sub-circuit, and a voltage regulating sub-circuit;

[0007] The driving sub-circuit is electrically connected to the constant voltage signal terminal, the first node, and the second node, respectively, and is configured to provide a signal to the second node under the control of the signals from the constant voltage signal terminal and the first node.

[0008] The voltage regulator sub-circuit is electrically connected to the constant voltage signal terminal and the first node respectively, and is configured to store the voltage difference between the signals of the constant voltage signal terminal and the first node.

[0009] The reading sub-circuit is electrically connected to the first control signal terminal, the signal reading terminal, and the second node, respectively, and is configured to provide the signal of the second node to the signal reading terminal under the control of the signal of the first control signal terminal.

[0010] The node control sub-circuit is electrically connected to the second control signal terminal, the third control signal terminal, the bias voltage terminal, the first node, and the third node, respectively, and is configured to provide the bias voltage terminal signal to the third node and the third node signal to the first node under the control of the signals of the second control signal terminal and the third control signal terminal.

[0011] The piezoelectric transducer is electrically connected to the third node and the transmitting signal terminal, respectively. It is configured to emit ultrasonic waves under the control of the signal from the transmitting signal terminal, and convert the ultrasonic wave signal reflected by the fingerprint to be identified into an electrical signal and transmit it to the third node.

[0012] In an exemplary embodiment, the node control subcircuit includes: a first control subcircuit and a second control subcircuit;

[0013] The first control sub-circuit is electrically connected to the second control signal terminal, the bias voltage terminal, and the third node, respectively, and is configured to provide the bias voltage terminal signal to the third node under the control of the signal at the second control signal terminal.

[0014] The second control sub-circuit is electrically connected to the third control signal terminal, the first node, and the third node, respectively, and is configured to provide the signal of the third node to the first node under the control of the signal of the third control signal terminal.

[0015] In an exemplary embodiment, the voltage regulator circuit includes a capacitor, which includes a first plate and a second plate.

[0016] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the constant voltage signal terminal.

[0017] In an exemplary embodiment, the driving sub-circuit includes a first transistor, and the reading sub-circuit includes a second transistor;

[0018] The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the constant voltage signal terminal, and the second electrode of the first transistor is electrically connected to the second node.

[0019] The control electrode of the second transistor is electrically connected to the first control signal terminal, the first electrode of the second transistor is electrically connected to the signal reading terminal, and the second electrode of the second transistor is electrically connected to the second node.

[0020] In an exemplary embodiment, the first control sub-circuit includes a third transistor, and the second control sub-circuit includes a fourth transistor;

[0021] The control electrode of the third transistor is electrically connected to the second control signal terminal, the first electrode of the third transistor is electrically connected to the bias voltage terminal, and the second electrode of the third transistor is electrically connected to the third node.

[0022] The control electrode of the fourth transistor is electrically connected to the third control signal terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the third node.

[0023] In an exemplary embodiment, the voltage regulator sub-circuit includes a capacitor, the capacitor including a first plate and a second plate; the driving sub-circuit includes a first transistor; the reading sub-circuit includes a second transistor; and the node control sub-circuit includes a third transistor and a fourth transistor.

[0024] The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the constant voltage signal terminal, and the second electrode of the first transistor is electrically connected to the second node.

[0025] The control electrode of the second transistor is electrically connected to the first control signal terminal, the first electrode of the second transistor is electrically connected to the signal reading terminal, and the second electrode of the second transistor is electrically connected to the second node.

[0026] The control electrode of the third transistor is electrically connected to the second control signal terminal, the first electrode of the third transistor is electrically connected to the bias voltage terminal, and the second electrode of the third transistor is electrically connected to the third node.

[0027] The control electrode of the fourth transistor is electrically connected to the third control signal terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the third node.

[0028] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the constant voltage signal terminal.

[0029] In an exemplary embodiment, the time periods during which the signals at the second control signal terminal and the third control signal terminal are at valid level signals at least partially overlap.

[0030] The time period during which the signal at the first control signal terminal is at an effective level does not overlap with the time period during which at least one of the second and third control signal terminals is at an effective level.

[0031] In an exemplary embodiment, the time period during which the signal at the second control signal terminal is at an effective level is within the range of the time period during which the signal at the third control signal terminal is at an effective level.

[0032] In a second aspect, this disclosure also provides a display substrate, including: a substrate and a plurality of the above-mentioned sensor components disposed on the substrate;

[0033] The structures of sensor assemblies located in adjacent columns of the same row are symmetrically arranged with respect to the virtual straight line extending along the second direction, and the structures of sensor assemblies located in adjacent rows of the same column are symmetrically arranged with respect to the virtual line extending along the first direction, which intersects with the second direction.

[0034] In an exemplary embodiment, it further includes: a plurality of bias voltage lines disposed on the substrate, at least one bias voltage line being electrically connected to the bias voltage terminal of at least one sensor assembly, and extending at least partially along a first direction;

[0035] The orthographic projection of the bias voltage line connected to the sensor assembly in row 2m-1 on the substrate is located on the side away from the orthographic projection of the sensor assembly in row 2m-1 on the substrate. The orthographic projection of the bias voltage line connected to the sensor assembly in row 2m on the substrate is located on the side away from the orthographic projection of the sensor assembly in row 2m-1 on the substrate. m is a positive integer greater than or equal to 1.

[0036] In an exemplary embodiment, it further includes: a plurality of bias connection lines disposed on the substrate, at least one bias connection line being electrically connected to the plurality of bias voltage lines and extending at least partially along the second direction;

[0037] Adjacent sensor components located in the same row as at least one sensor component include: a first adjacent sensor component and a second adjacent sensor component;

[0038] The orthographic projection of the at least one bias connection line on the substrate lies between the orthographic projection of the at least one sensor assembly on the substrate and the orthographic projection of the second adjacent sensor assembly on the substrate.

[0039] In an exemplary embodiment, the at least one bias connection line includes: a plurality of first connection structures and a plurality of second connection structures, the plurality of first connection structures and the plurality of second connection structures are alternately arranged, the orthographic projection of at least one first connection structure on the substrate overlaps with the orthographic projection of at least one bias voltage line on the substrate, and the orthographic projection of at least one second connection structure on the substrate is located between the orthographic projections of two bias voltage lines on the substrate.

[0040] The length of the first connecting structure along the first direction is greater than the length of the second connecting structure along the first direction.

[0041] In an exemplary embodiment, it further includes: a plurality of signal reading lines disposed on the substrate, at least one signal reading line being electrically connected to the signal reading end of at least one sensor component, and extending at least partially along a first direction;

[0042] The orthographic projection of the signal readout line connected to at least one row of sensor components on the substrate lies between the orthographic projection of the bias voltage line connected to at least one row of sensor components on the substrate and the orthographic projection of at least one row of sensor components on the substrate.

[0043] In an exemplary embodiment, it further includes: a plurality of constant voltage signal lines disposed on the substrate, at least one constant voltage signal line being electrically connected to the constant voltage signal terminal of at least one sensor assembly, and extending at least partially along a first direction;

[0044] The constant voltage signal line connected to the sensor assembly in row 2m-1 is the same signal line as the constant voltage signal line connected to the sensor assembly in row 2m. The orthographic projections of the sensor assembly in row 2m-1 and the constant voltage signal line connected to the sensor assembly in row 2m-1 on the substrate are located between the orthographic projections of the sensor assembly in row 2m-1 on the substrate and the orthographic projections of the sensor assembly in row 2m on the substrate, where m is a positive integer greater than or equal to 1.

[0045] In an exemplary embodiment, it further includes: a plurality of first control signal lines disposed on the substrate, at least one of the first control signal lines being electrically connected to a first control signal terminal of at least one sensor assembly and extending at least partially along a second direction, wherein the at least one sensor assembly includes: a first transistor to a fourth transistor;

[0046] The orthographic projection of the first control signal line connected to the at least one sensor assembly on the substrate lies between the orthographic projections of at least one of the third and fourth transistors of the at least one sensor assembly on the substrate and the orthographic projections of at least one of the first and second transistors on the substrate, and at least partially overlaps with the orthographic projection of the control electrode of the first transistor on the substrate.

[0047] In an exemplary embodiment, the system further includes: a plurality of first control signal lines disposed on the substrate, at least one of the first control signal lines being electrically connected to a first control signal terminal of at least one sensor assembly and extending at least partially along a second direction; the at least one sensor assembly includes: a first transistor to a fourth transistor;

[0048] The orthographic projection of the first control signal line connected to the at least one sensor assembly on the substrate is located on the same side of the orthographic projection of at least two of the first, second, third, and fourth transistors of the at least one sensor assembly on the substrate, and there is no overlap with the orthographic projection of the control electrode of the first transistor on the substrate.

[0049] In an exemplary embodiment, it further includes: a plurality of bias connection lines disposed on the substrate, at least one bias connection line including: at least one first connection structure, and adjacent sensor components located in the same row as at least one sensor component including: a first adjacent sensor component and a second adjacent sensor component.

[0050] The orthographic projection of at least one first control signal line on the substrate lies between the orthographic projection of at least one sensor assembly on the substrate and the orthographic projection of the second adjacent sensor assembly on the substrate;

[0051] At least one bias connection line is disposed between two first control signal lines, and a portion of the at least one first control signal line is disposed around a portion of at least one first connection structure of the bias connection line.

[0052] In an exemplary embodiment, it further includes: a plurality of second control signal lines disposed on the substrate, at least one of the second control signal lines being electrically connected to a second control signal terminal of at least one sensor assembly, and extending at least partially along a second direction;

[0053] Adjacent sensor components located in the same row as at least one sensor component include: a first adjacent sensor component and a second adjacent sensor component;

[0054] The orthographic projection of the second control signal line connected to the at least one sensor assembly on the substrate lies between the orthographic projection of the at least one sensor assembly on the substrate and the orthographic projection of the first adjacent sensor assembly on the substrate.

[0055] In an exemplary embodiment, it further includes: a plurality of second control signal lines and a plurality of third control signal lines disposed on the substrate, wherein at least one third control signal line is electrically connected to the third control signal terminal of at least one sensor assembly and extends at least partially along the second direction;

[0056] Adjacent sensor components located in the same row as at least one sensor component include: a first adjacent sensor component and a second adjacent sensor component;

[0057] The third control signal line connected to the at least one sensor assembly is the same signal line as the third control signal line connected to the first adjacent sensor assembly. The orthographic projection of the third control signal line connected to the at least one sensor assembly on the substrate is located on the side of the orthographic projection of the second control signal line connected to the at least one sensor assembly on the substrate that is away from the orthographic projection of the at least one sensor assembly on the substrate.

[0058] In an exemplary embodiment, at least one sensor component includes: a first transistor to a fourth transistor and a capacitor; at least one transistor includes: an active pattern and a control electrode;

[0059] The length of the active pattern of the third transistor along the first direction is greater than the length of the active pattern of at least one of the first transistor, the second transistor, and the fourth transistor along the first direction.

[0060] The length of the control electrode of the first transistor along the second direction is greater than the length of the control electrode of at least one of the second transistor, the third transistor, and the fourth transistor along the second direction;

[0061] The length of the capacitor along the second direction is greater than the length of the control electrode of the first transistor along the second direction.

[0062] In an exemplary embodiment, the device further includes: multiple bias voltage lines, multiple bias connection lines, multiple signal reading lines, multiple constant voltage signal lines, multiple first control signal lines, multiple second control signal lines, and multiple third control signal lines disposed on the substrate; at least one sensor component includes: a piezoelectric transducer, at least one transistor, and at least one capacitor; the at least one transistor includes: an active pattern, a control electrode, a first electrode, and a second electrode; the at least one capacitor includes: a first electrode plate and a second electrode plate; and the piezoelectric transducer includes: a first electrode and a second electrode.

[0063] The display substrate further includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially stacked on the substrate;

[0064] The semiconductor layer includes: an active pattern of at least one transistor in at least one sensor assembly;

[0065] The first conductive layer includes: multiple bias voltage lines, multiple signal readout lines, multiple constant voltage signal lines, and the control electrode of at least one transistor of at least one sensor component and the first plate of at least one capacitor;

[0066] The second conductive layer includes: multiple bias connection lines, multiple first control signal lines, multiple second control signal lines, multiple third control signal lines, and the first and second electrodes of at least one transistor of at least one sensor assembly, and the second electrode plate of at least one capacitor.

[0067] The third conductive layer includes: a connecting electrode, which is electrically connected to the second electrode of at least one transistor in at least one sensor assembly and the second electrode of a piezoelectric transducer, respectively.

[0068] The fourth conductive layer includes: a second electrode of a piezoelectric transducer in at least one sensor assembly;

[0069] The fifth conductive layer includes: at least one first electrode of a piezoelectric transducer in a sensor assembly.

[0070] In an exemplary embodiment, the line width of the bias voltage line along the second direction is greater than the line width of at least one of the signal lines, namely the signal readout line and the constant voltage signal line, along the second direction.

[0071] The line width of the bias connection line along the first direction is greater than the line width of at least one of the first control signal line, the second control signal line, and the third control signal line along the first direction.

[0072] Thirdly, this disclosure also provides a method for driving a sensor assembly, configured to drive the aforementioned sensor assembly, the method comprising:

[0073] The driving sub-circuit provides a signal to the second node under the control of the constant voltage signal terminal and the signal of the first node;

[0074] The voltage regulator circuit stores the voltage difference between the constant voltage signal terminal and the signal at the first node;

[0075] Under the control of the signal at the first control signal terminal, the reading sub-circuit provides the signal of the second node to the signal reading terminal;

[0076] Under the control of the signals at the second and third control signal terminals, the node control sub-circuit provides the bias voltage terminal signal to the third node and the signal of the third node to the first node;

[0077] Under the control of the signal at the transmitting end, the piezoelectric transducer emits ultrasonic waves and converts the ultrasonic signal reflected by the fingerprint to be identified into an electrical signal, which is then transmitted to the third node.

[0078] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0079] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0080] Overview of the attached figures

[0081] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0082] Figure 1 is a schematic diagram of the sensor assembly provided in an embodiment of this disclosure;

[0083] Figure 2 is a schematic diagram of the structure of a piezoelectric transducer provided in an exemplary embodiment;

[0084] Figure 3 is a schematic diagram of the working principle of a piezoelectric transducer;

[0085] Figure 4 is a schematic diagram of the structure of a sensor assembly provided in an exemplary embodiment;

[0086] Figure 5 shows the equivalent circuit diagram of the voltage regulator sub-circuit;

[0087] Figure 6 shows the equivalent circuit diagram of the driving sub-circuit and the reading sub-circuit;

[0088] Figure 7 shows the equivalent circuit diagram of the node control sub-circuit;

[0089] Figure 8 shows the equivalent circuit diagram of the sensor assembly.

[0090] Figure 9 is a timing diagram of the drive for the sensor assembly shown in Figure 8;

[0091] Figure 10A is a top view of a display substrate provided in an embodiment of this disclosure;

[0092] Figure 10B is a schematic diagram of a portion of the film layers in Figure 10A;

[0093] Figure 11A is a second top view of the display substrate provided in an embodiment of this disclosure;

[0094] Figure 11B is a schematic diagram of a portion of the film layers in Figure 11A;

[0095] Figure 12 is a schematic diagram of a portion of the film layers of a sensor assembly;

[0096] Figure 13 is a schematic diagram of the structure of some signal lines;

[0097] Figure 14 is a schematic diagram of the semiconductor layer pattern formed in Figures 10A and 11A;

[0098] Figure 15 is a schematic diagram of the first conductive layer pattern in Figures 10A and 11A;

[0099] Figure 16 is a schematic diagram of the first conductive layer pattern formed in Figures 10A and 11A;

[0100] Figure 17 is a schematic diagram of the second insulating layer pattern formed in Figures 10A and 11A;

[0101] Figure 18 is a schematic diagram of the second conductive layer pattern in Figure 10A;

[0102] Figure 19 is a schematic diagram after the second conductive layer pattern is formed in Figure 10A;

[0103] Figure 20 is a schematic diagram of the second conductive layer pattern in Figure 11A;

[0104] Figure 21 is a schematic diagram after the second conductive layer pattern is formed in Figure 11A;

[0105] Figure 22 is a schematic diagram after the first planarization layer pattern is formed in Figure 10A;

[0106] Figure 23 is a schematic diagram after the first planarization layer pattern is formed in Figure 11A;

[0107] Figure 24 is a schematic diagram of the third conductive layer pattern in Figures 10A and 11A;

[0108] Figure 25 is a schematic diagram after the formation of the third conductive layer pattern in Figure 10A;

[0109] Figure 26 is a schematic diagram after the formation of the third conductive layer pattern in Figure 11A;

[0110] Figure 27 is a schematic diagram after the formation of the second planarization layer in Figure 10A;

[0111] Figure 28 is a schematic diagram after the formation of the second planarization layer in Figure 11A;

[0112] Figure 29 is a schematic diagram of the fourth conductive layer pattern in Figures 10A and 11A;

[0113] Figure 30 is a schematic diagram after the fourth conductive layer pattern is formed in Figure 10A;

[0114] Figure 31 is a schematic diagram of the fourth conductive layer pattern formed in Figure 11A.

[0115] Detailed Explanation

[0116] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0117] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0118] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0119] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0120] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0121] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0122] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0123] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0124] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0125] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0126] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0127] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0128] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0129] The unstable signal at some nodes in a circuit used for fingerprint recognition results in low fingerprint recognition accuracy and reduces the reliability of the fingerprint recognition device.

[0130] Therefore, this disclosure provides a sensor assembly and its driving method, as well as a display substrate.

[0131] Figure 1 is a schematic diagram of the structure of the sensor assembly provided in an embodiment of this disclosure. As shown in Figure 1, the sensor assembly provided in an embodiment of this disclosure includes: a piezoelectric transducer 20 and a signal processing circuit 10. The signal processing circuit 10 includes: a driving sub-circuit, a reading sub-circuit, a node control sub-circuit, and a voltage regulating sub-circuit.

[0132] As shown in Figure 1, the driving sub-circuit is electrically connected to the constant voltage signal terminal AP, the first node N1, and the second node N2, respectively, and is configured to provide a signal to the second node N2 under the control of the signals from the constant voltage signal terminal AP and the first node N1.

[0133] As shown in Figure 1, the voltage regulator circuit is electrically connected to the constant voltage signal terminal AP and the first node N1, respectively, and is configured to store the voltage difference between the signals of the constant voltage signal terminal AP and the first node N1.

[0134] As shown in Figure 1, the read sub-circuit is electrically connected to the first control signal terminal Gate1, the signal reading terminal Read, and the second node N2, respectively. It is configured to provide the signal of the second node N2 to the signal reading terminal Read under the control of the signal of the first control signal terminal Gate1.

[0135] As shown in Figure 1, the node control sub-circuit is electrically connected to the second control signal terminal Gate2, the third control signal terminal Gate3, the bias voltage terminal BIAS, the first node N1, and the third node N3, respectively. It is configured to provide the bias voltage terminal BIAS signal to the third node N3 and the third node N3 signal to the first node N1 under the control of the signals of the second control signal terminal Gate2 and the third control signal terminal Gate3.

[0136] As shown in Figure 1, the piezoelectric transducer 20 is electrically connected to the third node N3 and the transmitting signal terminal Tx, respectively. It is configured to emit ultrasonic waves under the control of the signal from the transmitting signal terminal Tx, and convert the ultrasonic wave signal reflected by the fingerprint to be identified into an electrical signal and transmit it to the third node N3.

[0137] In an exemplary embodiment, the constant voltage signal terminal AP can continuously provide a high-level signal, and the signal of the constant voltage signal terminal AP is a DC signal.

[0138] In an exemplary embodiment, the bias voltage terminal BIAS can continuously provide a low-level signal, and the signal of the bias voltage terminal BIAS is a DC signal.

[0139] In an exemplary embodiment, the sensor assembly may further include an external detection unit, wherein the external detection unit is electrically connected to a signal reading terminal and is configured to determine fingerprint information based on an electrical signal from the signal reading terminal.

[0140] The sensor assembly provided in this embodiment can improve the stability of the signal at the first node, improve fingerprint recognition accuracy, and enhance the reliability of the sensor assembly by setting up a voltage regulator circuit.

[0141] In an exemplary embodiment, FIG2 is a schematic diagram of the structure of a piezoelectric transducer provided in an exemplary embodiment. As shown in FIG2, the piezoelectric transducer 20 includes: a first electrode 210, a second electrode 220 and a piezoelectric material layer 230, wherein the first electrode 210 and the second electrode 220 are respectively disposed on both sides of the piezoelectric material layer 230.

[0142] In an exemplary embodiment, as shown in FIG2, the first electrode 210 of the piezoelectric transducer 20 is connected to the transmitting signal terminal Tx, and the second electrode 220 of the piezoelectric transducer 20 is connected to the third node N3.

[0143] In an exemplary embodiment, the first electrode 210 and the second electrode 220 may be made of metal materials such as platinum, iridium, gold, aluminum, copper, titanium, stainless steel, or tin oxide conductive materials such as indium tin oxide or fluorine-doped tin oxide.

[0144] In an exemplary embodiment, the first electrode 210 and the second electrode 220 may employ a single-layer structure or a multi-layer structure. When at least one of the first electrode 210 and the second electrode 220 employs a multi-layer structure, the first electrode 210 and the second electrode 220 may include: a first metal layer, a second metal layer, and a third metal layer stacked sequentially, wherein the first metal layer may be made of titanium or molybdenum, the second metal layer may be made of aluminum, the third metal layer may be made of titanium or molybdenum, and the first metal layer is located on the side closest to the substrate.

[0145] In an exemplary embodiment, the piezoelectric material layer 230 may include: polydifluoroethylene (PVDF), aluminum nitride (AlN), or a perovskite-structured composite oxide based on lead zirconate titanate, etc., and this disclosure does not limit it in any way.

[0146] Figure 3 shows the working principle of the piezoelectric transducer. As shown in Figure 3, the working principle of the piezoelectric transducer is as follows: a first signal is applied to the first electrode 210 through the transmitting signal terminal Tx. The piezoelectric material layer 230 generates a piezoelectric effect due to voltage excitation, and the piezoelectric material layer will generate mechanical vibration, thereby emitting ultrasonic waves. When the emitted ultrasonic waves come into contact with the object to be identified, such as a finger, the intensity of the reflected ultrasonic vibrations varies because the finger has ridges and valleys. At this time, a second signal is applied to the first electrode 210 through the transmitting signal terminal Tx. The piezoelectric material layer 230 is affected by the reflected ultrasonic waves and generates a positive piezoelectric effect, generating an AC signal on the second electrode 220.

[0147] In an exemplary embodiment, the first signal may be a high-frequency AC voltage signal.

[0148] In an exemplary embodiment, the first signal can be a square wave AC signal or a sinusoidal AC signal. The frequency of the first signal can be in the range of 100 kHz to 20 MHz.

[0149] In an exemplary embodiment, the piezoelectric transducer may further include a piezoelectric matching layer for altering the ultrasonic wave transmission path, which is not limited in this disclosure.

[0150] In an exemplary embodiment, the piezoelectric transducer can be used in fingerprint recognition and also in the field of touch control.

[0151] In an exemplary embodiment, FIG4 is a schematic diagram of the structure of a sensor assembly provided in an exemplary embodiment. As shown in FIG4, the node control subcircuit may include: a first control subcircuit and a second control subcircuit.

[0152] In an exemplary embodiment, as shown in FIG4, the first control sub-circuit is electrically connected to the second control signal terminal Gate2, the bias voltage terminal BIAS, and the third node N3, respectively, and is configured to provide the bias voltage terminal BIAS signal to the third node N3 under the control of the signal of the second control signal terminal Gate2; the second control sub-circuit is electrically connected to the third control signal terminal Gate3, the first node N1, and the third node N3, respectively, and is configured to provide the third node N3 signal to the first node N1 under the control of the signal of the third control signal terminal Gate3.

[0153] In an exemplary embodiment, Figure 5 is an equivalent circuit diagram of the voltage regulator sub-circuit. As shown in Figure 5, the voltage regulator sub-circuit includes a capacitor C, which includes a first plate C1 and a second plate C2. The first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the constant voltage signal terminal AP.

[0154] The setting of capacitor C can ensure the stability of the signal at the first node N1 and improve the reliability of the sensor assembly.

[0155] Figure 5 illustrates an exemplary structure of the voltage regulator sub-circuit. It will be readily understood by those skilled in the art that the implementation of the voltage regulator sub-circuit is not limited to this; any implementation that achieves the desired function is acceptable.

[0156] In an exemplary embodiment, FIG6 is an equivalent circuit diagram of the driving sub-circuit and the reading sub-circuit. As shown in FIG6, the driving sub-circuit includes a first transistor T1, and the reading sub-circuit includes a second transistor T2. The control electrode of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the constant voltage signal terminal AP, and the second terminal of the first transistor T1 is electrically connected to the second node N2. The control electrode of the second transistor T2 is electrically connected to the first control signal terminal Gate1, the first terminal of the second transistor T2 is electrically connected to the signal reading terminal Read, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0157] In an exemplary embodiment, the first transistor T1 can be referred to as the driving transistor, and the second transistor T2 can be referred to as the reading transistor.

[0158] Figure 6 illustrates exemplary structures of the driving sub-circuit and the reading sub-circuit. It will be readily understood by those skilled in the art that the implementation of the driving sub-circuit and the reading sub-circuit is not limited to this; any implementation that achieves the desired functionality is acceptable.

[0159] In an exemplary embodiment, Figure 7 is an equivalent circuit diagram of the node control sub-circuit. As shown in Figure 7, in the node control sub-circuit, the first control sub-circuit includes a third transistor T3, and the second control sub-circuit includes a fourth transistor T4. The control electrode of the third transistor T3 is electrically connected to the second control signal terminal Gate2, the first electrode of the third transistor T3 is electrically connected to the bias voltage terminal BIAS, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the third control signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the first node N1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3.

[0160] Figure 7 illustrates an exemplary structure of the node control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the node control sub-circuit is not limited to this; any implementation that achieves the desired function is acceptable.

[0161] In an exemplary embodiment, FIG8 is an equivalent circuit diagram of the sensor assembly. As shown in FIG8, in the sensor assembly, the voltage regulator sub-circuit includes: a capacitor C, the capacitor C includes: a first plate C1 and a second plate C2; ​​the driving sub-circuit includes: a first transistor T1; the reading sub-circuit includes: a second transistor T2; and the node control sub-circuit includes: a third transistor T3 and a fourth transistor T4. Specifically, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the constant voltage signal terminal AP, and the second terminal of the first transistor T1 is electrically connected to the second node N2; the control electrode of the second transistor T2 is electrically connected to the first control signal terminal Gate1, the first terminal of the second transistor T2 is electrically connected to the signal reading terminal Read, and the second terminal of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the second control signal terminal Gate2, the first terminal of the third transistor T3 is electrically connected to the bias voltage terminal BIAS, and the second terminal of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the third control signal terminal Gate3, the first terminal of the fourth transistor T4 is electrically connected to the first node N1, and the second terminal of the fourth transistor T4 is electrically connected to the third node N3; the first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the constant voltage signal terminal AP.

[0162] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0163] In an exemplary embodiment, the N-type transistor can be an oxide thin-film transistor. The active pattern of the oxide thin-film transistor uses oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current, which can reduce power consumption and improve display quality.

[0164] In an exemplary embodiment, at least one of the first transistor T1 to the fourth transistor T4 can be an N-type transistor. Using the same type of transistor in the sensor assembly can simplify the process flow, reduce the manufacturing difficulty of the sensor assembly, and improve the product yield.

[0165] In an exemplary embodiment, any capacitor in capacitor C can be a capacitor device manufactured through a process, for example, by fabricating dedicated capacitor electrodes. Multiple capacitor electrodes can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. Alternatively, any capacitor in capacitor C can be a parasitic capacitance between multiple devices, implemented using the transistor itself and other devices or circuits. The connection method of any capacitor in capacitor C includes, but is not limited to, the methods described above; other applicable connection methods can be used, as long as the voltage level of the corresponding node is stored. Here, the exemplary embodiments of this disclosure do not limit this.

[0166] Figure 9 is a timing diagram of the sensor assembly shown in Figure 8. Figure 9 is illustrated using the example where all transistors in the signal processing circuit of the sensor assembly shown in Figure 8 are N-type transistors. As shown in Figure 9, during fingerprint recognition, the time periods during which the signals at the second control signal terminal Gate2 and the third control signal terminal Gate3 are at valid levels at least partially overlap. For example, the time period during which the signal at the second control signal terminal Gate2 is at a valid level is within the range of the time period during which the signal at the third control signal terminal Gate3 is at a valid level.

[0167] In an exemplary embodiment, as shown in FIG9, the time period during which the signal of the first control signal terminal Gate1 is an effective level signal does not overlap with the time period during which at least one of the second control signal terminal Gate2 and the third control signal terminal Gate3 is an effective level signal.

[0168] The technical solution of this disclosure will be further explained below with reference to Figures 8 and 9, through the working process of the sensor assembly.

[0169] In the first stage S1, the initialization stage, the signals at the second control signal terminal Gate2 and the third control signal terminal Gate3 are high-level signals, while the signal at the first control signal terminal Gate1 is low-level. The third transistor T3 and the fourth transistor T4 are turned on, while the second transistor T2 is turned off.

[0170] The third transistor T3 and the fourth transistor T4 are turned on, and the signal at the bias voltage terminal BIAS is written to the first node N1 and the third node N3 to initialize the signals of the first node N1 and the third node N3 and clear the original voltage in the first node N1 and the third node N3.

[0171] In the second stage, S2, which is the ultrasonic wave transmission and reception stage, the signal at the third control signal terminal Gate3 is a high-level signal, while the signals at the first control signal terminal Gate1 and the second control signal terminal Gate2 are low-level signals. The fourth transistor T4 is turned on, while the second transistor T2 and the third transistor T3 are turned off.

[0172] During the transmission phase, the fourth transistor T4 is turned on. The signals of the third node N3 and the first node N1 are maintained at the bias voltage terminal signals of the previous phase under the action of capacitor C, providing the first signal to the transmission signal terminal Tx. In this phase, the signal of the first electrode of the piezoelectric transducer is the first signal, and the signal of the second electrode of the piezoelectric transducer is the constant voltage signal. Under the action of the piezoelectric effect of the piezoelectric material layer, the piezoelectric transducer generates ultrasonic signals and transmits ultrasonic signals outward.

[0173] During the receiving phase, a second signal is provided to the transmitting signal terminal Tx. The second signal is a constant voltage signal. At this time, the signal of the first electrode of the piezoelectric transducer is the second signal. The piezoelectric material layer receives the ultrasonic signal reflected by the fingerprint under test. Under the piezoelectric effect of the piezoelectric material layer, the second electrode of the piezoelectric transducer generates an AC signal. The AC signal generated by the piezoelectric transducer is transmitted to the third node N3. Since the fourth transistor T4 is turned on, the signal of the third node N3 is written into the first node N1, realizing the conversion between the ultrasonic signal and the electrical signal.

[0174] In the third stage, S3, the reading stage, the signal at the first control signal terminal Gate1 is a high-level signal, while the signals at the second control signal terminal Gate2 and the third control signal terminal Gate3 are low-level signals. The second transistor T2 is turned on, while the third transistor T3 and the fourth transistor T4 are turned off.

[0175] The signal of the first node N1 is a high-level signal, the first transistor T1 is turned on, the second transistor T2 is turned on, and the signal reading terminal Read reads the signal of the second node N2 so that the external detection unit can determine the fingerprint information based on the electrical signal of the signal reading terminal.

[0176] This disclosure also provides a method for driving a sensor component, configured to drive the sensor component provided in any of the foregoing embodiments. The method for driving the sensor component may include:

[0177] Step 100: Under the control of the constant voltage signal terminal and the signal of the first node, the driving sub-circuit provides a signal to the second node.

[0178] Step 200: The voltage regulator circuit stores the voltage difference between the constant voltage signal terminal and the signal of the first node.

[0179] Step 300: Under the control of the signal at the first control signal terminal, the reading sub-circuit provides the signal of the second node to the signal reading terminal.

[0180] Step 400: Under the control of the signals at the second control signal terminal and the third control signal terminal, the node control sub-circuit provides the bias voltage terminal signal to the third node and provides the third node signal to the first node.

[0181] Step 500: Under the control of the signal at the transmitting signal end, the piezoelectric transducer emits ultrasonic waves and converts the ultrasonic signal reflected by the fingerprint to be identified into an electrical signal, which is then transmitted to the third node.

[0182] This disclosure also provides a display substrate. The display substrate provided in this disclosure may include: a substrate and a plurality of sensor components provided in any of the foregoing embodiments disposed on the substrate. The sensor components include: signal processing circuitry and a piezoelectric transducer.

[0183] Figure 10A is a top view of the display substrate provided in an embodiment of this disclosure, Figure 10B is a partial film layer schematic diagram of Figure 10A, Figure 11A is a top view of the display substrate provided in an embodiment of this disclosure, and Figure 11B is a partial film layer schematic diagram of Figure 11A. As shown in Figures 10A to 11B, in an exemplary embodiment, the structures of sensor components located in adjacent columns of the same row are symmetrically arranged with respect to the virtual straight line extending along the second direction D2, and the structures of sensor components located in adjacent rows of the same column are symmetrically arranged with respect to the virtual lines extending along the first direction D1. The sensor components include: a signal processing circuit 10 and a piezoelectric transducer, wherein the piezoelectric transducer includes: a second electrode 220, a piezoelectric material layer (not shown in the figure), and a first electrode (not shown in the figure).

[0184] In an exemplary embodiment, adjacent sensor components located in the same row as at least one sensor component include: a first adjacent sensor component and a second adjacent sensor component. For the sensor component in row 2m-1, column n+1, the first adjacent sensor component is the sensor component in row 2m-1, column n, and the second adjacent sensor component is the sensor component in row 2m-1, column n+2. Similarly, for the sensor component in row 2m-1, column n+2, the first adjacent sensor component is the sensor component in row 2m-1, column n+2, and the second adjacent sensor component is the sensor component in row 2m-1, column n+2. Finally, for the sensor component in row 2m, column n+2, the first adjacent sensor component is the sensor component in row 2m-1, column n, and the second adjacent sensor component is the sensor component in row 2m, column n+2.

[0185] In an exemplary embodiment, as shown in Figures 10A to 11B, the display substrate further includes: a plurality of bias voltage lines BIASL1 disposed on the substrate, at least one bias voltage line BIASL1 being electrically connected to the bias voltage terminal of at least one sensor component, and extending at least partially along the first direction D1.

[0186] In an exemplary embodiment, as shown in Figures 10A to 11B, the orthographic projection of the bias voltage line BIASL1 connected to the sensor assembly in row 2m-1 on the substrate is located on the side away from the orthographic projection of the sensor assembly in row 2m-1 on the substrate, and the orthographic projection of the bias voltage line BIASL1 connected to the sensor assembly in row 2m on the substrate is located on the side away from the orthographic projection of the sensor assembly in row 2m-1 on the substrate, where m is a positive integer greater than or equal to 1.

[0187] In an exemplary embodiment, as shown in Figures 10A to 11B, the display substrate further includes: a plurality of bias connection lines BIASL2 disposed on the substrate, at least one bias connection line BIASL2 being electrically connected to a plurality of bias voltage lines BIASL1, and extending at least partially along the second direction D2.

[0188] In an exemplary embodiment, as shown in Figures 10A to 11B, the orthographic projection of at least one bias connection line BIASL2 on the substrate is located between the orthographic projection of at least one sensor component on the substrate and the orthographic projection of a second adjacent sensor component on the substrate.

[0189] In an exemplary embodiment, multiple bias voltage lines and multiple bias connection lines are interwoven to form a mesh structure, which can make the signals at the bias signal terminals of multiple sensor components the same, thereby improving the uniformity of the display substrate.

[0190] In an exemplary embodiment, as shown in Figures 10B and 11B, at least one bias connection line BIASL2 includes: a plurality of first connection structures L11 and a plurality of second connection structures L12, the plurality of first connection structures L11 and the plurality of second connection structures L12 are alternately arranged, the orthographic projection of at least one first connection structure L11 on the substrate overlaps with the orthographic projection of at least one bias voltage line BIASL1 on the substrate, and the orthographic projection of at least one second connection structure L12 on the substrate is located between the orthographic projections of the two bias voltage lines BIASL1 on the substrate.

[0191] In an exemplary embodiment, as shown in Figures 10B and 11B, the length of the first connection structure L11 along the first direction D1 is greater than the length of the second connection structure L12 along the first direction D1. The fact that the length of the first connection structure L11 along the first direction D1 is greater than the length of the second connection structure L12 along the first direction D1 in this disclosure allows for a larger contact area between the bias connection line and the bias voltage line, thereby improving the stability of the connection.

[0192] In an exemplary embodiment, as shown in Figures 10A to 11B, the display substrate further includes: a plurality of signal readout lines ReadL disposed on the substrate, at least one of the signal readout lines ReadL being electrically connected to the signal readout end of at least one sensor component, and extending at least partially along the first direction D1.

[0193] In an exemplary embodiment, as shown in Figures 10A to 11B, the orthographic projection of the signal readout line ReadL connected to at least one row of sensor components on the substrate is located between the orthographic projection of the bias voltage line BIASL1 connected to at least one row of sensor components on the substrate and the orthographic projection of at least one row of sensor components on the substrate.

[0194] In an exemplary embodiment, as shown in Figures 10A to 11B, the display substrate further includes: a plurality of constant voltage signal lines APL disposed on the substrate, at least one constant voltage signal line APL being electrically connected to the constant voltage signal terminal of at least one sensor assembly, and extending at least partially along the first direction D1.

[0195] In an exemplary embodiment, as shown in Figures 10A to 11B, the constant voltage signal line APL connected to the sensor assembly in row 2m-1 is the same signal line as the constant voltage signal line APL connected to the sensor assembly in row 2m. The orthographic projections of the sensor assembly in row 2m-1 and the constant voltage signal line APL connected to the sensor assembly in row 2m-1 on the substrate are located between the orthographic projections of the sensor assembly in row 2m-1 on the substrate and the orthographic projections of the sensor assembly in row 2m on the substrate.

[0196] In an exemplary embodiment, as shown in Figures 10A to 11B, the display substrate further includes: a plurality of first control signal lines GateL1 disposed on the substrate, at least one of the first control signal lines GateL1 being electrically connected to a first control signal terminal of at least one sensor assembly and extending at least partially along the second direction D2, and at least one sensor assembly including: a first transistor T1 to a fourth transistor T4.

[0197] In an exemplary embodiment, as shown in Figures 10A and 11B, the orthographic projection of the first control signal line GateL1 connected to at least one sensor assembly on the substrate is located between the orthographic projections of at least one of the third transistors T3 and the fourth transistor T4 of the at least one sensor assembly on the substrate and the orthographic projections of at least one of the first transistors T1 and the second transistor T2 on the substrate, and at least partially overlaps with the orthographic projection of the control electrode 12 of the first transistor on the substrate.

[0198] In an exemplary embodiment, as shown in Figures 11A and 11B, the orthographic projection of the first control signal line GateL1 connected to at least one sensor assembly on the substrate is located on the same side of the orthographic projection of at least two of the first transistor T1, second transistor T2, third transistor T3, and fourth transistor T4 of the at least one sensor assembly on the substrate, and there is no overlapping area with the orthographic projection of the control electrode 12 of the first transistor on the substrate.

[0199] In an exemplary embodiment, as shown in Figures 11A and 11B, the orthographic projection of at least one first control signal line GateL1 on the substrate is located between the orthographic projection of at least one sensor assembly on the substrate and the orthographic projection of a second adjacent sensor assembly on the substrate.

[0200] In an exemplary embodiment, as shown in Figures 11A and 11B, at least one bias connection line BIASL2 is disposed between two first control signal lines GateL1, and a portion of the at least one first control signal line GateL1 is disposed around a portion of at least one first connection structure L11 of the bias connection line BIASL2.

[0201] In an exemplary embodiment, as shown in Figures 10A to 11B, the display substrate further includes: a plurality of second control signal lines GateL2 disposed on the substrate, at least one of the second control signal lines GateL2 being electrically connected to a second control signal terminal of at least one sensor assembly, and extending at least partially along the second direction D2.

[0202] In an exemplary embodiment, as shown in Figures 10A to 11B, the orthographic projection of the second control signal line GateL2, to which at least one sensor component is connected, onto the substrate lies between the orthographic projection of the at least one sensor component onto the substrate and the orthographic projection of the first adjacent sensor component onto the substrate.

[0203] In an exemplary embodiment, as shown in Figures 10A to 11B, the display substrate further includes: a plurality of third control signal lines GateL3 disposed on the substrate, at least one of the third control signal lines GateL3 being electrically connected to the third control signal terminal of at least one sensor assembly, and extending at least partially along the second direction D2.

[0204] In an exemplary embodiment, as shown in Figures 10A to 11B, the third control signal line GateL3 connected to at least one sensor assembly is the same signal line as the third control signal line GateL3 connected to the first adjacent sensor assembly. The orthographic projection of the third control signal line GateL3 connected to at least one sensor assembly on the substrate is located on the side of the orthographic projection of the second control signal line GateL2 connected to at least one sensor assembly on the substrate that is away from the orthographic projection of the at least one sensor assembly on the substrate.

[0205] In an exemplary embodiment, as shown in Figures 10B and 11B, at least one sensor component includes: a first transistor T1 to a fourth transistor T4 and a capacitor C; at least one transistor includes: an active pattern and a control electrode.

[0206] Figure 12 is a schematic diagram of a portion of the film layers of a sensor assembly. As shown in Figure 12, the length W13 of the active pattern 31 of the third transistor along the first direction D1 is greater than the length W11 of the active pattern 11 of the first transistor along the first direction D1, the length W12 of the active pattern 21 of the second transistor along the first direction D1, and the length W14 of the active pattern 41 of the fourth transistor along the first direction D1.

[0207] In an exemplary embodiment, as shown in FIG12, the length W21 of the control electrode 12 of the first transistor along the second direction D2 is greater than the length W22 of the control electrode 22 of the second transistor along the second direction D2, the length W23 of the control electrode 32 of the third transistor along the second direction D2, and the length W24 of the control electrode 42 of the fourth transistor along the second direction D2.

[0208] In an exemplary embodiment, as shown in Figures 11 and 11B, the length W25 of the capacitor along the second direction D2 is greater than the length W21 of the control electrode of the first transistor along the second direction D2.

[0209] In an exemplary embodiment, the display substrate further includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked on the substrate.

[0210] In an exemplary embodiment, the semiconductor layer includes an active pattern of at least one transistor in at least one sensor assembly.

[0211] In an exemplary embodiment, the first conductive layer includes: multiple bias voltage lines BIASL1, multiple signal readout lines ReadL, multiple constant voltage signal lines APL, and the control electrode of at least one transistor of at least one sensor assembly and the first plate of at least one capacitor.

[0212] In an exemplary embodiment, the second conductive layer includes: multiple bias connection lines BIASL2, multiple first control signal lines GateL1, multiple second control signal lines GateL2, multiple third control signal lines GateL3, and the first and second poles of at least one transistor of at least one sensor assembly, and the second plate of at least one capacitor.

[0213] In an exemplary embodiment, the third conductive layer includes a connecting electrode that is electrically connected to the second electrode of at least one transistor in at least one sensor assembly and the second electrode 220 of a piezoelectric transducer, respectively.

[0214] In an exemplary embodiment, the fourth conductive layer includes: a second electrode 220 of a piezoelectric transducer in at least one sensor assembly.

[0215] In an exemplary embodiment, the fifth conductive layer includes: a first electrode of a piezoelectric transducer in at least one sensor assembly.

[0216] Figure 13 is a schematic diagram of the structure of some signal lines. In an exemplary embodiment, as shown in Figure 13, the line width W31 of the bias voltage line BIASL1 along the second direction D2 is greater than at least one of the line widths W32 of the signal read line ReadL along the second direction D2 and W33 of the constant voltage signal line APL along the second direction D2.

[0217] In an exemplary embodiment, as shown in FIG13, the line width W41 of the bias connection line BIASL2 along the first direction D1 is greater than at least one of the line widths W42 of the first control signal line GateL1 along the first direction D1, W43 of the second control signal line GateL2 along the first direction D1, and W44 of the third control signal line GateL3 along the first direction D1.

[0218] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0219] Figures 14 to 31 are schematic diagrams illustrating the fabrication process of a display substrate according to an exemplary embodiment. Figures 14 to 31 are illustrated using a two-row, four-column sensor assembly as an example. The fabrication process of a display substrate according to an exemplary embodiment may include:

[0220] In an exemplary embodiment, at least one transistor includes an active pattern, a control electrode, a first electrode, and a second electrode, and at least one capacitor includes a first electrode plate and a second electrode plate.

[0221] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first semiconductor thin film on a substrate, and patterning the first semiconductor thin film by a patterning process to form a semiconductor layer pattern, as shown in FIG14, FIG14 being a schematic diagram of FIG10A and FIG11A after the semiconductor layer pattern has been formed.

[0222] In an exemplary embodiment, the semiconductor layer pattern may include an active pattern located on at least one transistor of at least one sensor component. The active pattern of at least one transistor of at least one sensor component may include active patterns 11 of a first transistor to active patterns 41 of a fourth transistor.

[0223] In an exemplary embodiment, the active patterns of at least one transistor in a sensor assembly located in adjacent columns of the same row are symmetrically arranged with respect to a virtual straight line extending along a second direction D2. The active patterns of at least one transistor in a sensor assembly located in the same column and row are symmetrically arranged with respect to a virtual straight line extending along a first direction D1.

[0224] In an exemplary embodiment, the active pattern 11 of the first transistor and the active pattern 21 of the second transistor in the same sensor assembly are an integral structure, and the active pattern 31 of the third transistor and the active pattern 41 of the fourth transistor are an integral structure.

[0225] In an exemplary embodiment, the active patterns 21 of the second transistor and 31 of the third transistor are arranged along the first direction D1, and the active patterns 11 of the first transistor and 41 of the fourth transistor are arranged along the first direction D1.

[0226] In an exemplary embodiment, the length of the active pattern 31 of the third transistor along the first direction D1 is greater than the length of the active pattern of at least one of the first transistor, the second transistor, and the fourth transistor along the first direction D1.

[0227] In an exemplary embodiment, at least one of the active patterns of the first transistor 11, the second transistor 21, the third transistor 31, and the fourth transistor 41 extends along the second direction D2.

[0228] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 11-2 of the active pattern 11 of the first transistor may serve as the second region 21-2 of the active pattern 21 of the second transistor, and the second region 31-2 of the active pattern 31 of the third transistor may serve as the second region 41-2 of the active pattern 41 of the fourth transistor. The first region 11-1 of the active pattern 11 of the first transistor, the first region 21-1 of the active pattern 21 of the second transistor, the first region 31-1 of the active pattern 31 of the third transistor, and the first region 41-1 of the active pattern 41 of the fourth transistor may be configured individually.

[0229] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed, and patterning the first insulating film and the first conductive film using a patterning process to form a first insulating layer pattern and a first conductive layer pattern located on the first insulating layer, as shown in Figures 15 and 16, wherein Figure 15 is a schematic diagram of the first conductive layer pattern in Figures 10A and 11A, and Figure 16 is a schematic diagram of Figures 10A and 11A after the formation of the first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a gate metal (GATE) layer.

[0230] In an exemplary embodiment, the first conductive layer pattern may include: a bias voltage line BIASL1, a signal readout line ReadL, a constant voltage signal line APL, and a control electrode of at least one transistor of at least one sensor assembly and a first plate of at least one capacitor. The control electrode of at least one transistor of at least one sensor assembly includes: control electrodes 12 of the first transistor to 42 of the fourth transistor. The first plate of at least one capacitor of at least one sensor assembly includes: a first plate C1 of the capacitor.

[0231] In an exemplary embodiment, the control electrode of at least one transistor and the first plate of at least one capacitor of at least one sensor assembly located in adjacent columns of the same row are symmetrically arranged with respect to a virtual straight line extending along a second direction D2. The control electrode of at least one transistor and the first plate of at least one capacitor of at least one sensor assembly located in adjacent rows of the same column are symmetrically arranged with respect to a virtual straight line extending along a first direction D1.

[0232] In an exemplary embodiment, the orthographic projections of the bias voltage line BIASL1 and the signal readout line ReadL connected to the sensor assembly in row 2m-1 on the substrate are located on the side of the orthographic projection of the sensor assembly in row 2m-1 on the substrate that are far from the orthographic projection of the sensor assembly in row 2m-1 on the substrate, and the orthographic projection of the signal readout line connected to the sensor assembly in row 2m-1 on the substrate is located on the side of the orthographic projection of the bias voltage line BIASL1 on the substrate that is close to the orthographic projection of the sensor assembly in row 2m-1 on the substrate.

[0233] In an exemplary embodiment, the constant voltage signal line APL connected to the 2m-1 row sensor assembly and the 2m row sensor assembly is the same signal line, and its orthographic projection on the substrate is located between the orthographic projection of the 2m-1 row sensor assembly on the substrate and the orthographic projection of the 2m row sensor on the substrate.

[0234] In an exemplary embodiment, the bias voltage line BIASL1, the signal readout line ReadL, and the constant voltage signal line APL can be line shapes in which the main body extends along the first direction D1.

[0235] In an exemplary embodiment, the linewidth of the bias voltage line BIASL1 along the second direction D2 is greater than the linewidth of at least one of the signal lines ReadL and APL along the second direction D2.

[0236] In an exemplary embodiment, the control electrode 12 of the first transistor in the same sensor assembly and the first plate C1 of the capacitor are integrally formed. The control electrode 12 of the first transistor in the same sensor assembly and the first plate C1 of the capacitor are arranged along the second direction D2.

[0237] In an exemplary embodiment, the first plate C1 of the capacitor and the control electrode 12 of the first transistor can be rectangular, and the length of the control electrode 12 of the first transistor along the second direction D2 is less than the length of the first plate C1 of the capacitor along the second direction D2.

[0238] In an exemplary embodiment, the control electrode 42 of the fourth transistor in at least one sensor assembly is the same electrode as the control electrode 42 of the fourth transistor in the first adjacent sensor assembly.

[0239] In an exemplary embodiment, the control electrode 22 of the second transistor to the control electrode 42 of the fourth transistor in the same sensor assembly are provided separately.

[0240] In an exemplary embodiment, at least one of the control electrodes of the second transistor 22 to the fourth transistor 42 in the same sensor assembly extends along the first direction D1.

[0241] In an exemplary embodiment, the control electrode 12 of the first transistor is disposed across the active pattern of the first transistor, the control electrode 22 of the second transistor is disposed across the active pattern of the second transistor, the control electrode 32 of the third transistor T3 is disposed across the active pattern of the third transistor T3, and the control electrode 42 of the fourth transistor is disposed across the active pattern of the fourth transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0242] In an exemplary embodiment, the process further includes a conductor-enhancing process. This process involves, after forming the first conductive layer pattern, using the semiconductor layer in the control electrode shielding region of the multiple transistors (i.e., the region where the semiconductor layer overlaps with the control electrode) as the channel region of the transistor, and processing the semiconductor layer in the region not shielded by the first conductive layer into a conductive region. The second region of the active pattern of the first transistor (which is also the second region of the active pattern of the second transistor) can serve as the second electrode 14 of the first transistor (which is also the second electrode 24 of the second transistor).

[0243] In an exemplary embodiment, the bias voltage line BIASL1, the signal readout line ReadL, and the constant voltage signal line APL can be straight lines or broken lines, and this disclosure does not limit them.

[0244] (3) Forming a second insulating layer pattern. In an exemplary embodiment, forming a second insulating layer pattern may include: depositing a second insulating film on a substrate on which the aforementioned pattern is formed, and patterning the second insulating film using a patterning process to form a second insulating layer pattern covering the first conductive layer. The second insulating layer pattern has a plurality of vias, as shown in FIG17. FIG17 is a schematic diagram of FIG10A and FIG11A after the second insulating layer pattern has been formed.

[0245] In an exemplary embodiment, the second insulating layer pattern is provided with a plurality of vias, including at least: a first via V1 to a twelfth via V11.

[0246] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is within the orthographic projection range of the first region of the active pattern of the first transistor on the substrate. The first insulating layer inside the first via V1 is etched away, exposing the first region of the active pattern of the first transistor. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active pattern of the first transistor through the via.

[0247] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the orthographic projection range of the first region of the active pattern of the second transistor onto the substrate. The first insulating layer within the second via V2 is etched away, exposing the surface of the first region of the active pattern of the second transistor. The second via V2 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the first region of the active pattern of the second transistor through the via.

[0248] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the third transistor onto the substrate. The first insulating layer within the third via V3 is etched away, exposing the surface of the first region of the active pattern of the third transistor. The third via V3 is configured to allow the first electrode of the subsequently formed third transistor to be connected to the first region of the active pattern of the third transistor through the via.

[0249] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor) onto the substrate. The first insulating layer within the fourth via V4 is etched away, exposing the surface of the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor). The fourth via V4 is configured to allow the second electrode of the subsequently formed third transistor (which is also the second electrode of the fourth transistor) to be connected to the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor) through the via.

[0250] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the range of the orthographic projection of the first region of the active pattern of the fourth transistor onto the substrate. The first insulating layer within the fifth via V5 is etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The fifth via V5 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the first region of the active pattern of the fourth transistor through the via.

[0251] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is within the range of the orthographic projection of the control electrode of the first transistor (which is also the first plate of the capacitor) on the substrate. The sixth via V6 exposes the surface of the control electrode of the first transistor (which is also the first plate of the capacitor). The sixth via V6 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the control electrode of the first transistor (which is also the first plate of the capacitor) through the via.

[0252] In an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the substrate is within the range of the orthogonal projection of the control electrode of the second transistor onto the substrate. The seventh via V7 exposes the surface of the control electrode of the second transistor. The seventh via V7 is configured to allow a subsequently formed first control signal line to be connected to the control electrode of the second transistor through the via.

[0253] In an exemplary embodiment, the orthogonal projection of the eighth via V8 onto the substrate is within the range of the orthogonal projection of the control electrode of the third transistor onto the substrate. The eighth via V8 exposes the surface of the control electrode of the third transistor. The eighth via V8 is configured to allow a subsequently formed second control signal line to be connected to the control electrode of the third transistor through the via.

[0254] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the substrate is within the range of the orthogonal projection of the control electrode of the fourth transistor onto the substrate. The ninth via V9 exposes the surface of the control electrode of the fourth transistor. The ninth via V9 is configured to allow a subsequently formed third control signal line to be connected to the control electrode of the fourth transistor through the via.

[0255] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the bias voltage line on the substrate. The tenth via V10 exposes the surface of the bias voltage line. The tenth via V10 is configured to allow the first electrode and bias connection line of the subsequently formed third transistor to be connected to the bias voltage line through the via.

[0256] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is within the range of the orthographic projection of the signal readout line on the substrate. The eleventh via V11 exposes the surface of the signal readout line. The eleventh via V11 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the signal readout line through the via.

[0257] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the constant voltage signal line on the substrate. The twelfth via V12 exposes the surface of the constant voltage signal line. The twelfth via V12 is configured to allow the second plate of the subsequently formed capacitor and the first electrode of the first transistor to be connected to the constant voltage signal line through the via.

[0258] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the second conductive thin film using a patterning process to form a second conductive layer pattern, as shown in Figures 18 to 21. Figure 18 is a schematic diagram of the second conductive layer pattern in Figure 10A, Figure 19 is a schematic diagram of Figure 10A after the second conductive layer pattern is formed, Figure 20 is a schematic diagram of the second conductive layer pattern in Figure 11A, and Figure 21 is a schematic diagram of Figure 11A after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0259] In an exemplary embodiment, the second conductive layer pattern includes at least: a bias connection line BIASL2, a first control signal line GateL1, a second control signal line GateL2, a third control signal line GateL3, and a first and second electrode of at least one transistor in at least one sensor assembly, and a second electrode of at least one capacitor. The first and second electrodes of the at least one transistor in the at least one sensor assembly include: a first electrode 13 and a second electrode 14 of the first transistor, a first electrode 23 and a second electrode 24 of the second transistor, a first electrode 33 and a second electrode 34 of the third transistor, and a first electrode 43 and a second electrode 44 of the fourth transistor. The second electrode of the at least one capacitor in the at least one sensor assembly includes: a second electrode C2 of the capacitor.

[0260] In an exemplary embodiment, the first and second electrodes of at least one transistor and the second plate of a capacitor in adjacent sensor assemblies located in the same row are symmetrically arranged relative to a virtual straight line extending along a second direction D2. The first and second electrodes of at least one transistor and the second plate of a capacitor in adjacent sensor assemblies located in the same column are symmetrically arranged relative to a virtual straight line extending along a first direction D1.

[0261] In an exemplary embodiment, in the display substrate provided in FIG10A and FIG11A, at least one bias connection line BIASL2 is located on the substrate between a first control signal line GateL1 connected to at least one sensor assembly and a first control signal line GateL1 connected to a second adjacent sensor assembly.

[0262] In an exemplary embodiment, in the display substrate provided in Figures 10A and 11A, the bias connection line BIASL2 can be a line shape in which the main body extends along the second direction D2. The bias connection line BIASL2 is electrically connected to the bias voltage line through a tenth via.

[0263] In an exemplary embodiment, in the display substrate provided in FIG10A and FIG11A, the bias connection line BIASL2 includes: a plurality of first connection structures L11 and a plurality of second connection structures L12, the plurality of first connection structures L11 and the plurality of second connection structures L12 are alternately arranged, the orthographic projection of at least one first connection structure L11 on the substrate overlaps with the orthographic projection of at least one bias voltage line on the substrate, and the orthographic projection of at least one second connection structure L12 on the substrate is between the orthographic projections of the two bias voltage lines on the substrate.

[0264] In an exemplary embodiment, the length of the first connecting structure L11 along the first direction D1 is greater than the length of the second connecting structure L12 along the first direction D1.

[0265] In an exemplary embodiment, in the display substrate provided in Figures 10A and 11A, the shape of the second control signal line GateL2 can be a line shape in which the main body extends along the second direction D2. The orthographic projection of the second control signal line GateL2 connected to at least one sensor assembly on the substrate lies between the orthographic projection of the at least one sensor assembly on the substrate and the orthographic projection of the first adjacent sensor assembly on the substrate. At least one second control signal line GateL2 is electrically connected to the control electrode of the third transistor of at least one sensor assembly through an eighth via.

[0266] In an exemplary embodiment, in the display substrate provided in Figures 10A and 11A, the shape of the third control signal line Gate L3 can be a line shape in which the main body extends along the second direction D2. The orthographic projection of the third control signal line Gate L3 connected to at least one sensor assembly onto the substrate lies between the orthographic projection of the at least one sensor assembly onto the substrate and the orthographic projection of the first adjacent sensor assembly onto the substrate, and the third control signal line Gate L3 connected to the at least one sensor assembly and the third control signal line Gate L3 connected to the first adjacent sensor assembly are the same signal line. At least one third control signal line Gate L3 is electrically connected to the control electrode of the fourth transistor of at least one sensor assembly through a ninth via.

[0267] In an exemplary embodiment, in the display substrate provided in Figures 10A and 11A, the orthographic projection of the third control signal line GateL3 connected to at least one sensor assembly on the substrate is located on the side away from the orthographic projection of the second control signal line GateL2 connected to at least one sensor assembly on the substrate.

[0268] In an exemplary embodiment, in the display substrate provided in FIG10A and FIG11A, the shape of the first control signal line GateL1 can be a line shape in which the main body extends along the second direction D2.

[0269] In an exemplary embodiment, in the display substrate provided in FIG10A, the orthographic projection of the first control signal line GateL1 connected to at least one sensor assembly on the substrate may be located between the orthographic projections of at least one of the first and second transistors of the at least one sensor assembly on the substrate and the orthographic projections of at least one of the third and fourth transistors on the substrate.

[0270] In an exemplary embodiment, in the display substrate provided in FIG10A, the orthographic projection of the first control signal line GateL1 connected to at least one sensor assembly on the substrate at least partially overlaps with the orthographic projection of the control electrode of the first transistor of at least one sensor assembly on the substrate.

[0271] In an exemplary embodiment, in the display substrate provided in FIG11A, the orthographic projection of the first control signal line GateL1 connected to at least one sensor component on the substrate may be located on the side of the orthographic projection of at least one sensor component on the substrate that is close to the orthographic projection of the second adjacent sensor component on the substrate.

[0272] In an exemplary embodiment, in the display substrate provided in FIG11A, the orthographic projection of the first control signal line connected to at least one sensor component on the substrate is located on the same side of the orthographic projection of at least two of the first transistor, second transistor, third transistor and fourth transistor of at least one sensor component on the substrate, and there is no overlapping area with the orthographic projection of the control electrode of the first transistor of at least one sensor component on the substrate.

[0273] In an exemplary embodiment, the orthographic projection of at least one bias connection line on the substrate lies between the orthographic projections of the two first control signal lines on the substrate.

[0274] In an exemplary embodiment, in the display substrate provided in FIG11A, at least a portion of at least one first control signal line GateL1 is disposed around a portion of the periphery of a first connection structure of at least one bias connection line.

[0275] In an exemplary embodiment, in the display substrate provided in FIG10A, in at least one sensor assembly, the second electrode 34 of the third transistor and the second electrode 44 of the fourth transistor are integrally formed. The first electrode 13 of the first transistor, the first electrode 23 of the second transistor, the first electrode 33 of the third transistor, the first electrode 43 of the fourth transistor, and the second electrode plate C2 of the capacitor are separately disposed.

[0276] In an exemplary embodiment, in the display substrate provided in FIG11A, the first electrode 33 of the third transistor of the sensor assembly located in the same column and in the 2m-1 row and the first electrode 33 of the third transistor of the sensor assembly located in the 2m-2 row are the same electrode.

[0277] In an exemplary embodiment, in the display substrate provided in FIG10A, the first electrode 13 of the first transistor of the sensor assembly located in the same column and in the 2m-1 row and the second electrode 13 of the first transistor of the sensor assembly located in the 2m row are the same electrode. The second electrode C2 of the capacitor of the sensor assembly located in the same column and in the 2m-1 row and the second electrode C2 of the capacitor of the sensor assembly located in the 2m row are the same electrode.

[0278] In an exemplary embodiment, in the display substrate provided in FIG11A, in at least one sensor assembly, the second electrode 34 of the third transistor and the second electrode 44 of the fourth transistor are integrally formed, and the first electrode 13 of the first transistor and the second electrode plate C2 of the capacitor are integrally formed. The first electrode 23 of the second transistor, the first electrode 33 of the third transistor, and the first electrode 43 of the fourth transistor are separately provided.

[0279] In an exemplary embodiment, in the display substrate provided in FIG11A, the first electrode 13 (also the second plate C2 of the capacitor) of the first transistor of the sensor assembly located in the same column and in the 2m-1 row and the second electrode 13 (also the second plate C2 of the capacitor) of the first transistor of the sensor assembly located in the 2m row are the same electrode.

[0280] In an exemplary embodiment, in the display substrate provided in Figures 10A and 11A, the first electrode 13 of the first transistor is shaped as a strip extending along the first direction D1. The second electrode C2 of the capacitor may be rectangular. The orthographic projection of the second electrode of the capacitor onto the substrate at least partially overlaps with the orthographic projection of the first electrode of the capacitor onto the substrate.

[0281] In the display substrate provided in Figure 10A, the first electrode 13 of the first transistor in at least one sensor assembly is electrically connected to the first region of the active pattern of the first transistor through a first via, and is electrically connected to the constant voltage signal line through a twelfth via. The second electrode of the capacitor in at least one sensor assembly is electrically connected to the constant voltage signal line through a twelfth via.

[0282] In the display substrate provided in FIG11A, the first electrode 13 of the first transistor in at least one sensor assembly (which is also the second electrode C2 of the capacitor) is electrically connected to the first region of the active pattern of the first transistor through a first via and electrically connected to the constant voltage signal line through a twelfth via.

[0283] In an exemplary embodiment, in the display substrate provided in Figures 10A and 11A, the first electrode 23 of the second transistor is shaped as a strip extending along the second direction D2. The first electrode 23 of the second transistor in at least one sensor assembly is electrically connected to the first region of the active pattern of the second transistor through a second via, and electrically connected to the signal readout line through an eleventh via.

[0284] In an exemplary embodiment, in the display substrate provided in Figures 10A and 11A, the first electrode 33 of the third transistor is shaped as a strip extending along the second direction D2. The first electrode 33 of the third transistor in at least one sensor assembly is electrically connected to the first region of the active pattern of the third transistor through a third via, and is electrically connected to the bias voltage line through a ninth via.

[0285] In an exemplary embodiment, in the display substrate provided in Figures 10A and 11A, the second electrode 34 of the third transistor (which is also the second electrode 44 of the fourth transistor) is shaped as a strip extending along a first direction D1. The second electrode 34 of the third transistor (which is also the second electrode 44 of the fourth transistor) in at least one sensor assembly is electrically connected to the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor) through a fourth via.

[0286] In an exemplary embodiment, in the display substrate provided in Figures 10A and 11A, the first electrode 43 of the fourth transistor is shaped as a strip extending along the second direction D2. The first electrode 43 of the fourth transistor in at least one sensor assembly is electrically connected to the second region of the active pattern of the fourth transistor through a fifth via, and electrically connected to the control electrode (which is also the first plate of the capacitor) of the first transistor through a sixth via.

[0287] In an exemplary embodiment, the bias connection line BIASL2, the first control signal line GateL1, the second control signal line GateL2, and the third control signal line GateL3 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0288] In an exemplary embodiment, the line width of the bias connection line BIASL2 along the first direction D1 is greater than the line width of at least one of the first control signal lines GateL1, the second control signal line GateL2, and the third control signal line GateL3 along the first direction D1.

[0289] (4) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and using a patterning process to pattern the third insulating film and the first planarization film to form a third insulating layer covering the second conductive layer pattern and a first planarization layer disposed on the third insulating layer. The first planarization layer is provided with a plurality of vias, as shown in Figures 22 and 23. Figure 22 is a schematic diagram of the first planarization layer pattern formed in Figure 10A, and Figure 23 is a schematic diagram of the first planarization layer pattern formed in Figure 11A.

[0290] In an exemplary embodiment, the plurality of vias on the first planarization layer pattern includes at least: a thirteenth via V13.

[0291] In an exemplary embodiment, the orthogonal projection of the thirteenth via V13 onto the substrate is located within the orthogonal projection of the second electrode of the third transistor (which is also the second electrode of the fourth transistor) onto the substrate. The third insulating layer within the thirteenth via V13 is etched away, exposing the surface of the second electrode of the third transistor (which is also the second electrode of the fourth transistor). The thirteenth via V13 is configured to connect the via to the second electrode of the third transistor (which is also the second electrode of the fourth transistor) of the subsequently formed connection electrode.

[0292] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer pattern disposed on a fourth insulating layer, as shown in Figures 24, 25, and 26. Figure 24 is a schematic diagram of the third conductive layer pattern in Figures 10A and 11A, Figure 25 is a schematic diagram of Figure 10A after the third conductive layer pattern is formed, and Figure 26 is a schematic diagram of Figure 11A after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0293] In an exemplary embodiment, the third conductive layer pattern includes at least a connection electrode AL located on at least one sensor component.

[0294] In an exemplary embodiment, the connecting electrode AL can be a strip-shaped portion extending along the first direction D1. The connecting electrode AL of at least one sensor assembly is connected to the second terminal (which is also the second terminal of the fourth transistor) of at least one sensor assembly via a thirteenth via.

[0295] In an exemplary embodiment, the connection electrode AL is connected to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) through the twentieth via.

[0296] (6) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film using a patterning process to form a second planarization layer covering the third conductive layer pattern, wherein a plurality of vias are provided on the second planarization layer. As shown in Figures 27 and 28, Figure 27 is a schematic diagram of Figure 10A after the formation of the second planarization layer, and Figure 28 is a schematic diagram of Figure 11A after the formation of the second planarization layer.

[0297] In an exemplary embodiment, the plurality of vias on the second planarization layer pattern includes at least a fourteenth via V14.

[0298] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the connecting electrode on the substrate, the fourteenth via V14 exposes the surface of the connecting electrode, and the fourteenth via V14 is configured to connect the via to the connecting electrode of the second electrode of the subsequently formed piezoelectric transducer.

[0299] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern disposed on the second planarization layer, as shown in Figures 29, 30 and 31. Figure 29 is a schematic diagram of the fourth conductive layer pattern in Figures 10A and 11A, Figure 30 is a schematic diagram of Figure 10A after the fourth conductive layer pattern is formed, and Figure 31 is a schematic diagram of Figure 11A after the fourth conductive layer pattern is formed.

[0300] In an exemplary embodiment, the fourth conductive layer pattern includes at least: a second electrode 220 of at least one piezoelectric transducer.

[0301] In an exemplary embodiment, the second electrode 220 of at least one piezoelectric transducer may be rectangular in shape. The second electrode 220 of at least one piezoelectric transducer is connected to the connection electrode of at least one sensor assembly through a fourteenth via.

[0302] In an exemplary embodiment, the orthographic projection of the second electrode 220 of at least one piezoelectric transducer onto the substrate covers the orthographic projection of at least one transistor and at least one capacitor in at least one sensor assembly onto the substrate.

[0303] (8) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a piezoelectric material film on the substrate on which the aforementioned pattern is formed, patterning the piezoelectric material film using a patterning process to form a piezoelectric material layer pattern disposed on the fourth conductive layer, depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer pattern disposed on the piezoelectric material layer.

[0304] The display substrate may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a first planarization layer, a third conductive layer, a second planarization layer, a fourth conductive layer, a piezoelectric material layer, and a fifth conductive layer, which are sequentially disposed on the substrate.

[0305] In an exemplary embodiment, the semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0306] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0307] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0308] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of organic materials, such as resin.

[0309] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0310] In an exemplary embodiment, the display substrate may further include a plurality of sub-pixels. At least one sub-pixel may include at least one pixel driving circuit and a light-emitting device, wherein the pixel driving circuit is configured to drive the light-emitting device to emit light.

[0311] In an exemplary embodiment, multiple sub-pixels can be located on the same side of the substrate or on different sides of the substrate with multiple sensor components, which can not only achieve the display effect of the display substrate, but also realize fingerprint recognition.

[0312] In an exemplary embodiment, when multiple sub-pixels and multiple sensor components are located on the same side of the substrate, the multiple sensor components are positioned on the side of the substrate closer to the multiple sub-pixels. This disclosure integrates multiple sensor components into a display substrate, achieving a high degree of integration.

[0313] In an exemplary embodiment, the display substrate may be disposed in the display device.

[0314] In exemplary embodiments, the display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are readily understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention. Implementation of this display device can refer to the aforementioned embodiment of the embedded touchscreen; repeated details will not be elaborated upon.

[0315] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0316] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0317] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A sensor assembly, comprising: A piezoelectric transducer and a signal processing circuit, wherein the signal processing circuit includes: a driving sub-circuit, a reading sub-circuit, a node control sub-circuit, and a voltage regulating sub-circuit; The driving sub-circuit is electrically connected to the constant voltage signal terminal, the first node, and the second node, respectively, and is configured to provide a signal to the second node under the control of the signals from the constant voltage signal terminal and the first node. The voltage regulator sub-circuit is electrically connected to the constant voltage signal terminal and the first node respectively, and is configured to store the voltage difference between the signals of the constant voltage signal terminal and the first node. The reading sub-circuit is electrically connected to the first control signal terminal, the signal reading terminal, and the second node, respectively, and is configured to provide the signal of the second node to the signal reading terminal under the control of the signal of the first control signal terminal. The node control sub-circuit is electrically connected to the second control signal terminal, the third control signal terminal, the bias voltage terminal, the first node, and the third node, respectively, and is configured to provide the bias voltage terminal signal to the third node and the third node signal to the first node under the control of the signals of the second control signal terminal and the third control signal terminal. The piezoelectric transducer is electrically connected to the third node and the transmitting signal terminal, respectively. It is configured to emit ultrasonic waves under the control of the signal at the transmitting signal terminal, and convert the ultrasonic wave signal reflected by the fingerprint to be identified into an electrical signal and transmit it to the third node.

2. The sensor assembly according to claim 1, wherein, The node control sub-circuit includes: a first control sub-circuit and a second control sub-circuit; The first control sub-circuit is electrically connected to the second control signal terminal, the bias voltage terminal, and the third node, respectively, and is configured to provide the bias voltage terminal signal to the third node under the control of the signal at the first control signal terminal; The second control sub-circuit is electrically connected to the third control signal terminal, the first node, and the third node, respectively, and is configured to provide the signal of the third node to the first node under the control of the signal of the second control signal terminal.

3. The sensor assembly according to claim 1, wherein, The voltage regulator circuit includes a capacitor, which includes a first plate and a second plate. The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the constant voltage signal terminal.

4. The sensor assembly according to claim 1, wherein, The driving sub-circuit includes a first transistor, and the reading sub-circuit includes a second transistor; The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the constant voltage signal terminal, and the second electrode of the first transistor is electrically connected to the second node. The control electrode of the second transistor is electrically connected to the first control signal terminal, the first electrode of the second transistor is electrically connected to the signal reading terminal, and the second electrode of the second transistor is electrically connected to the second node.

5. The sensor assembly according to claim 2, wherein, The first control sub-circuit includes a third transistor, and the second control sub-circuit includes a fourth transistor; The control electrode of the third transistor is electrically connected to the second control signal terminal, the first electrode of the third transistor is electrically connected to the bias voltage terminal, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the third control signal terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the third node.

6. The sensor assembly according to claim 1, wherein, The voltage regulator sub-circuit includes a capacitor, the capacitor including a first plate and a second plate; the driving sub-circuit includes a first transistor; the reading sub-circuit includes a second transistor; and the node control sub-circuit includes a third transistor and a fourth transistor. The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the constant voltage signal terminal, and the second electrode of the first transistor is electrically connected to the second node. The control electrode of the second transistor is electrically connected to the first control signal terminal, the first electrode of the second transistor is electrically connected to the signal reading terminal, and the second electrode of the second transistor is electrically connected to the second node. The control electrode of the third transistor is electrically connected to the second control signal terminal, the first electrode of the third transistor is electrically connected to the bias voltage terminal, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the third control signal terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the third node. The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the constant voltage signal terminal.

7. The sensor assembly according to claim 1, wherein, During the fingerprint recognition process, the time periods during which the signals from the second control signal terminal and the third control signal terminal are at valid level signals at least partially overlap. The time period during which the signal at the first control signal terminal is at an effective level does not overlap with the time period during which at least one of the second and third control signal terminals is at an effective level.

8. The sensor assembly according to claim 7, wherein, The time period during which the signal at the second control signal terminal is at an effective level is within the range of the time period during which the signal at the third control signal terminal is at an effective level.

9. A display substrate, comprising: A substrate and a plurality of sensor assemblies as described in any one of claims 1 to 8 disposed on the substrate; The structures of sensor assemblies located in adjacent columns of the same row are symmetrically arranged with respect to the virtual straight line extending along the second direction, and the structures of sensor assemblies located in adjacent rows of the same column are symmetrically arranged with respect to the virtual line extending along the first direction, which intersects with the second direction.

10. The display substrate according to claim 9, further comprising: Multiple bias voltage lines are disposed on the substrate, at least one of which is electrically connected to the bias voltage terminal of at least one sensor assembly and extends at least partially along a first direction. The orthographic projection of the bias voltage line connected to the sensor assembly in row 2m-1 on the substrate is located on the side away from the orthographic projection of the sensor assembly in row 2m-1 on the substrate. The orthographic projection of the bias voltage line connected to the sensor assembly in row 2m on the substrate is located on the side away from the orthographic projection of the sensor assembly in row 2m-1 on the substrate. m is a positive integer greater than or equal to 1.

11. The display substrate according to claim 10, further comprising: Multiple bias connection lines are disposed on the substrate, at least one of which is electrically connected to the multiple bias voltage lines and extends at least partially along the second direction; Adjacent sensor components located in the same row as at least one sensor component include: a first adjacent sensor component and a second adjacent sensor component; The orthographic projection of the at least one bias connection line on the substrate lies between the orthographic projection of the at least one sensor assembly on the substrate and the orthographic projection of the second adjacent sensor assembly on the substrate.

12. The display substrate according to claim 11, wherein, The at least one bias connection line includes: a plurality of first connection structures and a plurality of second connection structures, the plurality of first connection structures and the plurality of second connection structures are alternately arranged, the orthographic projection of at least one first connection structure on the substrate overlaps with the orthographic projection of at least one bias voltage line on the substrate, and the orthographic projection of at least one second connection structure on the substrate is located between the orthographic projections of two bias voltage lines on the substrate. The length of the first connecting structure along the first direction is greater than the length of the second connecting structure along the first direction.

13. The display substrate according to claim 10, further comprising: Multiple signal reading lines are disposed on the substrate, at least one of which is electrically connected to the signal reading end of at least one sensor component and extends at least partially along a first direction; The orthographic projection of the signal readout line connected to at least one row of sensor components on the substrate lies between the orthographic projection of the bias voltage line connected to at least one row of sensor components on the substrate and the orthographic projection of at least one row of sensor components on the substrate.

14. The display substrate according to claim 9, further comprising: Multiple constant voltage signal lines are disposed on the substrate, at least one of which is electrically connected to the constant voltage signal terminal of at least one sensor assembly and extends at least partially along a first direction; The constant voltage signal line connected to the sensor assembly in row 2m-1 is the same signal line as the constant voltage signal line connected to the sensor assembly in row 2m. The orthographic projections of the sensor assembly in row 2m-1 and the constant voltage signal line connected to the sensor assembly in row 2m-1 on the substrate are located between the orthographic projections of the sensor assembly in row 2m-1 on the substrate and the orthographic projections of the sensor assembly in row 2m on the substrate, where m is a positive integer greater than or equal to 1.

15. The display substrate according to claim 9, further comprising: Multiple first control signal lines are disposed on the substrate, at least one of which is electrically connected to a first control signal terminal of at least one sensor assembly and extends at least partially along a second direction. The at least one sensor assembly includes: a first transistor to a fourth transistor. The orthographic projection of the first control signal line connected to the at least one sensor assembly on the substrate lies between the orthographic projections of at least one of the third and fourth transistors of the at least one sensor assembly on the substrate and the orthographic projections of at least one of the first and second transistors on the substrate, and at least partially overlaps with the orthographic projection of the control electrode of the first transistor on the substrate.

16. The display substrate according to claim 9, further comprising: Multiple first control signal lines are disposed on the substrate, at least one of which is electrically connected to the first control signal terminal of at least one sensor assembly and extends at least partially along the second direction; The at least one sensor component includes: a first transistor to a fourth transistor; The orthographic projection of the first control signal line connected to the at least one sensor assembly on the substrate is located on the same side of the orthographic projection of at least two of the first, second, third, and fourth transistors of the at least one sensor assembly on the substrate, and there is no overlap with the orthographic projection of the control electrode of the first transistor on the substrate.

17. The display substrate according to claim 16, further comprising: Multiple bias connection lines disposed on the substrate, at least one bias connection line including: at least one first connection structure, and adjacent sensor components located in the same row as at least one sensor component including: a first adjacent sensor component and a second adjacent sensor component; The orthographic projection of at least one first control signal line on the substrate lies between the orthographic projection of at least one sensor assembly on the substrate and the orthographic projection of the second adjacent sensor assembly on the substrate; At least one bias connection line is disposed between two first control signal lines, and a portion of the at least one first control signal line is disposed around a portion of at least one first connection structure of the bias connection line.

18. The display substrate according to claim 9, further comprising: Multiple second control signal lines are disposed on the substrate, at least one of which is electrically connected to the second control signal terminal of at least one sensor assembly and extends at least partially along the second direction; Adjacent sensor components located in the same row as at least one sensor component include: a first adjacent sensor component and a second adjacent sensor component; The orthographic projection of the second control signal line connected to the at least one sensor assembly on the substrate lies between the orthographic projection of the at least one sensor assembly on the substrate and the orthographic projection of the first adjacent sensor assembly on the substrate.

19. The display substrate according to claim 9, further comprising: Multiple second control signal lines and multiple third control signal lines are disposed on the substrate, at least one of the third control signal lines is electrically connected to the third control signal terminal of at least one sensor assembly, and extends at least partially along the second direction; Adjacent sensor components located in the same row as at least one sensor component include: a first adjacent sensor component and a second adjacent sensor component; The third control signal line connected to the at least one sensor assembly is the same signal line as the third control signal line connected to the first adjacent sensor assembly. The orthographic projection of the third control signal line connected to the at least one sensor assembly on the substrate is located on the side of the orthographic projection of the second control signal line connected to the at least one sensor assembly on the substrate that is away from the orthographic projection of the at least one sensor assembly on the substrate.

20. The display substrate according to claim 9, wherein, At least one sensor component includes: a first transistor to a fourth transistor and a capacitor; at least one transistor includes: an active pattern and a control electrode; The length of the active pattern of the third transistor along the first direction is greater than the length of the active pattern of at least one of the first transistor, the second transistor, and the fourth transistor along the first direction. The length of the control electrode of the first transistor along the second direction is greater than the length of the control electrode of at least one of the second transistor, the third transistor, and the fourth transistor along the second direction; The length of the capacitor along the second direction is greater than the length of the control electrode of the first transistor along the second direction.

21. The display substrate according to claim 9, further comprising: Multiple bias voltage lines, multiple bias connection lines, multiple signal reading lines, multiple constant voltage signal lines, multiple first control signal lines, multiple second control signal lines, and multiple third control signal lines are disposed on the substrate. At least one sensor component includes: a piezoelectric transducer, at least one transistor, and at least one capacitor. The at least one transistor includes: an active pattern, a control electrode, a first electrode, and a second electrode. The at least one capacitor includes: a first electrode plate and a second electrode plate. The piezoelectric transducer includes: a first electrode and a second electrode. The display substrate further includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially stacked on the substrate; The semiconductor layer includes: an active pattern of at least one transistor in at least one sensor assembly; The first conductive layer includes: multiple bias voltage lines, multiple signal readout lines, multiple constant voltage signal lines, and the control electrode of at least one transistor of at least one sensor component and the first plate of at least one capacitor; The second conductive layer includes: multiple bias connection lines, multiple first control signal lines, multiple second control signal lines, multiple third control signal lines, and the first and second electrodes of at least one transistor of at least one sensor assembly, and the second electrode plate of at least one capacitor. The third conductive layer includes: a connecting electrode, which is electrically connected to the second electrode of at least one transistor in at least one sensor assembly and the second electrode of a piezoelectric transducer, respectively. The fourth conductive layer includes: a second electrode of a piezoelectric transducer in at least one sensor assembly; The fifth conductive layer includes: at least one first electrode of a piezoelectric transducer in a sensor assembly.

22. The display substrate according to claim 21, wherein, The line width of the bias voltage line along the second direction is greater than the line width of at least one of the signal lines, namely the signal readout line and the constant voltage signal line, along the second direction. The line width of the bias connection line along the first direction is greater than the line width of at least one of the first control signal line, the second control signal line, and the third control signal line along the first direction.

23. A method for driving a sensor assembly, configured to drive the sensor assembly as claimed in any one of claims 1 to 8, the method comprising: The driving sub-circuit provides a signal to the second node under the control of the constant voltage signal terminal and the signal of the first node; The voltage regulator circuit stores the voltage difference between the constant voltage signal terminal and the signal at the first node; Under the control of the signal at the first control signal terminal, the reading sub-circuit provides the signal of the second node to the signal reading terminal; Under the control of the signals at the second and third control signal terminals, the node control sub-circuit provides the bias voltage terminal signal to the third node and the signal of the third node to the first node; Under the control of the signal at the transmitting end, the piezoelectric transducer emits ultrasonic waves and converts the ultrasonic signal reflected by the fingerprint to be identified into an electrical signal, which is then transmitted to the third node.

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