Display panel and display device

Abstract

A display panel (PNL) and a display device, relating to the technical field of display. The display panel (PNL) comprises pixel driving circuits (PDCs) arranged in an array; each PDC comprises a first transistor (M1), and the first transistor (M1) is a metal oxide transistor and has a top gate (M1GB) and a bottom gate (M1GA); the display panel (PNL) has a plurality of pixel driving circuit sets (PDCSs), and each PDCS comprises one PDC or a plurality of adjacent PDCs in a same row; and the display panel (PNL) is provided with first conductive structures (MA1) in one-to-one correspondence with the PDCSs, and in the PDCS, the top gate (M1GB) of the first transistor (M1) and the bottom gate (M1GA) of the first transistor (M1) are both connected to the corresponding first conductive structure (MA1). The display panel (PNL) can improve uniformity.

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] With the development of display technology, the application of LTPO (Low Temperature Polycrystalline Silicon Transistor + Metal Oxide Transistor) driving technology is becoming increasingly widespread. Metal Oxide Transistors have advantages such as uniform characteristics and low leakage current, and they are generally driven simultaneously through the top and bottom gates. Improving the synchronization of the top and bottom gate signals is of great significance for improving the uniformity of the display panel.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device that improve the uniformity of the display panel.

[0005] According to a first aspect of this disclosure, a display panel is provided, including an array of pixel driving circuits; the pixel driving circuit includes a first transistor, the first transistor being a metal-oxide transistor and having a top gate and a bottom gate;

[0006] The display panel has multiple pixel driving circuit groups, each of which includes one pixel driving circuit or multiple adjacent pixel driving circuits in the same row.

[0007] The display panel is provided with a first conductive structure corresponding to each of the pixel driving circuit groups. The top gate and bottom gate of the first transistor in the pixel driving circuit group are both connected to the first conductive structure.

[0008] According to one embodiment of the present disclosure, the display panel includes a substrate, a second gate layer, a metal oxide semiconductor layer, a third gate layer, and a first source / drain metal layer stacked sequentially.

[0009] Wherein, the channel region of the first transistor is disposed in the metal oxide semiconductor layer, the bottom gate of the first transistor is disposed in the second gate layer, the top gate of the first transistor is located in the third gate layer, and the first conductive structure is located in the first source-drain metal layer.

[0010] Within the pixel driving circuit group, the bottom gate of the first transistor is electrically connected to the first conductive structure through a via, and the top gate of the first transistor is electrically connected to the first conductive structure through a via.

[0011] According to one embodiment of the present disclosure, the second gate layer is provided with a first trace that corresponds one-to-one with the pixel driving circuit row and extends along the row direction, and the bottom gate of each first transistor in the pixel driving circuit row is located on the corresponding first trace.

[0012] The third gate layer is provided with a second gate structure that corresponds one-to-one with each of the pixel driving circuit groups, and the top gate of each first transistor of the pixel driving circuit group is located in the second gate structure.

[0013] The second gate structure is electrically connected to the first trace through the first conductive structure.

[0014] According to one embodiment of the present disclosure, the first trace is electrically connected to the first conductive structure through a first via, and the second gate structure is electrically connected to the first conductive structure through a second via.

[0015] Alternatively, the first conductive structure may be electrically connected to both the first trace and the second gate structure via a third via, wherein the third via exposes a portion of the first trace and a portion of the second gate structure.

[0016] According to one embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, which is capable of controlling the magnitude of the driving current output by the pixel driving circuit according to the voltage on its gate.

[0017] The first source / drain metal layer further includes a second conductive structure, which is electrically connected to the gate of the driving transistor and to the second electrode of the first transistor; the second gate structure and the second conductive structure do not overlap.

[0018] According to one embodiment of the present disclosure, the third gate layer is provided with a second trace that corresponds one-to-one with the pixel driving circuit row and extends along the row direction, and the top gate of each first transistor in the pixel driving circuit row is located on the corresponding second trace.

[0019] The second gate layer is provided with a first gate structure corresponding to each of the pixel driving circuit groups, and the bottom gate of each first transistor of the pixel driving circuit group is located in the first gate structure.

[0020] The first gate structure and the second trace are electrically connected through the first conductive structure.

[0021] According to one embodiment of the present disclosure, the second trace is electrically connected to the first conductive structure through a second via, and the first gate structure is electrically connected to the first conductive structure through a first via.

[0022] Alternatively, the first conductive structure may be electrically connected to both the second trace and the first gate structure simultaneously through a third via, wherein the third via exposes a portion of the second trace and a portion of the first gate structure.

[0023] According to one embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, which is capable of controlling the magnitude of the driving current output by the pixel driving circuit according to the voltage on its gate.

[0024] The first source / drain metal layer further includes a second conductive structure, which is electrically connected to the gate of the driving transistor and to the second electrode of the first transistor; the first gate structure and the second conductive structure do not overlap.

[0025] According to one embodiment of the present disclosure, the second gate layer is provided with a first trace that corresponds one-to-one with the pixel driving circuit row and extends along the row direction, and the bottom gate of each first transistor in the pixel driving circuit row is located on the corresponding first trace.

[0026] The third gate layer is provided with a second trace that corresponds one-to-one with the pixel driving circuit row and extends along the row direction, and the top gate of each first transistor in the pixel driving circuit row is located on the corresponding second trace.

[0027] The first trace and the second trace are electrically connected through the first conductive structure.

[0028] According to one embodiment of the present disclosure, the first trace is electrically connected to the first conductive structure through a first via, and the second trace is electrically connected to the first conductive structure through a second via.

[0029] Alternatively, the first conductive structure may be electrically connected to both the first trace and the second trace simultaneously through a third via, wherein the third via exposes a portion of the first trace and a portion of the second trace.

[0030] According to one embodiment of the present disclosure, the display panel further includes an initialization voltage auxiliary trace extending along the column direction; the display panel is provided with an initialization voltage trace extending along the row direction, the initialization voltage trace being used to apply an initialization voltage to the pixel driving circuit; the initialization voltage auxiliary trace and the initialization voltage trace applying the same initialization voltage are electrically connected to each other;

[0031] At least a portion of the first conductive structure overlaps with the initialization voltage auxiliary trace.

[0032] According to one embodiment of the present disclosure, the display panel is provided with an initialization voltage auxiliary trace extending along the column direction; the display panel is provided with an initialization voltage trace extending along the row direction, the initialization voltage trace being used to apply an initialization voltage to the pixel driving circuit; the initialization voltage auxiliary trace and the initialization voltage trace applying the same initialization voltage are electrically connected to each other;

[0033] At least a portion of the first conductive structure is spaced apart from the adjacent initialization voltage auxiliary trace by one pixel driving circuit in the row direction.

[0034] According to one embodiment of the present disclosure, in the same pixel driving circuit group, the bottom gates of the first transistors are interconnected, and the top gates of the first transistors are interconnected.

[0035] According to another aspect of this disclosure, a display device is provided, including the display panel described above.

[0036] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0038] Figure 1 is a schematic diagram of the structure of the display panel in one embodiment of this disclosure.

[0039] Figure 2 is a partial cross-sectional view of the display panel in one embodiment of this disclosure.

[0040] Figure 3 is a schematic diagram of the equivalent circuit of the pixel driving circuit in one embodiment of this disclosure.

[0041] Figure 4 is a schematic diagram of the driving principle of a display panel for a metal oxide transistor in related technologies.

[0042] Figure 5 is a schematic diagram of the driving principle of the first transistor in the first embodiment of this disclosure.

[0043] Figure 6 is a partial structural schematic diagram of the second gate layer, the metal oxide semiconductor layer, the third gate layer, and the first source / drain metal layer in an example of the first embodiment of this disclosure.

[0044] Figure 7 is a partial structural schematic diagram of the second gate layer and the first source / drain metal layer in one example of the first embodiment of this disclosure.

[0045] Figure 8 is a partial structural schematic diagram of the third gate layer and the first source / drain metal layer in one example of the first embodiment of this disclosure.

[0046] Figure 9 is a partial structural schematic diagram of the second gate layer, the metal oxide semiconductor layer, the third gate layer, and the first source / drain metal layer in another example of the first embodiment of this disclosure.

[0047] Figure 10 is a partial structural schematic diagram of the second gate layer and the first source / drain metal layer in another example of the first embodiment of this disclosure.

[0048] Figure 11 is a partial structural schematic diagram of the third gate layer and the first source / drain metal layer in another example of the first embodiment of this disclosure.

[0049] Figure 12 is a schematic diagram of the driving principle of the first transistor in the second embodiment of this disclosure.

[0050] Figure 13 is a partial structural schematic diagram of the second gate layer, the metal oxide semiconductor layer, the third gate layer and the first source / drain metal layer in one example of the second embodiment of this disclosure.

[0051] Figure 14 is a partial structural schematic diagram of the second gate layer and the first source / drain metal layer in one example of the second embodiment of this disclosure.

[0052] Figure 15 is a partial structural schematic diagram of the third gate layer and the first source / drain metal layer in one example of the second embodiment of this disclosure.

[0053] Figure 16 is a partial structural schematic diagram of the second gate layer, the metal oxide semiconductor layer, the third gate layer and the first source / drain metal layer in another example of the second embodiment of this disclosure.

[0054] Figure 17 is a partial structural schematic diagram of the second gate layer and the first source / drain metal layer in another example of the second embodiment of this disclosure.

[0055] Figure 18 is a partial structural schematic diagram of the third gate layer and the first source / drain metal layer in another example of the second embodiment of this disclosure.

[0056] Figure 19 is a schematic diagram of the driving principle of the first transistor in the third embodiment of this disclosure.

[0057] Figure 20 is a partial structural schematic diagram of the second gate layer, the metal oxide semiconductor layer, the third gate layer and the first source / drain metal layer in one example of the third embodiment of this disclosure.

[0058] Figure 21 is a partial structural schematic diagram of the second gate layer and the first source / drain metal layer in one example of the third embodiment of this disclosure.

[0059] Figure 22 is a partial structural schematic diagram of the third gate layer and the first source / drain metal layer in one example of the third embodiment of this disclosure.

[0060] Figure 23 is a partial structural schematic diagram of the second gate layer, the metal oxide semiconductor layer, the third gate layer and the first source / drain metal layer in another example of the third embodiment of this disclosure.

[0061] Figure 24 is a partial structural schematic diagram of the second gate layer and the first source / drain metal layer in another example of the third embodiment of this disclosure.

[0062] Figure 25 is a partial structural schematic diagram of the third gate layer and the first source / drain metal layer in another example of the third embodiment of this disclosure.

[0063] Figure 26 is a schematic diagram showing the distribution of the first pixel driving circuit area and the second pixel driving circuit area in one embodiment of this disclosure.

[0064] Figure 27 is a schematic diagram showing the distribution of the first conductive structure in one embodiment of this disclosure.

[0065] Figure 28 is a schematic diagram showing the distribution of the first conductive structure in another embodiment of this disclosure.

[0066] Figure 29 is a schematic diagram of the distribution of the initialization voltage auxiliary traces in another embodiment of this disclosure.

[0067] Figure 30 is a schematic diagram of the structure of the metal light-shielding layer in one example of this disclosure.

[0068] Figure 31 is a schematic diagram of the stacked structure of a low-temperature polycrystalline silicon semiconductor layer and a first source / drain metal layer in one example of this disclosure.

[0069] Figure 32 is a schematic diagram of the structure of the first gate layer in one example of this disclosure.

[0070] Figure 33 is a schematic diagram of the stacked structure of a low-temperature polycrystalline silicon semiconductor layer and a first gate layer in one example of this disclosure.

[0071] Figure 34 is a schematic diagram of the stacked structure of the first source / drain metal layer and the first gate layer in one example of this disclosure.

[0072] Figure 35 is a schematic diagram of the structure of the second gate layer in one example of this disclosure.

[0073] Figure 36 is a schematic diagram of the stacked structure of the first source / drain metal layer and the second gate layer in one example of this disclosure.

[0074] Figure 37 is a schematic diagram of the stacked structure of a metal oxide semiconductor layer and a second gate layer in one example of this disclosure.

[0075] Figure 38 is a schematic diagram of a stacked structure of a metal oxide semiconductor layer and a first source / drain metal layer in one example of this disclosure.

[0076] Figure 39 is a schematic diagram of the structure of the third gate layer in one example of this disclosure.

[0077] Figure 40 is a schematic diagram of the stacked structure of a metal oxide semiconductor layer and a third gate layer in one example of this disclosure.

[0078] Figure 41 is a schematic diagram of the stacked structure of the first source / drain metal layer and the third gate layer in one example of this disclosure.

[0079] Figure 42 is a schematic diagram of the stacked structure of the second gate layer, the third gate layer, the metal oxide semiconductor layer and the first source / drain metal layer in one example of the present disclosure.

[0080] Figure 43 is a schematic diagram of the structure of the second source / drain metal layer in one example of this disclosure.

[0081] Figure 44 is a schematic diagram of the stacked structure of the first source / drain metal layer and the second source / drain metal layer in one example of this disclosure. Detailed Implementation

[0082] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0083] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0084] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0085] In this embodiment, the thin-film transistor has an active layer. The active layer is located within the semiconductor layer and includes a channel region and source and drain electrodes located on opposite sides of the channel region. The channel region retains semiconductor characteristics, and both the source and drain electrodes are partially or completely conductive. In this embodiment, in cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged; that is, the "source" and "drain" can be interchanged. In this embodiment, for any transistor, one of the "first electrode" and the "second electrode" is referred to as the source of the transistor, and the other is referred to as the drain of the transistor.

[0086] In this embodiment, the channel region of the transistor has a length direction and a width direction. The length direction of the channel region of the transistor refers to the direction in which current mainly flows, and the width direction of the channel region of the transistor is perpendicular to the direction in which current flows. Along the length direction of the channel region of the transistor, the active layer of the transistor sequentially includes a first electrode, a channel region, and a second electrode.

[0087] This disclosure provides a display panel PNL, as shown in FIG1. ​​The display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA, for example, the peripheral area BB surrounds the display area AA. In the display area AA, the display panel PNL is provided with an array of display units UU, each display unit UU including a sub-pixel PX and a pixel driving circuit PDC driving the sub-pixel PX. The display panel PNL does not provide display units UU in the peripheral area BB, or the provided display units UU are not used for displaying images. Referring to FIG1, the display panel PNL is provided with a plurality of first scan signal traces GPL extending along the row direction DH in the display area AA, each first scan signal trace GPL corresponding to a row of display units. The pixel driving circuit PDC of each display unit UU in a row of display units is electrically connected to the corresponding first scan signal trace GPL. The display panel PNL is also provided with a plurality of data traces DL extending along the column direction DV in the display area AA, each data trace DL corresponding to a column of display units. Each display unit UU in the display unit column has its pixel drive circuit (PDC) electrically connected to its corresponding data trace (DL). Thus, each display unit UU's pixel drive circuit (PDC) is connected to a first scan signal trace (GPL) and a data trace (DL). When a scan signal is applied to the first scan signal trace (GPL), the driving voltage applied to the data trace (DL) is written into the pixel drive circuit (PDC), allowing the pixel drive circuit (PDC) to control the brightness of the sub-pixel (PX) based on the written driving voltage.

[0088] Optionally, the pixel driving circuit PDC includes at least a data writing transistor, a driving transistor, and a storage capacitor. The gate of the driving transistor can be electrically connected to one electrode plate of the storage capacitor. The source of the data writing transistor can be electrically connected to the data trace DL, and the gate of the data writing transistor can be electrically connected to the first scan signal trace GPL. The pixel driving circuit PDC is configured such that when a scan signal is applied to the first scan signal trace GPL, the data writing transistor is turned on, thereby causing the driving voltage on the data trace DL to be written to the gate of the driving transistor and the storage capacitor. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel PX to emit light under the control of the voltage on its gate. It is understood that the pixel driving circuit PDC of this disclosure embodiment may also include other transistors or capacitors to give the pixel driving circuit PDC better driving performance. For example, the pixel driving circuit PDC can be a 7T1C (7 thin film transistors, thin film transistor TFTs and a storage capacitor), an 8T1C (8 thin film transistors, thin film transistor TFTs and a storage capacitor) or a pixel driving circuit PDC with other architectures.

[0089] In this embodiment of the disclosure, the sub-pixels PX in the display panel PNL are current-driven self-emissive elements, such as thin-film self-emissive elements. For example, the sub-pixels PX are OLED, PLED, QLED, etc. Furthermore, the sub-pixels PX located in the display area AA include sub-pixels PX of various colors. For example, the sub-pixels PX include red sub-pixels for emitting red light, green sub-pixels for emitting green light, and blue sub-pixels for emitting blue light. It is understood that in other embodiments of this disclosure, the sub-pixels PX in the display area AA may also be of only one color, or may have sub-pixels PX of other colors (e.g., yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0090] In one embodiment of this disclosure, referring to FIG2, the display panel PNL may include a substrate SBT, a driving layer DRL, and a pixel layer PXL stacked sequentially. The pixel layer PXL is provided with sub-pixels PX, and the driving layer DRL is provided with a pixel driving circuit PDC for driving the sub-pixels PX. Each sub-pixel PX can emit light under the drive of the pixel driving circuit PDC to display an image.

[0091] Optionally, the substrate SBT can be an inorganic material substrate or an organic material substrate; of course, it can also be a composite substrate formed by stacking inorganic and organic material substrates. For example, in some embodiments of this disclosure, the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In other embodiments of this disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof. In other embodiments of this disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT may include polyimide.

[0092] Optionally, in the driving layer DRL, any pixel driving circuit PDC may include a thin-film transistor (TFT) and a storage capacitor. Further, the TFT can be selected from top-gate, bottom-gate, or dual-gate TFTs; the active layer of the TFT can be made of amorphous silicon, low-temperature polycrystalline silicon, metal-oxide-semiconductor, organic semiconductor, carbon nanotube, or other types of semiconductor materials; the TFT can be an N-type or P-type TFT.

[0093] It is understood that any two transistors in a pixel driving circuit can be of the same or different types. For example, in some embodiments, some transistors in a pixel driving circuit can be N-type transistors and some transistors can be P-type transistors. Further exemplarily, in other embodiments, in a pixel driving circuit, the active layer material of some transistors can be low-temperature polycrystalline silicon semiconductor material, and the active layer material of some transistors can be metal-oxide-semiconductor material.

[0094] Optionally, the driving layer DRL may include a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric, a source / drain metal layer, a planarization layer, etc., stacked between the substrate SBT and the pixel layer PXL. Each thin-film transistor and storage capacitor can be formed from the semiconductor layer, gate insulating layer, gate layer, interlayer dielectric, source / drain metal layer, etc. The positional relationship of each layer can be determined according to the thin-film transistor's layer structure. Further, the semiconductor layer can be used to form the channel region of the transistor, and can also be used to form partial traces or conductive structures if necessary. The gate layer can be used to form one or more gate layer traces such as scan signal traces, reset signal traces, and light emission control signal traces, or it can be used to form the gate of the transistor, or it can be used to form part or all of the electrode plates of the storage capacitor. The source / drain metal layer can be used to form data traces, power supply voltage traces, etc., or it can be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of this disclosure, the driving layer DRL may also include other layers as needed, such as a light-shielding layer located between the semiconductor layer and the substrate SBT. Depending on the requirements, any one of the aforementioned semiconductor layers, gate layers, source / drain metal layers, etc., can be multiple layers. For example, the driving layer DRL may include two different semiconductor layers, or two or three source / drain metal layers, or two or three gate layers. Correspondingly, the insulating layers (e.g., gate insulating layer, interlayer dielectric layer, planarization layer, etc.) in the driving layer DRL can be adaptively increased or decreased, or new insulating layers can be added as needed. In the embodiments of this disclosure, the driving layer DRL includes at least a metal oxide semiconductor layer OSCL.

[0095] Optionally, the driving layer DRL may also include a passivation layer, which may be disposed on the surface of the source / drain metal layer away from the substrate SBT, in order to protect the source / drain metal layer.

[0096] As an example, referring to Figure 2, the driving layer DRL may include a metal light-shielding layer BSM, a first inorganic buffer layer BUF1, a low-temperature polysilicon semiconductor layer PSCL, a first gate insulating layer GI1, a first gate layer GT1, a second inorganic buffer layer BUF2, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer OSCL, a third gate insulating layer GI3, a third gate layer GT3, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, and a second planarization layer PLN2, stacked sequentially.

[0097] As another example, the driving layer DRL may also include a third source / drain metal layer SD3 and a third planarization layer PLN3 located on the side of the second planarization layer PLN2 away from the substrate SBT.

[0098] Referring to Figure 2, the light-emitting elements in the pixel layer PXL are thin-film light-emitting elements, which may include two electrodes stacked together and light-emitting functional units sandwiched between the two electrodes. For example, referring to Figure 2, the pixel layer PXL may include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML stacked sequentially. The pixel electrode layer PEL has multiple pixel electrodes in the display area of ​​the display panel; the portion of the light-emitting functional layer EFL connected to the pixel electrodes serves as the light-emitting functional unit of the light-emitting element; and the common electrode layer COML serves as the common electrode and is electrically connected to the light-emitting functional units of each light-emitting element.

[0099] Furthermore, the pixel layer PXL may also include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting functional layer EFL. The pixel definition layer PDL has multiple through-holes that correspond one-to-one with the multiple pixel electrodes, with each pixel opening exposing at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a portion of the internal region of the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective region of the pixel electrode (the region directly connected to the light-emitting functional unit), thereby defining the light-emitting region and light-emitting area of ​​the light-emitting element. The light-emitting functional layer EFL at least covers the pixel electrode exposed by the pixel definition layer PDL. The common electrode layer COML may cover the light-emitting functional layer EFL in the display area. The pixel electrodes and the common electrode layer COML provide charge carriers such as electrons and holes to the light-emitting functional layer EFL, causing the light-emitting functional layer EFL to emit light. The portion of the light-emitting functional layer EFL located between the pixel electrodes and the common electrode layer COML can serve as a light-emitting functional unit. The pixel electrodes, the common electrode layer COML, and the light-emitting functional unit form a light-emitting element. In this design, one of the pixel electrode and the common electrode layer COML serves as the anode of the light-emitting element, and the other serves as the cathode of the light-emitting element.

[0100] Optionally, referring to Figure 2, the display panel PNL may also have a thin-film encapsulation layer (TFE). The TFE can be disposed on the surface of the pixel layer PXL away from the substrate SBT. In one example, the TFE may include alternating layers of inorganic and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PXL and causing material aging in the pixel layer PXL. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer.

[0101] In the pixel driving circuit illustrated in Figure 3, the pixel driving circuit includes a gate reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, an electrode reset transistor T7, and a source reset transistor T8. The threshold compensation transistor T2 is an N-type thin-film transistor, such as a metal-oxide-semiconductor thin-film transistor. The driving transistor T3 and the data writing transistor T4 are P-type transistors, such as P-type low-temperature polycrystalline silicon thin-film transistors. Specifically, the second electrode of threshold compensation transistor T2, the first electrode CP1 of storage capacitor, and the gate of driving transistor T3 (which can be reused as the first electrode CP1 of storage capacitor) are electrically connected to the first node N1; the second electrode of the first light-emitting control transistor T5, the second electrode of data writing transistor T4, the second electrode of source reset transistor T8, and the first electrode of driving transistor T3 are electrically connected to the second node N2; the second electrode of driving transistor T3, the first electrode of threshold compensation transistor T2, the second electrode of gate reset transistor T1, and the first electrode of second light-emitting control transistor T6 are electrically connected to the third node N3; the second electrode of second light-emitting control transistor T6 and the second electrode of electrode reset transistor T7 are electrically connected to the fourth node N4 and to the light-emitting element; the first electrode of first light-emitting control transistor T5 and the second electrode CP2 of storage capacitor are electrically connected to the driving power supply voltage terminal (used to load the driving power supply voltage VDD); the first electrode of data writing transistor T4 is electrically connected to the data voltage terminal (used to load the data voltage Vdata); the first electrode of source reset transistor T8 is electrically connected to the data voltage terminal (used to load the data voltage Vdata); and the first electrode of source reset transistor T8 is electrically connected to the data voltage terminal (used to load the data voltage Vdata). The first transistor T1 is electrically connected to the third initialization voltage terminal (for loading the third initialization voltage Vinit3); the first terminal of the first transistor T1 is electrically connected to the first initialization voltage terminal (for loading the first initialization voltage Vinit1); the first terminal of the electrode reset transistor T7 is electrically connected to the second initialization voltage terminal (for loading the second initialization voltage Vinit2); the gate of the first transistor T1 is electrically connected to the first reset signal terminal (for loading the first reset signal Reset_P); the gate of the threshold compensation transistor T2 is electrically connected to the second scan signal terminal (for loading the second scan signal Gate_N); the gate of the data writing transistor T4 is electrically connected to the first scan signal terminal (for loading the first scan signal Gate_P); the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both electrically connected to the light-emitting control signal terminal (for loading the light-emitting control signal EM); the gates of the electrode reset transistor T7 and the source reset transistor T8 are both electrically connected to the second reset signal terminal (for loading the second reset signal Reset_H).

[0102] It is understood that the pixel driving circuit PDC of the display panel PNL of this disclosure is not limited to the example in FIG3. In the display panel PNL of this disclosure, the pixel driving circuit PDC contains at least one metal oxide transistor. The metal oxide transistor includes a bottom gate, a gate insulating layer, an active layer (the channel region of the active layer is shown in FIG4, FIG5, FIG12, FIG19, etc.), a gate insulating layer, and a top gate stacked sequentially. FIG4 is a schematic diagram of the driving method of the metal oxide transistor by the display panel PNL in the related art. Referring to FIG4, in the related art, for the metal oxide transistors in the same pixel row, the display panel PNL is provided with a first trace LA and a second trace LB extending along the row direction DH; the first trace LA is electrically connected to the bottom gate of each metal oxide transistor, and the second trace LB is electrically connected to the top gate of each metal oxide transistor; the first trace LA and the second trace LB are electrically connected in the peripheral area BB through a via. Within the display area AA, although the first trace LA and the second trace LB carry the same signal, they transmit signals independently. Therefore, there is a difference in the RC delay of the signals carried on the first trace LA and the second trace LB.

[0103] The inventors discovered that the further the pixel drive circuit (PDC) is from the signal source terminals of the first trace (LA) and the second trace (LB), the more significant and non-negligible the difference in RC delay of the signal on the first trace (LA) and the second trace (LB). The inventors also found that the more pixels in a pixel row, the greater the load on the first trace (LA) and the second trace (LB), and the greater the difference in RC delay of the signal on the first trace (LA) and the second trace (LB). This RC delay of the signal on the first trace (LA) and the second trace (LB) leads to differences in the charging rate of the pixel drive circuit (PDC) at different locations, thus reducing display quality. In particular, for large-size display panels (PNL) and high-resolution display panels (PNL), such as for 2K display panels, the difference in charging rate caused by the difference in signal delay on the first trace (LA) and the second trace (LB) is even more pronounced.

[0104] In response, the display panel PNL provided in this disclosure improves the driving method of at least one metal-oxide transistor in the pixel driving circuit PDC. In this disclosure embodiment, the metal-oxide transistor whose driving method is improved is referred to as the first transistor M1. For example, when the pixel driving circuit PDC of the display panel PNL is the pixel driving circuit PDC shown in FIG3, the first transistor M1 is a threshold compensation transistor T2.

[0105] It is understandable that when the pixel driving circuit PDC has multiple metal-oxide transistors, the first transistor M1 can refer only to the metal-oxide transistor whose driving method has been improved. The driving methods of each metal-oxide transistor can be improved, or only the driving method of one metal-oxide transistor can be improved.

[0106] Referring to Figures 5 to 25, in this embodiment of the present disclosure, the first transistor M1 is a metal-oxide-semiconductor transistor and has a top gate and a bottom gate. The display panel PNL has multiple pixel driving circuit groups (PDCS), each PDCS including a pixel driving circuit PDC or multiple adjacent pixel driving circuits PDC in the same row. The display panel PNL is provided with a first conductive structure MA1 corresponding one-to-one with the pixel driving circuit groups (PDCS). The top gate M1GB and the bottom gate M1GA of the first transistor in each PDCS are both connected to the first conductive structure MA1; for example, the top gate M1GB and the bottom gate M1GA of the first transistor in each PDCS are electrically connected through the first conductive structure MA1.

[0107] In this embodiment of the disclosure, at least a portion of the display area AA, the bottom gate M1GA and the top gate M1GB of the first transistor are electrically connected via a first conductive structure MA1. Thus, the signal controlling the first transistor M1 (e.g., the second scan signal controlling the threshold compensation transistor T2) is not transmitted independently and without interference on the first trace LA and the second trace LB, but is synchronized when it encounters the first conductive structure MA1 within the display area AA. This ensures the same RC delay, eliminates the difference in charging rate of the pixel drive circuit PDC at different locations caused by RC delay differences, and improves the uniformity of the PNL display on the display panel.

[0108] In one embodiment of this disclosure, referring to FIG2, the display panel PNL includes a substrate SBT, a second gate layer GT2, a metal-oxide-semiconductor layer OSCL, a third gate layer GT3, and a first source-drain metal layer SD1, which are stacked sequentially. The channel region of the first transistor M1 is disposed in the metal-oxide-semiconductor layer OSCL, the bottom gate M1GA of the first transistor is disposed in the second gate layer GT2, the top gate M1GB of the first transistor is located in the third gate layer GT3, and the first conductive structure MA1 is located in the first source-drain metal layer SD1. Within the pixel driving circuit group PDCS, the bottom gate M1GA of the first transistor is electrically connected to the first conductive structure MA1 through a via, and the top gate M1GB of the first transistor is also electrically connected to the first conductive structure MA1 through a via.

[0109] In other words, the bottom gate M1GA and the top gate M1GB of the first transistor are electrically connected through the first conductive structure MA1, thereby ensuring that the RC delay of the signals on the bottom gate M1GA and the top gate M1GB of the first transistor are consistent. In this embodiment, it is not necessary to create an additional via between the second gate layer GT2 and the third gate layer GT3 to electrically connect the bottom gate M1GA and the top gate M1GB of the first transistor. Instead, vias can be formed during the patterning of the interlayer dielectric layer ILD, and the bottom gate M1GA and the top gate M1GB of the first transistor can be electrically connected via the first source / drain metal layer SD1. This can improve the driving method of the first transistor M1 without increasing the fabrication process.

[0110] In one example, within the same pixel drive circuit group PDCS, the bottom gates M1GA of the first transistors are interconnected, and the top gates M1GB of the first transistors are interconnected.

[0111] Figure 5 illustrates a first strategy for improving the driving method of the first transistor M1. Referring to Figures 5-11, the second gate layer GT2 is provided with a first trace LA that corresponds one-to-one with the pixel driving circuit row HPDC and extends along the row direction DH. The bottom gate M1GA of each first transistor in the pixel driving circuit row HPDC is located on the corresponding first trace LA. The third gate layer GT3 is provided with a second gate structure GB that corresponds one-to-one with each pixel driving circuit group PDCS. The top gate M1GB of each first transistor in the pixel driving circuit group PDCS is located on the second gate structure GB. The second gate structure GB and the first trace LA are electrically connected through the first conductive structure MA1.

[0112] In other words, the display panel PNL only provides the first trace LA to drive the first transistor M1, without additionally providing a second trace LB paired with the first trace LA. In the third gate layer GT3, the top gate M1GB of the first transistor is used instead of the second trace LB. The peripheral region BB does not directly load signals to the top gate M1GB of the first transistor, but instead loads the signals to the first trace LA. The first trace LA synchronizes the signals to the top gate M1GB of the first transistor. Thus, the display panel PNL only loads signals to the first trace LA, and the top gate M1GB of the first transistor is electrically connected to the first trace LA to maintain signal synchronization. In related technologies, the first trace LA and the second trace LB are parallel traces over a long distance, which not only increases the signal load on the first / second traces but also increases power consumption and reduces display uniformity. In this embodiment, the large second trace LB is not provided, thereby reducing the signal load, lowering power consumption, and improving display uniformity.

[0113] In one example of this implementation, referring to FIG5, the pixel driving circuit group PDCS includes two pixel driving circuits PDC that are adjacent in the same row.

[0114] In one example of this embodiment, referring to Figures 6 to 8, the first trace LA is electrically connected to the first conductive structure MA1 through the first via V1, and the second gate structure GB is electrically connected to the first conductive structure MA1 through the second via V2.

[0115] In another example of this embodiment, referring to Figures 9-11, the first conductive structure MA1 is electrically connected to both the first trace LA and the second gate structure GB through a third via V3. The third via V3 exposes a portion of the first trace LA and a portion of the second gate structure GB. In this embodiment, the third via V3 is disposed across the edge of the second gate structure GB. The portion where the third via V3 overlaps with the second gate structure GB allows the first conductive structure MA1 to be electrically connected to the second gate structure GB. The portion where the third via V3 does not overlap with the second gate structure GB but overlaps with the first trace LA allows the first conductive structure MA1 to be electrically connected to the first trace LA.

[0116] Optionally, referring to Figures 13 to 18, the first trace LA is provided with a protrusion, the orthographic projection of which on the substrate SBT exceeds the orthographic projection of the second gate structure GB on the substrate SBT; the protrusion of the first trace LA is electrically connected to the first conductive structure MA1 through a via.

[0117] In one example, the pixel driving circuit PDC includes a driving transistor that controls the magnitude of the driving current output by the pixel driving circuit PDC based on the voltage on its gate. The first source-drain metal layer SD1 further includes a second conductive structure MA2, which is electrically connected to the gate of the driving transistor and to the second terminal M1D of the first transistor. Referring to Figure 40, the second gate structure GB and the second conductive structure MA2 do not overlap. Thus, the coupling between the first trace LA and the second gate structure GB and the second conductive structure MA2 is relatively small, which can reduce the influence of the signal loaded on the first trace LA on the first node N1. In particular, it can reduce the influence of the signal loaded on the first trace LA on the first node N1 at the rising or falling edge, thereby improving the uniformity of the voltage of the first node N1 of the pixel driving circuit PDC at different locations and improving display uniformity.

[0118] Figure 12 illustrates a second strategy for improving the driving method of the first transistor M1. Referring to Figures 12-18, the third gate layer GT3 is provided with second traces LB that correspond one-to-one with the pixel driving circuit rows HPDC and extend along the row direction DH. The top gate M1GB of each first transistor in the pixel driving circuit row HPDC is located on the corresponding second trace LB. The second gate layer GT2 is provided with first gate structures GA that correspond one-to-one with each pixel driving circuit group PDCS. The bottom gate M1GA of each first transistor in the pixel driving circuit group PDCS is located on the first gate structure GA. The first gate structure GA and the second trace LB are electrically connected through the first conductive structure MA1.

[0119] In other words, the display panel PNL only provides a second trace LB to drive the first transistor M1, without additionally providing a first trace LA to pair with the second trace LB. In the second gate layer GT2, the bottom gate M1GA of the first transistor is used instead of the first trace LA. The peripheral area BB does not directly load signals onto the bottom gate M1GA of the first transistor, but instead loads the signals onto the second trace LB. The second trace LB synchronizes the signals to the bottom gate M1GA of the first transistor. Thus, the display panel PNL only loads signals onto the second trace LB, and the bottom gate M1GA of the first transistor and the second trace LB are electrically connected within the display area AA to maintain signal synchronization. In related technologies, the first trace LA and the second trace LB are parallel traces over a long distance, which not only increases the signal load on the first / second traces but also increases power consumption and reduces display uniformity. In this embodiment, the large-sized first trace LA is not provided, thereby reducing the signal load, lowering power consumption, and improving display uniformity.

[0120] In one example of this implementation, referring to FIG12, the pixel driving circuit group PDCS includes two pixel driving circuits PDCs that are adjacent in the same row.

[0121] In one example of this embodiment, referring to Figures 13 to 15, the first gate structure GA is electrically connected to the first conductive structure MA1 through a first via V1, and the second trace LB is electrically connected to the first conductive structure MA1 through a second via V2.

[0122] In another example of this embodiment, referring to Figures 16-18, the first conductive structure MA1 is electrically connected to both the first gate structure GA and the second trace LB via a third via V3. The third via V3 exposes a portion of the first gate structure GA and a portion of the second trace LB. In this embodiment, the third via V3 is positioned across the edge of the second trace LB. The portion where the third via V3 overlaps with the second trace LB allows the first conductive structure MA1 to be electrically connected to the second trace LB. The portion where the third via V3 does not overlap with the second trace LB but overlaps with the first gate structure GA allows the first conductive structure MA1 to be electrically connected to the first gate structure GA.

[0123] Optionally, referring to Figures 13 to 18, the first gate structure GA is provided with a protrusion, the orthographic projection of which on the substrate SBT exceeds the orthographic projection of the second trace LB on the substrate SBT; the protrusion of the first gate structure GA is electrically connected to the first conductive structure MA1 through a via.

[0124] In one example, referring to Figures 13 and 16, the first gate structure GA does not overlap with the second conductive structure MA2. Thus, the size of the first gate structure GA is relatively small, and its coupling with other structures of the display panel PNL is also relatively small; this helps reduce crosstalk between the signal loaded on the second trace LB and other signals, and also helps reduce the load of the signal loaded on the second trace LB, reducing RC delay and power consumption.

[0125] Figure 19 illustrates a third strategy for improving the driving method of the first transistor M1. Referring to Figures 20-25, the second gate layer GT2 is provided with a first trace LA that corresponds one-to-one with the pixel driving circuit row HPDC and extends along the row direction DH. The bottom gate M1GA of each first transistor in the pixel driving circuit row HPDC is located on the corresponding first trace LA. The third gate layer GT3 is provided with a second trace LB that corresponds one-to-one with the pixel driving circuit row HPDC and extends along the row direction DH. The top gate M1GB of each first transistor in the pixel driving circuit row HPDC is located on the corresponding second trace LB. The first trace LA and the second trace LB are electrically connected through the first conductive structure MA1.

[0126] Compared to related technologies, in this embodiment, the first trace LA and the second trace LB are electrically connected multiple times through the first conductive structure MA1 during their extension within the display area AA, thereby ensuring that the first trace LA and the second trace LB are effectively connected in parallel within the display area AA and ensuring signal synchronization.

[0127] In one example of this implementation, referring to FIG19, the pixel driving circuit group PDCS includes two adjacent pixel driving circuits PDC in the same row. Thus, along the row direction DH, the first trace LA and the second trace LB are connected in parallel every two pixel driving circuits PDC.

[0128] In one example of this embodiment, referring to Figures 20-22, the first conductive structure MA1 is electrically connected to both the first trace LA and the second trace LB via a third via V3, which exposes a portion of the first trace LA and a portion of the second trace LB. In this embodiment, the third via V3 is positioned across the edge of the second trace LB. The portion where the third via V3 overlaps with the second trace LB allows the first conductive structure MA1 to be electrically connected to the second trace LB. The portion where the third via V3 does not overlap with the second trace LB but overlaps with the first trace LA allows the first conductive structure MA1 to be electrically connected to the first gate structure GA.

[0129] In another example of this embodiment, referring to Figures 23 to 25, the first trace LA is electrically connected to the first conductive structure MA1 through the first via V1, and the second trace LB is electrically connected to the first conductive structure MA1 through the second via V2.

[0130] Optionally, referring to Figures 20-25, the first trace LA is provided with a protrusion, the orthographic projection of which on the substrate SBT exceeds the orthographic projection of the second trace LB on the substrate SBT; the protrusion of the first trace LA is electrically connected to the first conductive structure MA1 through a via.

[0131] In one embodiment of this disclosure, referring to Figures 26-28, the transistors of two adjacent pixel driving circuits (PDCs) in the same row are arranged in a mirror-symmetrical manner. Thus, based on the relative arrangement of the transistors, the pixel driving circuits (PDCs) include two types: a first pixel driving circuit (PDC1) and a second pixel driving circuit (PDC2). In the example of Figure 26, the threshold compensation transistor T2 in the first pixel driving circuit (PDC1) is located to the right of the data writing transistor T4, and the threshold compensation transistor T2 in the second pixel driving circuit (PDC2) is located to the left of the data writing transistor T4. In this embodiment, the area where the first pixel driving circuit (PDC1) is located is referred to as the first pixel driving circuit area PDCA1, and the area where the second pixel driving circuit (PDC2) is located is referred to as the second pixel driving circuit area PDCA2. Thus, along the row direction DH, the first pixel driving circuit area PDCA1 and the second pixel driving circuit area PDCA2 are alternately arranged.

[0132] In one embodiment of this disclosure, a pixel driving circuit group PDCS may include two adjacent pixel driving circuits PDC in the same row, namely, a first pixel driving circuit PDC1 and a second pixel driving circuit PDC2. If the first pixel driving circuit PDC1 is located to the left of the second pixel driving circuit PDC2, then the pixel driving circuit group PDCS is the first pixel driving circuit group PDCS1; if the first pixel driving circuit PDC1 is located to the right of the second pixel driving circuit PDC2, then the pixel driving circuit group PDCS is the second pixel driving circuit group PDCS2. In other words, in the first pixel driving circuit group PDCS1, the threshold compensation transistors T2 of the two pixel driving circuits PDC are arranged adjacently. In the second pixel driving circuit group PDCS2, the data write transistors T4 of the two pixel driving circuits PDC are arranged adjacently. Referring to FIG26, in the first pixel driving circuit group PDCS1, there is a wiring space extending along the column direction DV between the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2, which does not have any transistors. An initialization voltage auxiliary trace VTLX extending along the column direction DV can be provided in this wiring space.

[0133] The display panel PNL has initialization voltage traces VTL extending along the row direction DH. These initialization voltage traces are used to apply an initialization voltage to the pixel driving circuit PDC. The initialization voltage auxiliary traces VTLX and VTL, which apply the same initialization voltage, are electrically connected to each other. This allows for a gridded distribution of the initialization voltage signal, improving the uniformity of the initialization voltage.

[0134] In one embodiment, referring to FIG27, at least a portion of the first conductive structure MA1 may be disposed in the first pixel driving circuit group PDCS1, that is, the first conductive structure MA1 may be located within the wiring space. This allows at least a portion of the first conductive structure MA1 to overlap with the initialization voltage auxiliary trace VTLX.

[0135] For example, each first conductive structure MA1 is disposed in the first pixel driving circuit group PDCS1, and is located between the two pixel driving circuits PDC of the first pixel driving circuit group PDCS1. Each first conductive structure MA1 overlaps with the initialization voltage auxiliary trace VTLX.

[0136] Optionally, the initialization voltage auxiliary trace VTLX is disposed on a metal layer above the first source / drain metal layer SD1 to avoid the first conductive structure MA1. For example, when the display panel PNL has a second source / drain metal layer SD2, in the case where the first conductive structure MA1 overlaps with the initialization voltage auxiliary trace VTLX, the initialization voltage auxiliary trace VTLX can be disposed on the second source / drain metal layer SD2.

[0137] In one example, the display panel PNL is provided with a data trace DL for loading data voltage and a power supply trace VDDL for loading drive power supply voltage VDD. The initialization voltage auxiliary trace VTLX is set on the same layer as the data trace DL and the power supply trace VDDL.

[0138] In one example, when the display panel PNL has a second gate structure GB but no second trace LB, or when the display panel PNL has a first gate structure GA but no first trace LA, the first conductive structure MA1 can be located in the first pixel driving circuit group PDCS1. In this example, the threshold compensation transistor T2 is located close to the first conductive structure MA1, and the first gate structure GA or the second gate structure GB can be configured to have a smaller size, especially reducing the size of the second gate structure GB or the first gate structure GA in the horizontal direction DH, thereby reducing the signal channel load of the signal loaded onto the gate of the first transistor M1.

[0139] In one embodiment, referring to FIG28, at least a portion of the first conductive structure MA1 may be disposed in the second pixel driving circuit group PDCS2, that is, the first conductive structure MA1 is not located in the wiring space. This ensures that at least a portion of the first conductive structure MA1 does not overlap with the initialization voltage auxiliary trace VTLX; in the row direction DH, the first conductive structure MA1 and the initialization voltage auxiliary trace VTLX are separated by a pixel driving circuit PDC.

[0140] Optionally, the initialization voltage assist trace VTLX can be placed on the first source-drain metal layer SD1, without needing to be placed on the second source-drain metal layer SD2 to avoid the first conductive structure MA1. This provides more space on the second source-drain metal layer SD2 for routing other traces.

[0141] In one example, the second gate layer GT2 is provided with a first trace LA that corresponds one-to-one with the pixel driving circuit row HPDC and extends along the row direction DH. The bottom gate M1GA of each first transistor in the pixel driving circuit row HPDC is located on the corresponding first trace LA. The third gate layer GT3 is provided with a second trace LB that corresponds one-to-one with the pixel driving circuit row HPDC and extends along the row direction DH. The top gate M1GB of each first transistor in the pixel driving circuit row HPDC is located on the corresponding second trace LB. The first trace LA and the second trace LB are electrically connected through the first conductive structure MA1. The first conductive structure MA1 is disposed in the second pixel driving circuit group PDCS2.

[0142] In one embodiment of this disclosure, referring to FIG29, the initialization voltage includes a first initialization voltage Vinit1, a second initialization voltage Vinit2, and a third initialization voltage Vinit3. Then, the display panel PNL is provided with a first initialization voltage trace VTL1, a second initialization voltage trace VTL2, and a third initialization voltage trace VTL3 extending along the row direction DH.

[0143] The first initialization voltage trace VTL1 is disposed on the gate layer, for example, on the second gate layer GT2. The initialization voltage auxiliary trace VTLX1 includes a first initialization voltage auxiliary trace VTLX1 electrically connected to the first initialization voltage trace VTL1 via a via. The first initialization voltage trace VTL1 and the first initialization voltage auxiliary trace VTLX1 are used to apply the first initialization voltage Vinit1. The first initialization voltage auxiliary trace VTLX1 and the first initialization voltage trace VTL1 are electrically connected via a via or via a metal structure located in a film layer such as the first source / drain metal layer SD1.

[0144] The second initialization voltage trace VTL2 is disposed on the gate layer, for example, on the third gate layer GT3. The initialization voltage auxiliary trace VTLX2 includes a second initialization voltage auxiliary trace VTLX2 electrically connected to the second initialization voltage trace VTL2 via a via. The second initialization voltage trace VTL2 and the second initialization voltage auxiliary trace VTLX2 are used to apply the second initialization voltage Vinit2. The second initialization voltage auxiliary trace VTLX2 and the second initialization voltage trace VTL2 are electrically connected via a via or through a metal structure located in a film layer such as the first source / drain metal layer SD1.

[0145] The third initialization voltage trace VTL3 is disposed on the gate layer, for example, on the third gate layer GT3. The initialization voltage auxiliary trace VTLX includes a third initialization voltage auxiliary trace VTLX3 electrically connected to the third initialization voltage trace VTL3 via a via. The third initialization voltage trace VTL3 and the third initialization voltage auxiliary trace VTLX3 are used to apply the third initialization voltage Vinit3. The third initialization voltage auxiliary trace VTLX3 and the third initialization voltage trace VTL3 are electrically connected via a via or through a metal structure located in a film layer such as the first source / drain metal layer SD1.

[0146] In the example of Figure 29, the initialization voltage auxiliary traces VTLX include three types: first initialization voltage auxiliary trace VTLX1, second initialization voltage auxiliary trace VTLX2, and third initialization voltage auxiliary trace VTLX3, so that the first initialization voltage Vinit1, the second initialization voltage Vinit2, and the third initialization voltage Vinit3 are respectively distributed in a grid. Only one type of initialization voltage auxiliary trace VTLX is set within each routing space.

[0147] In other embodiments of this disclosure, the initialization voltage-assisted trace VTLX may be meshed only for one or both of the first initialization voltage Vinit1, the second initialization voltage Vinit2, and the third initialization voltage Vinit3.

[0148] In the example of Figure 29, the three initialization voltage auxiliary traces VTLX1, VTLX2, and VTLX3 appear periodically, making the number of each type of VTLX approximately equal. In other embodiments of this disclosure, the number and order of the three initialization voltage auxiliary traces VTLX1, VTLX2, and VTLX3 can be adjusted, for example, making the number of the second initialization voltage auxiliary traces VTLX2 greater than the number of the first and second initialization voltage auxiliary traces VTLX1 and VTLX2.

[0149] In the example of Figure 29, initialization voltage auxiliary traces VTLX are provided in the wiring space of the first pixel driving circuit group PDCS1. It is understood that in other embodiments of this disclosure, at least a portion of the wiring space of the first pixel driving circuit group PDCS1 may not have initialization voltage auxiliary traces VTLX; for example, auxiliary lines for voltage meshing may not be provided, or the provided auxiliary lines may be used for other purposes. For instance, in one example, at least a portion of the wiring space of the first pixel driving circuit group PDCS1 includes reference voltage traces or data voltage conversion lines.

[0150] Figures 30 to 44 are partial structural diagrams of the driving layer DRL in a first example of the first embodiment of this disclosure, and the pixel driving circuit PDC shown is the pixel driving circuit PDC exemplified in Figure 3. Taking Figures 30 to 44 as examples, the structure of the display panel PNL of the embodiment of this disclosure will be further introduced and illustrated.

[0151] Figure 30 is a schematic diagram of the structure of the metal light-shielding layer BSM in this example. Referring to Figure 30, the metal light-shielding layer BSM is provided with a light-shielding part for light shielding. The light-shielding part can overlap with the channel region of the driving transistor to ensure the stability of the driving transistor's characteristics.

[0152] Referring to Figures 2 and 31-44, in this example, the driving layer DRL sequentially includes a low-temperature polysilicon semiconductor layer PSCL, a first gate layer GT1, a second gate layer GT2, a metal-oxide-semiconductor layer OSCL, a third gate layer GT3, a first source-drain metal layer SD1, and a second source-drain metal layer SD2. Figure 31 shows the channel regions of each low-temperature polysilicon transistor (i.e., the channel region T1A of the gate reset transistor, the channel region T3A of the driving transistor, the channel region T4A of the data write transistor, the channel region T5A of the first light-emitting control transistor, the channel region T6A of the second light-emitting control transistor, the channel region T7A of the electrode reset transistor, and the channel region T8A of the source reset transistor). Among them, the gate reset transistor T1, the driving transistor T3, the data write transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the electrode reset transistor T7, and the source reset transistor T8 are all low-temperature polysilicon transistors, and their active layers are disposed on the low-temperature polysilicon semiconductor layer PSCL. The threshold compensation transistor T2 serves as the first improved transistor M1, with its active layer disposed on the metal oxide semiconductor layer OSCL; in Figure 37, the location of the channel region T2A of the threshold compensation transistor is marked.

[0153] In this example, the first node N1 includes a first electrode CP1 of a storage capacitor located in the second gate layer GT2, a second conductive structure MA2 located in the first source / drain metal layer SD1, and a second electrode of a threshold compensation transistor T2 located in the metal-oxide-semiconductor layer OSCL. The first electrode CP1 of the storage capacitor is electrically connected to the second conductive structure MA2 via a via, and the second electrode of the threshold compensation transistor T2 is electrically connected to the second conductive structure MA2 via a via.

[0154] In this example, the second node N2 includes the second terminal of the data writing transistor T4 located in the low-temperature polycrystalline silicon semiconductor layer PSCL, the second terminal of the first light-emitting control transistor T5, the first terminal of the driving transistor T3, the second terminal of the source reset transistor T8, and a sixth conductive structure MA6 located in the first source-drain metal layer SD1. Referring to Figure 31, the second terminals of the data writing transistor T4, the first light-emitting control transistor T5, and the first terminal of the driving transistor T3 are all directly connected to the low-temperature polycrystalline silicon semiconductor layer PSCL. The second terminal of the first light-emitting control transistor T5 is electrically connected to the sixth conductive structure MA6 through a via, and the sixth conductive structure MA6 is electrically connected to the second terminal of the source reset transistor T8 through a via.

[0155] In this example, the third node N3 includes the second terminal of a driving transistor T3 located in the low-temperature polycrystalline silicon semiconductor layer PSCL, the second terminal of a gate reset transistor T1, the first terminal of a second light-emitting control transistor T6, the first terminal of a threshold compensation transistor T2 located in the metal oxide semiconductor layer OSCL, and a fifth conductive structure MA5 located in the first source / drain metal layer SD1. Referring to Figure 31, the second terminal of the driving transistor T3 and the first terminal of the second light-emitting control transistor T6 are located in the low-temperature polycrystalline silicon semiconductor layer PSCL and are directly connected; the second terminal of the driving transistor T3 is electrically connected to the fifth conductive structure MA5 through a via, and the fifth conductive structure MA5 is electrically connected to the second terminal of the gate reset transistor T1 through a via. Referring to Figure 38, the first terminal of the threshold compensation transistor T2 is electrically connected to the fifth conductive structure MA5 through a via.

[0156] In this example, the fourth node N4 includes the second terminal of the second light-emitting control transistor T6 located in the low-temperature polycrystalline silicon semiconductor layer PSCL, the second terminal of the electrode reset transistor T7, and a ninth conductive structure MA9 located in the first source-drain metal layer SD1 and a twelfth conductive structure MB12 located in the second source-drain metal layer SD2. Referring to Figure 31, the second terminals of the second light-emitting control transistor T6 and the electrode reset transistor T7 are both located in the low-temperature polycrystalline silicon semiconductor layer PSCL and are directly connected. The second terminal of the second light-emitting control transistor T6 is electrically connected to the ninth conductive structure MA9 through a via. Referring to Figure 44, the ninth conductive structure MA9 is electrically connected to the twelfth conductive structure MB12 through a via.

[0157] In this example, the driving power supply voltage VDD can be applied to the following electrically connected structures: the first terminal of the first light-emitting control transistor T5 located in the low-temperature polycrystalline silicon semiconductor layer PSCL, the second electrode CP2 of the storage capacitor located in the second gate layer GT2, the third conductive structure MA3 located in the first source-drain metal layer SD1, and the power supply voltage trace VDDL located in the second source-drain metal layer SD2. Referring to Figure 44, the power supply voltage trace VDDL for applying the driving power supply voltage VDD is electrically connected to the third conductive structure MA3 via a via. Referring to Figures 36 and 42, the third conductive structure MA3 is electrically connected to the second electrode CP2 of the storage capacitor via a via. Referring to Figure 31, the third conductive structure MA3 is electrically connected to the first terminal of the first light-emitting control transistor T5 via a via.

[0158] In this example, the data voltage Vdata can be applied to the following electrically connected structures: the first terminal of the data write transistor T4 located in the low-temperature polycrystalline silicon semiconductor layer PSCL, the fourth conductive structure MA4 located in the first source-drain metal layer SD1, and the data trace DL located in the second source-drain metal layer SD2. Referring to Figure 44, the data trace DL is electrically connected to the fourth conductive structure MA4 via a via. Referring to Figure 31, the fourth conductive structure MA4 is electrically connected to the first terminal of the data write transistor T4 via a via.

[0159] In this example, the first initialization voltage Vinit1 can be applied to the following electrically connected structures: the first terminal of the gate reset transistor T1 located in the low-temperature polysilicon semiconductor layer PSCL, the eleventh conductive structure MA11 located in the first source-drain metal layer SD1, and the first initialization voltage trace VTL1 located in the second gate layer GT2. Referring to Figure 36, the eleventh conductive structure MA11 is electrically connected to the first initialization voltage trace VTL1 via a via. Referring to Figure 31, the eleventh conductive structure MA11 is electrically connected to the first terminal of the gate reset transistor T1 via a via. If a first initialization voltage auxiliary trace VTLX1 is provided in the first pixel driving circuit group PDCS1, the first initialization voltage Vinit1 can also be applied to the first initialization voltage auxiliary trace VTLX1. Specifically, the first initialization voltage auxiliary trace VTLX1 can be electrically connected to the tenth conductive structure MA10 located in the first source-drain metal layer SD1 via a via, and the tenth conductive structure MA10 can be electrically connected to the first initialization voltage trace VTL1 via a via.

[0160] In this example, the second initialization voltage Vinit2 can be applied to the following electrically connected structures: the first terminal of the electrode reset transistor T7 located in the low-temperature polysilicon semiconductor layer PSCL, the eighth conductive structure MA8 located in the first source-drain metal layer SD1, and the second initialization voltage trace VTL2 located in the third gate layer GT3. Referring to Figure 31, the first terminal of the electrode reset transistor T7 is electrically connected to the eighth conductive structure MA8 via a via; referring to Figure 41, the eighth conductive structure MA8 is electrically connected to the second initialization voltage trace VTL2 via a via. In the example of Figure 41, the second initialization voltage Vinit2 can also be applied to the tenth conductive structure MA10 located in the first source-drain metal layer SD1 and the initialization voltage auxiliary trace VTLX located in the second source-drain metal layer SD2. Referring to Figure 41, the tenth conductive structure MA10 is electrically connected to the second initialization voltage trace VTL2 via a via; referring to Figure 44, the tenth conductive structure MA10 is electrically connected to the initialization voltage auxiliary trace VTLX via a via.

[0161] In this example, the third initialization voltage Vinit3 can be applied to the following electrically connected structures: the first terminal of the source reset transistor T8 located in the low-temperature polysilicon semiconductor layer PSCL, the seventh conductive structure MA7 located in the first source-drain metal layer SD1, and the third initialization voltage trace VTL3 located in the third gate layer GT3. Referring to Figure 31, the first terminal of the source reset transistor T8 is electrically connected to the seventh conductive structure MA7 via a via; referring to Figure 41, the seventh conductive structure MA7 is electrically connected to the third initialization voltage trace VTL3 via a via. If a third initialization voltage auxiliary trace VTLX3 is provided in the first pixel driving circuit group PDCS1, the third initialization voltage Vinit3 can also be applied to the third initialization voltage auxiliary trace VTLX3. Specifically, the third initialization voltage auxiliary trace VTLX3 can be electrically connected to the tenth conductive structure MA10 located in the first source-drain metal layer SD1 via a via, and the tenth conductive structure MA10 can be electrically connected to the third initialization voltage trace VTL3 via a via.

[0162] In this example, referring to Figures 32 and 33, the first gate layer GT1 is provided with a first scan signal trace GPL extending along the row direction DH. The first scan signal trace GPL is used to load the first scan signal Gate_P and overlaps with the channel region of the data writing transistor T4 to serve as the gate of the data writing transistor T4.

[0163] In this example, referring to Figures 32 and 33, the first gate layer GT1 is provided with a second reset signal trace RHL extending along the row direction DH. The second reset signal trace RHL is used to load the second reset signal Reset_H, and overlaps with the channel region of the electrode reset transistor T7 and the channel region of the source reset transistor T8, respectively, to serve as the gate of the electrode reset transistor T7 and the gate of the source reset transistor T8.

[0164] In this example, referring to Figures 32 and 33, the first gate layer GT1 is provided with an organic light-emitting layer EML extending along the row direction DH. The organic light-emitting layer EML is used to load the light-emitting control signal EM and overlaps with the channel regions of the first light-emitting control transistor T5 and the second light-emitting control transistor T6, respectively, to serve as the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6.

[0165] In this example, referring to Figures 32 and 33, the first gate layer GT1 is provided with a first reset signal trace RPL extending along the row direction DH. The first reset signal trace RPL is used to load the first reset signal Reset_P and overlaps with the channel region of the gate reset transistor T1 to serve as the gate of the gate reset transistor T1.

[0166] In this example, the second gate layer GT2 has a first trace LA extending along the row direction DH, and the third gate layer GT3 has a second gate structure GB. The first trace LA is used to load the second scan signal Gate_N and overlaps with the channel region of the threshold compensation transistor T2. The bottom gate of the threshold compensation transistor T2 is located on the first trace LA. The third gate layer GT3 overlaps with the channel regions of two adjacent threshold compensation transistors T2, serving as the top gate of these two transistors. The first trace LA is electrically connected to the first conductive structure MA1 through a first via V1, and the second gate structure GB is electrically connected to the first conductive structure MA1 through a second via V2.

[0167] In this example, the power supply voltage trace VDDL has a widened portion that can overlap with the channel region of the threshold compensation transistor T2 to shield the threshold compensation transistor T2 from light.

[0168] In this example, the initialization voltage auxiliary trace VTLX is set on the second source-drain metal layer SD2, which isolates two adjacent power supply voltage traces VDDL from each other by the initialization voltage auxiliary trace VTLX.

[0169] In other embodiments of this disclosure, for example, when initializing the voltage-assisted trace VTLX to the first source-drain metal layer SD1, two adjacent power supply voltage traces VDDL can be interconnected to achieve better shading and a larger trace area.

[0170] This disclosure also provides a display device, which includes any of the display panels described in the above-described display panel embodiments. The display device can be a smartphone screen, a smartwatch screen, or other types of display devices. Since this display device has any of the display panels described in the above-described display panel embodiments, it has the same beneficial effects, and will not be repeated here.

Claims

1. A display panel, comprising an array of pixel driving circuits; the pixel driving circuit comprising a first transistor, the first transistor being a metal-oxide transistor and having a top gate and a bottom gate; The display panel has multiple pixel driving circuit groups, each of which includes one pixel driving circuit or multiple adjacent pixel driving circuits in the same row. The display panel is provided with a first conductive structure corresponding to each of the pixel driving circuit groups. The top gate and bottom gate of the first transistor in the pixel driving circuit group are both connected to the first conductive structure.

2. The display panel according to claim 1, wherein, The display panel includes a substrate, a second gate layer, a metal oxide semiconductor layer, a third gate layer, and a first source / drain metal layer stacked sequentially. Wherein, the channel region of the first transistor is disposed in the metal oxide semiconductor layer, the bottom gate of the first transistor is disposed in the second gate layer, the top gate of the first transistor is located in the third gate layer, and the first conductive structure is located in the first source-drain metal layer. Within the pixel driving circuit group, the bottom gate of the first transistor is electrically connected to the first conductive structure through a via, and the top gate of the first transistor is electrically connected to the first conductive structure through a via.

3. The display panel according to claim 2, wherein, The second gate layer is provided with a first trace that corresponds one-to-one with the pixel driving circuit row and extends along the row direction. The bottom gate of each first transistor in the pixel driving circuit row is located on the corresponding first trace. The third gate layer is provided with a second gate structure that corresponds one-to-one with each of the pixel driving circuit groups, and the top gate of each first transistor of the pixel driving circuit group is located in the second gate structure. The second gate structure is electrically connected to the first trace through the first conductive structure.

4. The display panel according to claim 3, wherein, The first trace is electrically connected to the first conductive structure through the first via, and the second gate structure is electrically connected to the first conductive structure through the second via; Alternatively, the first conductive structure may be electrically connected to both the first trace and the second gate structure via a third via, wherein the third via exposes a portion of the first trace and a portion of the second gate structure.

5. The display panel of claim 3, wherein, The pixel driving circuit includes a driving transistor, which can control the magnitude of the driving current output by the pixel driving circuit according to the voltage on its gate. The first source / drain metal layer further includes a second conductive structure, which is electrically connected to the gate of the driving transistor and to the second electrode of the first transistor; the second gate structure and the second conductive structure do not overlap.

6. The display panel of claim 2, wherein, The third gate layer is provided with a second trace that corresponds one-to-one with the pixel driving circuit row and extends along the row direction, and the top gate of each first transistor in the pixel driving circuit row is located on the corresponding second trace. The second gate layer is provided with a first gate structure corresponding to each of the pixel driving circuit groups, and the bottom gate of each first transistor of the pixel driving circuit group is located in the first gate structure. The first gate structure and the second trace are electrically connected through the first conductive structure.

7. The display panel of claim 6, wherein, The second trace is electrically connected to the first conductive structure through the second via, and the first gate structure is electrically connected to the first conductive structure through the first via. Alternatively, the first conductive structure may be electrically connected to both the second trace and the first gate structure simultaneously through a third via, wherein the third via exposes a portion of the second trace and a portion of the first gate structure.

8. The display panel of claim 6, wherein, The pixel driving circuit includes a driving transistor, which can control the magnitude of the driving current output by the pixel driving circuit according to the voltage on its gate. The first source / drain metal layer further includes a second conductive structure, which is electrically connected to the gate of the driving transistor and to the second electrode of the first transistor; the first gate structure and the second conductive structure do not overlap.

9. The display panel of claim 2, wherein, The second gate layer is provided with a first trace that corresponds one-to-one with the pixel driving circuit row and extends along the row direction. The bottom gate of each first transistor in the pixel driving circuit row is located on the corresponding first trace. The third gate layer is provided with a second trace that corresponds one-to-one with the pixel driving circuit row and extends along the row direction, and the top gate of each first transistor in the pixel driving circuit row is located on the corresponding second trace. The first trace and the second trace are electrically connected through the first conductive structure.

10. The display panel of claim 9, wherein, The first trace is electrically connected to the first conductive structure through the first via, and the second trace is electrically connected to the first conductive structure through the second via; Alternatively, the first conductive structure may be electrically connected to both the first trace and the second trace simultaneously through a third via, wherein the third via exposes a portion of the first trace and a portion of the second trace.

11. The display panel according to any one of claims 1 to 10, wherein The display panel also includes an initialization voltage auxiliary trace extending along the column direction; the display panel is provided with an initialization voltage trace extending along the row direction, the initialization voltage trace being used to apply an initialization voltage to the pixel driving circuit; The initialization voltage auxiliary trace and the initialization voltage trace, which are loaded with the same initialization voltage, are electrically connected to each other. At least a portion of the first conductive structure overlaps with the initialization voltage auxiliary trace.

12. The display panel according to any one of claims 1 to 10, wherein The display panel is provided with an initialization voltage auxiliary trace extending along the column direction; the display panel is provided with an initialization voltage trace extending along the row direction, the initialization voltage trace being used to apply an initialization voltage to the pixel driving circuit; The initialization voltage auxiliary trace and the initialization voltage trace, which are loaded with the same initialization voltage, are electrically connected to each other. At least a portion of the first conductive structure is spaced apart from the adjacent initialization voltage auxiliary trace by one pixel driving circuit in the row direction.

13. The display panel according to any one of claims 1 to 10, wherein In the pixel driving circuit group, the bottom gates of the first transistors are interconnected, and the top gates of the first transistors are interconnected.

14. A display device comprising the display panel according to any one of claims 1 to 13.

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