Display panel and display apparatus

Abstract

Provided in the present disclosure are a display panel and a display apparatus. The display panel comprises a base substrate and a plurality of pixel units provided on the base substrate, wherein each pixel unit comprises at least three sub-pixels, and each sub-pixel comprises a sub-pixel driving circuit and a light-emitting element, which are coupled to each other; the plurality of pixel units are divided into a plurality of pixel unit rows, each pixel unit row comprises a plurality of pixel units arranged in a first direction, and the sub-pixel driving circuits comprised in the respective pixel units are sequentially arranged in the first direction; in the same pixel unit row, sub-pixel driving circuits comprised in two adjacent pixel units form at least one same-color unit group, the same-color unit group comprises two adjacent sub-pixel driving circuits, and light-emitting elements coupled to the two sub-pixel driving circuits emit light of the same color; and the two sub-pixel driving circuits in the same-color unit group are coupled to the same corresponding power transmission layer.

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, the application fields of display products are becoming more and more extensive. In order to better improve the display brightness and color effect of display products, the pixel arrangement methods in display products are becoming more and more diversified. By controlling the display product to adopt different arrangement methods, more diversified driving methods can be realized to meet different driving requirements. Summary of the Invention

[0003] The purpose of this disclosure is to provide a display panel and a display device.

[0004] To achieve the above objectives, this disclosure provides the following technical solution:

[0005] The first aspect of this disclosure provides a display panel, including: a substrate and a plurality of pixel units disposed on the substrate, wherein the pixel unit includes at least three sub-pixels, and the sub-pixels include a sub-pixel driving circuit and a light-emitting element coupled to each other;

[0006] The plurality of pixel units are divided into multiple rows of pixel units, each row of pixel units includes a plurality of pixel units arranged along a first direction, and each pixel unit includes sub-pixel driving circuits arranged sequentially along the first direction; in the same row of pixel units, the sub-pixel driving circuits of two adjacent pixel units form at least one group of units of the same color, the group of units of the same color includes two adjacent sub-pixel driving circuits, and the light-emitting elements coupled to the two sub-pixel driving circuits have the same light-emitting color; the two sub-pixel driving circuits in the group of units of the same color are coupled to the corresponding power transmission layer.

[0007] Optionally, in the same row of pixel units, the sub-pixel driving circuits of two adjacent pixel units form a group of the same color unit. The first sub-pixel driving circuit in the same color unit group belongs to the first pixel unit of the two adjacent pixel units, and the second sub-pixel driving circuit in the same color unit group belongs to the second pixel unit of the two adjacent pixel units.

[0008] Optionally, in the same row of pixel units, the sub-pixel driving circuits of two adjacent pixel units form two groups of the same color unit. The two sub-pixel driving circuits of the first group of the same color unit belong to the first pixel unit of the two adjacent pixel units, and the two sub-pixel driving circuits of the second group of the same color unit belong to the second pixel unit of the two adjacent pixel units.

[0009] Optionally, each pixel unit includes a first color sub-pixel, a second color sub-pixel, and two third color sub-pixels; the two sub-pixel driving circuits in the same color unit group belong to the third color sub-pixel;

[0010] In each pixel unit, the first sub-pixel driving circuit of the first color sub-pixel and the second sub-pixel driving circuit of the second color sub-pixel are both located between the two third sub-pixel driving circuits of the two third color sub-pixels.

[0011] Optionally, in each pixel unit, the sub-pixel driving circuits of the first third-color sub-pixel, the first-color sub-pixel, the second-color sub-pixel, and the second third-color sub-pixel are arranged sequentially along a first direction; or,

[0012] In each pixel unit, the subpixel driving circuits of the first third color subpixel, the second color subpixel, the first color subpixel, and the second third color subpixel are arranged sequentially along the first direction.

[0013] Optionally, each pixel unit includes a first color sub-pixel, a second color sub-pixel, and two third color sub-pixels; the two sub-pixel driving circuits in the same color unit group belong to the third color sub-pixel;

[0014] In each pixel unit, the two third sub-pixel driving circuits included in the two third color sub-pixels are located between the first sub-pixel driving circuit included in the first color sub-pixel and the second sub-pixel driving circuit included in the second color sub-pixel.

[0015] Optionally, in each pixel unit, the sub-pixel driving circuits of the first color sub-pixel, the first third color sub-pixel, the second third color sub-pixel, and the second color sub-pixel are arranged sequentially along a first direction; or,

[0016] In each pixel unit, the subpixel driving circuits of the second color subpixel, the first third color subpixel, the second third color subpixel, and the first color subpixel are arranged sequentially along the first direction.

[0017] Optionally, in one of the odd-numbered and even-numbered pixel unit rows, the light-emitting elements of the first color sub-pixel, the light-emitting elements of the first third color sub-pixel, the light-emitting elements of the second color sub-pixel, and the light-emitting elements of the second third color sub-pixel are arranged sequentially along a first direction in a pixel unit.

[0018] In another pixel unit included in the odd-numbered row and even-numbered row, the light-emitting elements included in the second color sub-pixel, the light-emitting elements included in the first third color sub-pixel, the light-emitting elements included in the first color sub-pixel, and the light-emitting elements included in the second third color sub-pixel are arranged sequentially along the first direction.

[0019] Optionally, the first color sub-pixel includes a red sub-pixel, the second color sub-pixel includes a blue sub-pixel, and the third color sub-pixel includes a green sub-pixel.

[0020] Optionally, the multiple sub-pixel driving circuits included in the multiple pixel units are divided into multiple columns of driving circuits, and the driving circuit columns include multiple sub-pixel driving circuits arranged along a second direction, the second direction intersecting with the first direction;

[0021] The light-emitting elements coupled to each sub-pixel driving circuit in the driving circuit column have the same light-emitting color, and each sub-pixel driving circuit in the same driving circuit column is coupled to the same power transmission layer.

[0022] Optionally, the sub-pixel driving circuit includes a driving transistor and a storage capacitor, wherein the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the corresponding power transmission layer.

[0023] The second plates of the storage capacitors included in the two sub-pixel driving circuits of the same color unit group are formed as an integral structure; the second plates of the storage capacitors included in the sub-pixel driving circuits of different colors are independent of each other.

[0024] Optionally, the same-color unit group includes a common conductive connection portion, and the integrally structured second electrode plate is coupled to the corresponding power transmission layer through the common conductive connection portion.

[0025] Optionally, the sub-pixel driving circuit includes a power control transistor, the second terminal of which is coupled to the first terminal of the driving transistor;

[0026] The common conductive connection includes a first portion and a second portion coupled together, the first portion extending along a first direction and the second portion extending along a second direction; the first portion is coupled to a corresponding power transmission layer; at least a portion of the orthographic projection of the second portion onto the substrate is located between the orthographic projections of the channel portions of the power control transistors included in the two sub-pixel driving circuits of the same color unit group onto the substrate; the first electrodes of the two power control transistors in the two sub-pixel driving circuits of the same color unit group are formed into an integral structure, and the second portion is coupled to the first electrode of the integral structure and the second electrode plate of the integral structure, respectively.

[0027] Optionally, the display panel includes a first power transmission layer, the first power transmission layer including a first sub-power layer and a second sub-power layer; at least a portion of the first sub-power layer is located between the second sub-power layer and the substrate; the first sub-power layer is coupled to the second sub-power layer; the first portion is coupled to the first sub-power layer.

[0028] Optionally, the first sub-power layer includes a plurality of first sub-power patterns; the first sub-power patterns corresponding to the two sub-pixel driving circuits included in the same color unit group are respectively coupled to the first part; the plurality of first sub-power patterns are respectively coupled to the second sub-power layer.

[0029] Optionally, the plurality of first sub-power patterns are divided into multiple rows of first power pattern rows, each row of first power pattern including a plurality of first sub-power patterns arranged along a first direction; the first sub-power layer further includes a plurality of first power connection lines, each first power connection line being coupled to at least a portion of the first sub-power patterns in the corresponding row of first power patterns.

[0030] Optionally, the sub-pixel driving circuit that does not belong to the same color unit group includes an independent conductive connection part, and the second plate of the storage capacitor included in the sub-pixel driving circuit that does not belong to the same color unit group is coupled to the corresponding power transmission layer through the independent conductive connection part.

[0031] Optionally, the sub-pixel driving circuit includes a power control transistor, the second terminal of which is coupled to the first terminal of the driving transistor; the orthographic projection of the independent conductive connection portion on the substrate at least partially overlaps with the orthographic projection of the channel portion of the power control transistor on the substrate; the independent conductive connection portion is also coupled to the first terminal of the power control transistor.

[0032] Optionally, the display panel includes a second power transmission layer, the second power transmission layer including a third sub-power layer and a fourth sub-power layer; at least a portion of the third sub-power layer is located between the fourth sub-power layer and the substrate.

[0033] The third sub-power layer includes a plurality of second sub-power patterns; the second sub-power patterns are coupled to the corresponding independent conductive connections; the plurality of second sub-power patterns are respectively coupled to the fourth sub-power layer;

[0034] The plurality of second sub-power patterns are divided into multiple rows of second power pattern rows, each row of second power pattern including a plurality of second sub-power patterns arranged along a first direction; the third sub-power layer also includes a plurality of second power connection lines, each second power connection line being coupled to at least a portion of the second sub-power patterns in the corresponding row of second power patterns.

[0035] Based on the above-described display panel technical solution, a second aspect of this disclosure provides a display device including the above-described display panel. Attached Figure Description

[0036] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0037] Figure 1 is a circuit schematic diagram of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0038] Figure 2 is a schematic diagram of a first layout of sub-pixels in a display panel provided in an embodiment of this disclosure;

[0039] Figure 3 shows the method of writing power signals when corresponding to the layout structure in Figure 2;

[0040] Figure 4 is a schematic diagram of a second layout of sub-pixels in a display panel provided in an embodiment of this disclosure;

[0041] Figure 5 is a schematic diagram of a third layout of sub-pixels in a display panel provided in an embodiment of this disclosure;

[0042] Figure 6 is a schematic diagram of the fourth layout of sub-pixels in the display panel provided in an embodiment of this disclosure;

[0043] Figure 7 is a schematic diagram of the layout of the first active layer and the first gate metal layer in the pixel unit of the array distribution provided in the embodiment of this disclosure;

[0044] Figure 8 is a schematic diagram of the layout of the second gate metal layer in the pixel unit of the array distribution provided in the embodiment of this disclosure;

[0045] Figure 9 is a schematic diagram of adding the structure of Figure 8 to the structure of Figure 7;

[0046] Figure 10 is a schematic diagram of the layout of the second active layer in the pixel unit of the array distribution provided in the embodiment of this disclosure;

[0047] Figure 11 is a schematic diagram of the layout of the third gate metal layer in the pixel unit of the array distribution provided in the embodiment of this disclosure;

[0048] Figure 12 is a schematic diagram of adding the structures of Figure 10 and Figure 11 to the structure of Figure 9;

[0049] Figure 13 is a schematic diagram of the layout of a first type of via penetrating the interlayer insulating layer in an array-distributed pixel unit provided in an embodiment of this disclosure;

[0050] Figure 14 is a schematic diagram of the layout of a second type of via penetrating the interlayer insulating layer in an array-distributed pixel unit provided in an embodiment of this disclosure;

[0051] Figure 15 is a schematic diagram of adding the structures of Figure 13 and Figure 14 to Figure 12;

[0052] Figure 16 is a schematic diagram of the layout of the first source / drain metal layer in the pixel unit of the array distribution provided in the embodiment of this disclosure;

[0053] Figure 17 is a schematic diagram of adding the structure of Figure 16 to Figure 15;

[0054] Figure 18 is a schematic diagram of the layout of vias penetrating the first planarization layer in the pixel units of the array distribution provided in an embodiment of the present disclosure;

[0055] Figure 19 is a schematic diagram of the layout of the second source / drain metal layer in the pixel unit of the array distribution provided in the embodiment of this disclosure;

[0056] Figure 20 is a schematic diagram of adding the structures of Figure 18 and Figure 19 to Figure 17;

[0057] Figure 21 is a schematic diagram of the layout of vias penetrating the second planarization layer in an array-distributed pixel unit provided in an embodiment of this disclosure;

[0058] Figure 22 is a schematic diagram of the layout of the third source / drain metal layer in the pixel unit of the array distribution provided in the embodiment of this disclosure;

[0059] Figure 23 is a schematic diagram of the structures of Figures 19, 21 and 22 superimposed;

[0060] Figure 24 is a schematic diagram of adding the structures of Figure 21 and Figure 22 to the structure of Figure 20;

[0061] Figure 25 is a schematic diagram of the layout of the via structure and the anode layer on the third planar layer in the pixel unit of the array distribution provided in the embodiment of this disclosure;

[0062] Figure 26 is a layout diagram of the structure shown in Figure 25 added to Figure 24;

[0063] Figure 27 is a schematic cross-sectional view of the film layer of the display panel provided in an embodiment of this disclosure;

[0064] Figure 28 is the driving timing diagram corresponding to Figure 1;

[0065] Figure 29 is a schematic diagram of a fifth layout of sub-pixels in a display panel provided in an embodiment of this disclosure;

[0066] Figure 30 is a schematic diagram of the layout of the light-emitting elements corresponding to the layout in Figure 29;

[0067] Figure 31 is a schematic diagram of a sixth layout of sub-pixels in a display panel provided in an embodiment of this disclosure;

[0068] Figure 32 is a schematic diagram of the layout of the third source / drain metal layer corresponding to the layout in Figure 31;

[0069] Figure 33 is a schematic diagram of the layout of the light-emitting elements corresponding to the layout in Figure 31;

[0070] Figure 34 is a schematic diagram of the layout of the third source / drain metal layer and the light-emitting element corresponding to the layout in Figure 31;

[0071] Figure 35 is a schematic diagram of the layout of the light-emitting elements corresponding to the layout in Figure 4. Detailed Implementation

[0072] To further illustrate the display panel and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0073] The traditional SDP (Separate Driving Pixel) scheme uses sub-pixel driving circuits arranged in an RGBG pattern. This RGBG arrangement, combined with the driving method of driving vertical columns of pixels separately with data signals and power signals, results in the grouping of power lines and the winding between the sub-pixel driving power supply and the light-emitting element coupled to it, which greatly increases the layout difficulty of display products.

[0074] Please refer to Figures 2 to 6. This disclosure provides a display panel, including: a substrate and a plurality of pixel units disposed on the substrate. Each pixel unit includes at least three sub-pixels (e.g., one red sub-pixel, one blue sub-pixel, and two green sub-pixels). Each sub-pixel includes a sub-pixel driving circuit and a light-emitting element coupled to each other; for example, the red sub-pixel includes a sub-pixel driving circuit Dr and a light-emitting element Er coupled to each other; the blue sub-pixel includes a sub-pixel driving circuit Db and a light-emitting element Eb coupled to each other; and the green sub-pixel includes a sub-pixel driving circuit Dg and a light-emitting element Eg coupled to each other.

[0075] The plurality of pixel units are divided into multiple rows of pixel units H1. Each row of pixel units H1 includes a plurality of pixel units arranged along a first direction. The sub-pixel driving circuits included in each pixel unit are arranged sequentially along the first direction. In the same row of pixel units H1, the sub-pixel driving circuits included in two adjacent pixel units form at least one group of the same color unit Z1. The same color unit group Z1 includes two adjacent sub-pixel driving circuits. The light-emitting elements coupled to the two sub-pixel driving circuits have the same light emission color. The two sub-pixel driving circuits in the same color unit group Z1 are coupled to the corresponding power transmission layer.

[0076] For example, two sub-pixel driving circuits in the same color unit group Z1 are coupled to the corresponding power transport layer and receive the same power signal; for example, the two sub-pixel driving circuits Dg in the same color unit group Z1 receive the same power signal VDD_G. Sub-pixel driving circuit Dr receives the power signal VDD_R. Sub-pixel driving circuit Db receives the power signal VDD_B.

[0077] For example, Figure 2 illustrates that each column of driving circuits L1 receives the same data signal; for example: the column of driving circuits formed by the sub-pixel driving circuit Dr of the red sub-pixel receives the same data signal Data_R; the column of driving circuits formed by the sub-pixel driving circuit Db of the blue sub-pixel receives the same data signal Data_B; and the column of driving circuits formed by the sub-pixel driving circuit Dg of the green sub-pixel receives the same data signal Data_G.

[0078] For example, the display panel includes a plurality of pixel units distributed in an array, and the sub-pixels in each pixel unit include sub-pixel driving circuits arranged sequentially along a first direction. The arrangement of the light-emitting elements in the sub-pixels in each pixel unit includes a variety of arrangements. The light-emitting elements may be located above the sub-pixel driving circuits they are coupled to, or above the peripheral sub-pixel driving circuits they are not coupled to.

[0079] For example, the specific structure of the sub-pixel driving circuit can vary, such as an 8T1C (8 transistors and 1 capacitor) circuit structure, but is not limited to this.

[0080] For example, the plurality of pixel units are divided into multiple rows of pixel units H1, which are arranged along a second direction. Each row of pixel units H1 includes a plurality of pixel units arranged along a first direction. The first direction intersects the second direction. For example, the first direction includes a horizontal direction and the second direction includes a vertical direction, but is not limited thereto.

[0081] For example, in the same row of pixel units H1, the sub-pixel driving circuits of two adjacent pixel units form a group of units of the same color Z1 or two groups of units of the same color Z1, but are not limited to this.

[0082] As can be seen from the specific structure of the display panel described above, in the display panel provided by this embodiment, in the same row of pixel units H1, at least one group of units of the same color Z1 can be formed in every two adjacent pixel units. The group of units of the same color Z1 includes two adjacent sub-pixel driving circuits. The light-emitting elements coupled to the two sub-pixel driving circuits have the same light emission color, and the two sub-pixel driving circuits in the group of units of the same color Z1 are coupled to the same power transmission layer. The above arrangement ensures that in the same row of pixel units H1, every two adjacent pixel units have two sub-pixel driving circuits in the group of units of the same color Z1 sharing the same power transmission layer. This helps to reduce the layout complexity of the display panel, save the layout space occupied by pixel units and power transmission layers, and thus effectively reduce the layout difficulty of the display panel. The display panel provided by this embodiment is beneficial for the design of high PPI pixels in SDP and for improving the transmittance of the display panel.

[0083] As shown in Figures 2 to 4 and Figure 17, in some embodiments, in the same row of pixel units H1, the sub-pixel driving circuits of two adjacent pixel units form a group of the same color unit Z1. The first sub-pixel driving circuit in the same color unit group Z1 belongs to the first pixel unit of the two adjacent pixel units, and the second sub-pixel driving circuit in the same color unit group Z1 belongs to the second pixel unit of the two adjacent pixel units. It should be noted that the part enclosed by each dashed box in Figure 17 represents a portion of the circuit structure included in a pixel unit.

[0084] For example, each pixel unit includes a first color sub-pixel, a second color sub-pixel, and two third color sub-pixels; the two sub-pixel driving circuits in the same color unit group Z1 belong to the third color sub-pixels; in each pixel unit, the first sub-pixel driving circuit included in the first color sub-pixel and the second sub-pixel driving circuit included in the second color sub-pixel are both located between the two third sub-pixel driving circuits included in the two third color sub-pixels.

[0085] For example, the first color sub-pixel includes a red sub-pixel, the second color sub-pixel includes a blue sub-pixel, and the third color sub-pixel includes a green sub-pixel.

[0086] For example, as shown in FIG3, in each pixel unit, the subpixel driving circuits of the first third color subpixel, the first color subpixel, the second color subpixel, and the second third color subpixel are arranged sequentially along a first direction; or, as shown in FIG4, in each pixel unit, the subpixel driving circuits of the first third color subpixel, the second color subpixel, the first color subpixel, and the second third color subpixel are arranged sequentially along a first direction.

[0087] In the display panel provided by the above embodiment, in the same row of pixel units H1, each pair of adjacent pixel units has two sub-pixel driving circuits in a set of same color unit group Z1 that share the same power transmission layer. This helps to reduce the layout complexity of the display panel, save the layout space occupied by pixel units and power transmission layer, and thus effectively reduce the layout difficulty of the display panel.

[0088] In the above embodiments, in one of the odd-numbered pixel unit rows H1 and even-numbered pixel unit rows H1, the light-emitting elements (e.g., Er) of the first color sub-pixel, the light-emitting elements (e.g., Eg) of the first third color sub-pixel, the light-emitting elements (e.g., Eb) of the second color sub-pixel, and the light-emitting elements (e.g., Eg) of the second third color sub-pixel are arranged sequentially along the first direction; in the other of the odd-numbered pixel unit rows H1 and even-numbered pixel unit rows H1, the light-emitting elements (e.g., Eb) of the second color sub-pixel, the light-emitting elements (e.g., Eg) of the first third color sub-pixel, the light-emitting elements (e.g., Er) of the first color sub-pixel, and the light-emitting elements (e.g., Eg) of the second third color sub-pixel are arranged sequentially along the first direction.

[0089] As shown in Figures 24 to 26, by way of example, in the same row of pixel units H1, the light-emitting element of the third color sub-pixel is at least partially offset from the light-emitting elements of other color sub-pixels along the second direction.

[0090] For example, in the pixel units included in the odd-numbered row pixel unit row H1, the light-emitting elements included in the first color sub-pixel, the light-emitting elements included in the first third color sub-pixel, the light-emitting elements included in the second color sub-pixel, and the light-emitting elements included in the second third color sub-pixel are arranged sequentially along the first direction; in the pixel units included in the even-numbered row pixel unit row H1, the light-emitting elements included in the second color sub-pixel, the light-emitting elements included in the first third color sub-pixel, the light-emitting elements included in the first color sub-pixel, and the light-emitting elements included in the second third color sub-pixel are arranged sequentially along the first direction.

[0091] For example, in the pixel units included in the even-numbered row pixel unit row H1, the light-emitting elements included in the first color sub-pixel, the light-emitting elements included in the first third color sub-pixel, the light-emitting elements included in the second color sub-pixel, and the light-emitting elements included in the second third color sub-pixel are arranged sequentially along the first direction; in the pixel units included in the odd-numbered row pixel unit row H1, the light-emitting elements included in the second color sub-pixel, the light-emitting elements included in the first third color sub-pixel, the light-emitting elements included in the first color sub-pixel, and the light-emitting elements included in the second third color sub-pixel are arranged sequentially along the first direction.

[0092] In related technologies, in a pixel unit, the subpixel driving circuits of the first color subpixel, the first third color subpixel, the second color subpixel, and the second third color subpixel are arranged sequentially along a first direction. The light-emitting element of the first color subpixel is located above the subpixel driving circuit of the second color subpixel, and the light-emitting element of the second color subpixel is located above the subpixel driving circuit of the first color subpixel. Therefore, when the subpixel driving circuit of the first color subpixel is connected to the light-emitting element, it needs to cross the subpixel driving circuit of the first third color subpixel; when the subpixel driving circuit of the second color subpixel is connected to the light-emitting element, it also needs to cross the subpixel driving circuit of the first third color subpixel. Due to limited layout space, the connection hole (via through the planarization layer) between the subpixel driving circuit and the anode of the light-emitting element in the first third color subpixel needs to be moved upward. This results in the via being close to the pixel opening area of ​​the light-emitting element of the first third color subpixel, which can easily cause the anode of the light-emitting element in the first third color subpixel to be uneven, thereby causing the risk of color shift.

[0093] In the display panel provided in the above embodiments, when the sub-pixel driving circuits of the first third color sub-pixel, the first color sub-pixel, the second color sub-pixel, and the second third color sub-pixel are arranged sequentially along the first direction in each pixel unit, and the light-emitting element is arranged in the above manner, the sub-pixel driving circuit of the first color sub-pixel and the light-emitting element are relatively close, and the sub-pixel driving circuit of the first third color sub-pixel and the light-emitting element are relatively close. When the sub-pixel driving circuit of the first color sub-pixel and the light-emitting element are coupled together, and when the sub-pixel driving circuit of the first third color sub-pixel and the light-emitting element are coupled together, the connection line between the sub-pixel driving circuit and the light-emitting element is simplified, and the connection hole of the first third color sub-pixel is not required to avoid it, thus avoiding the risk of color deviation of the first third color sub-pixel.

[0094] Furthermore, when the light-emitting elements are arranged in the above manner, the lengths of the connecting lines between the light-emitting elements and the sub-pixel driving circuits in the first color sub-pixels of each row are approximately equal, and no special compensation is required.

[0095] It should be noted that in sub-pixels of various colors, the sub-pixel driving circuits are coupled to the light-emitting elements via connecting lines. The light-emitting element comprises an anode pattern, a light-emitting functional layer, and a cathode, sequentially stacked along a direction away from the substrate. All light-emitting elements in the display panel can reuse a single cathode layer. The connecting lines can be formed as an integral structure with the anode pattern to which they are coupled. The orthographic projection of the boundary of the pixel opening area corresponding to the sub-pixel onto the substrate is located inside the orthographic projection of the anode pattern onto the substrate.

[0096] As shown in Figures 5 and 6, in some embodiments, in the same row of pixel units H1, the sub-pixel driving circuits of two adjacent pixel units form two groups of the same color unit Z1. The two sub-pixel driving circuits of the first group of the same color unit Z1 belong to the first pixel unit of the two adjacent pixel units, and the two sub-pixel driving circuits of the second group of the same color unit Z1 belong to the second pixel unit of the two adjacent pixel units.

[0097] For example, each pixel unit includes a first color sub-pixel, a second color sub-pixel, and two third color sub-pixels; the two sub-pixel driving circuits in the same color unit group Z1 belong to the third color sub-pixels; in each pixel unit, the two third sub-pixel driving circuits included in the two third color sub-pixels are located between the first sub-pixel driving circuit included in the first color sub-pixel and the second sub-pixel driving circuit included in the second color sub-pixel.

[0098] For example, the first color sub-pixel includes a red sub-pixel, the second color sub-pixel includes a blue sub-pixel, and the third color sub-pixel includes a green sub-pixel.

[0099] For example, as shown in FIG5, in each pixel unit, the sub-pixel driving circuits of the first color sub-pixel, the first third color sub-pixel, the second third color sub-pixel, and the second color sub-pixel are arranged sequentially along a first direction; or, as shown in FIG6, in each pixel unit, the sub-pixel driving circuits of the second color sub-pixel, the first third color sub-pixel, the second third color sub-pixel, and the first color sub-pixel are arranged sequentially along a first direction.

[0100] In the above embodiments, in one of the odd-numbered pixel unit rows H1 and even-numbered pixel unit rows H1, the light-emitting elements of the first color sub-pixel, the light-emitting elements of the first third color sub-pixel, the light-emitting elements of the second color sub-pixel, and the light-emitting elements of the second third color sub-pixel are arranged sequentially along a first direction; in the other of the odd-numbered pixel unit rows H1 and even-numbered pixel unit rows H1, the light-emitting elements of the second color sub-pixel, the light-emitting elements of the first third color sub-pixel, the light-emitting elements of the first color sub-pixel, and the light-emitting elements of the second third color sub-pixel are arranged sequentially along a first direction.

[0101] In the display panel provided by the above embodiments, each pixel unit in the same row of pixel units H1 has two sub-pixel driving circuits in a set of same color unit groups Z1 that share the same power transmission layer. This helps to reduce the layout complexity of the display panel, save the layout space occupied by pixel units and power transmission layers, and thus effectively reduce the layout difficulty of the display panel.

[0102] As shown in Figures 3 to 6, in some embodiments, the multiple sub-pixel driving circuits included in the multiple pixel units are divided into multiple columns of driving circuits L1. The driving circuit column L1 includes multiple sub-pixel driving circuits arranged along a second direction, which intersects with the first direction. The light-emitting elements coupled to each sub-pixel driving circuit in the driving circuit column L1 have the same light emission color. Each sub-pixel driving circuit in the same column of driving circuits L1 is coupled to the same power transmission layer and receives the same power signal.

[0103] For example, the multiple sub-pixel driving circuits included in the multiple pixel units are divided into multiple columns of driving circuits L1 arranged along the first direction.

[0104] For example, the drive circuit array L1 connecting different color light-emitting elements is coupled to different power transmission layers.

[0105] For example, the power transmission layer is used to transmit power signals.

[0106] The aforementioned configuration involves each sub-pixel driving circuit in the same column L1 of driving circuits being coupled to the same corresponding power transmission layer. Driving circuits in columns L1 of different colors of light-emitting elements are coupled to different power transmission layers, enabling the power signals received by sub-pixels of different colors to be controlled independently. This allows for the provision of corresponding power signals according to the actual needs of sub-pixels of different colors, thereby minimizing the power consumption of the display panel.

[0107] As shown in Figures 1, 7, 8, 9, 16, and 17, in some embodiments, the sub-pixel driving circuit includes a driving transistor T3 and a storage capacitor C1. The first plate C11 of the storage capacitor C1 is coupled to the gate of the driving transistor T3, and the second plate C12 of the storage capacitor C1 is coupled to the corresponding power transmission layer. The second plates C12 of the storage capacitors C1 included in the two sub-pixel driving circuits in the same color unit group Z1 are formed into an integral structure (X1 in Figure 8). The second plates C12 of the storage capacitors C1 included in the sub-pixel driving circuits of different colors are independent of each other (X2 in Figure 8).

[0108] For example, as shown in Figure 1, the sub-pixel driving circuit adopts a 9T1C structure, and the sub-pixel driving circuit specifically includes:

[0109] The first reset transistor T1 has its gate coupled to the first scan signal line GL1, its first terminal coupled to the first initialization signal transmission line V1, and its second terminal coupled to the second terminal of the driving transistor T3.

[0110] The second reset transistor T7 has its gate coupled to the second scan signal line GL2, its first electrode coupled to the second initialization signal transmission line V2, and its second electrode coupled to the anode of the light-emitting element.

[0111] The third reset transistor T8 has its gate coupled to the third scan signal line GL3, its first terminal coupled to the third initialization signal transmission line V3, and its second terminal coupled to the first terminal of the driving transistor T3. It should be noted that the second scan signal line GL2 and the third scan signal line GL3 can be multiplexed as the same scan line.

[0112] A data writing transistor T4 is used, the gate of which is coupled to the fourth scan signal line GL4, the first terminal of which is coupled to the data line DL, and the second terminal of which is coupled to the first terminal of the driving transistor T3.

[0113] A power control transistor T5 has its gate coupled to the light emission control signal line EM, its first terminal coupled to the power signal transmission layer VDD, and its second terminal coupled to the first terminal of the driving transistor T3.

[0114] A light-emitting control transistor T6 is provided, the gate of which is coupled to the light-emitting control signal line EM. The first terminal of the light-emitting control transistor T6 is coupled to the second terminal of the driving transistor T3. The second terminal of the light-emitting control transistor T6 is coupled to the anode of the light-emitting element. The cathode of the light-emitting element receives the VSS signal.

[0115] A compensation transistor T2 is provided, with its gate coupled to the fifth scan signal line GL5. The first terminal of the compensation transistor T2 is coupled to the second terminal of the driving transistor T3, and the second terminal of the compensation transistor T2 is coupled to the gate of the driving transistor T3. It should be noted that the compensation transistor T2 includes an oxide transistor, as shown in Figure 10, and includes an active layer 50. As shown in Figures 8 to 12, the fifth scan signal line GL5 includes a first sub-scan line GL51 and a second sub-scan line GL52.

[0116] The first plate C11 of the storage capacitor C1 is formed as an integral structure with the gate T3-g of the driving transistor T3, and the second plate C12 of the storage capacitor C1 is coupled to the power signal transmission layer.

[0117] In the above-mentioned configuration, the second plate C12 of the storage capacitor C1 included in the two sub-pixel driving circuits of the same color unit group Z1 is formed into an integral structure; the second plate C12 of the storage capacitor C1 included in the sub-pixel driving circuits of different colors are independent of each other, which not only helps to improve the stability of the second plate C12 of the storage capacitor C1 in the same color unit group Z1 receiving the power signal, but also ensures that the power signals received by the sub-pixels of different colors are independent of each other.

[0118] As shown in Figures 8, 9, 16, 17, 19 to 23, in some embodiments, the same-color unit group Z1 is provided to include a common conductive connection part 20, and the integrally structured second electrode plate C12 is coupled to the corresponding power transmission layer through the common conductive connection part 20.

[0119] The above setup helps to further simplify the layout structure of pixel units, reduce the layout space occupied by pixel units, and reduce the layout difficulty of the display panel.

[0120] As shown in Figures 7 to 9 and Figures 13 to 17, in some embodiments, the sub-pixel driving circuit includes a power control transistor T5, the second terminal of which is coupled to the first terminal of the driving transistor T3.

[0121] The common conductive connection portion 20 includes a first portion 201 and a second portion 202 coupled together. The first portion 201 extends along a first direction, and the second portion 202 extends along a second direction. The first portion 201 is coupled to a corresponding power transmission layer. At least a portion of the orthographic projection of the second portion 202 on the substrate is located between the orthographic projections of the channel portions (marked as 30 in FIG. 7) of the power control transistors T5 included in the two sub-pixel driving circuits of the same color unit group Z1 on the substrate. The first poles of the two power control transistors T5 in the two sub-pixel driving circuits included in the same color unit group Z1 are formed into an integral structure. The second portion 202 is coupled to the first pole of the integral structure and the second pole plate C12 of the integral structure, respectively.

[0122] For example, the first portion 201 and the second portion 202 are formed as a T-shaped integral structure.

[0123] For example, the channel portion of the power control transistor T5 is the portion where the orthographic projection of the active layer of the power control transistor T5 on the substrate overlaps with the orthographic projection of the gate of the power control transistor T5 on the substrate.

[0124] The above configuration allows the power control transistor T5 and the storage capacitor C1 in the two sub-pixel driving circuits of the same color unit group Z1 to be coupled to the corresponding power transmission layer through a common conductive connection part 20, which helps to further simplify the layout structure of the pixel unit, reduce the layout space occupied by the pixel unit, and reduce the layout difficulty of the display panel.

[0125] The above-described configuration places at least a portion of the orthographic projection of the second part 202 on the substrate between the orthographic projections of the channel portion of the power control transistor T5 included in the two sub-pixel driving circuits of the same color unit group Z1 on the substrate; this reduces the overlap area between the orthographic projection of the second part 202 on the substrate and the orthographic projection of the active layer of the power control transistor on the substrate, reduces the parasitic capacitance generated by the common conductive connection portion 20, and further improves the working performance of the sub-pixel driving circuit.

[0126] In some embodiments, the display panel includes a first power transport layer, the first power transport layer including a first sub-power layer and a second sub-power layer; at least a portion of the first sub-power layer is located between the second sub-power layer and the substrate; the first sub-power layer is coupled to the second sub-power layer; the first portion 201 is coupled to the first sub-power layer.

[0127] For example, the first sub-power layer is formed of a second source / drain metal layer, and the second sub-power layer is formed of a third source / drain metal layer.

[0128] The above configuration of the first power transmission layer, which includes a first sub-power layer and a second sub-power layer coupled together, helps to reduce the loading of the first power transmission layer and improve the uniformity of the power signal transmitted by the first power transmission layer.

[0129] As shown in Figures 16 to 23, in some embodiments, the first sub-power layer includes a plurality of first sub-power patterns 41; the first sub-power patterns 41 corresponding to the two sub-pixel driving circuits included in the same color unit group Z1 are respectively coupled to the first part 201; the plurality of first sub-power patterns 41 are respectively coupled to the second sub-power layer.

[0130] For example, the plurality of first sub-power patterns 41 correspond one-to-one with the plurality of third color sub-pixels included in the display panel, and the first sub-power patterns 41 corresponding to the sub-pixel driving circuits of the two third color sub-pixels included in the same color unit group Z1 are respectively coupled to the first part 201.

[0131] The above configuration allows the sub-pixel driving circuit in each third-color sub-pixel to be coupled to the corresponding first sub-power pattern 41 via the common conductive connection 20, and then coupled to the second sub-power layer via the first sub-power pattern 41. This configuration not only ensures that the sub-pixel driving circuit in each third-color sub-pixel can be coupled to the second sub-power layer via its corresponding first sub-power pattern 41, guaranteeing the stability of the power signal received by the sub-pixel driving circuit, but also helps reduce the loading of the first power transmission layer and improves the uniformity of the power signal transmitted by the first power transmission layer.

[0132] As shown in Figures 16 to 23, in some embodiments, the plurality of first sub-power patterns 41 are divided into multiple rows of first power pattern rows, each row of first power pattern including a plurality of first sub-power patterns 41 arranged along a first direction; the first sub-power layer also includes a plurality of first power connection lines 42, each first power connection line 42 being coupled to at least a portion of the first sub-power patterns 41 in the corresponding row of first power pattern.

[0133] For example, the plurality of first power connection lines 42 correspond one-to-one with the plurality of first power graphic rows, but this is not the only possibility.

[0134] For example, the plurality of first sub-power patterns 41 are divided into multiple columns of first power patterns, each column comprising a plurality of first sub-power patterns 41 arranged along a second direction. The second sub-power layer comprises a plurality of first sub-power lines 61, each sub-power line 61 including at least a portion extending along the second direction. Each of the plurality of first sub-power lines 61 corresponds one-to-one with one of the columns of first power patterns, and each first sub-power line 61 is coupled to each first sub-power pattern 41 in its corresponding column.

[0135] As shown in Figures 19 to 23, the first sub-power line 61 is coupled to each of the first sub-power patterns 41 in the corresponding first power pattern column through the twenty-third via Via 23.

[0136] The above configuration allows the first sub-power layer and the second sub-power layer to jointly form a grid-like structure for the first power transmission layer. This structure of the power transmission layer has a small loading and the transmitted power signal has good uniformity.

[0137] As shown in Figures 8, 9, 16, 17, 19 to 23, in some embodiments, the sub-pixel driving circuit that does not belong to the same color unit group Z1 includes an independent conductive connection part 21, and the second plate C12 of the storage capacitor C1 included in the sub-pixel driving circuit that does not belong to the same color unit group Z1 is coupled to the corresponding power transmission layer through the independent conductive connection part 21.

[0138] The above configuration not only ensures the stability of the power signal received by the second plate C12 of the storage capacitor C1 which does not belong to the same color unit group Z1, but also ensures that the power signals received by sub-pixels of different colors are independent of each other.

[0139] As shown in Figures 8, 9, 16, 17, 19 to 23, in some embodiments, the sub-pixel driving circuit includes a power control transistor T5, the second terminal of which is coupled to the first terminal of the driving transistor T3; the orthographic projection of the independent conductive connection portion 21 on the substrate at least partially overlaps with the orthographic projection of the channel portion of the power control transistor T5 on the substrate; the independent conductive connection portion 21 is also coupled to the first terminal of the power control transistor T5.

[0140] The aforementioned independent conductive connection portion 21 is coupled to the first electrode of the power control transistor T5 and the second electrode plate C12 of the storage capacitor C1 in its respective sub-pixel driving circuit, and is also coupled to the corresponding power transmission layer. This not only ensures the stability of the power signal received by the sub-pixel driving circuit that does not belong to the same color unit group Z1, and ensures that the power signals received by sub-pixels of different colors are independent of each other, but also helps to reduce the layout space occupied by the pixel unit and reduce the layout difficulty of the display panel.

[0141] The above-mentioned arrangement ensures that the orthographic projection of the independent conductive connection portion 21 on the substrate overlaps at least partially with the orthographic projection of the channel portion of the power control transistor T5 on the substrate, thereby avoiding the independent conductive connection portion 21 occupying additional layout space, further reducing the layout space occupied by the pixel unit, and reducing the layout difficulty of the display panel.

[0142] As shown in Figures 16 to 23, in some embodiments, the display panel includes a second power transmission layer, the second power transmission layer including a third sub-power layer and a fourth sub-power layer; at least a portion of the third sub-power layer is located between the fourth sub-power layer and the substrate.

[0143] The third sub-power layer includes a plurality of second sub-power patterns 43; the second sub-power patterns 43 are coupled to the corresponding independent conductive connection portions 21; the plurality of second sub-power patterns 43 are respectively coupled to the fourth sub-power layer;

[0144] The plurality of second sub-power patterns 43 are divided into multiple rows of second power pattern rows, and the second power pattern rows include a plurality of second sub-power patterns 43 arranged along a first direction; the third sub-power layer also includes a plurality of second power connection lines 44, and the second power connection lines 44 are coupled to at least a portion of the second sub-power patterns 43 in the corresponding second power pattern rows.

[0145] For example, the third sub-power layer is formed by the second source / drain metal layer, and the fourth sub-power layer is formed by the third source / drain metal layer.

[0146] The above configuration of the second power transmission layer, which includes a coupled third sub-power layer and a fourth sub-power layer, helps to reduce the loading of the second power transmission layer and improve the uniformity of the power signal transmitted by the second power transmission layer.

[0147] For example, the plurality of second sub-power patterns 43 correspond one-to-one with other color sub-pixels (such as the first color sub-pixel and the second color sub-pixel) included in the display panel, except for the third color sub-pixel. The second sub-power patterns 43 corresponding to the sub-pixel driving circuits in the other color sub-pixels are respectively coupled to the independent conductive connection portion 21.

[0148] The above configuration allows each sub-pixel driving circuit in other color sub-pixels to be coupled to the corresponding second sub-power pattern 43 via an independent conductive connection 21, and then coupled to the fourth sub-power layer via the second sub-power pattern 43. This configuration not only ensures that each sub-pixel driving circuit in other color sub-pixels can be coupled to the fourth sub-power layer via its corresponding second sub-power pattern 43, guaranteeing the stability of the power signal received by the sub-pixel driving circuit, but also helps reduce the loading of the second power transmission layer and improves the uniformity of the power signal transmitted by the second power transmission layer.

[0149] For example, the plurality of second power connection lines 44 correspond one-to-one with the plurality of second power graphic rows, but are not limited thereto.

[0150] For example, the plurality of second sub-power patterns 43 are divided into multiple columns of second power patterns, each column comprising a plurality of second sub-power patterns 43 arranged along a second direction. The fourth sub-power layer comprises a plurality of second sub-power lines 62, each sub-power line 62 including at least a portion extending along the second direction. Each of the plurality of second sub-power lines 62 corresponds one-to-one with one of the columns of second power patterns, and each second sub-power line 62 is coupled to each second sub-power pattern 43 in its corresponding column.

[0151] As shown in Figures 19 to 23, the second sub-power line 62 is coupled to each of the second sub-power patterns 43 in the corresponding second power pattern column through the twenty-third via Via 23.

[0152] The above configuration allows the third sub-power layer and the fourth sub-power layer to form a grid-like structure of the second power transmission layer. This structure of the power transmission layer has a small loading and the transmitted power signal has good uniformity.

[0153] More specifically, as shown in Figure 27, the display panel includes, sequentially stacked along a direction away from the substrate 70, a buffer layer BF, a first active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, a third gate insulating layer GI3, a second active layer ACT, a fourth gate insulating layer GI4, a third gate metal layer gate3, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a passivation layer PVX, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, a third source / drain metal layer SD3, a third planarization layer PLN3, an anode layer ANO, a pixel boundary layer PDL, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2. The display panel may also include a light-shielding layer located between the first active layer poly and the substrate 70.

[0154] As shown in Figures 7 to 26, in the actual layout of the display panel provided in the above embodiments, the adjacent sub-pixel driving circuits are symmetrically arranged along the first direction.

[0155] Referring to Figures 7 to 26, the specific connection relationships between the various structures in the display panel are explained in detail below.

[0156] As shown in Figures 16 to 20, the first portion 201 of the common conductive connection portion 20 is coupled to the first sub-power pattern 41 through the twentieth via 20. The independent conductive connection portion 21 is coupled to the first sub-power pattern 43 through the twentieth via 20. It should be noted that each sub-pixel driving circuit includes the twentieth via 20, and the functions of the twentieth via 20 included in the sub-pixel driving circuit belonging to the same color unit group Z1 and the sub-pixel driving circuit not belonging to the same color unit group Z1 are different.

[0157] As shown in Figures 7 to 17, the second part 202 of the common conductive connection part 20 is coupled to the second electrode plate C12 of the integrated structure through the sixth via Via6, and the second part 202 is coupled to the first electrode of the power control transistor T5 of the integrated structure through the ninth via Via9.

[0158] As shown in Figures 7 to 17, the independent conductive connection part 21 is coupled to the second electrode plate C12 through the twelfth via Via12, and the independent conductive connection part 21 is coupled to the first electrode of the power control transistor T5 through the eleventh via Via11.

[0159] As shown in Figures 7 to 17, the second conductive connection part 22 is coupled to the first pole of the seventh transistor T7 through the twenty-ninth via Via 29, and the second conductive connection part 22 is coupled to the second initialization signal transmission line V2 through the sixteenth via Via 16.

[0160] As shown in Figures 7 to 23, the third conductive connection part 23 is coupled to the first pole of the seventh transistor T4 through the third via Via3, the third conductive connection part 23 is coupled to the tenth conductive connection part 210 through the nineteenth via Via19, and the tenth conductive connection part 210 is coupled to the data line DL through the twenty-second via Via22.

[0161] As shown in Figures 7 to 17, the fourth conductive connection part 24 is coupled to the gate T3-g of the driving transistor T3 through the fifth via Via5, and the fourth conductive connection part 24 is coupled to the second electrode of the compensation transistor T2 through the seventeenth via Via17.

[0162] As shown in Figures 7 to 17, the fifth conductive connection part 25 is coupled to the second terminal of the first reset transistor T1 through the second via Via2, the fifth conductive connection part 25 is coupled to the first terminal of the compensation transistor T2 through the thirteenth via Via13, and the fifth conductive connection part 25 is coupled to the second terminal of the driving transistor T3 through the fourth via Via4.

[0163] As shown in Figures 7 to 17, the sixth conductive connection part 26 is coupled to the second terminal of the power control transistor T5 through the seventh via Via7, and the sixth conductive connection part 26 is coupled to the second terminal of the third reset transistor T8 through the eighteenth via Via18.

[0164] As shown in Figures 7 to 23, the seventh conductive connection 27 is coupled to the second electrode of the light-emitting control transistor T6 through the eighth via Via8, the seventh conductive connection 27 is coupled to the eleventh conductive connection 211 through the twenty-first via Via21, the eleventh conductive connection 211 is coupled to the twelfth conductive connection 212 through the twenty-fourth via Via24, and the twelfth conductive connection 212 is coupled to the corresponding anode through the twenty-fifth via Via25.

[0165] As shown in Figures 7 to 17, the eighth conductive connection part 28 is coupled to the first pole of the third reset transistor T8 through the tenth via Via10, and the eighth conductive connection part 28 is coupled to the third initialization signal transmission line V3 through the fourteenth via Via14.

[0166] As shown in Figures 7 to 17, the ninth conductive connection part 29 is coupled to the first pole of the first reset transistor T1 through the first via Via1, and the ninth conductive connection part 29 is coupled to the first initialization signal transmission line V3 through the fifteenth via Via15.

[0167] As shown in Figures 29 to 34, this embodiment of the present disclosure also provides a display panel, including a substrate and a plurality of pixel units disposed on the substrate. Each pixel unit includes at least three sub-pixels, and each sub-pixel includes a sub-pixel driving circuit and a light-emitting element coupled to each other. The plurality of pixel units are divided into multiple rows of pixel units H1, and each row of pixel units H1 includes a plurality of pixel units arranged along a first direction. The sub-pixel driving circuits included in each pixel unit are arranged sequentially along the first direction.

[0168] In some embodiments, the pixel unit includes a first color sub-pixel, a second color sub-pixel, and two third color sub-pixels. For example, the first color sub-pixel includes a red sub-pixel, the second color sub-pixel includes a blue sub-pixel, and the third color sub-pixel includes a green sub-pixel.

[0169] As shown in Figures 29 to 34, in some embodiments, in a pixel unit, the sub-pixel driving circuits in the second color sub-pixel (e.g., Db), the sub-pixel driving circuits in the first third color sub-pixel (e.g., Dg), the sub-pixel driving circuits in the first color sub-pixel (e.g., Dr), and the sub-pixel driving circuits in the second third color sub-pixel (e.g., Dg) are arranged sequentially along the first direction.

[0170] As shown in Figures 29 and 30, exemplarily, in the multi-row pixel unit rows, in the pixel units included in the odd-numbered rows, the light-emitting elements (e.g., Er) of the first color sub-pixel, the light-emitting elements (e.g., Eg) of the first third color sub-pixel, the light-emitting elements (e.g., Eb) of the second color sub-pixel, and the light-emitting elements (e.g., Eg) of the second third color sub-pixel are arranged sequentially along the first direction; in the pixel units included in the even-numbered rows, the light-emitting elements (e.g., Eb) of the second color sub-pixel, the light-emitting elements (e.g., Eg) of the first third color sub-pixel, the light-emitting elements (e.g., Er) of the first color sub-pixel, and the light-emitting elements (e.g., Eg) of the second third color sub-pixel are arranged sequentially along the first direction.

[0171] It should be noted that the light-emitting element includes an anode, which comprises an integrally structured anode body and an anode connecting portion. The orthographic projection of the pixel opening area of ​​the light-emitting element onto the substrate is located inside the orthographic projection of the anode body onto the substrate. The anode connecting portion is coupled to the corresponding twelfth conductive connecting portion 212. The shape of the anode body can vary, but it is generally a standard shape, such as a quadrilateral or a circle. The shape of the anode connecting portion also varies, but it is generally a non-standard shape, mainly for electrically connecting the anode body and the twelfth conductive connecting portion 212 together within a limited layout space.

[0172] As shown in Figures 29 and 30, exemplarily, in the multi-row pixel unit rows, in the pixel units included in the odd-numbered rows, the anode body of the light-emitting element (e.g., Er) included in the first color sub-pixel, the anode body of the light-emitting element (e.g., Eg) included in the first third color sub-pixel, the anode body of the light-emitting element (e.g., Eb) included in the second color sub-pixel, and the anode body of the light-emitting element (e.g., Eg) included in the second third color sub-pixel are arranged sequentially along a first direction; simultaneously, the anode body of the light-emitting element (e.g., Er) included in the first color sub-pixel is offset from the anode body of the light-emitting element (e.g., Eg) included in the first third color sub-pixel along a second direction; the anode body of the light-emitting element (e.g., Eb) included in the second color sub-pixel is offset from the anode body of the light-emitting element (e.g., Eg) included in the second third color sub-pixel along a second direction.

[0173] It should be noted that the dashed box in Figure 30 indicates that in the odd-numbered rows of pixel units, the anode body of the light-emitting element (e.g., Er) included in the first color sub-pixel is interchanged with the anode body of the light-emitting element (e.g., Eb) included in the second color sub-pixel. That is, the anode body of the light-emitting element (e.g., Er) included in the first color sub-pixel is placed above the sub-pixel driving circuit (e.g., Db) in the second color sub-pixel, and the anode body of the light-emitting element (e.g., Eb) included in the second color sub-pixel is placed above the sub-pixel driving circuit (e.g., Dr) in the first color sub-pixel.

[0174] As shown in Figures 29 and 30, exemplarily, in the multi-row pixel unit rows, in the pixel units included in the even-numbered rows, the anode body of the light-emitting element (e.g., Eb) included in the second color sub-pixel, the anode body of the light-emitting element (e.g., Eg) included in the first third color sub-pixel, the anode body of the light-emitting element (e.g., Er) included in the first color sub-pixel, and the anode body of the light-emitting element (e.g., Eg) included in the second third color sub-pixel are arranged sequentially along a first direction; simultaneously, the anode body of the light-emitting element (e.g., Er) included in the first color sub-pixel is offset from the anode body of the light-emitting element (e.g., Eg) included in the first third color sub-pixel along a second direction; the anode body of the light-emitting element (e.g., Eb) included in the second color sub-pixel is offset from the anode body of the light-emitting element (e.g., Eg) included in the second third color sub-pixel along a second direction.

[0175] It should be noted that if the anode body of the light-emitting element (e.g., Er) of the first color sub-pixel is swapped with the anode body of the light-emitting element (e.g., Eb) of the second color sub-pixel in an even-numbered row of pixel units, the length of the anode connection of the light-emitting element (e.g., Eb) of the second color sub-pixel will be longer. Since the pixel area (i.e., the area of ​​the pixel opening region) of the second color sub-pixel is larger, that is, the parasitic capacitance of the second color sub-pixel is larger, if the length of the anode connection of the light-emitting element (e.g., Eb) of the second color sub-pixel is longer, the loading of the second color sub-pixel will be further increased, resulting in an increase in the turn-on voltage, which will cause the high-brightness mode to fail.

[0176] By arranging the pixel units in the above manner and changing the swapped positions to odd-numbered rows, the length of the anode connection portion of the light-emitting element (e.g., Er) included in the first color sub-pixel is longer, while the length of the anode connection portion of the light-emitting element (e.g., Eb) included in the second color sub-pixel is shorter. Since the pixel area (i.e., the area of ​​the pixel opening region) of the first color sub-pixel is smaller, that is, the parasitic capacitance of the first color sub-pixel is smaller, even if the length of the anode connection portion of the light-emitting element (e.g., Er) included in the first color sub-pixel is longer, it will increase the loading of the first color sub-pixel. However, the increased loading is still less than the loading of the second color sub-pixel. Therefore, arranging the pixel units in the above manner is beneficial for pixel opening and improves display quality.

[0177] Meanwhile, in current OLED displays, to save bezel space, all GOAs except P_Gate GOAs are designed as one-to-two (i.e., one GOA drives two rows of pixel units). This means that odd-numbered rows of pixel units are charged first, and even-numbered rows are charged later. Since one N_Gate GOA drives two rows of pixel units, the odd-numbered rows that are charged first by P_Gate GOA will have better charging performance than the even-numbered rows that are charged later. Therefore, swapping their positions to the odd-numbered rows will reduce the risk of brightness differences between odd and even rows caused by the difference in charging performance.

[0178] It should be noted that the above P_Gate GOA corresponds to the fourth scan signal line GL4, and N_Gate GOA corresponds to the fifth scan signal line GL4. As shown in Figure 28, GL4_odd represents the signal transmitted by the fourth scan signal line GL4 coupled to the odd-numbered row of pixel units, and GL4_even represents the signal transmitted by the fourth scan signal line GL4 coupled to the even-numbered row of pixel units.

[0179] In some embodiments, in a pixel unit, the subpixel driving circuits in the first color subpixel, the first third color subpixel, the second color subpixel, and the second third color subpixel are arranged sequentially along the first direction.

[0180] For example, in the multi-row pixel unit rows, in the pixel units included in the odd-numbered rows, the light-emitting elements included in the second color sub-pixel, the light-emitting elements included in the first third color sub-pixel, the light-emitting elements included in the first color sub-pixel, and the light-emitting elements included in the second third color sub-pixel are arranged sequentially along the first direction; in the pixel units included in the even-numbered rows, the light-emitting elements included in the first color sub-pixel, the light-emitting elements included in the first third color sub-pixel, the light-emitting elements included in the second color sub-pixel, and the light-emitting elements included in the second third color sub-pixel are arranged sequentially along the first direction.

[0181] As shown in Figures 31 to 34, in some embodiments, in a pixel unit, the sub-pixel driving circuits in the second color sub-pixel (e.g., Db), the sub-pixel driving circuits in the first third color sub-pixel (e.g., Dg), the sub-pixel driving circuits in the first color sub-pixel (e.g., Dr), and the sub-pixel driving circuits in the second third color sub-pixel (e.g., Dg) are arranged sequentially along the first direction.

[0182] For example, in the multi-row pixel unit rows, in the pixel units included in the odd-numbered rows, the light-emitting elements (e.g., Er) of the first color sub-pixel, the light-emitting elements (e.g., Eg) of the first third color sub-pixel, the light-emitting elements (e.g., Eb) of the second color sub-pixel, and the light-emitting elements (e.g., Eg) of the second third color sub-pixel are arranged sequentially along a first direction; the orthographic projection of the anode body of the light-emitting element (e.g., Er) of the first color sub-pixel on the substrate at least partially overlaps with the orthographic projection of the sub-pixel driving circuit (e.g., Dg) of the adjacent third color sub-pixel on the left on the substrate; the orthographic projection of the anode body of the light-emitting element (e.g., Eb) of the second color sub-pixel on the substrate at least partially overlaps with the orthographic projection of the sub-pixel driving circuit (e.g., Dg) of the adjacent third color sub-pixel on the left on the substrate.

[0183] For example, in the pixel units included in the even-numbered rows of pixel units, the light-emitting elements (e.g., Eb) of the second color sub-pixel, the light-emitting elements (e.g., Eg) of the first third color sub-pixel, the light-emitting elements (e.g., Er) of the first color sub-pixel, and the light-emitting elements (e.g., Eg) of the second third color sub-pixel are arranged sequentially along a first direction. The orthographic projection of the anode body of the light-emitting element (e.g., Eb) of the second color sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the sub-pixel driving circuit (e.g., Dg) of the adjacent third color sub-pixel on the right onto the substrate; the orthographic projection of the anode body of the light-emitting element (e.g., Er) of the first color sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the sub-pixel driving circuit (e.g., Dg) of the adjacent third color sub-pixel on the right onto the substrate.

[0184] Arranging the pixel units in the above manner results in a longer anode connection portion of the light-emitting element (e.g., Er) included in the first color sub-pixel, and a shorter anode connection portion of the light-emitting element (e.g., Eb) included in the second color sub-pixel. Since the pixel area (i.e., the area of ​​the pixel opening region) of the first color sub-pixel is smaller, that is, the parasitic capacitance of the first color sub-pixel is smaller, even if the length of the anode connection portion of the light-emitting element (e.g., Er) included in the first color sub-pixel is longer, it will increase the loading of the first color sub-pixel. However, the increased loading is still less than the loading of the second color sub-pixel. Therefore, arranging the pixel units in the above manner is beneficial for pixel opening and improves display quality.

[0185] At the same time, the above settings will reduce the risk of brightness differences between odd and even rows caused by differences in charging between odd and even rows.

[0186] As shown in Figures 4 and 35, in some embodiments, in each pixel unit, the subpixel driving circuits of the first third color subpixel, the second color subpixel, the first color subpixel, and the second third color subpixel are arranged sequentially along a first direction.

[0187] For example, in the multi-row pixel unit rows, in the pixel units included in the odd-numbered rows, the anode body of the light-emitting element (e.g., Er) included in the first color sub-pixel, the anode body of the light-emitting element (e.g., Eg) included in the first third color sub-pixel, the anode body of the light-emitting element (e.g., Eb) included in the second color sub-pixel, and the anode body of the light-emitting element (e.g., Eg) included in the second third color sub-pixel are arranged sequentially along a first direction; at the same time, the anode body of the light-emitting element (e.g., Er) included in the first color sub-pixel is offset from the anode body of the light-emitting element (e.g., Eg) included in the first third color sub-pixel along a second direction; the anode body of the light-emitting element (e.g., Eb) included in the second color sub-pixel is offset from the anode body of the light-emitting element (e.g., Eg) included in the second third color sub-pixel along a second direction.

[0188] By arranging the pixel units in the above manner and changing the swapped positions to odd-numbered rows, the length of the anode connection portion of the light-emitting element (e.g., Er) included in the first color sub-pixel is longer, while the length of the anode connection portion of the light-emitting element (e.g., Eb) included in the second color sub-pixel is shorter. Since the pixel area (i.e., the area of ​​the pixel opening region) of the first color sub-pixel is smaller, that is, the parasitic capacitance of the first color sub-pixel is smaller, even if the length of the anode connection portion of the light-emitting element (e.g., Er) included in the first color sub-pixel is longer, it will increase the loading of the first color sub-pixel. However, the increased loading is still less than the loading of the second color sub-pixel. Therefore, arranging the pixel units in the above manner is beneficial for pixel opening and improves display quality.

[0189] At the same time, swapping the positions to odd-numbered rows will reduce the risk of brightness differences between odd and even rows due to differences in charging between them.

[0190] This disclosure also provides a display device, including the display panel provided in the above embodiments.

[0191] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0192] In the display panel provided in the above embodiment, in the same row of pixel units H1, at least one group of units of the same color Z1 can be formed in every two adjacent pixel units. The group of units of the same color Z1 includes two adjacent sub-pixel driving circuits. The light-emitting elements coupled to the two sub-pixel driving circuits have the same light emission color, and the two sub-pixel driving circuits in the group of units of the same color Z1 are coupled to the same power transmission layer. The above arrangement ensures that in the same row of pixel units H1, every two adjacent pixel units have two sub-pixel driving circuits in the group of units of the same color Z1 sharing the same power transmission layer. This helps to reduce the layout complexity of the display panel, saves the layout space occupied by pixel units and power transmission layers, and thus effectively reduces the layout difficulty of the display panel.

[0193] Therefore, the display device provided in this embodiment of the present disclosure, when including the above-described display panel, also has the above-described beneficial effects, which will not be repeated here.

[0194] It should be noted that the signal line extending in a certain direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0195] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0196] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0197] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0198] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0199] It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "below" another element, the element may be located "directly" on or "below" the other element, or there may be intermediate elements. In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above descriptions are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

A display panel comprising: A substrate and a plurality of pixel units arranged on the substrate, the pixel unit comprising at least three sub-pixels, the sub-pixels comprising a sub-pixel driving circuit and a light emitting element coupled thereto; The plurality of pixel units are divided into a plurality of pixel unit rows, each pixel unit row comprising a plurality of pixel units arranged along a first direction, the sub-pixel driving circuits of each pixel unit are arranged along the first direction in sequence; in the same pixel unit row, the sub-pixel driving circuits of two adjacent pixel units form at least one same-color unit group, the same-color unit group comprising two adjacent sub-pixel driving circuits, the light emitting elements coupled to the two adjacent sub-pixel driving circuits have the same light emitting color; the two sub-pixel driving circuits in the same-color unit group are coupled to the same power transmission layer. The display panel of claim 1, wherein In the same pixel unit row, the sub-pixel driving circuits of two adjacent pixel units form a same-color unit group, the first sub-pixel driving circuit in the same-color unit group belongs to the first pixel unit of the two adjacent pixel units, and the second sub-pixel driving circuit in the same-color unit group belongs to the second pixel unit of the two adjacent pixel units. The display panel of claim 1, wherein, In the same pixel unit row, the sub-pixel driving circuits of two adjacent pixel units form two same-color unit groups, the two sub-pixel driving circuits in the first same-color unit group belong to the first pixel unit of the two adjacent pixel units, and the two sub-pixel driving circuits in the second same-color unit group belong to the second pixel unit of the two adjacent pixel units. The display panel according to claim 2, wherein, Each pixel unit comprises a first color sub-pixel, a second color sub-pixel, and two third color sub-pixels; the two sub-pixel driving circuits in the same-color unit group belong to the third color sub-pixels; In each pixel unit, the first sub-pixel driving circuit of the first color sub-pixel and the second sub-pixel driving circuit of the second color sub-pixel are both located between the two third sub-pixel driving circuits of the two third color sub-pixels. The display panel according to claim 4, wherein, In each pixel unit, the sub-pixel driving circuit of the first third color sub-pixel, the sub-pixel driving circuit of the first color sub-pixel, the sub-pixel driving circuit of the second color sub-pixel, and the sub-pixel driving circuit of the second third color sub-pixel are arranged in sequence along the first direction; or In each pixel unit, the sub-pixel driving circuit of the first third color sub-pixel is arranged between the sub-pixel driving circuit of the first color sub-pixel and the sub-pixel driving circuit of the second color sub-pixel along the first direction. The display panel according to claim 3, wherein, Each pixel unit comprises a first color sub-pixel, a second color sub-pixel, a third color sub-pixel, and a fourth color sub-pixel; the two sub-pixel driving circuits in the same-color unit group belong to the third color and fourth color sub-pixels; In each pixel unit, the two third sub-pixel driving circuits of the two third color sub-pixels are both located between the first sub-pixel driving circuit of the first color sub-pixel and the second sub-pixels driving circuit of the second color sub-pixel. The display panel according to claim 6, wherein In each pixel unit, the sub-pixel driving circuit of the first color sub-pixel, the sub-pixel driving circuit of the first third color sub-pixel, the sub-pixel driving circuit of the second third color sub-pixel, and the sub-pixel driving circuit of the second color sub-pixel are arranged in the first direction in sequence; or, In each pixel unit, the sub-pixel driving circuit of the second color sub-pixel, the sub-pixel driving circuit of the first third color sub-pixel, the sub-pixel driving circuit of the second third color sub-pixel, and the sub-pixel driving circuit of the first color sub-pixel are arranged in the first direction in sequence. The display panel according to claim 5 or 7, wherein In the pixel units included in one of the odd row pixel unit row and the even row pixel unit row, the light emitting elements included in the first color sub-pixel, the light emitting elements included in the first third color sub-pixel, the light emitting elements included in the second color sub-pixel, and the light emitting elements included in the second third color sub-pixel are arranged in the first direction in sequence; In the pixel units included in the other of the odd row pixel unit row and the even row pixel unit row, the light emitting elements of the second color sub-pixel, the light emitting elements of the first third color sub-pixel, the light emitting elements of the first color sub-pixel, and the light emitting elements of the second third color sub-pixel are arranged in the first direction in sequence. The display panel according to claim 5 or 7, wherein The first color sub-pixel includes a red sub-pixel, the second color sub-pixel includes a blue sub-pixel, and the third color sub-pixel includes a green sub-pixel. The display panel according to any one of claims 1 to 7, wherein The plurality of sub-pixel driving circuits included in the plurality of pixel units are divided into a plurality of driving circuit columns, each of the driving circuit columns includes a plurality of sub-pixel driving circuits arranged in a second direction, and the second direction intersects the first direction; The light emitting elements coupled to each of the sub-pixel driving circuits in the driving circuit column have the same light emitting color, and each of the sub-pixel driving circuits in the same driving circuit column is coupled to a corresponding same power transmission layer. The display panel according to any one of claims 1 to 7, wherein The sub-pixel driving circuit includes a driving transistor and a storage capacitor, a first plate of the storage capacitor is coupled to a gate of the driving transistor, and a second plate of the storage capacitor is coupled to the corresponding power transmission layer; The second plates of the storage capacitors included in the two sub-pixel driving circuits in the same color unit group are formed in an integrated structure, and the second plates of the storage capacitors included in the sub-pixel driving circuits of the sub-pixels of different colors are independent of each other. The display panel according to claim 11, wherein, The same color unit group includes a common conductive connection part, and the second plates of the storage capacitors in the integrated structure are coupled to the corresponding power transmission layer through the common conductive connection part. The display panel according to claim 12, wherein, The sub-pixel driving circuit includes a power control transistor, a second electrode of the power control transistor is coupled to a first electrode of the driving transistor; The common conductive connection part includes a first part and a second part coupled to each other, the first part extends in the first direction, and the second part extends in the second direction; The first part is coupled to the corresponding power transmission layer; and The second part is coupled to the corresponding power transmission layer. At least part of the orthographic projection of the second part on the substrate substrate is located between the orthographic projections of the channel portions of the two power control transistors included in the two sub-pixel drive circuits of the same color unit group on the substrate substrate; the first poles of the two power control transistors included in the two sub-pixel drive circuits of the same color unit group are formed as an integrated structure, and the second part is coupled with the first poles of the integrated structure and the second poles of the integrated structure, respectively. The display panel according to claim 13, wherein, The display panel includes a first power transmission layer, and the first power transmission layer includes a first sub-power layer and a second sub-power layer; at least part of the first sub-power layer is located between the second sub-power layer and the substrate substrate; the first sub-power layer is coupled with the second sub-power layer; and the first part is coupled with the first sub-power layer. The display panel according to claim 14, wherein, The first sub-power layer includes a plurality of first sub-power patterns; the first sub-power patterns corresponding to the two sub-pixel drive circuits of the same color unit group, respectively, are coupled with the first part; and the plurality of first sub-power patterns are coupled with the second sub-power layer, respectively. The display panel of claim 15, wherein, The plurality of first sub-power patterns are divided into a plurality of first power pattern rows arranged along a first direction; and the first sub-power layer further includes a plurality of first power connection lines coupled with at least part of the first sub-power patterns in the corresponding first power pattern row. The display panel according to claim 11, wherein, The sub-pixel drive circuit not belonging to the same color unit group includes an independent conductive connection part, and the second pole of the storage capacitor included in the sub-pixel drive circuit not belonging to the same color unit group is coupled with the corresponding power transmission layer through the independent conductive connection part. The display panel of claim 17, wherein, The sub-pixel drive circuit includes a power control transistor, and the second pole of the power control transistor is coupled with the first pole of the drive transistor; the orthographic projection of the independent conductive connection part on the substrate substrate at least partially overlaps with the orthographic projection of the channel portion of the power control transistor on the substrate substrate; and the independent conductive connection part is further coupled with the first pole of the power control transistor. The display panel of claim 18, wherein, The display panel includes a second power transmission layer, and the second power transmission layer includes a third sub-power layer and a fourth sub-power layer; at least part of the third sub-power layer is located between the fourth sub-power layer and the substrate substrate; The third sub-power layer includes a plurality of second sub-power patterns; the second sub-power patterns are coupled with the corresponding independent conductive connection parts; the plurality of second sub-power patterns are coupled with the fourth sub-power layer, respectively; the plurality of second sub-power patterns are divided into a plurality of second power pattern rows arranged along a first direction; the second power pattern row includes a plurality of second sub-power patterns arranged along the first direction; and the third sub-power layer further includes a plurality of second power connection lines coupled with at least part of the second sub-power patterns in the corresponding second power pattern row. The display device includes the display panel according to any one of claims 1-19.

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