Driving method for display panel, and display apparatus

Abstract

A driving method for a display panel, and a display apparatus. The display panel comprises a pixel circuit (200), a first electrode (D1), a plurality of stacked light-emitting units (L1, L2), and a second electrode (D2), which are sequentially located on a base substrate (100), wherein the plurality of stacked light-emitting units (L1, L2) are electrically connected between the first electrode (D1) and the second electrode (D2), the pixel circuit (200) comprises a first reset transistor (T1), and the first reset transistor (T1) is electrically connected to the first electrode (D1). The driving method comprises: (S100) when the current refresh frequency of a display panel is less than a maximum refresh frequency, in a refresh sub-frame in a current display frame, controlling a first reset transistor (T1) to be turned on, and inputting a first initialization voltage to a first electrode (D1), wherein the current display frame comprises a plurality of consecutive display sub-frames, a first display sub-frame sequentially appearing among the plurality of display sub-frames is the refresh sub-frame, and the remaining display sub-frames are holding sub-frames; and (S200) in at least some holding sub-frames in the current display frame, controlling the first reset transistor (T1) to be turned on, and inputting the first initialization voltage to the first electrode (D1).

Description

Display panel driving method and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving method and display device for a display panel. Background Technology

[0002] Tandem organic light-emitting diodes (TANDEM) are OLED device structures formed by stacking multiple traditional OLED devices in series through a charge generation layer (CGL). Display panels manufactured using Tandem OLED technology have advantages such as high current across voltage, low current, and high luminous efficiency. However, the increased sensitivity of Tandem OLED display panels to current leads to problems such as ghosting and flickering at low brightness levels, resulting in noticeable image quality issues. Summary of the Invention

[0003] The present disclosure provides a method for driving a display panel, the display panel comprising: a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes a pixel circuit, a first electrode, a plurality of light-emitting units stacked on the substrate, and a second electrode sequentially disposed on the substrate; the plurality of light-emitting units stacked on the substrate are electrically connected between the first electrode and the second electrode, the pixel circuit is electrically connected to the first electrode, and the pixel circuit includes a first reset transistor, the first reset transistor being electrically connected to the first electrode;

[0004] The driving method includes:

[0005] When the current refresh frequency of the display panel is less than the maximum refresh frequency, in the refresh subframe of the current display frame, the first reset transistor is turned on, and the first initialization voltage is input to the first electrode; wherein, the current display frame includes a plurality of consecutive sub-display frames, the first sub-display frame that appears sequentially among the plurality of sub-display frames is the refresh subframe, and the remaining sub-display frames are hold subframes;

[0006] In at least a portion of the hold subframes within the current display frame, the first reset transistor is turned on, and a first initialization voltage is input to the first electrode.

[0007] In some possible implementations, the current refresh rate is 1 / n of the maximum refresh rate, and the current display frame includes n sub-display frames, where n is an integer greater than 1.

[0008] In some possible implementations, the plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels;

[0009] The first initialization voltage applied to the pixel circuit in the green sub-pixel is less than the first initialization voltage applied to the pixel circuit in the red sub-pixel;

[0010] The first initialization voltage applied to the pixel circuit in the green sub-pixel is less than the first initialization voltage applied to the pixel circuit in the blue sub-pixel.

[0011] In some possible implementations, the signal at the control terminal of the first reset transistor includes an active level and an inactive level in the refresh subframe and at least part of the hold subframe, respectively. The active level at the control terminal of the first reset transistor is used to control the first reset transistor to be turned on, and the inactive level at the control terminal of the first reset transistor is used to control the first reset transistor to be turned off.

[0012] In some possible implementations, the holding subframe includes a first holding subframe and a second holding subframe; the signal at the control terminal of the first reset transistor includes an active level and an inactive level in the first holding subframe; the signal at the control terminal of the first reset transistor includes an inactive level in the second holding subframe.

[0013] There is at least one second hold subframe between any two adjacent first hold subframes.

[0014] In some possible implementations, the pixel circuit further includes a light-emitting control transistor, wherein the signal at the control terminal of the light-emitting control transistor includes an active level and an inactive level in the refresh subframe and each of the hold subframes, respectively; the active level at the control terminal of the light-emitting control transistor is used to control the light-emitting control transistor to be turned on, and the inactive level at the control terminal of the light-emitting control transistor is used to control the light-emitting control transistor to be turned off.

[0015] The duration of the active level of the control terminal of the first reset transistor falls within the duration of the inactive level of the control terminal of the light-emitting control transistor.

[0016] In some possible implementations, the light-emitting control transistor includes: a first light-emitting control transistor and a second light-emitting control transistor;

[0017] In the refresh subframe and hold subframe of the current display frame, the first light-emitting control transistor is turned on to input the first power supply voltage to the first node, and the second light-emitting control transistor is turned on to input the signal of the second node to the first electrode.

[0018] In some possible implementations, the pixel circuit further includes a second reset transistor and a driving transistor, wherein a first terminal of the second reset transistor is electrically connected to a first terminal of the driving transistor; a first terminal of the driving transistor is electrically connected to a first node, and a second terminal of the driving transistor is electrically connected to a second node.

[0019] In the refresh subframe of the current display frame, the second reset transistor is turned on, and the second initialization voltage is input to the first terminal of the driving transistor;

[0020] In at least a portion of the hold subframes in the current display frame, the second reset transistor is turned on, and a second initialization voltage is input to the first terminal of the drive transistor.

[0021] In some possible implementations, the signal at the control terminal of the second reset transistor includes an active level and an inactive level in the refresh subframe and at least part of the hold subframe, respectively. The active level at the control terminal of the second reset transistor is used to control the second reset transistor to be turned on, and the inactive level at the control terminal of the second reset transistor is used to control the second reset transistor to be turned off.

[0022] In some possible implementations, the control terminal of the second reset transistor is electrically connected to the control terminal of the first reset transistor.

[0023] In some possible implementations, the pixel circuit further includes a data writing transistor, wherein the signal at the control terminal of the data writing transistor includes an active level and an inactive level in the refresh subframe, and the signal at the control terminal of the data writing transistor includes an inactive level in each of the hold subframes; the active level of the control terminal of the data writing transistor is used to control the data writing transistor to be turned on, and the inactive level of the control terminal of the data writing transistor is used to control the data writing transistor to be turned off.

[0024] In the refresh subframe, the duration of the active level of the control terminal of the first reset transistor does not overlap with the duration of the active level of the control terminal of the data write transistor.

[0025] In some possible implementations, the pixel circuit further includes a third reset transistor, wherein the signal at the control terminal of the third reset transistor includes an active level and an inactive level in the refresh subframe, and the signal at the control terminal of the third reset transistor includes an inactive level in each of the hold subframes. The active level at the control terminal of the third reset transistor is used to control the third reset transistor to be turned on, and the inactive level at the control terminal of the third reset transistor is used to control the third reset transistor to be turned off.

[0026] In the refresh subframe, the duration of the effective level of the control terminal of the first reset transistor does not overlap with the duration of the effective level of the control terminal of the third reset transistor.

[0027] In some possible implementations, the pixel circuit further includes a threshold compensation transistor, wherein the signal at the control terminal of the threshold compensation transistor includes an active level and an inactive level in the refresh subframe, and the signal at the control terminal of the threshold compensation transistor includes an inactive level in each of the hold subframes; the active level at the control terminal of the threshold compensation transistor is used to control the threshold compensation transistor to be turned on, and the inactive level at the control terminal of the threshold compensation transistor is used to control the threshold compensation transistor to be turned off.

[0028] In the refresh subframe, the duration of the active level of the control terminal of the first reset transistor does not overlap with the duration of the active level of the control terminal of the threshold compensation transistor.

[0029] This disclosure also provides a display device, which includes:

[0030] The display panel includes a substrate, a pixel circuit, a first electrode, a plurality of stacked light-emitting units, and a second electrode sequentially disposed on the substrate; the plurality of stacked light-emitting units are connected between the first electrode and the second electrode, the pixel circuit is electrically connected to the first electrode, and the pixel circuit includes a first reset transistor, which is electrically connected to the first electrode.

[0031] A timing controller, electrically connected to the display panel, is used to control the first reset transistor to turn on in the refresh subframe of the current display frame when the current refresh frequency of the display panel is less than the maximum refresh frequency, and to input the first initialization voltage to the first electrode; wherein, the current display frame includes a plurality of consecutive sub-display frames, the first sub-display frame appearing sequentially in the plurality of sub-display frames is the refresh subframe, and the remaining sub-display frames are hold subframes;

[0032] In at least a portion of the hold subframes within the current display frame, the first reset transistor is turned on, and a first initialization voltage is input to the first electrode. Attached Figure Description

[0033] Figure 1a is a schematic diagram of the structure of the display panel in an embodiment of this disclosure;

[0034] Figure 1b is a simulation curve diagram of an embodiment of this disclosure;

[0035] Figure 2 is a schematic diagram of the pixel circuit provided in an embodiment of this disclosure;

[0036] Figure 3 is a flowchart of the driving method for the display panel provided in an embodiment of this disclosure;

[0037] Figure 4 is a timing diagram of some signals in the embodiments of this disclosure;

[0038] Figure 5 shows some other signal timing diagrams in the embodiments of this disclosure;

[0039] Figure 6 shows some more signal timing diagrams in the embodiments of this disclosure;

[0040] Figure 7 shows some more signal timing diagrams in the embodiments of this disclosure;

[0041] Figure 8 shows some more signal timing diagrams in the embodiments of this disclosure;

[0042] Figure 9 shows some more signal timing diagrams in the embodiments of this disclosure. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0045] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0046] In some embodiments of this disclosure, the display panel may include a substrate and a plurality of sub-pixels disposed on the substrate. Exemplarily, the plurality of sub-pixels may include red, green, and blue sub-pixels, allowing for color mixing of red, green, and blue to achieve color display. Alternatively, the plurality of sub-pixels may include red, green, blue, and white sub-pixels, allowing for color mixing of red, green, blue, and white to achieve color display. Of course, in practical applications, the emission colors of the plurality of sub-pixels can be designed and determined according to the actual application environment, and are not limited thereto.

[0047] In some embodiments of this disclosure, as shown in FIG1a, each sub-pixel may include: a pixel circuit 200, a first electrode D1, a plurality of light-emitting units L1, L2 stacked on a substrate 100, and a second electrode D2; the plurality of light-emitting units L1, L2 stacked are electrically connected between the first electrode D1 and the second electrode D2; the pixel circuit 200 is electrically connected to the first electrode D1, wherein the light-emitting unit L1 is electrically connected to the light-emitting unit L2 through a charge generation layer CGL.

[0048] In some embodiments of this disclosure, as shown in FIG2, the pixel circuit 200 includes a first reset transistor T1, which is electrically connected to a first electrode D1; the control terminal of the first reset transistor T1 is electrically connected to a first reset signal terminal Reset1, the first terminal of the first reset transistor T1 is electrically connected to the first electrode D1, and the second terminal of the first reset transistor T1 is electrically connected to a first initialization signal terminal Vinit1. The first initialization signal terminal Vinit1 is loaded with a first initialization voltage.

[0049] For example, if the control terminal of the first reset transistor T1 is electrically connected to the first reset control signal terminal Reset1, then the signal at the control terminal of the first reset transistor is the first reset signal transmitted on the first reset signal terminal Reset1. For instance, the first reset transistor T1 can be configured as a P-type transistor, in which case the effective level of the first reset signal is low, and the ineffective level of the first reset signal is high. Alternatively, the first reset transistor T1 can also be configured as an N-type transistor, in which case the effective level of the first reset signal is high, and the ineffective level of the first reset signal is low.

[0050] For example, the light-emitting unit can be configured as an electroluminescent diode, such as at least one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro LED, and a mini LED. The light-emitting unit mainly consists of a light-emitting layer, which may further include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0051] For example, the light-emitting layers of multiple light-emitting units can be light-emitting layers of the same color. For instance, if the light-emitting layers of multiple light-emitting units are all red light-emitting layers, they emit red light; or, if the light-emitting layers of multiple light-emitting units are all green light-emitting layers, they emit green light; or, if the light-emitting layers of multiple light-emitting units are all blue light-emitting layers, they emit blue light. Of course, the light-emitting layers of multiple light-emitting units can also be light-emitting layers of different colors. For example, if the light-emitting layers of multiple light-emitting units are red light-emitting layers, green light-emitting layers, and blue light-emitting layers, then white light is emitted by superimposing the red light-emitting layers, green light-emitting layers, and blue light-emitting layers.

[0052] For example, as shown in Figure 1a, a slight short circuit occurs between the charge generation layer CGL and the second electrode D2 at the isolation slot GW position of the display panel. Due to the presence of this slight short circuit, most of the voltage is applied to the light-emitting unit L1. Since the voltage required for multiple light-emitting units L1 and L2 is relatively large, most of the voltage applied to the light-emitting unit L1 will result in most of the charge being injected into the light-emitting unit L1, making the light-emitting unit L1 brighter than normal. However, only a small portion of the charge is injected into the light-emitting unit L2, so the light-emitting unit L2 cannot be turned on for a short time, resulting in abnormal light emission and thus causing a flickering problem. Furthermore, since the green sub-pixels are more sensitive to current, there may be a problem of greening of the display. For example, when performing a ghosting test on the display panel, the simulation curve obtained is shown in Figure 1b, where the horizontal axis represents time and the vertical axis represents brightness. As shown in Figure 1b, the display brightness is as high as 1.1 between 0.07 and 0.12 seconds, which shows that the display brightness between 0.07 and 0.12 seconds is much greater than the display brightness in other time periods. Due to the presence of a slight short circuit, the display panel exhibits a noticeable flashing green tint at low brightness, which affects the display effect and quality, negatively impacting user experience and viewing.

[0053] This disclosure provides a method for driving a display panel, as shown in FIG3, including:

[0054] S100. When the current refresh frequency of the display panel is less than the maximum refresh frequency, in the refresh subframe of the current display frame, the first reset transistor is turned on and the first initialization voltage is input to the first electrode; wherein, the current display frame includes a number of consecutive sub-display frames, the first sub-display frame that appears in sequence among the multiple sub-display frames is the refresh subframe, and the remaining sub-display frames are the hold subframes.

[0055] S200: In at least a portion of the holding subframes in the current display frame, control the first reset transistor to turn on and input the first initialization voltage to the first electrode.

[0056] This embodiment of the present disclosure controls the first reset transistor to be turned on in at least a portion of the holding subframes in the current display frame, and inputs the first initialization voltage to the first electrode. That is, by controlling the first reset transistor to input the first initialization voltage to the first electrode in multiple holding subframes, the voltage difference between the first electrode and the charge generation layer can be improved, thereby making the voltage difference on both sides of the light-emitting unit lower, until multiple light-emitting units emit light simultaneously after charging is completed, thereby avoiding the problem of flashing green in the low brightness state, improving the display effect, and improving the display quality.

[0057] In some embodiments of this disclosure, the current refresh rate is 1 / n of the maximum refresh rate, and the current display frame includes n sub-display frames, where n is an integer greater than 1. For example, if the maximum refresh rate is 120Hz, the current refresh rate can be 60Hz, or 40Hz, or 30Hz, or 10Hz. For example, if the maximum refresh rate is 90Hz, the current refresh rate can be 45Hz, or 30Hz, or 10Hz.

[0058] In some embodiments of this disclosure, the plurality of sub-pixels includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel; wherein, the first initialization voltage applied to the pixel circuit in the green sub-pixel is less than the first initialization voltage applied to the pixel circuit in the red sub-pixel; and the first initialization voltage applied to the pixel circuit in the green sub-pixel is less than the first initialization voltage applied to the pixel circuit in the blue sub-pixel.

[0059] This embodiment of the disclosure, by making the first initialization voltage loaded on the pixel circuit of the green sub-pixel less than the first initialization voltage loaded on the pixel circuit of the red sub-pixel and less than the first initialization voltage loaded on the pixel circuit of the blue sub-pixel, can avoid the green sub-pixel from turning on too quickly after a slight short circuit occurs, thereby further avoiding the problem of greening of the display, improving problems such as ghosting, and improving the display effect.

[0060] For example, as shown in Figure 2, the second electrode D2 is electrically connected to the second power supply voltage terminal VSS, wherein the second power supply voltage terminal VSS is loaded with the second power supply voltage; the first initialization voltage loaded on the pixel circuit in the green sub-pixel is less than or equal to the second power supply voltage.

[0061] For example, as shown in Figure 4, the current display frame includes 12 sub-display frames. Among these 12 sub-display frames, there is one refresh sub-frame F1 and 11 hold sub-frames F2.

[0062] In some embodiments of this disclosure, as shown in Figures 2 and 4, the signal reset1 at the control terminal of the first reset transistor T1 includes an active level (low level) and an inactive level (high level) in the refresh subframe F1 and at least partially hold subframe F2, respectively. The active level (high level) at the control terminal of the first reset transistor T1 is used to control the first reset transistor T1 to be turned on, and the inactive level (low level) at the control terminal of the first reset transistor T1 is used to control the first reset transistor T1 to be turned off.

[0063] In some embodiments of this disclosure, as shown in FIG2, the pixel circuit 200 further includes a light-emitting control transistor T2; wherein, the light-emitting control transistor T2 includes: a first light-emitting control transistor T21 and a second light-emitting control transistor T22; the control terminal of the first light-emitting control transistor T21 is electrically connected to the light-emitting control signal terminal EM, the first terminal of the first light-emitting control transistor T21 is electrically connected to the first power supply voltage terminal VDD, and the second terminal of the first light-emitting control transistor T21 is electrically connected to the first node N1; the control terminal of the second light-emitting control transistor T22 is electrically connected to the light-emitting control signal terminal EM, the first terminal of the second light-emitting control transistor T22 is electrically connected to the second node N2, and the second terminal of the second light-emitting control transistor T22 is electrically connected to the first electrode D1; wherein, a first power supply voltage is applied to the first power supply voltage terminal VDD.

[0064] For example, if the control terminal of the light-emitting control transistor T2 is electrically connected to the light-emitting control signal terminal EM, then the signal at the control terminal of the light-emitting control transistor T2 is the light-emitting control signal transmitted on the light-emitting control signal terminal EM. For instance, the light-emitting control transistor T2 can be configured as a P-type transistor, in which case the effective level of the light-emitting control signal is low, and the ineffective level of the light-emitting control signal is high. Alternatively, the light-emitting control transistor T2 can also be configured as an N-type transistor, in which case the effective level of the light-emitting control signal is high, and the ineffective level of the light-emitting control signal is low.

[0065] In some embodiments of this disclosure, as shown in Figures 2 and 4, the signal em at the control terminal of the light-emitting control transistor T2 includes an effective level (low level) and an invalid level (high level) in the refresh subframe F1 and each hold subframe F2, respectively. The effective level (low level) at the control terminal of the light-emitting control transistor T2 is used to control the light-emitting control transistor T2 to be turned on, and the invalid level (high level) at the control terminal of the light-emitting control transistor T2 is used to control the light-emitting control transistor T2 to be turned off.

[0066] The duration of the active level (low level) of the signal reset1 at the control terminal of the first reset transistor T1 falls within the duration of the inactive level (high level) of the signal em at the control terminal of the light-emitting control transistor.

[0067] In some embodiments of this disclosure, as shown in Figures 2 and 4, in the refresh subframe F1 and hold subframe F2 of the current display frame, the first light-emitting control transistor T21 is turned on to input the first power supply voltage to the first node N1, and the second light-emitting control transistor T22 is turned on to input the signal of the second node N1 to the first electrode D1.

[0068] In some embodiments of this disclosure, as shown in FIG2, the pixel circuit 200 further includes a second reset transistor T3 and a driving transistor T0. The control terminal of the second reset transistor T3 is electrically connected to the first reset signal terminal Reset1, the first terminal of the second reset transistor T3 is electrically connected to the first terminal of the driving transistor T0, and the second terminal of the second reset transistor T3 is electrically connected to the second initialization signal terminal Vinit2. The first terminal of the driving transistor T0 is electrically connected to the first node N1, and the second terminal of the driving transistor T0 is electrically connected to the second node N2. A second initialization voltage is applied to the second initialization signal terminal Vinit2.

[0069] For example, if the control terminal of the second reset transistor T3 is electrically connected to the first reset control signal terminal Reset1, then the signal at the control terminal of the second reset transistor T3 is the first reset signal transmitted on the first reset signal terminal Reset1. For instance, the second reset transistor T3 can be configured as a P-type transistor, in which case the effective level of the first reset signal is low, and the ineffective level is high. Alternatively, the second reset transistor T3 can also be configured as an N-type transistor, in which case the effective level of the first reset signal is high, and the ineffective level is low.

[0070] In some embodiments of this disclosure, as shown in Figures 2 and 4, in the refresh subframe F1 of the current display frame, the second reset transistor T3 is turned on, and the second initialization voltage is input to the first terminal of the drive transistor T0.

[0071] In at least part of the holding subframe F2 in the current display frame, the second reset transistor T3 is turned on, and the second initialization voltage is input to the first terminal of the drive transistor T0.

[0072] In some embodiments of this disclosure, as shown in Figures 2 and 4, the signal reset1 at the control terminal of the second reset transistor T3 includes an active level (high level) and an inactive level (low level) in the refresh subframe F1 and at least partially hold subframe F2, respectively. The active level (high level) at the control terminal of the second reset transistor T3 is used to control the second reset transistor T3 to be turned on, and the inactive level (low level) at the control terminal of the second reset transistor T3 is used to control the second reset transistor to be turned off.

[0073] In some embodiments of this disclosure, as shown in FIG2, the control terminal of the second reset transistor T3 is electrically connected to the control terminal of the first reset transistor T1. That is, both the control terminals of the second reset transistor T3 and the first reset transistor T1 are electrically connected to the first reset signal terminal reset1.

[0074] In some embodiments of this disclosure, as shown in FIG2, the pixel circuit 200 further includes a data writing transistor T4. The control terminal of the data writing transistor T4 is electrically connected to the first scan signal terminal SS1, the first terminal of the data writing transistor T4 is electrically connected to the first node N1, and the second terminal of the data writing transistor T4 is electrically connected to the data writing signal terminal DA.

[0075] For example, if the control terminal of the data writing transistor T4 is electrically connected to the first scan signal terminal SS1, then the signal at the control terminal of the data writing transistor T4 is the first scan signal transmitted on the first scan signal terminal SS1. For instance, the data writing transistor T4 can be configured as a P-type transistor, in which case the effective level of the first scan signal is low and the ineffective level of the first scan signal is high. Alternatively, the data writing transistor T4 can also be configured as an N-type transistor, in which case the effective level of the first scan signal is high and the ineffective level of the first scan signal is low.

[0076] In some embodiments of this disclosure, as shown in Figures 2 and 4, the signal ss1 at the control terminal of the data writing transistor T4 includes an active level (low level) and an inactive level (high level) in the refresh subframe F1, and the signal ss1 at the control terminal of the data writing transistor T4 includes an inactive level (high level) in each hold subframe F2. The active level (low level) at the control terminal of the data writing transistor T4 is used to control the data writing transistor T4 to be turned on, and the inactive level (high level) at the control terminal of the data writing transistor T4 is used to control the data writing transistor T4 to be turned off.

[0077] In refresh subframe F1, the duration of the active level (low level) of the control terminal of the first reset transistor T1 does not overlap with the duration of the active level (low level) of the control terminal of the data write transistor T4.

[0078] In some embodiments of this disclosure, as shown in FIG2, the pixel circuit 200 further includes a third reset transistor T5. The control terminal of the third reset transistor T5 is electrically connected to the second reset signal terminal Reset2, the first terminal of the third reset transistor T5 is electrically connected to the second node N2, and the second terminal of the third reset transistor T5 is electrically connected to the third initialization signal terminal Vinit3.

[0079] For example, if the control terminal of the third reset transistor T5 is electrically connected to the second reset signal terminal Reset2, then the signal at the control terminal of the third reset transistor T5 is the second reset signal transmitted on the second reset signal terminal Reset2. For instance, the third reset transistor T5 can be configured as a P-type transistor, in which case the effective level of the second reset signal is low, and the ineffective level is high. Alternatively, the third reset transistor T5 can also be configured as an N-type transistor, in which case the effective level of the second reset signal is high, and the ineffective level is low.

[0080] In some embodiments of this disclosure, as shown in Figures 2 and 4, the signal reset2 at the control terminal of the third reset transistor T5 includes an active level (low level) and an inactive level (high level) in the refresh subframe F1, and the signal reset2 at the control terminal of the third reset transistor T5 includes an inactive level (high level) in each hold subframe F2. The active level (low level) at the control terminal of the third reset transistor T5 is used to control the third reset transistor T5 to be turned on, and the inactive level (high level) at the control terminal of the third reset transistor T5 is used to control the third reset transistor T5 to be turned off.

[0081] In refresh subframe F1, the duration of the effective level (low level) of the control terminal of the first reset transistor T1 does not overlap with the duration of the effective level (low level) of the control terminal of the third reset transistor T5.

[0082] In some embodiments of this disclosure, as shown in FIG2, the pixel circuit 200 further includes a threshold compensation transistor T6. The control terminal of the threshold compensation transistor T6 is electrically connected to the second scan signal terminal SS2, the first terminal of the threshold compensation transistor T6 is electrically connected to the gate of the driving transistor T0, and the second terminal of the threshold compensation transistor T6 is electrically connected to the second node N2.

[0083] For example, if the control terminal of the threshold compensation transistor T6 is electrically connected to the second scan signal terminal SS2, then the signal at the control terminal of the threshold compensation transistor T6 is the second scan signal transmitted on the second scan signal terminal SS2. For instance, the threshold compensation transistor T6 can be configured as a P-type transistor, in which case the effective level of the second scan signal is low, and the ineffective level is high. Alternatively, the threshold compensation transistor T6 can also be configured as an N-type transistor, in which case the effective level of the second scan signal is high, and the ineffective level is low.

[0084] In some embodiments of this disclosure, as shown in Figures 2 and 4, the signal ss2 at the control terminal of the threshold compensation transistor T6 includes an active level (high level) and an inactive level (low level) in the refresh subframe F1, and the signal ss2 at the control terminal of the threshold compensation transistor T6 includes an inactive level (low level) in each hold subframe F2. The active level (high level) at the control terminal of the threshold compensation transistor T6 is used to control the threshold compensation transistor T6 to be turned on, and the inactive level (low level) at the control terminal of the threshold compensation transistor T6 is used to control the threshold compensation transistor T6 to be turned off.

[0085] In refresh subframe F1, the duration of the effective level (low level) of the control terminal of the first reset transistor T1 does not overlap with the duration of the effective level (high level) of the control terminal of the threshold compensation transistor T6.

[0086] In some embodiments of this disclosure, as shown in FIG2, the pixel circuit 200 further includes a first capacitor Cst, the first plate of the first capacitor Cst being electrically connected to a first power supply voltage terminal, and the second plate of the first capacitor Cst being electrically connected to the gate of the driving transistor T0.

[0087] It should be noted that in the embodiments of this disclosure, the first electrode of the transistor can be its source and the second electrode can be its drain; or the first electrode can be its drain and the second electrode can be its source. This can be designed and determined according to the needs of the actual application.

[0088] In this embodiment, the threshold compensation transistor T6 and the second reset transistor T3 can be configured as N-type transistors, and the active layer materials of both the threshold compensation transistor T6 and the second reset transistor T3 can be configured as metal-oxide-semiconductor materials, i.e., both the threshold compensation transistor T6 and the second reset transistor T3 can be configured as oxide-type transistors. This results in lower leakage current for the threshold compensation transistor T6 and the second reset transistor T3. Furthermore, the first reset transistor T1, the light-emitting control transistor T2, the data writing transistor T4, the third reset transistor T5, and the driving transistor T0 can be configured as P-type transistors, and the active layer materials of these transistors can be configured as low-temperature polycrystalline silicon materials, i.e., all the first reset transistor T1, the light-emitting control transistor T2, the data writing transistor T4, the third reset transistor T5, and the driving transistor T0 can be configured as LTPS-type transistors. This results in higher mobility for the first reset transistor T1, the light-emitting control transistor T2, the data writing transistor T4, the third reset transistor T5, and the driving transistor T0, allowing them to be made thinner, smaller, and with lower power consumption. By combining the transistor fabrication processes of LTPS and oxide transistors to fabricate LTPO pixel circuits using low-temperature polycrystalline silicon oxide, the leakage current of the driving transistor gate can be reduced, as can the power consumption.

[0089] The embodiments disclosed herein, by controlling the first reset transistor to input the first initialization voltage to the first electrode in multiple holding subframes, can avoid the problem of flashing green in low brightness states, improve the display effect, and enhance the display quality.

[0090] When the display panel is in a high brightness state, the signal timing diagram of the display panel is shown in Figure 5. When the display panel is in a low brightness state, the signal timing diagram of the display panel is shown in Figure 4. When the display panel is adjusted from a high brightness state to a low brightness state, there may be a problem of uneven brightness adjustment, and the lower the brightness, the more obvious the problem of uneven brightness adjustment.

[0091] Based on this, in some embodiments of this disclosure, as shown in FIG6, the holding subframe F2 includes a first holding subframe F21 and a second holding subframe F22; the signal reset1 at the control terminal of the first reset transistor T1 includes an active level (low level) and an inactive level (high level) in the first holding subframe F21; the signal at the control terminal of the first reset transistor T1 includes an inactive level (high level) in the second holding subframe F22; there is at least one second holding subframe F22 between two adjacent first holding subframes F21.

[0092] By having at least one second holding subframe between two adjacent first holding subframes, the brightness adjustment of the display panel from a high brightness state to a low brightness state is smoother, improving the display effect and enhancing the user experience.

[0093] In some embodiments of this disclosure, as shown in FIG5, in the first brightness range, the current display frame has one refresh subframe F1 and two hold subframes F2, wherein the signal reset1 at the control terminal of the first reset transistor T1 includes an active level (low level) and an inactive level (high level) in the refresh subframe F1 and each hold subframe F2, respectively.

[0094] In some embodiments of this disclosure, as shown in FIG6, in the second brightness range, the current display frame has one refresh subframe F1 and eleven hold subframes F2, wherein one hold subframe F2 includes two first hold subframes F21 and nine second hold subframes F22, and there are three second hold subframes F22 between two adjacent first hold subframes F21; wherein the signal reset1 of the control terminal of the first reset transistor T1 includes an active level (low level) and an inactive level (high level) in the first hold subframe F21; the signal reset1 of the control terminal of the first reset transistor T1 includes an inactive level (high level) in the second hold subframe F22;

[0095] In some embodiments of this disclosure, as shown in FIG4, in the third brightness range, the current display frame has one refresh subframe F1 and eleven hold subframes F2, wherein the signal reset1 at the control terminal of the first reset transistor T1 includes an active level (low level) and an inactive level (high level) in the refresh subframe F1 and each hold subframe F2, respectively.

[0096] For example, when adjusting from the first brightness range to the third brightness range, it passes through the second brightness range. By having three second hold subframes F22 between two adjacent first hold subframes F21 in the second brightness range, the smoothness of the adjustment from the first brightness range to the third brightness range can be improved, thereby enhancing the display effect and user experience.

[0097] In some embodiments of this disclosure, as shown in FIG5, in the first brightness range, the current display frame has one refresh subframe F1 and two hold subframes F2, wherein the signal reset1 at the control terminal of the first reset transistor T1 includes an active level (low level) and an inactive level (high level) in the refresh subframe F1 and each hold subframe F2, respectively.

[0098] In some embodiments of this disclosure, as shown in FIG7, in the second brightness range, the current display frame has one refresh subframe F1 and five hold subframes F2, wherein the five hold subframes F2 include two first hold subframes F21 and three second hold subframes F22, and there is one second hold subframe F22 between two adjacent first hold subframes F21; wherein the signal reset1 of the control terminal of the first reset transistor T1 includes an active level (low level) and an inactive level (high level) in the first hold subframe F21; the signal reset1 of the control terminal of the first reset transistor T1 includes an inactive level (high level) in the second hold subframe F22;

[0099] In some embodiments of this disclosure, as shown in FIG8, in the third brightness range, the current display frame has one refresh subframe F1 and five hold subframes F2, wherein the signal reset1 at the control terminal of the first reset transistor T1 includes an active level (low level) and an inactive level (high level) in the refresh subframe F1 and each hold subframe F2, respectively.

[0100] In some embodiments of this disclosure, as shown in FIG9, in the fourth brightness range, the current display frame has one refresh subframe F1 and 11 hold subframes F2, wherein the 11 hold subframes F2 include 5 first hold subframes F21 and 6 second hold subframes F22, and there is one second hold subframe F22 between two adjacent first hold subframes F21; wherein the signal reset1 of the control terminal of the first reset transistor T1 includes an active level (low level) and an inactive level (high level) in the first hold subframe F21; the signal reset1 of the control terminal of the first reset transistor T1 includes an inactive level (high level) in the second hold subframe F22;

[0101] In some embodiments of this disclosure, as shown in FIG4, in the fifth brightness range, the current display frame has one refresh subframe F1 and eleven hold subframes F2, wherein the signal reset1 at the control terminal of the first reset transistor T1 includes an active level (low level) and an inactive level (high level) in the refresh subframe F1 and each hold subframe F2, respectively.

[0102] For example, when adjusting from the first brightness range to the fifth brightness range, the adjustment passes through the second brightness range, the third brightness range, and the fourth brightness range. By having a second holding subframe F22 between two adjacent first holding subframes F21 in the second and fourth brightness ranges, the smoothness of the adjustment from the first brightness range to the fifth brightness range can be further improved, thereby enhancing the display effect and user experience.

[0103] This disclosure also provides a display device, including:

[0104] The display panel includes a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes a pixel circuit, a first electrode, a plurality of light-emitting units stacked on the substrate, and a second electrode, which are sequentially located on the substrate; the plurality of light-emitting units stacked on the substrate are connected between the first electrode and the second electrode; the pixel circuit is electrically connected to the first electrode; the pixel circuit includes a first reset transistor, which is electrically connected to the first electrode.

[0105] A timing controller, electrically connected to the display panel, is used to control the first reset transistor to turn on in the refresh subframe of the current display frame when the current refresh frequency of the display panel is less than the maximum refresh frequency, and input the first initialization voltage to the first electrode; wherein, the current display frame includes a plurality of consecutive sub-display frames, the first sub-display frame appearing sequentially among the plurality of sub-display frames is the refresh subframe, and the remaining sub-display frames are hold subframes;

[0106] In at least a portion of the hold subframes in the current display frame, the first reset transistor is turned on, and a first initialization voltage is input to the first electrode.

[0107] It should be noted that the working principle and specific implementation method of this display device are the same as those of the driving method in the above embodiments. Therefore, the working method of this display device can be implemented by referring to the specific implementation method of the driving method in the above embodiments, and will not be repeated here.

[0108] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0109] The display panel driving method and display device provided in this disclosure can, when the current refresh frequency is less than the maximum refresh frequency, control the first reset transistor to be turned on in the refresh sub-frame of the current display frame, and input a first initialization voltage to the first electrode. The current display frame includes a plurality of consecutive sub-display frames, where the first sub-display frame appearing sequentially is the refresh sub-frame, and the remaining sub-display frames are hold sub-frames. In at least some of the hold sub-frames of the current display frame, the first reset transistor is turned on, and the first initialization voltage is input to the first electrode. That is, by controlling the first reset transistor to input the first initialization voltage to the first electrode in the plurality of hold sub-frames, the voltage difference between the first electrode and the charge generation layer can be improved, thereby reducing the voltage difference across the light-emitting unit until the plurality of light-emitting units emit light simultaneously after charging is complete. This avoids the problem of flashing green in low-brightness states, improves the display effect, and enhances the display quality.

[0110] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0111] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A method for driving a display panel, wherein, The display panel includes: a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes a pixel circuit, a first electrode, a plurality of light-emitting units stacked on the substrate, and a second electrode, which are sequentially located on the substrate; the plurality of light-emitting units stacked on the substrate are electrically connected between the first electrode and the second electrode; the pixel circuit is electrically connected to the first electrode; the pixel circuit includes a first reset transistor, which is electrically connected to the first electrode. The driving method includes: When the current refresh frequency of the display panel is less than the maximum refresh frequency, in the refresh subframe of the current display frame, the first reset transistor is turned on, and the first initialization voltage is input to the first electrode; wherein, the current display frame includes a plurality of consecutive sub-display frames, the first sub-display frame that appears sequentially among the plurality of sub-display frames is the refresh subframe, and the remaining sub-display frames are hold subframes; In at least a portion of the hold subframes within the current display frame, the first reset transistor is turned on, and a first initialization voltage is input to the first electrode.

2. The driving method as described in claim 1, wherein, The current refresh rate is 1 / n of the maximum refresh rate, and the current display frame includes n sub-display frames, where n is an integer greater than 1.

3. The driving method as described in claim 1, wherein, The plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels; The first initialization voltage applied to the pixel circuit in the green sub-pixel is less than the first initialization voltage applied to the pixel circuit in the red sub-pixel; The first initialization voltage applied to the pixel circuit in the green sub-pixel is less than the first initialization voltage applied to the pixel circuit in the blue sub-pixel.

4. The driving method according to any one of claims 1-3, wherein, The signal at the control terminal of the first reset transistor includes an active level and an inactive level in the refresh subframe and at least part of the hold subframe, respectively. The active level at the control terminal of the first reset transistor is used to control the first reset transistor to be turned on, and the inactive level at the control terminal of the first reset transistor is used to control the first reset transistor to be turned off.

5. The driving method as described in claim 4, wherein, The holding subframe includes a first holding subframe and a second holding subframe; the signal at the control terminal of the first reset transistor includes an active level and an inactive level in the first holding subframe; the signal at the control terminal of the first reset transistor includes an inactive level in the second holding subframe; There is at least one second hold subframe between any two adjacent first hold subframes.

6. The driving method as described in claim 4, wherein, The pixel circuit further includes a light-emitting control transistor. The signal at the control terminal of the light-emitting control transistor includes an active level and an inactive level in the refresh subframe and each of the hold subframes, respectively. The active level at the control terminal of the light-emitting control transistor is used to control the light-emitting control transistor to be turned on, and the inactive level at the control terminal of the light-emitting control transistor is used to control the light-emitting control transistor to be turned off. The duration of the active level of the control terminal of the first reset transistor falls within the duration of the inactive level of the control terminal of the light-emitting control transistor.

7. The driving method as described in claim 6, wherein, The light-emitting control transistor includes: a first light-emitting control transistor and a second light-emitting control transistor; In the refresh subframe and hold subframe of the current display frame, the first light-emitting control transistor is turned on to input the first power supply voltage to the first node, and the second light-emitting control transistor is turned on to input the signal of the second node to the first electrode.

8. The driving method according to any one of claims 1-7, wherein, The pixel circuit further includes a second reset transistor and a driving transistor, wherein a first terminal of the second reset transistor is electrically connected to a first terminal of the driving transistor; a first terminal of the driving transistor is electrically connected to a first node, and a second terminal of the driving transistor is electrically connected to a second node. In the refresh subframe of the current display frame, the second reset transistor is turned on, and the second initialization voltage is input to the first terminal of the driving transistor; In at least a portion of the hold subframes in the current display frame, the second reset transistor is turned on, and a second initialization voltage is input to the first terminal of the drive transistor.

9. The driving method as described in claim 8, wherein, The signal at the control terminal of the second reset transistor includes an active level and an inactive level in the refresh subframe and at least part of the hold subframe, respectively. The active level at the control terminal of the second reset transistor is used to control the second reset transistor to be turned on, and the inactive level at the control terminal of the second reset transistor is used to control the second reset transistor to be turned off.

10. The driving method as described in claim 8 or 9, wherein, The control terminal of the second reset transistor is electrically connected to the control terminal of the first reset transistor.

11. The driving method according to any one of claims 1-10, wherein, The pixel circuit further includes a data writing transistor. The signal at the control terminal of the data writing transistor includes an active level and an inactive level in the refresh subframe. The signal at the control terminal of the data writing transistor includes an inactive level in each of the hold subframes. The active level of the control terminal of the data writing transistor is used to control the data writing transistor to be turned on, and the inactive level of the control terminal of the data writing transistor is used to control the data writing transistor to be turned off. In the refresh subframe, the duration of the active level of the control terminal of the first reset transistor does not overlap with the duration of the active level of the control terminal of the data write transistor.

12. The driving method according to any one of claims 1-10, wherein, The pixel circuit further includes a third reset transistor. The signal at the control terminal of the third reset transistor includes an active level and an inactive level in the refresh subframe. The signal at the control terminal of the third reset transistor includes an inactive level in each of the hold subframes. The active level of the control terminal of the third reset transistor is used to control the third reset transistor to be turned on, and the inactive level of the control terminal of the third reset transistor is used to control the third reset transistor to be turned off. In the refresh subframe, the duration of the effective level of the control terminal of the first reset transistor does not overlap with the duration of the effective level of the control terminal of the third reset transistor.

13. The driving method according to any one of claims 1-10, wherein, The pixel circuit further includes a threshold compensation transistor. The signal at the control terminal of the threshold compensation transistor includes an active level and an inactive level in the refresh subframe. The signal at the control terminal of the threshold compensation transistor includes an inactive level in each of the hold subframes. The active level of the control terminal of the threshold compensation transistor is used to control the threshold compensation transistor to be turned on, and the inactive level of the control terminal of the threshold compensation transistor is used to control the threshold compensation transistor to be turned off. In the refresh subframe, the duration of the active level of the control terminal of the first reset transistor does not overlap with the duration of the active level of the control terminal of the threshold compensation transistor.

14. A display device, wherein, include: The display panel includes a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes a pixel circuit, a first electrode, a plurality of light-emitting units stacked on the substrate, and a second electrode, which are sequentially located on the substrate; the plurality of light-emitting units stacked on the substrate are connected between the first electrode and the second electrode; the pixel circuit is electrically connected to the first electrode; the pixel circuit includes a first reset transistor, which is electrically connected to the first electrode. A timing controller, electrically connected to the display panel, is used to control the first reset transistor to turn on in the refresh subframe of the current display frame when the current refresh frequency of the display panel is less than the maximum refresh frequency, and to input the first initialization voltage to the first electrode; wherein, the current display frame includes a plurality of consecutive sub-display frames, the first sub-display frame appearing sequentially in the plurality of sub-display frames is the refresh subframe, and the remaining sub-display frames are hold subframes; In at least a portion of the hold subframes within the current display frame, the first reset transistor is turned on, and a first initialization voltage is input to the first electrode.

Images