Gate driving circuit and driving method therefor, and display apparatus

Abstract

A gate driving circuit and a driving method therefor, and a display apparatus. The gate driving circuit comprises: N cascaded selection units (100); N control units (200), wherein a first input end of an i-th control unit (200) is electrically connected to an output end of an i-th selection unit (100), a second input end of the i-th control unit (200) is electrically connected to an enable signal end (EN), and a third input end of the i-th control unit (200) is electrically connected to a control signal end (GSTV); and N scanning groups (300), wherein each scanning group (300) comprises a plurality of cascaded shift registers (310), an input end of the first shift register (310) in an i-th scanning group (300) is electrically connected to an output end of the i-th control unit (200), and an output end of the last shift register (310) in a j-th scanning group (300) is electrically connected to a fourth input end of a (j+1)-th control unit (200). Each selection unit (100) comprises: a first gating circuit (110) and a second gating circuit (120); and each control unit (200) is configured to connect one of a third input end and a fourth input end to an output end of the control unit (200).

Description

Gate driving circuit and its driving method, display device Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a gate driving circuit and its driving method, and a display device. Background Technology

[0002] In a display device, a gate driving circuit is used to provide scanning signals to the gate lines of the display panel to control the pixels of the display panel to be turned on line by line. Each time a row of pixels is turned on, the source driving circuit provides data signals to the row of pixels that are turned on, thereby refreshing the pixels.

[0003] Generally, display panels (such as those in mobile phones) typically have only one refresh rate per frame. At a high refresh rate, the display panel refreshes from top to bottom at a high frequency; at a low refresh rate, the display panel refreshes from top to bottom at a low frequency. However, high refresh rates result in high power consumption, which poses a challenge to battery capacity and lifespan, while low refresh rates can cause display flickering or reduced smoothness. Summary of the Invention

[0004] This disclosure provides a gate driving circuit and driving method thereof, as well as a display device.

[0005] In a first aspect, this disclosure provides a gate driving circuit, comprising:

[0006] The N cascaded selection units are configured to sequentially output a first level signal in response to a start signal provided by a start signal terminal and a signal provided by a first clock signal terminal.

[0007] N control units; the first input terminal of the i-th control unit is electrically connected to the output terminal of the i-th selection unit, the second input terminal of the i-th control unit is electrically connected to the enable signal terminal, and the third input terminal of the i-th control unit is electrically connected to the control signal terminal;

[0008] There are N scan groups, each scan group comprising multiple cascaded shift registers. The input of the first shift register in the i-th scan group is electrically connected to the output of the i-th control unit, and the output of the last shift register in the j-th scan group is electrically connected to the fourth input of the (j+1)-th control unit. Wherein, N is a positive integer greater than 1, i is a positive integer less than or equal to N, and j is a positive integer less than N.

[0009] The selection unit includes a first gating circuit and a second gating circuit, wherein the first gating circuit and the second gating circuit are electrically connected to a first node, and the second gating circuit is electrically connected to the control unit to a second node.

[0010] The first gating circuit is configured to control the connection and disconnection between the first level signal terminal and the first node, and the connection and disconnection between the second level signal terminal and the first node, in response at least to the input signal at the input terminal of the selection unit and the signal at the first clock signal terminal.

[0011] The second gating circuit is configured to, at least in response to the signal of the first node, control the on / off state between the first level signal terminal and the second node, and the on / off state between the second level signal terminal and the second node;

[0012] The control unit is configured to connect one of the third input terminal and the fourth input terminal to the output terminal of the control unit in response to the signal of the second node and the signal of the enable signal terminal.

[0013] In some embodiments, the first gating circuit includes:

[0014] The first control sub-circuit is configured to control the first level signal terminal to be turned on with the first node in response to the second level signal at the input terminal of the selection unit and the second level signal at the second clock signal terminal.

[0015] The second control sub-circuit is configured to control the second level signal terminal to be turned on with the first node in response to the first level signal at the input terminal of the selection unit and the first level signal at the first clock signal terminal.

[0016] The signals at the first clock signal terminal and the second clock signal terminal switch between a first level and a second level, and the signals at the first clock signal terminal and the second clock signal terminal are out of phase for at least a portion of the time.

[0017] In some embodiments, the first control sub-circuit includes: a first transistor and a second transistor, wherein the gate of the first transistor is electrically connected to the second clock signal terminal, the first terminal of the first transistor is electrically connected to the first level signal terminal, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the gate of the second transistor is electrically connected to the input terminal of the selection unit, and the second terminal of the second transistor is electrically connected to the first node.

[0018] The second control sub-circuit includes a third transistor and a fourth transistor. The gate of the third transistor is electrically connected to the input terminal of the selection unit. The first terminal of the third transistor is electrically connected to the first node. The second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor. The second terminal of the fourth transistor is electrically connected to the second level signal terminal. The gate of the fourth transistor is electrically connected to the first clock signal terminal.

[0019] In some embodiments, the first gating circuit further includes:

[0020] The inverting sub-circuit is configured to invert the signal at the first clock signal terminal and then provide it to the second clock signal terminal.

[0021] In some embodiments, the inverting sub-circuit includes: a fifth transistor and a sixth transistor, the gates of the fifth transistor and the sixth transistor are both electrically connected to the first clock signal terminal, the first terminal of the fifth transistor is electrically connected to the first level signal terminal, the second terminal of the fifth transistor and the first terminal of the sixth transistor are both electrically connected to the second clock signal terminal, and the second terminal of the sixth transistor is electrically connected to the second level signal terminal;

[0022] One of the fifth transistor and the sixth transistor is an N-type transistor, and the other is a P-type transistor.

[0023] In some embodiments, the second gating circuit includes:

[0024] The third control sub-circuit is configured to connect the first level signal terminal to the first node in response to the second level signal of the first clock signal terminal and the second level signal of the second node.

[0025] The fourth control sub-circuit is configured to connect the second level signal terminal to the first node in response to the first level signal of the second clock signal terminal and the first level signal of the second node;

[0026] The fifth control sub-circuit is configured to, in response to a first level signal from the first node, connect the second level signal terminal to the second node; or, in response to a second level signal from the first node, connect the first level signal terminal to the second node.

[0027] In some embodiments, the third control sub-circuit includes: a seventh transistor and an eighth transistor, wherein the gate of the seventh transistor is electrically connected to the first clock signal terminal, the first terminal of the seventh transistor is electrically connected to the first level signal terminal, the second terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor, the second terminal of the eighth transistor is electrically connected to the first node, and the gate of the eighth transistor is electrically connected to the second node.

[0028] The fourth control sub-circuit includes a ninth transistor and a tenth transistor. The gate of the ninth transistor is electrically connected to the second node, the first terminal of the ninth transistor is electrically connected to the first node, the second terminal of the ninth transistor is electrically connected to the first terminal of the tenth transistor, the second terminal of the tenth transistor is electrically connected to the second level signal terminal, and the gate of the tenth transistor is electrically connected to the second clock signal terminal.

[0029] The fifth control sub-circuit includes an eleventh transistor and a twelfth transistor. The gate of the eleventh transistor and the gate of the twelfth transistor are both electrically connected to the first node. The first terminal of the eleventh transistor is electrically connected to the first level signal terminal. The second terminal of the eleventh transistor and the first terminal of the twelfth transistor are both electrically connected to the second node. The second terminal of the twelfth transistor is electrically connected to the second level signal terminal.

[0030] Among them, one of the eighth transistor and the ninth transistor is an N-type transistor and the other is a P-type transistor. The eleventh transistor is of the same type as the eighth transistor, and the twelfth transistor is of the same type as the ninth transistor.

[0031] In some embodiments, the second gating circuit includes:

[0032] The third control sub-circuit is configured to connect the first level signal terminal to the first node in response to the second level signal of the second node.

[0033] The fourth control sub-circuit is configured to connect the second level signal terminal to the first node in response to the first level signal of the second node;

[0034] The fifth control sub-circuit is configured to, in response to a first level signal from the first node, connect the second level signal terminal to the second node; or, in response to a second level signal from the first node, connect the first level signal terminal to the second node.

[0035] In some embodiments, the third control sub-circuit includes: an eighth transistor, the gate of which is electrically connected to the second node, the first terminal of which is electrically connected to the first level signal terminal, and the second terminal of which is electrically connected to the first node;

[0036] The fourth control sub-circuit includes: a ninth transistor, the gate of which is electrically connected to the second node, the first terminal of which is electrically connected to the first node, and the second terminal of which is electrically connected to the second level signal terminal;

[0037] The fifth control sub-circuit includes an eleventh transistor and a twelfth transistor. The gates of the eleventh transistor and the twelfth transistor are both electrically connected to the first node. The first terminal of the eleventh transistor is electrically connected to the first level signal terminal. The second terminal of the eleventh transistor and the first terminal of the twelfth transistor are both electrically connected to the second node. The second terminal of the twelfth transistor is electrically connected to the second level signal terminal.

[0038] In some embodiments, the control unit includes: an intermediate control circuit and an output control circuit, wherein the intermediate control circuit and the output control circuit are electrically connected to a third node and a fourth node;

[0039] The intermediate control circuit is configured to control the potentials of the third node and the fourth node in response to the signal of the second node, the signal of the enable signal terminal and the signal of the reset signal terminal;

[0040] The output control circuit is configured to, in response to the third level signal of the third node and the fourth level signal of the fourth node, connect one of the third input terminal and the fourth input terminal to the output terminal of the control unit; and in response to the fourth level signal of the third node and the third level signal of the fourth node, connect the other of the third input terminal and the fourth input terminal to the output terminal of the control unit.

[0041] In some embodiments, the intermediate control circuit includes an enable sub-circuit, a latch sub-circuit, and a reset sub-circuit, wherein the enable sub-circuit, the latch sub-circuit, and the reset sub-circuit are electrically connected to the fourth node;

[0042] The enabling sub-circuit is configured to, in response to a first level signal from the second node, connect the enabling signal terminal to the fourth node; or, in response to both a first level signal from the second node and a second level signal from the enabling signal terminal, connect the first level signal terminal to the fourth node.

[0043] The reset sub-circuit is configured to, in response to the reset signal at the reset signal terminal, connect the second level signal terminal to the fourth node to provide a second level signal to the fourth node;

[0044] The latch sub-circuit is configured to provide the third node with a signal that is inversely phase to the signal of the fourth node, and to maintain the potentials of the fourth node and the third node when the fourth node is in a floating state.

[0045] In some embodiments, the enabling sub-circuit includes: a thirteenth transistor, the gate of which is electrically connected to the second node, a first terminal of which is electrically connected to the enable signal terminal, and a second terminal of which is electrically connected to the fourth node; or,

[0046] The enabling sub-circuit includes: a thirteenth transistor and a fourteenth transistor.

[0047] The gate of the thirteenth transistor is electrically connected to the second node, and the second terminal of the thirteenth transistor is electrically connected to the fourth node;

[0048] The gate of the fourteenth transistor is electrically connected to the enable signal terminal, the first terminal of the fourteenth transistor is electrically connected to the first level signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the first terminal of the thirteenth transistor.

[0049] In some embodiments, the latch sub-circuit includes: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor;

[0050] The gates of the fifteenth transistor and the sixteenth transistor are both electrically connected to the third node. The first terminal of the fifteenth transistor is electrically connected to the third level signal terminal. The second terminals of the fifteenth transistor and the first terminals of the sixteenth transistor are both electrically connected to the fourth node. The second terminal of the sixteenth transistor is electrically connected to the fourth level signal terminal.

[0051] The gates of the seventeenth transistor and the eighteenth transistor are both electrically connected to the fourth node. The first terminal of the seventeenth transistor is electrically connected to the third level signal terminal. The second terminal of the seventeenth transistor and the first terminal of the eighteenth transistor are both electrically connected to the third node. The second terminal of the eighteenth transistor is electrically connected to the fourth level signal terminal.

[0052] Of the fifteenth and sixteenth transistors, one is an N-type transistor and the other is a P-type transistor; the seventeenth transistor is of the same type as the fifteenth transistor, and the eighteenth transistor is of the same type as the sixteenth transistor.

[0053] In some embodiments, the reset sub-circuit includes:

[0054] The nineteenth transistor has its gate electrically connected to the reset signal terminal, its first terminal electrically connected to the fourth node, and its second terminal electrically connected to the second level signal terminal.

[0055] In some embodiments, the output control circuit includes: a twentieth transistor, a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor;

[0056] The gate of the twentieth transistor is electrically connected to the fourth node, the gate of the twentieth transistor is electrically connected to the third node, the first terminals of the twentieth and twentieth transistors are both electrically connected to the fourth input terminal of the control unit, and the second terminals of the twentieth and twentieth transistors are both electrically connected to the output terminal of the control unit.

[0057] The gate of the 22nd transistor is electrically connected to the third node, the gate of the 23rd transistor is electrically connected to the fourth node, the first terminals of the 22nd transistor and the 23rd transistor are both electrically connected to the third input terminal of the control unit, and the second terminals of the 22nd transistor and the 23rd transistor are both electrically connected to the output terminal of the control unit.

[0058] Secondly, this disclosure also provides a gate driving circuit, comprising:

[0059] The N cascaded selection units are configured to sequentially output a first level signal in response to a start signal provided by a start signal terminal and a signal provided by a first clock signal terminal.

[0060] N control units; the first input terminal of the i-th control unit is electrically connected to the output terminal of the i-th selection unit at the second node, the second input terminal of the i-th control unit is electrically connected to the enable signal terminal, and the third input terminal of the i-th control unit is electrically connected to the control signal terminal;

[0061] There are N scan groups, each scan group comprising multiple cascaded shift registers. The input of the first shift register in the i-th scan group is electrically connected to the output of the i-th control unit, and the output of the last shift register in the j-th scan group is electrically connected to the fourth input of the (j+1)-th control unit. Wherein, N is a positive integer greater than 1, i is a positive integer less than or equal to N, and j is a positive integer less than N.

[0062] The control unit includes an intermediate control circuit and an output control circuit, wherein the intermediate control circuit and the output control circuit are electrically connected to the third node and the fourth node;

[0063] The intermediate control circuit is configured to control the potentials of the third node and the fourth node in response to the signal of the second node, the signal of the enable signal terminal and the signal of the reset signal terminal;

[0064] The output control circuit is configured to, in response to the third level signal of the third node and the fourth level signal of the fourth node, connect one of the third input terminal and the fourth input terminal to the output terminal of the control unit; and in response to the fourth level signal of the third node and the third level signal of the fourth node, connect the other of the third input terminal and the fourth input terminal to the output terminal of the control unit.

[0065] In some embodiments, the intermediate control circuit includes an enable sub-circuit, a latch sub-circuit, and a reset sub-circuit, wherein the enable sub-circuit, the latch sub-circuit, and the reset sub-circuit are electrically connected to the fourth node;

[0066] The enabling sub-circuit is configured to, in response to a first level signal from the second node, connect the enabling signal terminal to the fourth node; or, in response to both a first level signal from the second node and a second level signal from the enabling signal terminal, connect the first level signal terminal to the fourth node.

[0067] The reset sub-circuit is configured to, in response to the reset signal at the reset signal terminal, connect the second level signal terminal to the fourth node to provide a second level signal to the fourth node;

[0068] The latch sub-circuit is configured to provide the third node with a signal that is inversely phase to the signal of the fourth node, and to maintain the potentials of the fourth node and the third node when the fourth node is in a floating state.

[0069] In some embodiments, the enabling sub-circuit includes: a thirteenth transistor, the gate of which is electrically connected to the second node, a first terminal of which is electrically connected to the enable signal terminal, and a second terminal of which is electrically connected to the fourth node; or,

[0070] The enabling sub-circuit includes: a thirteenth transistor and a fourteenth transistor.

[0071] The gate of the thirteenth transistor is electrically connected to the second node, and the second terminal of the thirteenth transistor is electrically connected to the fourth node;

[0072] The gate of the fourteenth transistor is electrically connected to the enable signal terminal, the first terminal of the fourteenth transistor is electrically connected to the first level signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the first terminal of the thirteenth transistor.

[0073] In some embodiments, the latch sub-circuit includes: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor;

[0074] The gates of the fifteenth transistor and the sixteenth transistor are both electrically connected to the third node. The first terminal of the fifteenth transistor is electrically connected to the third level signal terminal. The second terminals of the fifteenth transistor and the first terminals of the sixteenth transistor are both electrically connected to the fourth node. The second terminal of the sixteenth transistor is electrically connected to the fourth level signal terminal.

[0075] The gates of the seventeenth transistor and the eighteenth transistor are both electrically connected to the fourth node. The first terminal of the seventeenth transistor is electrically connected to the third level signal terminal. The second terminals of the seventeenth transistor and the first terminals of the eighteenth transistor are both electrically connected to the third node. The second terminal of the eighteenth transistor is electrically connected to the fourth level signal terminal.

[0076] In some embodiments, the reset sub-circuit includes:

[0077] The nineteenth transistor has its gate electrically connected to the reset signal terminal, its first terminal electrically connected to the fourth node, and its second terminal electrically connected to the second level signal terminal.

[0078] In some embodiments, the output control circuit includes: a twentieth transistor, a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor;

[0079] The gate of the twentieth transistor is electrically connected to the fourth node, the gate of the twentieth transistor is electrically connected to the third node, the first terminals of the twentieth and twentieth transistors are both electrically connected to the fourth input terminal of the control unit, and the second terminals of the twentieth and twentieth transistors are both electrically connected to the output terminal of the control unit.

[0080] The gate of the 22nd transistor is electrically connected to the third node, the gate of the 23rd transistor is electrically connected to the fourth node, the first terminals of the 22nd transistor and the 23rd transistor are both electrically connected to the third input terminal of the control unit, and the second terminals of the 22nd transistor and the 23rd transistor are both electrically connected to the output terminal of the control unit.

[0081] Thirdly, this disclosure also provides a driving method for the gate driving circuit as described above, comprising:

[0082] A start signal is provided to the first selection unit among the N selection units, so that the N selection units output a first level signal in sequence;

[0083] The signal potentials of the control signal terminal and the enable signal terminal of each of the selection units are controlled so that each of the shift registers outputs a corresponding scan signal.

[0084] In some embodiments, the gate driving circuit is used to provide a scanning signal to the display panel, the display panel including N display sub-regions, each display sub-region having a refresh frequency independently selected from one of a first frequency and a second frequency, the first frequency being greater than the second frequency; each selection unit corresponds to one display sub-region; wherein, the maximum value of the first frequency is related to the output frequency of the selection unit.

[0085] In some embodiments, when the refresh frequency of the display sub-region is the first frequency, the scan signals output by each shift register in the scan group corresponding to the display sub-region sequentially reach the first level potential; the step of controlling the signal potential of the control signal terminal and the enable signal terminal of each selection unit so that each shift register outputs the corresponding scan signal specifically includes:

[0086] When the refresh frequency of the kth display sub-region is the same as the refresh frequency of the (k-1)th display sub-region, the signal potential of the enable signal terminal is controlled so that the fourth input terminal and the output terminal of the kth control unit are turned on.

[0087] When the refresh frequency of the (k-1)th display sub-region is the first frequency and the refresh frequency of the kth display sub-region is the second frequency, the signal potential of the enable signal terminal is controlled so that the third input terminal and the output terminal of the kth control unit are connected, and a second level signal is provided to the control signal terminal so that the scan signals output by each shift register in the kth scan group are all at the second level potential;

[0088] When the refresh frequency of the (k-1)th display sub-region is the second frequency and the refresh frequency of the kth display sub-region is the first frequency, the signal potential of the enable signal terminal is controlled so that the third input terminal and the output terminal of the kth control unit are connected, and a trigger signal at the first level potential is provided to the control signal terminal so that the scan signals output by each shift register in the kth scan group sequentially reach the first level potential.

[0089] Fourthly, this disclosure provides a display device, including the gate driving circuit described above, and a display panel. The display panel includes N display sub-regions, each display sub-region having multiple gate lines. Each scan group corresponds to one display sub-region, and the shift register in the scan group is electrically connected to the gate line in the corresponding display sub-region. Attached Figure Description

[0090] Figure 1 is a schematic diagram of the gate driving circuit and display panel provided in some embodiments of this disclosure.

[0091] Figure 2 is a schematic diagram of the selection unit provided in some embodiments of this disclosure.

[0092] Figure 3 is another schematic diagram of the selection unit provided in some embodiments of this disclosure.

[0093] Figure 4 is a schematic diagram of a control unit provided in some embodiments of this disclosure.

[0094] Figure 5 is a schematic diagram of the selection unit and control unit provided in some embodiments of this disclosure.

[0095] Figure 6 is a timing diagram of the selection unit and control unit shown in Figure 5.

[0096] Figure 7 is a timing diagram of a gate drive circuit provided in some embodiments of this disclosure.

[0097] Figure 8 is another timing diagram of the gate drive circuit provided in some embodiments of this disclosure.

[0098] Figure 9 is another specific circuit diagram of the selection unit and control unit provided in some embodiments of this disclosure.

[0099] Figure 10 is a timing diagram of the selection unit and control unit shown in Figure 9.

[0100] Figure 11 is another specific circuit diagram of the selection unit and control unit provided in some embodiments of this disclosure.

[0101] Figure 12A is another schematic diagram of the selection unit provided in some embodiments of this disclosure.

[0102] Figure 12B is another specific circuit diagram of the selection unit and control unit provided in some embodiments of this disclosure. Detailed Implementation

[0103] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0104] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this disclosure do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this disclosure are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to such processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this disclosure are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” in this disclosure refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can indicate: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," "third," etc., used in this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. "Above," "below," "left," "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0105] It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between them. In the embodiments of this disclosure, to distinguish the source and drain of the transistor, one of them is called the first terminal, the other is called the second terminal, and the gate is called the control terminal. Furthermore, according to their characteristics, transistors can be classified into N-type and P-type. When an N-type transistor is used, the first terminal is the source, the second terminal is the drain, and when the gate input is high, the source and drain are conducting; the opposite is true for P-type transistors. Additionally, according to the material of the active layer in the transistor, transistors can be classified into oxide thin-film transistors, low-temperature polycrystalline silicon thin-film transistors, etc. Generally, oxide thin-film transistors are N-type transistors, and low-temperature polycrystalline silicon thin-film transistors are P-type transistors.

[0106] Figure 1 is a schematic diagram of a gate driving circuit and a display panel provided in some embodiments of this disclosure. As shown in Figure 1, the gate driving circuit includes N cascaded selection units 100, N control units 200, and N scan groups 300, where N is a positive integer greater than 1. The input terminal of the first-stage selection unit 100 is electrically connected to the start signal terminal STV, and the input terminal of each selection unit 100 from the second stage to the last stage is electrically connected to the output terminal of the previous stage selection unit 100. The N selection units 100 are configured to sequentially output a first-level signal in response to the start signal provided by the start signal terminal STV and the signal provided by the first clock signal terminal CK1. One of the first level and the second level is high, and the other is low. For example, if the first level is high and the second level is low, then the first-level signal, the first-level signal terminal VGH1, and the first-level potential are respectively a high-level signal, a high-level signal terminal, and a high-level potential; the second-level signal, the second-level signal terminal VGL1, and the second-level potential are respectively a low-level signal, a low-level signal terminal, and a low-level potential.

[0107] Each control unit 200 is connected to a selection unit 100 in a one-to-one correspondence. The first input terminal of the i-th control unit 200 is electrically connected to the output terminal of the i-th selection unit 100, the second input terminal of the i-th control unit 200 is electrically connected to the enable signal terminal EN, and the third input terminal of the i-th control unit 200 is electrically connected to the control signal terminal GSTV. The enable signal terminal EN connected to each control unit 200 can be electrically connected to the same enable signal line ENL, and the control signal terminal GSTV connected to each control unit 200 can be electrically connected to the same control signal line.

[0108] Each scan group 300 is connected to a control unit 200 in a one-to-one correspondence. Each scan group 300 includes multiple cascaded shift registers 310. The number of shift registers 310 in each scan group 300 is not limited; for example, each scan group 300 may include 4, 6, 8, or 12 shift registers 310, or other numbers of shift registers 310. The input terminal of the first shift register 310 in the i-th scan group 300 is electrically connected to the output terminal of the i-th control unit 200, and the output terminal of the last shift register 310 in the j-th scan group 300 is electrically connected to the fourth input terminal of the (j+1)-th control unit 200; where i is a positive integer less than or equal to N, and j is a positive integer less than N. In other words, the input terminal of the first shift register 310 in each scan group 300 is electrically connected to the output terminal of the corresponding control unit 200. Except for the last scan group 300, the output terminal of the last shift register 310 in each of the remaining scan groups 300 is electrically connected to the fourth input terminal of the control unit 200 corresponding to the next scan group 300.

[0109] Figure 2 is a schematic diagram of a selection unit 100 provided in some embodiments of this disclosure. The selection unit 100 includes a first gating circuit 110 and a second gating circuit 120. The first gating circuit 110 and the second gating circuit 120 are electrically connected to a first node N1, and the second gating circuit 120 is electrically connected to a control unit 200 at a second node N2. The first gating circuit 110 is configured to control the on / off state between a first level signal terminal VGH1 and the first node N1, and between a second level signal terminal VGL1 and the first node N1, at least in response to the input signal at the input terminal IN of the selection unit 100 and the signal at the first clock signal terminal CK1. The second gating circuit 120 is configured to control the on / off state between the first level signal terminal VGH1 and the second node N2, and between the second level signal terminal VGL1 and the second node N2, at least in response to the signal at the first node N1.

[0110] In this embodiment of the disclosure, the control unit 200 is configured to connect one of the third input terminal and the fourth input terminal to the output terminal of the control unit 200 in response to the signal provided by the second node N2 and the enable signal terminal EN.

[0111] The gate driving circuit in this embodiment enables the display panel to achieve HRD (Hybrid Refresh Display). Specifically, the display area of ​​the display panel can be divided into N display sub-regions 410, each corresponding to a scan group 300. For the k-th display sub-region 410, when the refresh rate of the k-th display sub-region 410 is the same as that of the (k-1)-th display sub-region 410, when the k-th selection unit 100 outputs a first level signal, the signal potential of the enable signal terminal EN is controlled to make the fourth input terminal and output terminal of the k-th control unit 200 conduct, thereby electrically connecting the input terminal of the first shift register 310 in the k-th scan group 300 to the output terminal of the last shift register 310 in the (k-1)-th scan group 300. Consequently, the scan signals provided by each shift register 310 in the k-th scan group 300 and the (k-1)-th scan group 300 to the corresponding gate line sequentially reach the effective level potential. For example, the scanning direction is shown in Figure 1. When the k-th display sub-region 410 uses a high refresh rate and the (k-1)-th display sub-region 410 uses a low refresh rate, when the k-th selection unit 100 outputs a first level signal, the signal potential of the enable signal terminal EN is controlled to make the third input terminal and output terminal of the k-th control unit 200 conduct, and provide an invalid level signal to the aforementioned control signal terminal GSTV, so that the first shift register 310 in the k-th scan group 300 receives an invalid level signal, thereby making the scan signals output by each shift register 310 in the k-th scan group 300 reach the invalid level potential. When the k-th display sub-region 410 uses a low refresh rate and the (k-1)-th display sub-region 410 uses a high refresh rate, when the k-th selection unit 100 outputs a first-level signal, the signal potential of the enable signal terminal EN is controlled to connect the third input terminal and the output terminal of the k-th control unit 200, and a trigger signal with an effective level potential is provided to the control signal terminal GSTV. This causes the first shift register 310 in the k-th scan group 300 to receive the trigger signal at an effective level potential, and the scan signals output by each shift register 310 in the k-th scan group 300 sequentially reach the effective level potential. 1 < k ≤ N, and k is a positive integer.

[0112] The valid level signal (or potential) at the output of shift register 310 refers to the signal (or potential) used to turn on the transistor connected to the gate line; the invalid level signal (or potential) refers to the signal (or potential) used to turn off the transistor connected to the gate line.

[0113] When the display panel simultaneously contains both high refresh rate and low refresh rate areas, the shift register 310 corresponding to the low refresh rate area only needs to maintain an invalid level signal output, without needing to cascade signal transmission with the shift register 310 corresponding to the high refresh rate area. This frees up time in the low refresh rate area for the high refresh rate area, thereby achieving ultra-high refresh rates. For example, if the display panel includes three display sub-areas 410, each containing 800 rows of pixels, assuming the first and third display sub-areas 410 use low refresh rates and the second display sub-area 410 uses a high refresh rate, then when driving the display panel, the first and third scan groups 300 of the gate drive circuit do not operate. The 800 shift registers 310 of the second scan group 300 sequentially output valid level signals, allowing the second display sub-area 410 to utilize more time for ultra-high frequency operation, achieving smooth display. The first and third display sub-areas 410 achieve ultra-low refresh rates, thus reducing power consumption.

[0114] As shown in Figure 2, in some embodiments, the first gating circuit 110 includes a first control sub-circuit 111 and a second control circuit. The first control sub-circuit 111 is configured to control the first level signal terminal VGH1 to conduct with the first node N1 in response to the second level signal of the input terminal IN of the selection unit 100 and the second level signal of the first clock signal terminal CB1. The second control sub-circuit 112 is configured to control the second level signal terminal VGL1 to conduct with the first node N1 in response to the first level signal of the input terminal IN of the selection unit 100 and the first level signal of the first clock signal terminal CK1. The signals of the first clock signal terminal CK1 and the second clock signal terminal CB1 switch between the first level and the second level, and the signals of the first clock signal terminal CK1 and the second clock signal terminal CB1 are out of phase for at least a portion of the time. In one example, when the signal of one of the first clock signal terminal CK1 and the second clock signal terminal CB1 is at the first level potential, the other is at the second level potential.

[0115] In some embodiments, the second gating circuit 120 includes a third control sub-circuit 121, a fourth control sub-circuit 122, and a fifth control sub-circuit 123. The third control sub-circuit 121 is configured to connect the first level signal terminal VGH1 to the first node N1 in response to a second level signal from the first clock signal terminal CK1 and a second level signal from the second node N2. The fourth control sub-circuit 122 is configured to connect the second level signal terminal VGL1 to the first node N1 in response to a first level signal from the second clock signal terminal CB1 and a first level signal from the second node N2. The fifth control sub-circuit 123 is configured to connect the second level signal terminal VGL1 to the second node N2 in response to a first level signal from the first node N1; or, in response to a second level signal from the first node N1, connect the first level signal terminal VGH1 to the second node N2.

[0116] For the selection unit 100 shown in Figure 2, the second clock signal terminal CB1 can be connected to the driver chip through the clock signal line, thereby receiving the second clock signal directly provided by the driver chip.

[0117] In some embodiments, as shown in FIG3, the first gating circuit 110, in addition to including the first control sub-circuit 111 and the second control sub-circuit 112 described above, also includes an inverting sub-circuit 113. The inverting sub-circuit 113 is configured to invert the signal of the first clock signal terminal CK1 and provide it to the second clock signal terminal CB1. In this case, the second clock signal terminal CB1 is actually the connection node between the inverting sub-circuit 113 and the first control sub-circuit 111, and the driver chip does not need to directly provide a clock signal to the second clock signal terminal CB1 of the selection unit 100. The structure of the second gating circuit 120 in the selection unit 100 shown in FIG3 is the same as that of the second gating circuit 120 in FIG2, and will not be described again here.

[0118] Figure 4 is a schematic diagram of a control unit 200 provided in some embodiments of this disclosure. As shown in Figure 4, the control unit 200 includes an intermediate control circuit 210 and an output control circuit 220, which are electrically connected to a third node N3 and a fourth node N4.

[0119] Intermediate control circuit 210 is configured to control the potentials of third node N3 and fourth node N4 in response to the signal of second node N2, the signal of enable signal terminal EN, and the signal of reset signal terminal Reset. Output control circuit 220 is configured to connect one of the third input terminal and the fourth input terminal to the output terminal of control unit 200 in response to the third level signal of third node N3 and the fourth level signal of fourth node N4; and to connect the other of the third input terminal and the fourth input terminal to the output terminal of control unit 200 in response to the fourth level signal of third node N3 and the third level signal of fourth node N4. Wherein, one of the third level and the fourth level is high, and the other is low. For example, if the third level is high and the fourth level is low, correspondingly, the third level signal, the third level signal terminal VGH2, and the third level potential are high level signal, high level signal terminal, and high level potential, respectively; and the fourth level signal, the fourth level signal terminal VGL2, and the fourth level potential are low level signal, low level signal terminal, and low level potential, respectively. It should be noted that when the first level signal terminal VGH1 and the third level signal terminal VGH2 are both high level signal terminals, and the second level signal terminal VGL1 and the fourth level signal terminal VGL2 are both low level signal terminals, the potential of the signals provided by the first level signal terminal VGH1 and the third level signal terminal VGH2 can be the same or different; the potential of the signals provided by the second level signal terminal VGL1 and the fourth level signal terminal VGL2 can be the same or different.

[0120] In some embodiments, the intermediate control circuit 210 includes an enable sub-circuit 221, a latch sub-circuit 213, and a reset sub-circuit 212, which are electrically connected to the fourth node N4.

[0121] The enable sub-circuit 221 is configured to, in response to the first level signal of the second node N2, turn on the enable signal terminal EN and the fourth node N4; or, in response to the first level signal of the second node N2 and the second level signal of the enable signal terminal EN, turn on the first level signal terminal VGH1 and the fourth node N4.

[0122] The reset sub-circuit 212 is configured to, in response to the reset signal at the Reset terminal, connect the second-level signal terminal VGL1 to the fourth node N4, thereby providing a second-level signal to the fourth node N4. The Reset terminal can load a reset signal before each frame is displayed, thus resetting the fourth node N4.

[0123] The latch circuit 213 is configured to provide the third node N3 with a signal that is inversely phase to the signal of the fourth node N4, and to maintain the potentials of the fourth node N4 and the third node N3 when the fourth node N4 is in a floating state.

[0124] Figure 5 is a schematic diagram of the selection unit 100 and control unit 200 provided in some embodiments of this disclosure. As shown in Figure 5, in some embodiments, the selection unit 100 includes a first gating circuit 110 and a second gating circuit 120. The first gating circuit 110 includes a first control sub-circuit 111, a second control sub-circuit 112, and an inverting sub-circuit 113. The first control sub-circuit 111 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is electrically connected to the second clock signal terminal CB1, the first terminal of the first transistor T1 is electrically connected to the first level signal terminal VGH1, the second terminal of the first transistor T1 is electrically connected to the first terminal of the second transistor T2, the gate of the second transistor T2 is electrically connected to the input terminal IN of the selection unit 100, and the second terminal of the second transistor T2 is electrically connected to the first node N1.

[0125] The second control sub-circuit 112 includes a third transistor T3 and a fourth transistor T4. The gate of the third transistor T3 is electrically connected to the input terminal IN of the selection unit 100. The first terminal of the third transistor T3 is electrically connected to the first node N1. The second terminal of the third transistor T3 is electrically connected to the first terminal of the fourth transistor T4. The second terminal of the fourth transistor T4 is electrically connected to the second level signal terminal VGL1. The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CK1. The inverting sub-circuit 113 includes a fifth transistor T5 and a sixth transistor T6. The gates of both the fifth transistor T5 and the sixth transistor T6 are electrically connected to the first clock signal terminal CK1. The first terminal of the fifth transistor T5 is electrically connected to the first level signal terminal VGH1. The second terminals of both the fifth transistor T5 and the sixth transistor T6 are electrically connected to the second clock signal terminal CB1. The second terminal of the sixth transistor T6 is electrically connected to the second level signal terminal VGL1. One of the fifth transistor T5 and the sixth transistor T6 is an N-type transistor, and the other is a P-type transistor.

[0126] Referring again to Figure 5, the second gating circuit 120 includes a third control sub-circuit 121, a fourth control sub-circuit 122, and a fifth control sub-circuit 123. The third control sub-circuit 121 includes a seventh transistor T7 and an eighth transistor T8. The gate of the seventh transistor T7 is electrically connected to the first clock signal terminal CK1, the first terminal of the seventh transistor T7 is electrically connected to the first level signal terminal VGH1, the second terminal of the seventh transistor T7 is electrically connected to the first terminal of the eighth transistor T8, the second terminal of the eighth transistor T8 is electrically connected to the first node N1, and the gate of the eighth transistor T8 is electrically connected to the second node N2.

[0127] The fourth control sub-circuit 122 includes: a ninth transistor T9 and a tenth transistor T10. The gate of the ninth transistor T9 is electrically connected to the second node N2, the first terminal of the ninth transistor T9 is electrically connected to the first node N1, the second terminal of the ninth transistor T9 is electrically connected to the first terminal of the tenth transistor T10, the second terminal of the tenth transistor T10 is electrically connected to the second level signal terminal VGL1, and the gate of the tenth transistor T10 is electrically connected to the second clock signal terminal CB1.

[0128] The fifth control sub-circuit 123 includes an eleventh transistor T11 and a twelfth transistor T12. The gates of both transistors are electrically connected to the first node N1. The first terminal of transistor T11 is electrically connected to the first level signal terminal VGH1. The second terminals of both transistors are electrically connected to the second node N2. The second terminal of transistor T12 is electrically connected to the second level signal terminal VGL1. One of the eighth transistor T8 and the ninth transistor T9 is an N-type transistor, and the other is a P-type transistor. Transistor T11 is of the same type as transistor T8, and transistor T12 is of the same type as transistor T9. For example, transistors T8 and T11 can both be N-type transistors, and transistors T9 and T12 can both be P-type transistors. Transistors T8, T9, T11, and T12 constitute a latch.

[0129] Referring again to Figure 5, in some embodiments, the control unit 200 includes an intermediate control circuit 210 and an output control circuit 220. The intermediate control circuit 210 includes an enable sub-circuit 221, a latch sub-circuit 213, and a reset sub-circuit 212. The enable sub-circuit 221 includes a thirteenth transistor T13, the gate of which is electrically connected to the second node N2, the first terminal of which is electrically connected to the enable signal terminal EN, and the second terminal of which is electrically connected to the fourth node N4.

[0130] The latch circuit 213 includes: a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18. The gates of both the fifteenth transistor T15 and the sixteenth transistor T16 are electrically connected to the third node N3. The first terminal of the fifteenth transistor T15 is electrically connected to the third-level signal terminal VGH2. The second terminals of both the fifteenth transistor T15 and the sixteenth transistor T16 are electrically connected to the fourth node N4. The second terminal of the sixteenth transistor T16 is electrically connected to the fourth-level signal terminal VGL2. Similarly, the gates of both the seventeenth transistor T17 and the eighteenth transistor T18 are electrically connected to the fourth node N4. The first terminal of the seventeenth transistor T17 is electrically connected to the third-level signal terminal VGH2. The second terminals of both the seventeenth transistor T17 and the eighteenth transistor T18 are electrically connected to the third node N3. The second terminal of the eighteenth transistor T18 is electrically connected to the fourth-level signal terminal VGL2. The reset circuit 212 includes: a nineteenth transistor T19, the gate of which is electrically connected to the reset signal terminal Reset; the first terminal of which is electrically connected to the fourth node N4; and the second terminal of which is electrically connected to the second level signal terminal VGL1. One of the fifteenth transistor T15 and the sixteenth transistor T16 is an N-type transistor, and the other is a P-type transistor; the seventeenth transistor T17 is of the same type as the fifteenth transistor T15, and the eighteenth transistor T18 is of the same type as the sixteenth transistor T16.

[0131] Referring again to Figure 5, the output control circuit 220 includes: a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, and a twenty-third transistor T23. The gate of the twentieth transistor T20 is electrically connected to the fourth node N4, and the gate of the twenty-first transistor T21 is electrically connected to the third node N3. The first terminals of both the twentieth transistor T20 and the twenty-first transistor T21 are electrically connected to the fourth input terminal of the control unit 200, and the second terminals of both the twentieth transistor T20 and the twenty-first transistor T21 are electrically connected to the output terminal of the control unit 200. Similarly, the gate of the twenty-second transistor T22 is electrically connected to the third node N3, and the gate of the twenty-third transistor T23 is electrically connected to the fourth node N4. The first terminals of both the twenty-second transistor T22 and the twenty-third transistor T23 are electrically connected to the third input terminal of the control unit 200, and the second terminals of both the twenty-second transistor T22 and the twenty-third transistor T23 are electrically connected to the output terminal of the control unit 200.

[0132] When the fourth node N4 is at the first level potential and the third node N3 is at the second level potential, the twentieth transistor T20 and the twenty-first transistor T21 are turned off, while the twenty-second transistor T22 and the twenty-third transistor T23 are turned on. This connects the fourth input terminal and the output terminal of the control unit 200, that is, the input terminal G_in(n+1) of the shift register 310 connected to the control unit 200 is connected to the control signal terminal GSTV. When the fourth node N4 is at the second level potential and the third node N3 is at the first level potential, the twentieth transistor T20 and the twenty-first transistor T21 are turned on, while the twenty-second transistor T22 and the twenty-third transistor T23 are turned off. This connects the output terminal and the fourth input terminal of the control unit 200, that is, the input terminal G_in(n+1) of the shift register 310 connected to the control unit 200 is connected to the output terminal G_out(n) of the previous stage shift register 310.

[0133] Figure 6 is a timing diagram of the selection unit 100 and control unit 200 shown in Figure 5. The following description uses the example of a high-level signal for the first level and a low-level signal for the second level to illustrate the operation of the selection unit 100 and control unit 200 shown in Figure 5. Specifically, transistors T1, T2, T5, T7, T8, T11, T15, T17, T20, and T22 are all P-type transistors; transistors T3, T4, T6, T9, T10, T12, T13, T19, T16, T18, T21, and T23 are all N-type transistors.

[0134] Referring to Figures 5 and 6, in the first stage t1, the input terminal IN of the selection unit 100 provides a high-level signal, and the first clock signal terminal CK1 provides a low-level signal. At this time, the third transistor T3 and the fifth transistor T5 are turned on; the second transistor T2 and the fourth transistor T4 are turned off; the first node N1 maintains the high-level potential of the previous stage, thereby turning on the twelfth transistor T12 and turning off the eleventh transistor T11. The second node N2 maintains the low-level potential of the previous stage, thereby turning on the seventh transistor T7 and the eighth transistor T8, and turning off the ninth transistor T9. In the second stage t2, both the input terminal IN of the selection unit 100 and the first clock signal terminal CK1 provide high-level signals. At this time, the fourth transistor T4 is turned off, and the fifth transistor T5 and the sixth transistor T6 are turned on, thereby connecting the second-level signal terminal VGL1 to the first node N1, pulling down the potential of the first node N1. Because the potential of the first node N1 is pulled low, the eleventh transistor T11 is turned on and the twelfth transistor T12 is turned off, thereby connecting the first level signal terminal VGH1 with the second node N2, and the scanning unit outputs a high-level signal. In the third stage t3, both the input terminal IN of the selection unit 100 and the first clock signal terminal CK1 provide low-level signals. At this time, the fifth transistor T5 is turned on, and the second clock signal terminal CB1 is connected to the first level signal terminal VGH1, thereby reaching a high-level potential, which in turn turns off the first transistor T1. In addition, because the input terminal IN of the selection unit 100 receives a low-level signal, the third transistor T3 and the fourth transistor T4 are both turned off. Under the holding effect of the latch composed of the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12, the potentials of the first node N1 and the second node N2 remain unchanged from the previous stage. In the fourth stage t4, a low-level signal is input to the input terminal IN of selection unit 100, and a high-level signal is input to the first clock signal terminal CK1. At this time, the sixth transistor T6 is turned on, thereby pulling down the potential of the second clock signal terminal CB1, which in turn turns on the first transistor T1. In addition, under the control of the low-level signal provided at the input terminal, the second transistor T2 is turned on, and the third transistor T3 and the fourth transistor T4 are turned off, thereby connecting the first node N1 with the first level signal terminal VGH1, reaching a high-level potential. Under the potential control of the first node N1, the eleventh transistor T11 is turned off, and the twelfth transistor T12 is turned on, thereby connecting the second node N2 with the second level signal terminal VGL1, outputting a low-level signal. It can be seen that selection unit 100 can realize the function of shift output.

[0135] Referring again to Figures 5 and 6, when the second node N2 is at a high level and the enable signal terminal EN provides a high-level signal, the thirteenth transistor T13 is turned on, thereby transmitting the high-level signal of the enable signal terminal EN to the fourth node N4, which in turn turns on the eighteenth transistor T18, and the third node N3 receives the low-level potential of the fourth level signal terminal VGL2. At this time, the twenty-second transistor T22 and the twenty-third transistor T23 are turned on to connect the third input terminal and the output terminal of the control unit 200, thereby transmitting the signal of the control signal terminal GSTV to the input terminal of the shift register 310 corresponding to this stage control unit 200. When the second node N2 is at a high level and the enable signal terminal EN provides a low-level signal, the third transistor T3 is turned on, thereby transmitting the low-level signal of the enable signal terminal EN to the fourth node N4, which in turn turns on the seventeenth transistor T17, and the third node N3 receives the high-level potential of the third level signal terminal VGH2. At this time, the twentieth transistor T20 and the twenty-first transistor T21 are turned on to connect the fourth input terminal and the output terminal of the control unit 200, thereby connecting the input terminal of the shift register 310 corresponding to the current control unit 200 with the output terminal of the previous shift register 310.

[0136] As can be seen, when driving the display panel, for each control unit 200 from the second to the last, when the display sub-area 410 corresponding to this control unit 200 needs to maintain the same refresh rate as the previous display sub-area 410, a low-level signal is provided to the enable signal terminal EN of this control unit 200. At this time, the control unit 200 will connect the output terminal of the last shift register 310 in the previous scan group 300 to the input terminal of the first shift register 310 in the scan group 300 corresponding to this control unit 200, thereby performing cascaded signal transmission. When the refresh rate of the display sub-area 410 corresponding to this control unit 200 is different from that of the previous display sub-area 410, a high-level signal is provided to the enable signal terminal EN of this control unit 200, and a reasonable signal is provided to the control signal terminal GSTV, so that the control unit 200 provides the signal of the control signal terminal GSTV to the input terminal of the first shift register 310 in the corresponding scan group 300. For the first selection unit 100, when the first selection unit 100 outputs a high-level signal, a high-level signal can be provided to the enable signal terminal EN, and a suitable signal can be provided to the control signal terminal GSTV according to the refresh rate required by the corresponding display sub-area. For example, when the first display sub-area requires a low refresh rate, a low-level signal can be provided to the control signal terminal GSTV when the first selection unit 100 outputs a high-level signal, so that each shift register 310 in the first scan group 300 outputs a low-level signal in sequence; when the first display sub-area requires a high refresh rate, a trigger signal can be provided to the control signal terminal GSTV when the first selection unit 100 outputs a high-level signal, so that each level of shift register 310 in the first scan group 300 outputs a high-level signal in sequence based on the trigger signal.

[0137] Taking the gate driving circuit and display panel shown in Figure 1 as an example, the display panel includes three display sub-areas 410, and the gate driving circuit includes three selection units 100, three control units 200, and three scan groups 300. Each scan group 300 includes a 6-stage shift register 310. In one example, the entire display area of ​​the display panel is displayed at a high refresh rate (e.g., 120Hz). The operating timing of the gate driving circuit is shown in Figure 7. The three selection units 100 output high-level signals in sequence. When the first selection unit 100 outputs a high level, it provides a high-level signal to the enable signal terminal EN of the first control unit 200 and provides a trigger signal to the control signal terminal GSTV of the first control unit 200, thereby turning on the third signal terminal and the output terminal of the control unit 200. The trigger signal is output to the first-stage shift register 310, which in turn causes the 6-stage shift register 310 in the first scan group 300 to output high-level signals in sequence. When the second and third selection units 100 output a high level, a low level signal is provided to the enable signal terminal EN of the second and third control units 200, thereby connecting the input terminal of the first-stage shift register 310 in the second scan group 300 to the output terminal of the last-stage shift register 310 in the first scan group 300, and connecting the input terminal of the first-stage shift register 310 in the third scan group 300 to the output terminal of the last-stage shift register 310 in the second scan group 300. The pulse width of the high-level signal provided to the enable signal terminal EN of the first control unit 200 can be less than or equal to the pulse width of the high-level signal output by the shift register 310.

[0138] In another example, the first and third display sub-areas of the display panel use a low refresh rate, while the second display sub-area uses a high refresh rate. The timing diagram of the gate drive circuit is shown in Figure 8. The three selection units 100 sequentially output high-level signals. When the first selection unit 100 outputs a high level, it provides a high-level signal to the enable signal terminal EN of the first control unit 200 and a low-level signal to the control signal terminal GSTV of the first control unit 200, thereby causing each shift register 310 of the first group to output a low-level signal. When the second selection unit 100 outputs a high level, it provides a high-level signal to the enable signal terminal EN of the second control unit 200 and a low-level signal to the control signal terminal GSTV of the second control unit 200. The control signal terminal GSTV of control unit 200 provides a high-level trigger signal, thereby connecting the third signal terminal and the output terminal of control unit 200. The trigger signal is transmitted to the first-stage shift register 310 in the second scan group 300, and each shift register 310 in the second scan group 300 sequentially outputs a high-level signal. When the third selection unit 100 outputs a high-level signal, it provides a high-level signal to the enable signal terminal EN of the three control units 200 and a low-level signal to the control signal terminal GSTV of the third control unit 200, thereby connecting the third signal terminal and the output terminal of control unit 200, and each shift register 310 in the third scan group 300 outputs a low-level signal. The pulse width of the high-level signal provided to each enable signal terminal EN and the pulse width of the trigger signal provided to the control signal terminal GSTV are both less than or equal to the pulse width of the high-level signal output by the shift register 310.

[0139] Figure 9 is another specific circuit diagram of the selection unit 100 and control unit 200 provided in some embodiments of this disclosure. The circuit shown in Figure 9 is similar to the circuit structure shown in Figure 5, except that in Figure 9, the enable sub-circuit 221 responds to the first level signal of the second node N2 and the second level signal of the enable signal terminal EN, and turns on the first level signal terminal VGH1 and the fourth node N4. Specifically, the enable sub-circuit 221 includes a thirteenth transistor T13 and a fourteenth transistor T14. The gate of the thirteenth transistor T13 is electrically connected to the second node N2, and the second terminal of the thirteenth transistor T13 is electrically connected to the fourth node N4. The gate of the fourteenth transistor T14 is electrically connected to the enable signal terminal EN, the first terminal of the fourteenth transistor T14 is electrically connected to the first level signal terminal VGH1, and the second terminal of the fourteenth transistor T14 is electrically connected to the first terminal of the thirteenth transistor T13. The fourteenth transistor T14 can be a P-type transistor or an N-type transistor.

[0140] Figure 10 is a timing diagram of the selection unit 100 and control unit 200 shown in Figure 9. The fourteenth transistor T14 in Figure 9 is illustrated using a P-type transistor as an example. The other transistors are described in the above description of Figure 5. Combining Figures 9 and 10, the timing of the selection unit 100 and control unit 200 is similar to that in Figure 6. The only difference is that when the second node N2 is at a high level, the thirteenth transistor T13 is turned on. At this time, to provide a low-level signal to the enable signal terminal EN, the fourteenth transistor T14 can be turned on, thereby allowing the fourth node N4 to receive the high-level signal from the first level signal terminal VGH1, which in turn causes the third node N3 to reach a low level. In other words, for the circuit shown in Figure 9, when the second node N2 is at a high level, by providing a low level to the enable signal terminal EN, the output terminal of the control unit 200 can be connected to the third input terminal, and the shift register 310 connected to the control unit 200 receives the signal from the control signal terminal GSTV; by providing a high level to the enable signal terminal EN, the output terminal of the control unit 200 can be connected to the fourth input terminal, and the shift register 310 connected to the control unit 200 is cascaded with the previous shift register 310.

[0141] It should be noted that the fourteenth transistor T14 can also be an N-type transistor. In this case, the signal timing in Figure 9 is the same as in Figure 6.

[0142] In the circuit shown in Figure 9, when the second node N2 is at a high level, the third level signal terminal VGH2 provides a signal to the fourth node N4. In practical applications, the third level signal terminal VGH2 is electrically connected to the third level signal line. When wiring, the third level signal line can have a larger width to reduce resistance, thereby reducing the voltage drop on the third level signal line. This ensures that the fourth node N4 can reach the required potential, and thus ensures that the transistor controlled by the fourth node N4 can reach the required on / off state.

[0143] Figure 11 is another specific circuit diagram of the selection unit 100 and control unit 200 provided in some embodiments of this disclosure. The circuit structure shown in Figure 11 is similar to that in Figure 5, except that the selection unit 100 in Figure 11 does not include the inverter sub-circuit 113. In this case, the second clock signal terminal CB1 is directly connected to the driver chip through the clock signal line to receive the clock signal provided by the driver chip. The clock signal provided by the driver chip to the second clock signal terminal CB1 is out of phase with the clock signal provided to the first clock signal terminal CK1.

[0144] For the circuit shown in Figure 11, its signal timing is the same as that in Figure 10, and the on / off states of each transistor are the same as those of the corresponding transistors in Figure 9, which will not be repeated here.

[0145] Figure 12A is another schematic diagram of the selection unit provided in some embodiments of this disclosure, and Figure 12B is yet another specific circuit schematic diagram of the selection unit 100 and the control unit 200 provided in some embodiments of this disclosure. Figure 12B illustrates a specific implementation of the selection unit 100 and the control unit 200 in Figure 12A. The structure shown in Figure 12A is similar to that in Figure 2, and the specific circuit structure shown in Figure 12B is similar to that in Figure 11, the only difference is that the third control sub-circuit 121 and the fourth control sub-circuit 122 of the selection unit 100 are different from those in Figure 11. Specifically, the third control sub-circuit 121 in Figure 12A is configured to connect the first level signal terminal VGH1 to the first node N1 in response to the second level signal of the second node N2; the fourth control sub-circuit 122 is configured to connect the second level signal terminal VGL1 to the first node N1 in response to the first level signal of the second node N2. Specifically, as shown in Figure 12B, the third control sub-circuit 121 includes: an eighth transistor T8, the gate of which is electrically connected to the second node N2, the first terminal of which is electrically connected to the first level signal terminal VGH1, and the second terminal of which is electrically connected to the first node N1. The fourth control sub-circuit 122 includes: a ninth transistor T9, the gate of which is electrically connected to the second node N2, the first terminal of which is electrically connected to the first node N1, and the second terminal of which is electrically connected to the second level signal terminal VGL1.

[0146] Compared to Figure 11, the number of transistors in Figure 12B is reduced, and the circuit structure is simpler.

[0147] For the circuit shown in Figure 12B, its signal timing is the same as that in Figure 10, and the switching state of each transistor is the same as the on / off state of the corresponding transistor in Figure 9, which will not be repeated here.

[0148] This disclosure also provides a display device, as shown in FIG1. ​​The display device includes a display panel and the gate driving circuit in the above embodiments. The display area of ​​the display panel includes multiple display sub-areas, each display sub-area including multiple gate lines. Each scan group 300 of the gate driving circuit corresponds to one display sub-area, and multiple shift registers 310 in the scan group 300 are electrically connected to the multiple gate lines in the corresponding display sub-area.

[0149] This disclosure also provides a driving method for the above-described gate driving circuit, including:

[0150] S1. Provide a start signal to the first selection unit 100 among the N selection units 100, so that the N selection units 100 sequentially output a first level signal.

[0151] S2. Control the signal potentials of the control signal terminal GSTV and the enable signal terminal EN of each selection unit 100 so that each shift register 310 outputs the corresponding scan signal.

[0152] The gate driving circuit provides scanning signals to the display panel, which includes N display sub-regions 410. The refresh frequency of each display sub-region 410 is independently selected from a first frequency and a second frequency; that is, the refresh frequency of each display sub-region 410 can be either the first frequency or the second frequency. Different display sub-regions 410 can have the same or different refresh frequencies. The first frequency is greater than the second frequency. Each selection unit 100 corresponds to one display sub-region 410. The maximum value of the first frequency is related to the output frequency of the selection unit 100.

[0153] For example, there are three display sub-regions 410, and each scan group 300 includes six shift registers 310. The basic refresh rate of the display panel 400 is 120Hz, meaning that when the display area of ​​the display panel 400 uniformly adopts a high refresh rate, it can reach 120Hz. Assuming that the display panel is controlled by HRD, so that one display sub-region 410 adopts a high refresh rate and the other two display sub-regions 410 adopt a low refresh rate, then as mentioned above, the refresh time of the two low-frequency refresh display sub-regions 410 can be reserved for the high-frequency refresh display sub-regions 410, achieving a maximum refresh rate of 360Hz, thus realizing an ultra-high frequency refresh rate.

[0154] In one example, when the gate line of the display panel is loaded with an effective level potential, the transistor connected to the gate line is turned on. That is, when the refresh frequency of the display sub-region 410 is the first frequency, the scan signals output by each shift register 310 in the scan group 300 corresponding to the display sub-region 410 sequentially reach the effective level potential. In this case, the above S2 specifically includes one of the following three situations:

[0155] Case 1: When the refresh frequency of the kth display sub-area 410 is the same as the refresh frequency of the (k-1)th display sub-area 410, control the signal potential of the enable signal terminal EN so that the fourth input terminal and the output terminal of the kth control unit 200 are connected.

[0156] Case 2: When the refresh frequency of the (k-1)th display sub-area 410 is the first frequency and the refresh frequency of the (k-1)th display sub-area 410 is the second frequency, control the signal potential of the enable signal terminal EN so that the third input terminal and output terminal of the kth control unit 200 are connected, and provide an invalid level signal to the control signal terminal GSTV so that the scan signals output by each shift register 310 in the kth scan group 300 are all at the second level potential.

[0157] Case 3: When the refresh frequency of the (k-1)th display sub-area 410 is the second frequency and the refresh frequency of the (k-1)th display sub-area 410 is the first frequency, control the signal potential of the enable signal terminal EN so that the third input terminal and output terminal of the kth control unit 200 are connected, and provide a trigger signal at an effective level potential to the control signal terminal GSTV so that the scan signals output by each shift register 310 in the kth scan group 300 sequentially reach the effective level potential.

[0158] Where 1 < k ≤ N, and k is a positive integer. In one example, the effective level potential is the first level potential, and the effective level signal is the first level signal; the invalid level potential is the second level potential, and the invalid level signal is the second level signal.

[0159] The specific working process of the gate drive circuit is described in the above embodiments and will not be repeated here.

[0160] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A gate driving circuit, comprising: The N cascaded selection units are configured to sequentially output a first level signal in response to a start signal provided by a start signal terminal and a signal provided by a first clock signal terminal. N control units; the first input terminal of the i-th control unit is electrically connected to the output terminal of the i-th selection unit, the second input terminal of the i-th control unit is electrically connected to the enable signal terminal, and the third input terminal of the i-th control unit is electrically connected to the control signal terminal; There are N scan groups, each scan group comprising multiple cascaded shift registers. The input of the first shift register in the i-th scan group is electrically connected to the output of the i-th control unit, and the output of the last shift register in the j-th scan group is electrically connected to the fourth input of the (j+1)-th control unit. Wherein, N is a positive integer greater than 1, i is a positive integer less than or equal to N, and j is a positive integer less than N. The selection unit includes a first gating circuit and a second gating circuit, wherein the first gating circuit and the second gating circuit are connected to a first node, and the second gating circuit is electrically connected to the control unit at a second node. The first gating circuit is configured to control the connection and disconnection between the first level signal terminal and the first node, and the connection and disconnection between the second level signal terminal and the first node, in response at least to the input signal at the input terminal of the selection unit and the signal at the first clock signal terminal. The second gating circuit is configured to, at least in response to the signal of the first node, control the on / off state between the first level signal terminal and the second node, and the on / off state between the second level signal terminal and the second node; The control unit is configured to connect one of the third input terminal and the fourth input terminal to the output terminal of the control unit in response to the signal of the second node and the signal of the enable signal terminal.

2. The gate driving circuit according to claim 1, wherein, The first gating circuit includes: The first control sub-circuit is configured to control the first level signal terminal to be turned on with the first node in response to the second level signal at the input terminal of the selection unit and the second level signal at the second clock signal terminal. The second control sub-circuit is configured to control the second level signal terminal to be turned on with the first node in response to the first level signal at the input terminal of the selection unit and the first level signal at the first clock signal terminal. The signals at the first clock signal terminal and the second clock signal terminal switch between a first level and a second level, and the signals at the first clock signal terminal and the second clock signal terminal are out of phase for at least a portion of the time.

3. The gate driving circuit according to claim 2, wherein, The first control sub-circuit includes: a first transistor and a second transistor, wherein the gate of the first transistor is electrically connected to the second clock signal terminal, the first terminal of the first transistor is electrically connected to the first level signal terminal, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the gate of the second transistor is electrically connected to the input terminal of the selection unit, and the second terminal of the second transistor is electrically connected to the first node. The second control sub-circuit includes a third transistor and a fourth transistor. The gate of the third transistor is electrically connected to the input terminal of the selection unit. The first terminal of the third transistor is electrically connected to the first node. The second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor. The second terminal of the fourth transistor is electrically connected to the second level signal terminal. The gate of the fourth transistor is electrically connected to the first clock signal terminal.

4. The gate driving circuit according to claim 2, wherein, The first gating circuit further includes: The inverting sub-circuit is configured to invert the signal at the first clock signal terminal and then provide it to the second clock signal terminal.

5. The gate driving circuit according to claim 4, wherein, The inverting sub-circuit includes a fifth transistor and a sixth transistor. The gates of the fifth transistor and the sixth transistor are both electrically connected to the first clock signal terminal. The first terminal of the fifth transistor is electrically connected to the first level signal terminal. The second terminal of the fifth transistor and the first terminal of the sixth transistor are both electrically connected to the second clock signal terminal. The second terminal of the sixth transistor is electrically connected to the second level signal terminal. One of the fifth transistor and the sixth transistor is an N-type transistor, and the other is a P-type transistor.

6. The gate driving circuit according to claim 2, wherein, The second gating circuit includes: The third control sub-circuit is configured to connect the first level signal terminal to the first node in response to the second level signal of the first clock signal terminal and the second level signal of the second node. The fourth control sub-circuit is configured to connect the second level signal terminal to the first node in response to the first level signal of the second clock signal terminal and the first level signal of the second node; The fifth control sub-circuit is configured to, in response to a first level signal from the first node, connect the second level signal terminal to the second node; or, in response to a second level signal from the first node, connect the first level signal terminal to the second node.

7. The gate driving circuit according to claim 6, wherein, The third control sub-circuit includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is electrically connected to the first clock signal terminal, the first terminal of the seventh transistor is electrically connected to the first level signal terminal, the second terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor, the second terminal of the eighth transistor is electrically connected to the first node, and the gate of the eighth transistor is electrically connected to the second node. The fourth control sub-circuit includes a ninth transistor and a tenth transistor. The gate of the ninth transistor is electrically connected to the second node, the first terminal of the ninth transistor is electrically connected to the first node, the second terminal of the ninth transistor is electrically connected to the first terminal of the tenth transistor, the second terminal of the tenth transistor is electrically connected to the second level signal terminal, and the gate of the tenth transistor is electrically connected to the second clock signal terminal. The fifth control sub-circuit includes an eleventh transistor and a twelfth transistor. The gate of the eleventh transistor and the gate of the twelfth transistor are both electrically connected to the first node. The first terminal of the eleventh transistor is electrically connected to the first level signal terminal. The second terminal of the eleventh transistor and the first terminal of the twelfth transistor are both electrically connected to the second node. The second terminal of the twelfth transistor is electrically connected to the second level signal terminal. Among them, one of the eighth transistor and the ninth transistor is an N-type transistor and the other is a P-type transistor. The eleventh transistor is of the same type as the eighth transistor, and the twelfth transistor is of the same type as the ninth transistor.

8. The gate driving circuit according to claim 2, wherein, The second gating circuit includes: The third control sub-circuit is configured to connect the first level signal terminal to the first node in response to the second level signal of the second node. The fourth control sub-circuit is configured to connect the second level signal terminal to the first node in response to the first level signal of the second node; The fifth control sub-circuit is configured to, in response to a first level signal from the first node, connect the second level signal terminal to the second node; or, in response to a second level signal from the first node, connect the first level signal terminal to the second node.

9. The gate driving circuit according to claim 8, wherein, The third control sub-circuit includes: an eighth transistor, the gate of which is electrically connected to the second node, the first terminal of which is electrically connected to the first level signal terminal, and the second terminal of which is electrically connected to the first node; The fourth control sub-circuit includes: a ninth transistor, the gate of which is electrically connected to the second node, the first terminal of which is electrically connected to the first node, and the second terminal of which is electrically connected to the second level signal terminal; The fifth control sub-circuit includes an eleventh transistor and a twelfth transistor. The gates of the eleventh transistor and the twelfth transistor are both electrically connected to the first node. The first terminal of the eleventh transistor is electrically connected to the first level signal terminal. The second terminal of the eleventh transistor and the first terminal of the twelfth transistor are both electrically connected to the second node. The second terminal of the twelfth transistor is electrically connected to the second level signal terminal.

10. The gate drive circuit according to any one of claims 1 to 9, wherein, The control unit includes: an intermediate control circuit and an output control circuit, wherein the intermediate control circuit and the output control circuit are electrically connected to the third node and the fourth node; The intermediate control circuit is configured to control the potentials of the third node and the fourth node in response to the signal of the second node, the signal of the enable signal terminal and the signal of the reset signal terminal; The output control circuit is configured to, in response to the third level signal of the third node and the fourth level signal of the fourth node, connect one of the third input terminal and the fourth input terminal to the output terminal of the control unit; and in response to the fourth level signal of the third node and the third level signal of the fourth node, connect the other of the third input terminal and the fourth input terminal to the output terminal of the control unit.

11. The gate driving circuit according to claim 10, wherein, The intermediate control circuit includes an enable sub-circuit, a latch sub-circuit, and a reset sub-circuit, wherein the enable sub-circuit, the latch sub-circuit, and the reset sub-circuit are electrically connected to the fourth node; The enabling sub-circuit is configured to, in response to a first level signal from the second node, connect the enabling signal terminal to the fourth node; or, in response to both a first level signal from the second node and a second level signal from the enabling signal terminal, connect the first level signal terminal to the fourth node. The reset sub-circuit is configured to, in response to the reset signal at the reset signal terminal, connect the second level signal terminal to the fourth node to provide a second level signal to the fourth node; The latch sub-circuit is configured to provide the third node with a signal that is inversely phase to the signal of the fourth node, and to maintain the potentials of the fourth node and the third node when the fourth node is in a floating state.

12. The gate driving circuit according to claim 11, wherein, The enabling sub-circuit includes: a thirteenth transistor, the gate of which is electrically connected to the second node, the first terminal of which is electrically connected to the enable signal terminal, and the second terminal of which is electrically connected to the fourth node; or, The enabling sub-circuit includes: a thirteenth transistor and a fourteenth transistor. The gate of the thirteenth transistor is electrically connected to the second node, and the second terminal of the thirteenth transistor is electrically connected to the fourth node; The gate of the fourteenth transistor is electrically connected to the enable signal terminal, the first terminal of the fourteenth transistor is electrically connected to the first level signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the first terminal of the thirteenth transistor.

13. The gate driving circuit according to claim 11, wherein, The latch sub-circuit includes: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor; The gates of the fifteenth transistor and the sixteenth transistor are both electrically connected to the third node. The first terminal of the fifteenth transistor is electrically connected to the third level signal terminal. The second terminals of the fifteenth transistor and the first terminals of the sixteenth transistor are both electrically connected to the fourth node. The second terminal of the sixteenth transistor is electrically connected to the fourth level signal terminal. The gates of the seventeenth transistor and the eighteenth transistor are both electrically connected to the fourth node. The first terminal of the seventeenth transistor is electrically connected to the third level signal terminal. The second terminal of the seventeenth transistor and the first terminal of the eighteenth transistor are both electrically connected to the third node. The second terminal of the eighteenth transistor is electrically connected to the fourth level signal terminal. Of the fifteenth and sixteenth transistors, one is an N-type transistor and the other is a P-type transistor; the seventeenth transistor is of the same type as the fifteenth transistor, and the eighteenth transistor is of the same type as the sixteenth transistor.

14. The gate driving circuit according to claim 11, wherein, The reset sub-circuit includes: The nineteenth transistor has its gate electrically connected to the reset signal terminal, its first terminal electrically connected to the fourth node, and its second terminal electrically connected to the second level signal terminal.

15. The gate drive circuit according to claim 11, wherein, The output control circuit includes: a twentieth transistor, a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor; The gate of the twentieth transistor is electrically connected to the fourth node, the gate of the twentieth transistor is electrically connected to the third node, the first terminals of the twentieth and twentieth transistors are both electrically connected to the fourth input terminal of the control unit, and the second terminals of the twentieth and twentieth transistors are both electrically connected to the output terminal of the control unit. The gate of the 22nd transistor is electrically connected to the third node, the gate of the 23rd transistor is electrically connected to the fourth node, the first terminals of the 22nd transistor and the 23rd transistor are both electrically connected to the third input terminal of the control unit, and the second terminals of the 22nd transistor and the 23rd transistor are both electrically connected to the output terminal of the control unit.

16. A gate driving circuit, comprising: The N cascaded selection units are configured to sequentially output a first level signal in response to a start signal provided by a start signal terminal and a signal provided by a first clock signal terminal. N control units; the first input terminal of the i-th control unit is electrically connected to the output terminal of the i-th selection unit at the second node, the second input terminal of the i-th control unit is electrically connected to the enable signal terminal, and the third input terminal of the i-th control unit is electrically connected to the control signal terminal; There are N scan groups, each scan group comprising multiple cascaded shift registers. The input of the first shift register in the i-th scan group is electrically connected to the output of the i-th control unit, and the output of the last shift register in the j-th scan group is electrically connected to the fourth input of the (j+1)-th control unit. Wherein, N is a positive integer greater than 1, i is a positive integer less than or equal to N, and j is a positive integer less than N. The control unit includes an intermediate control circuit and an output control circuit, wherein the intermediate control circuit and the output control circuit are electrically connected to the third node and the fourth node; The intermediate control circuit is configured to control the potentials of the third node and the fourth node in response to the signal of the second node, the signal of the enable signal terminal and the signal of the reset signal terminal; The output control circuit is configured to, in response to the third level signal of the third node and the fourth level signal of the fourth node, connect one of the third input terminal and the fourth input terminal to the output terminal of the control unit; and in response to the fourth level signal of the third node and the third level signal of the fourth node, connect the other of the third input terminal and the fourth input terminal to the output terminal of the control unit.

17. The gate drive circuit according to claim 16, wherein, The intermediate control circuit includes an enable sub-circuit, a latch sub-circuit, and a reset sub-circuit, wherein the enable sub-circuit, the latch sub-circuit, and the reset sub-circuit are electrically connected to the fourth node; The enabling sub-circuit is configured to, in response to a first level signal from the second node, connect the enabling signal terminal to the fourth node; or, in response to both a first level signal from the second node and a second level signal from the enabling signal terminal, connect the first level signal terminal to the fourth node. The reset sub-circuit is configured to, in response to the reset signal at the reset signal terminal, connect the second level signal terminal to the fourth node to provide a second level signal to the fourth node; The latch sub-circuit is configured to provide the third node with a signal that is inversely phase to the signal of the fourth node, and to maintain the potentials of the fourth node and the third node when the fourth node is in a floating state.

18. The gate drive circuit according to claim 17, wherein, The enabling sub-circuit includes: a thirteenth transistor, the gate of which is electrically connected to the second node, the first terminal of which is electrically connected to the enable signal terminal, and the second terminal of which is electrically connected to the fourth node; or, The enabling sub-circuit includes: a thirteenth transistor and a fourteenth transistor. The gate of the thirteenth transistor is electrically connected to the second node, and the second terminal of the thirteenth transistor is electrically connected to the fourth node; The gate of the fourteenth transistor is electrically connected to the enable signal terminal, the first terminal of the fourteenth transistor is electrically connected to the first level signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the first terminal of the thirteenth transistor.

19. The gate drive circuit according to claim 17, wherein, The latch sub-circuit includes: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor; The gates of the fifteenth transistor and the sixteenth transistor are both electrically connected to the third node. The first terminal of the fifteenth transistor is electrically connected to the third level signal terminal. The second terminals of the fifteenth transistor and the first terminals of the sixteenth transistor are both electrically connected to the fourth node. The second terminal of the sixteenth transistor is electrically connected to the fourth level signal terminal. The gates of the seventeenth transistor and the eighteenth transistor are both electrically connected to the fourth node. The first terminal of the seventeenth transistor is electrically connected to the third level signal terminal. The second terminals of the seventeenth transistor and the first terminals of the eighteenth transistor are both electrically connected to the third node. The second terminal of the eighteenth transistor is electrically connected to the fourth level signal terminal.

20. The gate drive circuit according to claim 17, wherein, The reset sub-circuit includes: The nineteenth transistor has its gate electrically connected to the reset signal terminal, its first terminal electrically connected to the fourth node, and its second terminal electrically connected to the second level signal terminal.

21. The gate drive circuit according to claim 17, wherein, The output control circuit includes: a twentieth transistor, a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor; The gate of the twentieth transistor is electrically connected to the fourth node, the gate of the twentieth transistor is electrically connected to the third node, the first terminals of the twentieth and twentieth transistors are both electrically connected to the fourth input terminal of the control unit, and the second terminals of the twentieth and twentieth transistors are both electrically connected to the output terminal of the control unit. The gate of the 22nd transistor is electrically connected to the third node, the gate of the 23rd transistor is electrically connected to the fourth node, the first terminals of the 22nd transistor and the 23rd transistor are both electrically connected to the third input terminal of the control unit, and the second terminals of the 22nd transistor and the 23rd transistor are both electrically connected to the output terminal of the control unit.

22. A driving method for a gate driving circuit as described in any one of claims 1 to 21, comprising: A start signal is provided to the first selection unit among the N selection units, so that the N selection units output a first level signal in sequence; The signal potentials of the control signal terminal and the enable signal terminal of each of the selection units are controlled so that each of the shift registers outputs a corresponding scan signal.

23. The driving method according to claim 22, wherein, The gate driving circuit is used to provide a scanning signal to the display panel. The display panel includes N display sub-regions. The refresh frequency of each display sub-region is independently selected from one of a first frequency and a second frequency, wherein the first frequency is greater than the second frequency. Each selection unit corresponds to one display sub-region. The maximum value of the first frequency is related to the output frequency of the selection unit.

24. The driving method according to claim 23, wherein, When the refresh frequency of the display sub-region is the first frequency, the scan signals output by each shift register in the scan group corresponding to the display sub-region sequentially reach the first level potential; The step of controlling the signal potentials of the control signal terminals and the enable signal terminals of each of the selection units, so that each of the shift registers outputs a corresponding scan signal, specifically includes: When the refresh frequency of the kth display sub-region is the same as the refresh frequency of the (k-1)th display sub-region, the signal potential of the enable signal terminal is controlled so that the fourth input terminal and the output terminal of the kth control unit are turned on. When the refresh frequency of the (k-1)th display sub-region is the first frequency and the refresh frequency of the kth display sub-region is the second frequency, the signal potential of the enable signal terminal is controlled so that the third input terminal and the output terminal of the kth control unit are connected, and a second level signal is provided to the control signal terminal so that the scan signals output by each shift register in the kth scan group are all at the second level potential; When the refresh frequency of the (k-1)th display sub-region is the second frequency and the refresh frequency of the kth display sub-region is the first frequency, the signal potential of the enable signal terminal is controlled so that the third input terminal and the output terminal of the kth control unit are turned on, and a trigger signal at the first level potential is provided to the control signal terminal so that the scan signals output by each shift register in the kth scan group sequentially reach the first level potential; Where 1 < k ≤ N, and k is a positive integer.

25. A display device comprising a gate driving circuit according to any one of claims 1 to 21, and a display panel, the display panel comprising N display sub-regions, wherein a plurality of gate lines are disposed in the display sub-regions, each scan group corresponds to one display sub-region, and a shift register in the scan group is electrically connected to the gate line in the corresponding display sub-region.

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