Display panel and display device

Abstract

The present invention relates to the technical field of display, and provides a display panel and a display device. The display panel comprises a display area (AA), a dummy area (Dmy) located around the display area (AA), and a frame area located on the side of the dummy area (Dmy) distant from the display area (AA). The display panel further comprises: a base substrate (100), a plurality of pixel driving circuits (Pix), first-type signal lines (Lnx), an active layer, a first source-drain layer, and an insulating layer group (10). The plurality of pixel driving circuits (Pix) are located on one side of the base substrate (100); each pixel driving circuit (Pix) comprises a first-type transistor, and the first-type transistor is an oxide transistor; and the plurality of pixel driving circuits (Pix) comprise first pixel driving circuits (Pix1) and second pixel driving circuits (Pix2), the first pixel driving circuits (Pix1) are located in the display area (AA), and the second pixel driving circuits (Pix2) are located in the dummy area (Dmy). The first-type signal lines (Lnx) are located on one side of the base substrate; and each first-type signal line (Lnx) is connected to first electrodes of first-type transistors in the first pixel driving circuits (Pix1), and the first-type signal line (Lnx) is disconnected from first electrodes of first-type transistors in the second pixel driving circuits (Pix2). The active layer is located on one side of the base substrate (100); and at least a part of the structure of the active layer is used to form channel areas of oxide transistors in the pixel driving circuits (Pix). The first source-drain layer is located on the side of the active layer facing away from the base substrate (100); and at least a part of the structure of the first source-drain layer is connected to the oxide transistors by means of via holes. The insulating layer group (10) comprises a plurality of insulating layers; the insulating layer group (10) is located

Description

Display panel, display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, due to edge effects, oxide transistors located at the edges of display panels are prone to threshold shift or even channel region conductor formation, which can easily lead to horizontal or vertical stripes on the display panel.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a display panel is provided, the display panel including a display area, a virtual area surrounding the display area, and a border area located on the side of the virtual area away from the display area, the display panel further including:

[0005] Substrate;

[0006] Multiple pixel driving circuits are located on one side of the substrate. Each pixel driving circuit includes a first type of transistor, which is an oxide transistor. The multiple pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit. The first pixel driving circuit is located in the display area, and the second pixel driving circuit is located in the virtual area.

[0007] The first type of signal line is located on one side of the substrate. The first type of signal line is connected to the first electrode of the first type of transistor in the first pixel driving circuit, and the first type of signal line is disconnected from the first electrode of the first type of transistor in the second pixel driving circuit.

[0008] An active layer is located on one side of the substrate, and at least a portion of the structure of the active layer is used to form the channel region of the oxide transistor in the pixel driving circuit.

[0009] A first source / drain layer is located on the side of the active layer opposite to the substrate, and at least a portion of the structure of the first source / drain layer is connected to the oxide transistor through vias;

[0010] An insulating layer group includes multiple insulating layers, the insulating layer group being located between the first source / drain layer and the substrate, and a plurality of virtual holes are formed on the insulating layer group;

[0011] At least a portion of the virtual holes are located in one or more areas of the virtual area and the border area.

[0012] In one exemplary embodiment of this disclosure, a plurality of pixel driving circuits are arrayed along a first direction and a second direction, wherein the first direction and the second direction intersect.

[0013] The virtual area includes a first virtual area, which is located on one or both sides of the display area in the second direction;

[0014] The display panel includes multiple first-type signal lines, among which a first signal line is included. The orthographic projection of the first signal line on the substrate extends along the second direction, and the first electrode of the first-type transistor in the second pixel driving circuit of the first virtual area is disconnected from the first signal line.

[0015] In one exemplary embodiment of this disclosure, a plurality of pixel driving circuits are arrayed along a first direction and a second direction, wherein the first direction and the second direction intersect.

[0016] The virtual area includes a second virtual area, which is located on one or both sides of the display area in the first direction;

[0017] The display panel includes multiple first-type signal lines, among which a second signal line is included. The orthographic projection of the second signal line on the substrate extends along the first direction, and the first electrode of the first-type transistor in the second pixel driving circuit of the second virtual area and the second signal line are disconnected.

[0018] In one exemplary embodiment of this disclosure, the display panel includes a plurality of first-type signal lines, among which a data line is included, and the data line is used to provide data signals to the pixel driving circuit;

[0019] The pixel driving circuit includes one or more transistors of the first type, and the one or more transistors of the first type include a fourth transistor;

[0020] The data line is connected to the first terminal of the fourth transistor in the first pixel driving circuit, and the data line is disconnected from the first terminal of the fourth transistor in the second pixel driving circuit.

[0021] In one exemplary embodiment of this disclosure, the display panel includes a plurality of first-type signal lines, among which a first initial signal line is included;

[0022] The pixel driving circuit includes one or more first-type transistors and a driving transistor, wherein the one or more first-type transistors include a second transistor, and the second terminal of the second transistor is connected to the gate of the driving transistor.

[0023] The first initial signal line is connected to the first terminal of the second transistor in the first pixel driving circuit, and the first initial signal line and the first terminal of the second transistor in the second pixel driving circuit are disconnected.

[0024] In one exemplary embodiment of this disclosure, the display panel includes a plurality of first-type signal lines, among which a first power line is included, and the first power line is used to provide a power signal to the pixel driving circuit;

[0025] The pixel driving circuit includes one or more transistors of the first type, and the one or more transistors of the first type include a fifth transistor;

[0026] The first power line is connected to the first terminal of the fifth transistor in the first pixel driving circuit, and the first power line and the first terminal of the fifth transistor in the second pixel driving circuit are disconnected.

[0027] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the display panel includes a plurality of first-type signal lines, among which a second initial signal line is included;

[0028] The pixel driving circuit includes one or more first-type transistors, and the one or more first-type transistors include a seventh transistor, the second electrode of which is connected to the first electrode of the light-emitting unit;

[0029] The second initial signal line is connected to the first terminal of the seventh transistor in the first pixel driving circuit, and the second initial signal line and the first terminal of the seventh transistor in the second pixel driving circuit are disconnected.

[0030] In one exemplary embodiment of this disclosure, the first type of signal line and the first electrode of the first type of transistor in the first pixel driving circuit are connected by a via, and there is no via connection between the first type of signal line and the first electrode of the first type of transistor in the second pixel driving circuit.

[0031] In an exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit includes a plurality of first-type transistors, a first transistor, a driving transistor, a sixth transistor, and two capacitors, the two capacitors including a first capacitor and a second capacitor, and the plurality of first-type transistors including a second transistor, a fourth transistor, a fifth transistor, and a seventh transistor.

[0032] The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor.

[0033] The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the first electrode of the first capacitor.

[0034] The second terminal of the second transistor is connected to the gate of the driving transistor, and the first terminal of the second transistor in the first pixel driving circuit is connected to the first initial signal line;

[0035] The second terminal of the fourth transistor is connected to the gate of the driving transistor, and the first terminal of the fourth transistor in the first pixel driving circuit is connected to the data line.

[0036] The second terminal of the fifth transistor is connected to the first terminal of the driving transistor, and the first terminal of the fifth transistor in the first pixel driving circuit is connected to the first power supply line.

[0037] The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit.

[0038] The second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, and the first electrode of the seventh transistor in the first pixel driving circuit is connected to the second initial signal line.

[0039] The first transistor, the driving transistor, and the sixth transistor are oxide transistors.

[0040] In one exemplary embodiment of this disclosure, the display panel further includes:

[0041] A resist area is provided, and the resist area and the virtual hole are correspondingly provided. The resist area is located at the bottom of the substrate facing the virtual hole.

[0042] In one exemplary embodiment of this disclosure, the etching portion is suspended in the air.

[0043] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a capacitor, and the display panel further includes:

[0044] A first gate layer is located between the active layer and the substrate, and at least a portion of the structure of the first gate layer is used to form the first electrode of the capacitor;

[0045] A second gate layer is located between the first gate layer and the active layer, and at least a portion of the structure of the second gate layer is used to form the bottom gate of the oxide transistor;

[0046] A third gate layer is located between the active layer and the first source / drain layer, and at least a portion of the structure of the third gate layer is used to form the top gate of the oxide transistor;

[0047] The insulating layer group has a plurality of virtual holes formed thereon, including a first virtual hole and a second virtual hole;

[0048] The resist portion corresponding to the first virtual hole is located in one or more layers of the first gate layer and the second gate layer, and the resist portion corresponding to the second virtual hole is located in one or more layers of the active layer and the third gate layer.

[0049] In one exemplary embodiment of this disclosure, the number of the first virtual holes within the unit area is greater than the number of the second virtual holes within the unit area.

[0050] In one exemplary embodiment of this disclosure, the display panel further includes:

[0051] A passivation layer is located on the side of the first source / drain layer away from the substrate, and a portion of the passivation layer is filled within the virtual hole.

[0052] In one exemplary embodiment of this disclosure, at least a portion of the virtual hole is located in the display area.

[0053] In one exemplary embodiment of this disclosure, a plurality of pixel driving circuits are arrayed along a first direction and a second direction, wherein the first direction and the second direction intersect.

[0054] At least a portion of the structure of the first source / drain layer is connected to the oxide transistor via vias;

[0055] The display panel also includes:

[0056] The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes multiple column-oriented extension lines, and the orthogonal projection of the column-oriented extension lines on the substrate extends along the second direction.

[0057] The virtual area includes a second virtual area, which is located on one or both sides of the display area in the first direction. At least a portion of the column extension lines in the second virtual area are disconnected from the pixel driving circuit, and the at least portion of the column extension lines disconnected from the pixel driving circuit are connected to a regulated signal terminal.

[0058] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is connected to the first electrode of the light-emitting unit;

[0059] The display panel further includes a first power line and a second power line, wherein the first power line is used to provide a power signal to the pixel driving circuit, and the second power line is used to provide a power signal to the second electrode of the light-emitting unit;

[0060] The first power line or the second power line provides the regulated signal terminal.

[0061] In one exemplary embodiment of this disclosure, the display panel includes a plurality of pixel driving circuit groups, which are arrayed along a first direction and a second direction, wherein the first direction and the second direction intersect.

[0062] The pixel driving circuit group includes a plurality of pixel driving circuits that are adjacent in a first direction. In the same pixel driving circuit group, there is at least one set of two adjacent pixel driving circuits whose orthogonal projections on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along a second direction.

[0063] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor and two capacitors, the two capacitors being a first capacitor and a second capacitor, the first electrode of the first capacitor being connected to the first electrode of the second capacitor, the second electrode of the first capacitor being connected to the second electrode of the driving transistor, and the second electrode of the second capacitor being connected to the gate of the driving transistor.

[0064] The display panel also includes:

[0065] A first gate layer is located between the substrate and the active layer. The first gate layer includes a first conductive portion and a second conductive portion connected in the same layer. The first conductive portion is used to form a first electrode of the first capacitor, and the second conductive portion is used to form a first electrode of the second capacitor.

[0066] A second gate layer is located between the first gate and the active layer. The second gate layer includes a sixth conductive portion and a seventh conductive portion. The orthographic projection of the sixth conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap. The sixth conductive portion is used to form the second electrode of the first capacitor. The orthographic projection of the seventh conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate at least partially overlap. The seventh conductive portion is used to form the second electrode of the second capacitor.

[0067] The orthographic projections of the sixth conductive part and the seventh conductive part on the substrate are distributed along the second direction.

[0068] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor and two capacitors, one of which is a first capacitor and the other is a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor.

[0069] The display panel also includes:

[0070] A second gate layer is located between the substrate and the active layer. The second gate layer includes a sixth conductive portion, which is used to form the second electrode of the first capacitor.

[0071] The active layer further includes a third active portion, which is used to form the channel region of the driving transistor;

[0072] Wherein, the orthogonal projection of the sixth conductive part on the substrate covers the orthogonal projection of the third active part on the substrate.

[0073] In one exemplary embodiment of this disclosure, the pixel driving circuit includes one or more first-type transistors, and the one or more first-type transistors include a fifth transistor; the display panel includes multiple first-type signal lines and light-emitting units, and the multiple first-type signal lines include a first power line.

[0074] The pixel driving circuit further includes a driving transistor, two capacitors, and a sixth transistor. The two capacitors include a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor.

[0075] The second terminal of the fifth transistor is connected to the first terminal of the driving transistor, the gate is connected to the third enable signal line, and the first terminal of the fifth transistor in the first pixel driving circuit is connected to the first power supply line.

[0076] The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the fourth enable signal line.

[0077] The display panel also includes:

[0078] The second gate layer is located between the substrate and the active layer. The second gate layer includes a sixth conductive portion, a seventh conductive portion, a third enable signal line, and a fourth enable signal line. The sixth conductive portion is used to form the second electrode of the first capacitor, the seventh conductive portion is used to form the second electrode of the second capacitor, a portion of the structure of the third enable signal line is used to form the bottom gate of the fifth transistor, and a portion of the structure of the fourth enable signal line is used to form the bottom gate of the sixth transistor.

[0079] Wherein, the orthographic projections of the third enable signal line and the fourth enable signal line on the substrate extend along the first direction. In the same pixel driving circuit, the orthographic projections of the sixth conductive part and the seventh conductive part on the substrate are located between the orthographic projections of the third enable signal line and the fourth enable signal line on the substrate.

[0080] In one exemplary embodiment of this disclosure, the pixel driving circuit includes one or more first-type transistors, the one or more first-type transistors including a fifth transistor and a seventh transistor, the display panel includes multiple first-type signal lines and light-emitting units, the multiple first-type signal lines including a first power line and a second initial signal line, and the pixel driving circuit further includes a driving transistor and a sixth transistor;

[0081] The second terminal of the fifth transistor is connected to the first terminal of the driving transistor, the gate is connected to the first enable signal line, and the first terminal of the fifth transistor in the first pixel driving circuit is connected to the first power supply line.

[0082] The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the second enable signal line.

[0083] The second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, the gate is connected to the first reset signal line, and the first electrode of the seventh transistor in the first pixel driving circuit is connected to the second initial signal line.

[0084] A portion of the structure of the active layer is used to form the channel regions of the driving transistor, the fifth transistor, the sixth transistor, and the seventh transistor;

[0085] The display panel also includes:

[0086] A third gate layer is located between the active layer and the first source / drain layer. The third gate layer includes a first enable signal line, a second enable signal line, a first reset signal line, and an eleventh conductive portion. A portion of the structure of the first enable signal line is used to form the top gate of the fifth transistor, a portion of the structure of the second enable signal line is used to form the top gate of the sixth transistor, a portion of the structure of the first reset signal line is used to form the top gate of the seventh transistor, and the eleventh conductive portion is used to form the top gate of the driving transistor.

[0087] In the same pixel driving circuit, the orthographic projections of the first enable signal line, the second enable signal line, and the first reset signal line on the substrate extend along a first direction and are sequentially spaced along a second direction. The orthographic projection of the eleventh conductive part on the substrate is located between the orthographic projections of the first enable signal line and the second enable signal line on the substrate. The orthographic projection of the first reset signal line on the substrate is located on the side of the second enable signal line on the substrate away from the orthographic projection of the eleventh conductive part on the substrate.

[0088] In one exemplary embodiment of this disclosure, the pixel driving circuit includes one or more first-type transistors, the one or more first-type transistors including a second transistor and a fourth transistor, the display panel includes multiple first-type signal lines, the multiple first-type signal lines including a data line and a first initial signal line, and the pixel driving circuit further includes a first transistor and two capacitors;

[0089] The two capacitors include a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor.

[0090] The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the first electrode of the first capacitor.

[0091] The second terminal of the second transistor is connected to the gate of the driving transistor, and the first terminal of the second transistor in the first pixel driving circuit is connected to the first initial signal line;

[0092] The second terminal of the fourth transistor is connected to the gate of the driving transistor, and the first terminal of the fourth transistor in the first pixel driving circuit is connected to the data line.

[0093] The display panel also includes:

[0094] A third gate layer is located between the active layer and the first source / drain layer. The third gate layer includes an eighth conductive portion, a ninth conductive portion, and a tenth conductive portion. The eighth conductive portion is used to form the top gate of the first transistor, the ninth conductive portion is used to form the top gate of the second transistor, and the tenth conductive portion is used to form the top gate of the fourth transistor.

[0095] A portion of the structure of the active layer is used to form the channel regions of the first transistor, the second transistor, and the fourth transistor;

[0096] The first source / drain layer further includes a gate line, a second reset signal line, and a third reset signal line. The gate line is connected to the tenth conductive part through a via, the second reset signal line is connected to the ninth conductive part through a via, and the third reset signal line is connected to the eighth conductive part through a via. The orthogonal projections of the gate line, the second reset signal line, and the third reset signal line on the substrate extend along a first direction.

[0097] In the same pixel driving circuit, the orthographic projection of the gate line on the substrate is located between the orthographic projection of the first enable signal line on the substrate and the orthographic projection of the eleventh conductive part on the substrate; the orthographic projection of the second reset signal line on the substrate is located between the orthographic projection of the eleventh conductive part on the substrate and the orthographic projection of the second enable signal line on the substrate; and the orthographic projection of the third reset signal line on the substrate is located between the orthographic projection of the second reset signal line on the substrate and the orthographic projection of the second enable signal line on the substrate.

[0098] In one exemplary embodiment of this disclosure, the pixel driving circuit includes one or more first-type transistors, the one or more first-type transistors including a second transistor, a fourth transistor, a fifth transistor, and a seventh transistor; the display panel includes multiple first-type signal lines and light-emitting units, the multiple first-type signal lines including a data line, a first initial signal line, and a first power line; the pixel driving circuit further includes a driving transistor, a first transistor, a sixth transistor, and two capacitors.

[0099] The two capacitors include a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor.

[0100] The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the first electrode of the first capacitor.

[0101] The second terminal of the second transistor is connected to the gate of the driving transistor, and the first terminal of the second transistor in the first pixel driving circuit is connected to the first initial signal line;

[0102] The second terminal of the fourth transistor is connected to the gate of the driving transistor, and the first terminal of the fourth transistor in the first pixel driving circuit is connected to the data line.

[0103] The second terminal of the fifth transistor is connected to the first terminal of the driving transistor, and the first terminal of the fifth transistor in the first pixel driving circuit is connected to the first power line.

[0104] The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit.

[0105] The second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, and the first electrode of the seventh transistor in the first pixel driving circuit is connected to the second initial signal line.

[0106] The active layer includes a first main active portion and a second main active portion. The orthographic projection of the first main active portion on the substrate and the orthographic projection of the second main active portion on the substrate extend along a second direction and are spaced apart in a first direction.

[0107] The first main active portion includes a first active portion, a second active portion, and a fourth active portion that are sequentially spaced apart along a second direction. The first active portion is used to form the channel region of the first transistor, the second active portion is used to form the channel region of the second transistor, and the fourth active portion is used to form the channel region of the fourth transistor.

[0108] The second main active portion includes a sixth active portion, a third active portion, and a fifth active portion that are sequentially spaced apart along a second direction. The sixth active portion is used to form the channel region of the sixth transistor, the third active portion is used to form the channel region of the driving transistor, and the fifth active portion is used to form the channel region of the fifth transistor.

[0109] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0110] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0111] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0112] Figure 1 is a schematic diagram of the structure of a display panel in an exemplary embodiment of the present disclosure;

[0113] Figure 2 is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure;

[0114] Figure 3 is a timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 2;

[0115] Figure 4 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0116] Figure 5 is a structural layout of the first gate layer in the display panel shown in Figure 4;

[0117] Figure 6 is a structural layout of the second gate layer in the display panel shown in Figure 4;

[0118] Figure 7 is a structural layout of the active layer in the display panel shown in Figure 4;

[0119] Figure 8 is a structural layout of the third gate layer in the display panel shown in Figure 4;

[0120] Figure 9 is a structural layout of the first source / drain layer in the display panel shown in Figure 4;

[0121] Figure 10 is a structural layout of the second source / drain layer in the display panel shown in Figure 4;

[0122] Figure 11 is a structural layout of the electrode layer in the display panel shown in Figure 4;

[0123] Figure 12 is a structural layout of the first gate layer and the second gate layer in the display panel shown in Figure 4;

[0124] Figure 13 is a structural layout of the first gate layer, the second gate layer, and the active layer in the display panel shown in Figure 4.

[0125] Figure 14 is a structural layout of the first gate layer, the second gate layer, the active layer, and the third gate layer in the display panel shown in Figure 4.

[0126] Figure 15 is a structural layout of the first gate layer, second gate layer, active layer, third gate layer, and first source / drain layer in the display panel shown in Figure 4.

[0127] Figure 16 is a structural layout of the first gate layer, second gate layer, active layer, third gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 4.

[0128] Figure 17 is a partial cross-sectional view of the display panel shown in Figure 4, cut along the dashed line CC.

[0129] Figure 18 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0130] Figure 19 is a partial structural layout of the area where the virtual hole is located in an exemplary embodiment of the display panel of this disclosure;

[0131] Figure 20 is a structural layout of the resist etching section in Figure 19;

[0132] Figure 21 is a cross-sectional view of the display panel shown in Figure 19 along the dashed line DD;

[0133] Figure 22 is a partial structural layout of the area where the virtual hole is located in another exemplary embodiment of the display panel of this disclosure;

[0134] Figure 23 is a structural layout of the resist etching section in Figure 22;

[0135] Figure 24 is a cross-sectional view of the display panel shown in Figure 22 along the dashed line EE;

[0136] Figure 25 is a partial structural layout of a display panel in an exemplary embodiment of the present disclosure;

[0137] Figure 26 is a partial structural layout of another exemplary embodiment of the display panel of this disclosure. Detailed Implementation

[0138] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0139] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0140] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.

[0141] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0142] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.

[0143] Figure 1 shows a schematic diagram of a structure in an exemplary embodiment of the display panel of this disclosure. The display panel includes a display area AA and a virtual area Dmy located around the display area AA. The display panel also includes a substrate, a plurality of pixel driving circuits Pix, and a first type signal line Lnx. The plurality of pixel driving circuits Pix are located on one side of the substrate. Each pixel driving circuit Pix includes a first type of transistor, which is an oxide transistor. The plurality of pixel driving circuits include a first pixel driving circuit Pix1 and a second pixel driving circuit Pix2. The first pixel driving circuit Pix1 is located in the display area AA, and the second pixel driving circuit Pix2 is located in the virtual area Dmy. The first type signal line Lnx is located on one side of the substrate. The first type signal line Lnx is connected to the first electrode of the first type of transistor in the first pixel driving circuit Pix1, and the first type signal line Lnx and the first electrode of the first type of transistor in the second pixel driving circuit Pix2 are disconnected.

[0144] In this exemplary embodiment, the oxide transistors in the virtual region Dmy are located at the edge of multiple oxide transistors in the display panel. Due to the edge effect, the characteristics of the oxide transistors in the virtual region Dmy are unstable, the threshold of the oxide transistors in the virtual region Dmy is prone to shift, and even the channel region of the oxide transistors may become conductive. This exemplary embodiment disconnects the first type signal line Lnx from the first type transistors in the virtual region Dmy, thereby preventing the first type signal line Lnx from being short-circuited with other signal lines through the first type transistors.

[0145] In this exemplary embodiment, as shown in FIG1, a plurality of pixel driving circuits Pix are arrayed along a first direction X and a second direction Y, the first direction X and the second direction Y intersect, for example, the first direction X can be a row direction and the second direction Y can be a column direction. The virtual area Dmy can include a first virtual area Dmy1, the first virtual area Dmy1 being located on one or both sides of the display area AA in the second direction Y; the display panel can include a plurality of first type signal lines Lnx, among which the plurality of first type signal lines Lnx includes a first signal line Ln1, the orthographic projection of the first signal line Ln1 on the substrate extends along the second direction Y, and the first signal line Ln1 and the first pole of the first type transistor in the second pixel driving circuit located in the first virtual area Dmy1 are disconnected. This arrangement can prevent the first signal line Ln1 from being short-circuited to other signal lines through the first type transistor in the first virtual area Dmy1.

[0146] In this exemplary embodiment, as shown in FIG1, the virtual area Dmy includes a second virtual area Dmy2, which is located on one or both sides of the display area AA in the first direction X. Among the plurality of first-type signal lines is a second signal line Ln2, whose orthogonal projection on the substrate extends along the first direction X. Furthermore, the second signal line Ln2 and the first terminal of the first-type transistor in the second pixel driving circuit Pix2 located in the second virtual area Dmy2 are disconnected. This arrangement prevents the second signal line Ln2 from being short-circuited to other signals through the first-type transistor in the second virtual area Dmy2.

[0147] Figure 2 shows a schematic diagram of a pixel driving circuit in an exemplary embodiment of the display panel of this disclosure. This pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit includes: a plurality of first-type transistors, two capacitors, a first transistor T1, a sixth transistor T6, and a driving transistor T3. The plurality of first-type transistors includes: a second transistor T2, a fourth transistor T4, a fifth transistor T5, and a seventh transistor T7. The two capacitors include a first capacitor C1 and a second capacitor C2. The gate of the driving transistor T3 is connected to a first node N1, its first electrode is connected to a second node N2, and its second electrode is connected to a third node N3. The first electrode of the second capacitor C2 is connected to a fourth node N4, and its second electrode is connected to the first node N1. The first electrode of the first capacitor C1 is connected to the fourth node N4, and its second electrode is connected to the third node N3. The first electrode of the first transistor T1 is connected to a first initial signal line Vinit1, its second electrode is connected to the fourth node N4, and its gate is connected to a third reset signal terminal Re3. The first electrode of the second transistor T2 is connected to the first initial signal line Vinit1, its second electrode is connected to the first node N1, and its gate is connected to a second reset signal terminal Re2. Transistor T4 has its first electrode connected to the data line Da, its second electrode connected to the fifth node N5, and its gate connected to the gate drive signal terminal Gate; transistor T5 has its first electrode connected to the first power supply line VDD, its second electrode connected to the second node N2, and its gate connected to the first enable signal terminal EM1; transistor T6 has its first electrode connected to the third node N3, its second electrode connected to the first electrode of the light-emitting unit L, and its gate connected to the second enable signal terminal EM2; transistor T7 has its first electrode connected to the second initial signal line Vinit2, its second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the first reset signal terminal Re1; the second electrode of the light-emitting unit L is connected to the second power supply line VSS. The first electrode of the light-emitting unit can be an anode, and the second electrode can be a cathode.

[0148] As shown in Figure 2, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be N-type metal-oxide transistors.

[0149] Figure 3 shows the timing diagram of each node in one driving method of the pixel driving circuit shown in Figure 2. The driving method of this pixel driving circuit includes: reset stage t1, threshold compensation stage t2, data writing stage t3, and light emission stage t4.

[0150] During the reset phase t1: the first reset signal terminal Re1, the second reset signal terminal Re2, the third reset signal terminal Re3, and the second enable signal terminal EM2 output high-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are turned on. The first initial signal line Vinit1 outputs the first initial signal to the first node N1 and the fourth node N4. The second initial signal line Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit L and the third node N3.

[0151] During the threshold compensation stage t2: the second reset signal terminal Re2, the third reset signal terminal Re3, and the first enable signal terminal EM1 output high-level signals, the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, and the first power supply line VDD inputs the compensation voltage V1-Vth to the third node N3, where V1 is the voltage of the first initial signal and Vth is the threshold voltage of the driving transistor.

[0152] During the data writing phase t3: the third reset signal terminal Re3 and the gate drive signal terminal Gate output high-level signals, the first transistor T1 and the fourth transistor T4 are turned on, and the data line Da inputs data signals to the first node N1. The voltage of the first node N1 is Vdata, and Vdata is the voltage of the data signal.

[0153] During the light-emitting stage t4: the first enable signal terminal EM1 and the second enable signal terminal EM2 output high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistor T3 increases the driving current to the light-emitting unit L. The output current of the driving transistor T3 is I = (μWCox / 2L)(Vgs-Vth). 2 =(μWCox / 2L)(Vdata-(V1-Vth)-Vth) 2 =(μWCox / 2L)(Vdata-V1) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current, where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; and Vgs is the gate-source voltage difference of the driving transistor.

[0154] In this exemplary embodiment, the plurality of first-type signal lines may include: a data line Da, a first power supply line VDD, a first initial signal line Vinit1, and a second initial signal line Vinit2. This exemplary embodiment may disconnect one or more of the data line Da, the first power supply line VDD, the first initial signal line Vinit1, and the second initial signal line Vinit2 from the corresponding oxide transistors in the virtual region Dmy. For example, this exemplary embodiment can disconnect the data line Da and the first terminal of the fourth transistor in the virtual region Dmy, which can prevent the data line Da and the first initial signal line Vinit1 from being shorted; this exemplary embodiment can also disconnect the first initial signal line Vinit1 and the first terminal of the second transistor T2 in the virtual region Dmy, which can prevent the first initial signal line Vinit1 from being shorted and the data line Da; this exemplary embodiment can also disconnect the first power line VDD and the first terminal of the fifth transistor T5 in the virtual region Dmy, which can prevent the first power line VDD and the second initial signal line Vinit2 from being shorted; this exemplary embodiment can also disconnect the second initial signal line Vinit2 and the first terminal of the seventh transistor T7 in the virtual region Dmy, which can prevent the first power line VDD and the second initial signal line Vinit2 from being shorted.

[0155] It should be understood that in other exemplary embodiments, the pixel driving circuit may also have other structures. For example, in other exemplary embodiments, the pixel driving circuit may include both oxide transistors and polysilicon transistors. As long as the pixel driving circuit includes oxide transistors, this exemplary embodiment can avoid short-circuiting the first type of signal lines through the oxide transistors in the virtual area and other signal lines by disconnecting the first type of signal lines from the oxide transistors in the virtual area.

[0156] In this exemplary embodiment, the display panel may include a substrate, a first gate layer, a second gate layer, an active layer, a third gate layer, a first source / drain layer, and a second source / drain layer, which are sequentially stacked. An insulating layer is disposed between the aforementioned layers. As shown in Figures 4-16, Figure 4 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 5 is a structural layout diagram of the first gate layer in the display panel shown in Figure 4; Figure 6 is a structural layout diagram of the second gate layer in the display panel shown in Figure 4; Figure 7 is a structural layout diagram of the active layer in the display panel shown in Figure 4; Figure 8 is a structural layout diagram of the third gate layer in the display panel shown in Figure 4; Figure 9 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 4; Figure 10 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 4; Figure 11 is a structural layout diagram of the electrode layer in the display panel shown in Figure 4; Figure 12 is a structural layout diagram of… Figure 4 shows the structural layout of the first gate layer and the second gate layer in the display panel shown in Figure 4. Figure 13 shows the structural layout of the first gate layer, the second gate layer, and the active layer in the display panel shown in Figure 4. Figure 14 shows the structural layout of the first gate layer, the second gate layer, the active layer, and the third gate layer in the display panel shown in Figure 4. Figure 15 shows the structural layout of the first gate layer, the second gate layer, the active layer, the third gate layer, the first source / drain layer, and the second source / drain layer in the display panel shown in Figure 4. Figure 16 shows the structural layout of the first gate layer, the second gate layer, the active layer, the third gate layer, the first source / drain layer, and the second source / drain layer in the display panel shown in Figure 4. Figure 4 shows a partial layout structure of the display area AA.

[0157] As shown in Figure 16, the display panel may include multiple pixel driving circuit groups Pz, which may be arrayed along a first direction X and a second direction Y. Each pixel driving circuit group Pz includes three adjacent pixel driving circuits in the first direction X: a first pixel driving circuit Pix1, a second pixel driving circuit Pix2, and a third pixel driving circuit Pix3. The structure of the pixel driving circuits may be as shown in Figure 2. It should be understood that in other exemplary embodiments, the pixel driving circuit group Pz may also include other numbers of adjacent pixel driving circuits in the first direction X.

[0158] As shown in Figure 16, at least a portion of the orthographic projections of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 onto the substrate are mirror-symmetrically arranged with respect to the axis of symmetry BB extending along the second direction Y.

[0159] This exemplary embodiment sets at least a portion of the orthographic projections of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 onto the substrate in a mirror-symmetrical manner, thereby improving the integration of the pixel driving circuits.

[0160] As shown in Figures 4, 5, and 12, the first gate layer may include a first conductive portion 11, a second conductive portion 12, and a first via connection portion 13. The first conductive portion 11 is connected between the second conductive portion 12 and the first via connection portion 13. The first conductive portion 11 is used to form the first electrode of the first capacitor C1, and the second conductive portion 12 is used to form the first electrode of the second capacitor C2.

[0161] As shown in Figures 4, 6, and 12, the second gate layer includes: a third enable signal line 2EM1, a fourth enable signal line 2EM2, a fourth reset signal line 2Re1, a third conductive portion 23, a fourth conductive portion 24, a fifth conductive portion 25, a sixth conductive portion 26, and a seventh conductive portion 27. The orthogonal projections of the third enable signal line 2EM1, the fourth enable signal line 2EM2, and the fourth reset signal line 2Re1 onto the substrate extend along a first direction X. The third enable signal line 2EM1 provides the first enable signal terminal in Figure 2, the fourth enable signal line 2EM2 provides the second enable signal terminal in Figure 2, and the fourth reset signal line 2Re1 provides the first reset signal terminal in Figure 2. The sixth conductive portion 26 forms the second electrode of the first capacitor C1; the seventh conductive portion 27 forms the second electrode of the second capacitor C2.

[0162] As shown in Figures 4, 7, and 13, the active layer may include: a first main active unit 701, a second main active unit 702, a seventh active unit 77, and a sixteenth active unit 716. The first main active unit 701 includes: a first active unit 71, a second active unit 72, a fourth active unit 74, an eighth active unit 78, a ninth active unit 79, a tenth active unit 710, an eleventh active unit 711, and a twelfth active unit 712. The second main active unit 702 includes: a third active unit 73, a fifth active unit 75, a sixth active unit 76, a thirteenth active unit 713, a fourteenth active unit 714, and a fifteenth active unit 715. The first active portion 71 is used to form the channel region of the first transistor T1; the second active portion 72 is used to form the channel region of the second transistor T2; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 is connected to the end of the first active portion 71 away from the second active portion 72; and the ninth active portion 79 is connected to the first active portion 71 and the second active portion 72. Between the active portions 72, the tenth active portion 710 is connected between the second active portion 72 and the fourth active portion 74; the eleventh active portion 711 is connected between the tenth active portion 710 and the fourth active portion 74; the twelfth active portion 712 is connected to the end of the fourth active portion 74 away from the second active portion 72; the thirteenth active portion 713 is connected to the end of the fifth active portion 75 away from the third active portion 73; the fourteenth active portion 714 is connected between the third active portion 73 and the sixth active portion 76; the fifteenth active portion 715 is connected between the sixth active portion 76 and the seventh active portion 77; and the sixteenth active portion 716 is connected to the end of the seventh active portion 77 away from the sixth active portion 76. The active layer can be formed of indium gallium zinc oxide (IGaZn), and correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be N-type metal-oxide thin-film transistors.

[0163] As shown in Figures 4, 6, 7, and 13, the orthographic projection of the sixth conductive portion 26 on the substrate covers the orthographic projection of the third active portion 73 on the substrate. The sixth conductive portion 26 can shield the third active portion 73 from light, thereby reducing the impact of illumination on the characteristics of the driving transistor T3. The orthographic projection of the third conductive portion 23 on the substrate covers the orthographic projection of the first active portion 71 on the substrate. The third conductive portion 23 is used to form the bottom gate of the first transistor T1. The orthographic projection of the fourth conductive portion 24 on the substrate covers the orthographic projection of the second active portion 72 on the substrate. The fourth conductive portion 24 is used to form the bottom gate of the second transistor T2. The orthographic projection of the fifth conductive portion 25 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate. The fifth conductive portion 25 is used to form the bottom gate of the fourth transistor T4. The orthogonal projection of the third enable signal line 2EM1 on the substrate can cover the orthogonal projection of the fifth active part 75 on the substrate. A portion of the structure of the third enable signal line 2EM1 can be used to form the bottom gate of the fifth transistor T5. The orthogonal projection of the fourth enable signal line 2EM2 on the substrate can cover the orthogonal projection of the sixth active part 76 on the substrate. A portion of the structure of the fourth enable signal line 2EM2 can be used to form the bottom gate of the sixth transistor T6. The orthogonal projection of the fourth reset signal line 2Re1 on the substrate can cover the orthogonal projection of the seventh active part 77 on the substrate. A portion of the structure of the fourth reset signal line 2Re1 can be used to form the bottom gate of the seventh transistor T7.

[0164] As shown in Figures 4, 6, 7, and 13, the orthographic projections of the sixth conductive portion 26 and the seventh conductive portion 27 on the substrate are distributed along the second direction. In the same pixel driving circuit, the orthographic projections of the sixth conductive portion 26 and the seventh conductive portion 27 on the substrate are located between the orthographic projections of the third enable signal line 2EM1 and the fourth enable signal line 2EM2 on the substrate.

[0165] As shown in Figures 4, 8, and 14, the third gate layer may include: a first enable signal line 3EM1, a second enable signal line 3EM2, a first reset signal line 3Re1, an eighth conductive portion 38, a ninth conductive portion 39, a tenth conductive portion 310, and an eleventh conductive portion 311. The orthographic projections of the first enable signal line 3EM1, the second enable signal line 3EM2, and the first reset signal line 3Re1 onto the substrate extend along a first direction X. The first enable signal line 3EM1 provides the first enable signal terminal in Figure 2, the second enable signal line 3EM2 provides the second enable signal terminal in Figure 2, and the first reset signal line 3Re1 provides the first reset signal terminal in Figure 2. The first enable signal line 3EM1 and the third enable signal line 3EM2 can be connected via vias in the display area or the bezel area; the second enable signal line 3EM2 and the fourth enable signal line 2EM2 can be connected via vias in the display area or the bezel area; and the first reset signal line 3Re1 and the fourth reset signal line 2Re1 can be connected via vias in the display area or the bezel area.

[0166] As shown in Figures 4, 8, and 14, the orthogonal projection of the first enable signal line 3EM1 on the substrate can cover the orthogonal projection of the fifth active part 75 on the substrate. A portion of the structure of the first enable signal line 3EM1 can be used to form the top gate of the fifth transistor T5. The orthogonal projection of the second enable signal line 3EM2 on the substrate can cover the orthogonal projection of the sixth active part 76 on the substrate. A portion of the structure of the second enable signal line 3EM2 can be used to form the top gate of the sixth transistor T6. The orthogonal projection of the first reset signal line 3Re1 on the substrate can cover the orthogonal projection of the seventh active part 77 on the substrate. A portion of the structure of the first reset signal line 3Re1 can be used to form the top gate of the seventh transistor T7. The orthographic projection of the eighth conductive portion 38 onto the substrate covers the orthographic projection of the first active portion 71 onto the substrate. The eighth conductive portion 38 is used to form the top gate of the first transistor T1. The orthographic projection of the ninth conductive portion 39 onto the substrate covers the orthographic projection of the second active portion 72 onto the substrate. The ninth conductive portion 39 is used to form the top gate of the second transistor. The orthographic projection of the tenth conductive portion 310 onto the substrate covers the orthographic projection of the fourth active portion 74 onto the substrate. The tenth conductive portion 310 is used to form the top gate of the fourth transistor T4. The orthographic projection of the eleventh conductive portion 311 onto the substrate covers the orthographic projection of the third active portion 73 onto the substrate. The eleventh conductive portion 311 is used to form the top gate of the driving transistor T3. This display panel can use the third gate layer as a mask to perform conductor processing on the active layer. That is, the area of ​​the active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the third gate layer forms a conductor structure.

[0167] As shown in Figures 4, 8, and 14, in the same pixel driving circuit, the orthographic projections of the first enable signal line 3EM1, the second enable signal line 3EM2, and the first reset signal line 3Re1 on the substrate extend along the first direction X and are sequentially spaced along the second direction Y. The orthographic projection of the eleventh conductive part 311 on the substrate is located between the orthographic projections of the first enable signal line 3EM1 and the second enable signal line 3EM2 on the substrate. The orthographic projection of the first reset signal line 3Re1 on the substrate is located on the side of the second enable signal line 3EM2 on the substrate that is away from the orthographic projection of the eleventh conductive part 311 on the substrate.

[0168] As shown in Figures 4, 9, and 15, the first source / drain layer may include: a first power supply line VDD, a gate line Gate, a second reset signal line Re2, a first initial signal line Vinit1, a third reset signal line Re3, a second initial signal line Vinit2, a second power supply line VSS, a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, and a sixth bridging portion 46. The first power supply line VDD, the gate line Gate, the second reset signal line Re2, the first initial signal line Vinit1, the third reset signal line Re3, the second initial signal line Vinit2, and the second power supply line VSS have their orthogonal projections on the substrate extending along the first direction X. The gate line Gate provides the gate drive signal terminal in Figure 2, the second reset signal line Re2 provides the second reset signal terminal in Figure 2, and the third reset signal line Re3 provides the third reset signal terminal in Figure 2. The first power supply line VDD is connected to the thirteenth active portion 713 through a via to connect to the first terminal of the fifth transistor T5. The gate line (Gate) is connected to the fifth conductive part 25 and the tenth conductive part 310 via vias to connect the gate drive signal terminal and the bottom gate and top gate of the fourth transistor T4. The second reset signal line (Re2) is connected to the fourth conductive part 24 and the ninth conductive part 39 via vias to connect the second reset signal terminal and the bottom gate and top gate of the second transistor T2. The first initial signal line (Vinit1) is connected to the ninth active part 79 via vias to connect the first initial signal line and the first terminal of the second transistor T2 and the first terminal of the first transistor T1. The third reset signal line (Re3) is connected to the third conductive part 23 and the eighth conductive part 38 via vias to connect the third reset signal terminal and the bottom gate and top gate of the first transistor T1. The second initial signal line (Vinit2) is connected to the sixteenth active part 716 via vias to connect the second initial signal line and the first terminal of the seventh transistor T7. The first bridging part 41 can be connected to the twelfth active part 712 via vias to connect the first terminal of the fourth transistor T4. The second bridging portion 42 can be connected to the seventh conductive portion 27 and the eleventh active portion 711 via vias, respectively, to connect the second electrode of the second capacitor C2 to the second electrode of the fourth transistor T4 and the second electrode of the second transistor T2. The third bridging portion 43 can be connected to the eleventh conductive portion 311 and the tenth active portion 710 via vias, respectively, to connect the gate of the driving transistor T3 to the second electrode of the fourth transistor T4 and the second electrode of the second transistor T2. The fourth bridging portion 44 is connected to the fourteenth active portion 714 and the sixth conductive portion 26 via vias, respectively, to connect the second electrode of the driving transistor T3 to the second electrode of the first capacitor C1. The fifth bridging portion 45 is connected to the first via connection portion 13 and the eighth active portion 78 via vias, respectively, to connect the second electrode of the first transistor T1 to the first electrode of the first capacitor C1 and the first electrode of the second capacitor C2.The sixth bridging section 46 is connected to the fifteenth active section 715 through a via to connect the second terminal of the sixth transistor T6 and the second terminal of the seventh transistor T7.

[0169] As shown in Figures 4, 9, and 15, in the same pixel driving circuit, the orthographic projection of the gate line Gate on the substrate is located between the orthographic projection of the first enable signal line 3EM1 on the substrate and the orthographic projection of the eleventh conductive part 311 on the substrate. The orthographic projection of the second reset signal line Re2 on the substrate is located between the orthographic projection of the eleventh conductive part 311 on the substrate and the orthographic projection of the second enable signal line 3EM2 on the substrate. The orthographic projection of the third reset signal line Re3 on the substrate is located between the orthographic projection of the second reset signal line Re2 on the substrate and the orthographic projection of the second enable signal line 3EM2 on the substrate.

[0170] As shown in Figures 4, 10, and 16, the second source / drain layer includes: a data line Da, a second power connection line 5VSS, a first power connection line 5VDD, a first initial connection line 5Vinit1, a second initial connection line 5Vinit2, and a seventh bridging portion 57. The orthographic projections of the data line Da, the second power connection line 5VSS, the first power connection line 5VDD, the first initial connection line 5Vinit1, and the second initial connection line 5Vinit2 onto the substrate extend along the second direction Y. The second power connection line 5VSS is connected via a via to a second power line 4VSS intersecting its orthographic projection onto the substrate. The second power connection line 5VSS and the second power line 4VSS form a mesh structure at least in the display area. This mesh structure can be connected to a common cathode in the display panel to reduce the voltage difference of the second power lines at different locations on the display panel. The common cathode in the display panel is used to form the cathode of the light-emitting unit, and the common cathode can be located on the side of the light-emitting unit L facing away from the substrate. The seventh bridging portion 57 can be connected to the sixth bridging portion 46 via a via. The first initial connection line 5Vinit1 can be connected to the intersecting first initial signal line Vinit1 via a via, the second initial connection line 5Vinit2 can be connected to the intersecting second initial signal line Vinit2 via a via, and the first power connection line 5VDD can be connected to the intersecting first power line VDD via a via. The orthographic projections of the first initial connection line 5Vinit1, the second initial connection line 5Vinit2, and the first power connection line 5VDD on the substrate can be alternately distributed along the first direction.

[0171] As shown in Figures 3 and 11, the electrode layer includes multiple electrode sections, including a first electrode section R, a second electrode section G, and a third electrode section B. The first electrode section R forms the first electrode of the red light-emitting unit, the second electrode section G forms the first electrode of the green light-emitting unit, and the third electrode section B forms the first electrode of the blue light-emitting unit. Each electrode section is connected to its corresponding seventh bridge section 57 via vias to connect the second electrode of the sixth transistor T6 and the first electrode of the light-emitting unit. Specifically, the third pixel driving circuit Pix3 drives the red light-emitting unit, the second pixel driving circuit Pix2 drives the green light-emitting unit, and the first pixel driving circuit Pix1 drives the blue light-emitting unit.

[0172] Furthermore, as shown in Figure 4-16, the two mirror-symmetrical pixel driving circuits can share the same third conductive part 23, and the shared third conductive part 23 can be connected to the third reset signal line Re3 through a via. At least partially mirror-symmetrical two pixel driving circuits can share the same eighth conductive part 38, and the shared eighth conductive part 38 can be connected to the third reset signal line Re3 through a via.

[0173] As shown in Figure 4-16, the two mirror-symmetrical pixel driving circuits can share the same fourth conductive part 24, and the shared fourth conductive part 24 can be connected to the second reset signal line Re2 through a via. At least partially mirror-symmetrical two pixel driving circuits can share the same ninth conductive part 39, and the shared ninth conductive part 39 can be connected to the second reset signal line Re2 through a via.

[0174] As shown in Figure 4-16, two mirror-symmetrical pixel driving circuits can share the same fifth conductive part 25, and the shared fifth conductive part 25 can be connected to the gate line via a via. At least partially mirror-symmetrical two pixel driving circuits can share the same tenth conductive part 310, and the shared tenth conductive part 310 can be connected to the gate line via a via.

[0175] As shown in Figure 4-16, in a mirror-symmetric two-pixel driving circuit, the two seventh active units 77 can be connected through the sixteenth active unit 716.

[0176] In this exemplary embodiment, as shown in FIG4-16, in a mirror-symmetric two-pixel driving circuit, the orthographic projections of the channel regions of two identical transistors on the substrate are mirror-symmetric with respect to an axis of symmetry extending along the second direction Y. For example, the orthographic projections of driving transistor T3 in one pixel driving circuit and driving transistor T1 in another pixel driving circuit on the substrate are mirror-symmetric with respect to an axis of symmetry extending along the second direction Y, and the orthographic projections of first transistor T1 in one pixel driving circuit and first transistor T1 in another pixel driving circuit on the substrate are mirror-symmetric with respect to an axis of symmetry extending along the second direction Y.

[0177] Figure 17 shows a partial cross-sectional view of the display panel shown in Figure 4, taken along the dashed line CC. The display panel may further include a first insulating layer 101, a buffer layer 102, a second insulating layer 103, a dielectric layer 104, a passivation layer 105, a first planarization layer 106, and a second planarization layer 107. The substrate 100, first gate layer, first insulating layer 101, second gate layer, buffer layer 102, active layer, second insulating layer 103, third gate layer, dielectric layer 104, first source / drain layer, passivation layer 105, first planarization layer 106, second source / drain layer, second planarization layer 107, and electrode layer are sequentially stacked. The buffer layer 102, the first insulating layer 101, and the second insulating layer 103 can be single-layer or multi-layer structures, and the materials of the buffer layer 102, the first insulating layer 101, and the second insulating layer 103 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer 104 can be a silicon nitride layer; the materials of the first planarization layer 106 and the second planarization layer 107 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 105 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of any one of the first and second source / drain layers can be less than the sheet resistance of any one of the first, second, and third gate layers.

[0178] In this exemplary embodiment, the first type of signal line and the first electrode of the first type of transistor in the first pixel driving circuit are connected through vias, while there is no via connection between the first type of signal line and the first electrode of the first type of transistor in the second pixel driving circuit. For example, the first signal line Ln1 may include a data line Da. As shown in FIG4-16, in the display area AA, the data line Da is connected to the first bridging portion 41 through a via, and the first bridging portion 41 is connected to the twelfth active portion 712 through a via, so as to connect the data line Da and the first electrode of the fourth transistor T4. In the first virtual area Dmy1, this exemplary embodiment may remove the via between the data line Da and the first bridging portion 41, or remove the via between the first bridging portion 41 and the twelfth active portion 712, so that the data line Da and the first electrode of the fourth transistor T4 are disconnected. The multiple second signal lines Ln2 may include a first power line VDD, a first initial signal line Vinit1, and a second initial signal line Vinit2. In display area AA, the first power line VDD is connected to the thirteenth active part 713 via a via, connecting the first power line VDD and the first terminal of the fifth transistor T5. In the second virtual area Dmy2, this exemplary embodiment can remove the via between the first power line VDD and the thirteenth active part 713, thereby disconnecting the first power line VDD from the first terminal of the fifth transistor. In display area AA, the first initial signal line Vinit1 is connected to the ninth active part 79 via a via, connecting the first initial signal line Vinit1 and the first terminal of the second transistor T2. In the second virtual area Dmy2, this exemplary embodiment can remove the via between the first initial signal line Vinit1 and the ninth active part 79, thereby disconnecting the first initial signal line Vinit1 from the first terminal of the second transistor T2. In display area AA, the second initial signal line Vinit2 is connected to the sixteenth active part 716 via a via, thereby connecting the second initial signal line Vinit2 and the first electrode of the seventh transistor T7; in the second virtual area Dmy2, this exemplary embodiment can remove the via between the second initial signal line Vinit2 and the sixteenth active part 716 to disconnect the second initial signal line Vinit2 from the first electrode of the seventh transistor T7. It should be understood that in other exemplary embodiments, the first type of signal line and the first type of transistor can also be disconnected by removing part of the active layer structure.

[0179] In this exemplary embodiment, the multilayer insulating layers located between the substrate and the first source / drain layer can form an insulating layer group. For example, as shown in FIG17, the first insulating layer 101, buffer layer 102, second insulating layer 103, and dielectric layer 104 can form an insulating layer group 10. FIG18 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. A virtual via Hdy is formed on the insulating layer group 10. The virtual via Hdy is a hole added in addition to a normal via. The display panel can release hydrogen in the first insulating layer 101, buffer layer 102, second insulating layer 103, and dielectric layer 104 through the virtual via Hdy to reduce the influence of hydrogen on the threshold of the oxide transistor.

[0180] As shown in Figure 18, the display panel further includes a border area Bk located on the side of the virtual area Dmy away from the display area AA. A virtual aperture Hdy may be located in the border area Bk. The display panel may also include a gate driving circuit, which may be integrated into the border area Bk. It should be understood that, in other exemplary embodiments, the virtual aperture Hdy may also be located in one or more of the display area AA, the virtual area Dmy, and the border area Bk.

[0181] As shown in Figures 19, 20, and 21, Figure 19 is a partial structural layout of the area where the virtual hole is located in an exemplary embodiment of the display panel of this disclosure, Figure 20 is a structural layout of the resist portion in Figure 19, and Figure 21 is a cross-sectional view of the display panel shown in Figure 19 along the dashed line DD. The display panel further includes a resist portion Zk, which is correspondingly disposed with the virtual hole Hdy. The resist portion Zk is located at the bottom of the substrate facing the virtual hole Hdy. During the process of forming the virtual hole Hdy through an etching process, the resist portion Zk can be used to prevent over-etching of the virtual hole. The plurality of resist portions Zk includes a first resist portion Zk1 and a second resist portion Zk2. The first resist portion Zk1 can be located in the first gate layer, and the second resist portion Zk2 can be located in the active layer.

[0182] As shown in Figures 22, 23, and 24, Figure 22 is a partial structural layout of the area where the virtual hole is located in another exemplary embodiment of the display panel of this disclosure, Figure 23 is a structural layout of the resist portion in Figure 22, and Figure 24 is a cross-sectional view of the display panel shown in Figure 22 along the dashed line EE. The display panel further includes a resist portion Zk, which is correspondingly disposed with the virtual hole Hdy. The resist portion Zk is located at the bottom of the substrate facing the virtual hole Hdy. During the process of forming the virtual hole Hdy through an etching process, the resist portion Zk can be used to prevent over-etching of the virtual hole. The plurality of resist portions Zk includes a first resist portion Zk1, a second resist portion Zk2, and a third resist portion Zk3. The first resist portion Zk1 can be located in the first gate layer, the second resist portion Zk2 can be located in the active layer, and the third resist portion Zk3 can be located in the second gate layer.

[0183] In this exemplary embodiment, as shown in Figures 19-24, the multiple resistive etched portions Zk can be suspended, meaning that the resistive etched portions Zk are not connected to other conductive structures and do not receive potential signals from other conductive portions. It should be understood that in other exemplary embodiments, the resistive etched portions Zk can also be connected to other conductive portions, whereby the resistive etched portions Zk can regulate the voltage of other conductive structures or couple their own voltage changes to other conductive portions.

[0184] In this exemplary embodiment, as shown in Figures 19-24, the resist part Zk and the virtual hole Hdy are configured in a one-to-one correspondence. It should be understood that in other exemplary embodiments, one resist part Zk may also correspond to multiple virtual holes Hdy.

[0185] In this exemplary embodiment, as shown in Figures 19-24, the virtual aperture Hdy may not be filled with the first source / drain layer, and a portion of the passivation layer 105 may fill the virtual aperture Hdy. It should be understood that in other exemplary embodiments, a portion of the first source / drain layer may also fill the virtual aperture Hdy.

[0186] In this exemplary embodiment, as shown in Figures 19-24, the plurality of virtual holes include a first virtual hole Hdy1 and a second virtual hole Hdy2; the resist portion Zk corresponding to the first virtual hole Hdy1 is located in one or more layers of the first gate layer and the second gate layer, and the resist portion Zk corresponding to the second virtual hole Hdy2 is located in one or more layers of the active layer and the third gate layer.

[0187] In this exemplary embodiment, during the fabrication of the display panel, after forming the dielectric layer 104 on the side of the third gate layer facing away from the substrate, holes can be formed on the insulating layer group 10 through two patterning processes. The first patterning process is used to form vias connecting the first source / drain layer and the first gate layer, as well as vias connecting the first source / drain layer and the second gate layer. The second patterning process is used to form vias connecting the first source / drain layer and the active layer, as well as vias connecting the first source / drain layer and the third gate layer. The first virtual hole Hdy1 can be formed in the first patterning process, and the second virtual hole Hdy2 can be formed in the second patterning process. In this exemplary embodiment, after the first patterning process and before the second patterning process, the active layer needs to be annealed. However, in the high-temperature environment of the annealing process, hydrogen in the first insulating layer 101, buffer layer 102, second insulating layer 103, and dielectric layer 104 is prone to overflow. The first virtual hole Hdy1 can effectively remove hydrogen from the display panel to avoid hydrogen affecting the performance of the oxide transistor. Therefore, in this exemplary embodiment, the first virtual hole Hdy1 plays a major role in hydrogen removal. As shown in Figures 19-24, the number of first virtual vias Hdy1 within a unit area is greater than the number of second virtual vias Hdy2 within a unit area. This exemplary embodiment, by setting a larger number of first virtual vias Hdy1, can facilitate hydrogen removal from the display panel. The second virtual vias Hdy2 are mainly used to simulate vias connecting the first source / drain layer to the active layer and the third gate layer, thereby improving the process stability of the vias.

[0188] In this exemplary embodiment, as shown in Figures 19-21, the ratio of the number of the first virtual hole Hdy1 and the second virtual hole Hdy2 per unit area can be 2:1. In this exemplary embodiment, as shown in Figures 22-24, the ratio of the number of the first virtual hole Hdy1 and the second virtual hole Hdy2 per unit area can be 3:2.

[0189] In this exemplary embodiment, as shown in Figures 4-16, the second source / drain layer includes multiple column-oriented extension lines Lv. These multiple column-oriented extension lines Lv may include a data line Da, a second power connection line 5VSS, a first power connection line 5VDD, a first initial connection line 5Vinit1, and a second initial connection line 5Vinit2. Figure 25 shows a partial structural layout of a display panel in an exemplary embodiment of this disclosure. Figure 25 illustrates the structural layout of the first and second source / drain layers in the second virtual area Dmy2. In the second virtual region Dmy2, at least part of the column extension line Lv and the pixel driving circuit are disconnected. For example, the via between the data line Da and the first bridge portion 41, or the via between the first bridge portion 41 and the twelfth active portion 712, can be removed to disconnect the data line Da from the first terminal of the fourth transistor T4; the via between the first power connection line 5VDD and the first power line VDD can be removed to disconnect the first power connection line 5VDD from the first terminal of the fifth transistor; the via between the first initial connection line 5Vinit1 and the first initial signal line Vinit1 can be removed to disconnect the first initial connection line 5Vinit1 from the first terminal of the second transistor T2; the via between the second initial connection line 5Vinit2 and the second initial signal line Vinit2 can be removed to disconnect the second initial connection line 5Vinit2 from the first terminal of the seventh transistor T7. In the second virtual area Dmy2, data line Da, second power connection line 5VSS, first power connection line 5VDD, first initial connection line 5Vinit1, and second initial connection line 5Vinit2 can be connected on the same layer to jointly connect to the second power line VSS. The second power line VSS is used to provide a power signal to the second electrode of the light-emitting unit. This arrangement allows the column extension line Lv in the second virtual area Dmy2 to not need to receive normal signals, thereby simplifying the display panel structure. For example, data line Da in the second virtual area Dmy2 may not require a corresponding source drive circuit.

[0190] It should be understood that in other exemplary embodiments, the column extension lines Lv can also be connected to other regulated signal terminals. For example, as shown in FIG26, a partial structural layout of another exemplary embodiment of the display panel of this disclosure is shown. FIG26 shows a structural layout of the first source / drain layer and the second source / drain layer in the second virtual area Dmy2. Multiple column extension lines Lv can be connected on the same layer and connected to the first power line VDD. The first power line VDD is used to provide power signals to the pixel driving circuit.

[0191] It should be noted that the other structures of the pixel driving circuit in the virtual area Dmy can be the same as those in the display area AA.

[0192] It should be noted that, as shown in Figure 4-26, the chamfered black squares drawn on the side of the first source / drain layer facing away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black rectangles drawn on the side of the second source / drain layer facing away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. Vias at different locations can penetrate different insulating layers.

[0193] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The drawings described in this disclosure are only schematic diagrams of the structure. In addition, the qualifiers such as first, second, and x are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction. The first and second electrodes of the transistor are the source / drain electrodes.

[0194] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0195] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0196] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes a display area, a virtual area surrounding the display area, and a border area located on the side of the virtual area away from the display area. The display panel also includes: Substrate; Multiple pixel driving circuits are located on one side of the substrate. Each pixel driving circuit includes a first type of transistor, which is an oxide transistor. The multiple pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit. The first pixel driving circuit is located in the display area, and the second pixel driving circuit is located in the virtual area. The first type of signal line is located on one side of the substrate. The first type of signal line is connected to the first electrode of the first type of transistor in the first pixel driving circuit, and the first type of signal line is disconnected from the first electrode of the first type of transistor in the second pixel driving circuit. An active layer is located on one side of the substrate, and at least a portion of the structure of the active layer is used to form the channel region of the oxide transistor in the pixel driving circuit. A first source / drain layer is located on the side of the active layer opposite to the substrate, and at least a portion of the structure of the first source / drain layer is connected to the oxide transistor through vias; An insulating layer group includes multiple insulating layers, the insulating layer group being located between the first source / drain layer and the substrate, and a plurality of virtual holes are formed on the insulating layer group; At least a portion of the virtual holes are located in one or more areas of the virtual area and the border area.

2. The display panel according to claim 1, wherein, The plurality of pixel driving circuits are arrayed along a first direction and a second direction, the first direction and the second direction intersecting; The virtual area includes a first virtual area, which is located on one or both sides of the display area in the second direction; The display panel includes multiple first-type signal lines, among which a first signal line is included. The orthographic projection of the first signal line on the substrate extends along the second direction, and the first electrode of the first-type transistor in the second pixel driving circuit of the first virtual area is disconnected from the first signal line.

3. The display panel according to claim 1, wherein, The plurality of pixel driving circuits are arrayed along a first direction and a second direction, the first direction and the second direction intersecting; The virtual area includes a second virtual area, which is located on one or both sides of the display area in the first direction; The display panel includes multiple first-type signal lines, among which a second signal line is included. The orthographic projection of the second signal line on the substrate extends along the first direction, and the first electrode of the first-type transistor in the second pixel driving circuit of the second virtual area and the second signal line are disconnected.

4. The display panel according to claim 1, wherein, The display panel includes multiple signal lines of the first type, among which a data line is included. The data line is used to provide data signals to the pixel driving circuit. The pixel driving circuit includes one or more transistors of the first type, and the one or more transistors of the first type include a fourth transistor; The data line is connected to the first terminal of the fourth transistor in the first pixel driving circuit, and the data line is disconnected from the first terminal of the fourth transistor in the second pixel driving circuit.

5. The display panel according to claim 1, wherein, The display panel includes multiple signal lines of the first type, among which a first initial signal line is included; The pixel driving circuit includes one or more first-type transistors and a driving transistor, wherein the one or more first-type transistors include a second transistor, and the second terminal of the second transistor is connected to the gate of the driving transistor. The first initial signal line is connected to the first terminal of the second transistor in the first pixel driving circuit, and the first initial signal line and the first terminal of the second transistor in the second pixel driving circuit are disconnected.

6. The display panel according to claim 1, wherein, The display panel includes multiple signal lines of the first type, among which a first power line is included. The first power line is used to provide a power signal to the pixel driving circuit. The pixel driving circuit includes one or more transistors of the first type, and the one or more transistors of the first type include a fifth transistor; The first power line is connected to the first terminal of the fifth transistor in the first pixel driving circuit, and the first power line and the first terminal of the fifth transistor in the second pixel driving circuit are disconnected.

7. The display panel according to claim 1, wherein, The display panel further includes a light-emitting unit, and the display panel includes multiple first-type signal lines, among which a second initial signal line is included; The pixel driving circuit includes one or more first-type transistors, and the one or more first-type transistors include a seventh transistor, the second electrode of which is connected to the first electrode of the light-emitting unit; The second initial signal line is connected to the first terminal of the seventh transistor in the first pixel driving circuit, and the second initial signal line and the first terminal of the seventh transistor in the second pixel driving circuit are disconnected.

8. The display panel according to any one of claims 1-7, wherein, The first type of signal line and the first electrode of the first type of transistor in the first pixel driving circuit are connected through a via, while there is no via connection between the first type of signal line and the first electrode of the first type of transistor in the second pixel driving circuit.

9. The display panel according to any one of claims 1-7, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit includes a plurality of first-type transistors, a first transistor, a driving transistor, a sixth transistor, and two capacitors. The two capacitors include a first capacitor and a second capacitor. The plurality of first-type transistors include a second transistor, a fourth transistor, a fifth transistor, and a seventh transistor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the first electrode of the first capacitor. The second terminal of the second transistor is connected to the gate of the driving transistor, and the first terminal of the second transistor in the first pixel driving circuit is connected to the first initial signal line; The second terminal of the fourth transistor is connected to the gate of the driving transistor, and the first terminal of the fourth transistor in the first pixel driving circuit is connected to the data line. The second terminal of the fifth transistor is connected to the first terminal of the driving transistor, and the first terminal of the fifth transistor in the first pixel driving circuit is connected to the first power supply line. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit. The second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, and the first electrode of the seventh transistor in the first pixel driving circuit is connected to the second initial signal line. The first transistor, the driving transistor, and the sixth transistor are oxide transistors.

10. The display panel according to claim 1, wherein, The display panel also includes: A resist area is provided, and the resist area and the virtual hole are correspondingly provided. The resist area is located at the bottom of the substrate facing the virtual hole.

11. The display panel according to claim 10, wherein, The etching part is suspended in the air.

12. The display panel according to claim 10, wherein, The pixel driving circuit also includes capacitors, and the display panel also includes: A first gate layer is located between the active layer and the substrate, and at least a portion of the structure of the first gate layer is used to form the first electrode of the capacitor; A second gate layer is located between the first gate layer and the active layer, and at least a portion of the structure of the second gate layer is used to form the bottom gate of the oxide transistor; A third gate layer is located between the active layer and the first source / drain layer, and at least a portion of the structure of the third gate layer is used to form the top gate of the oxide transistor; The insulating layer group has a plurality of virtual holes formed thereon, including a first virtual hole and a second virtual hole; The resist portion corresponding to the first virtual hole is located in one or more layers of the first gate layer and the second gate layer, and the resist portion corresponding to the second virtual hole is located in one or more layers of the active layer and the third gate layer.

13. The display panel according to claim 12, wherein, The number of the first virtual holes within the unit area is greater than the number of the second virtual holes within the unit area.

14. The display panel according to claim 1, wherein, The display panel also includes: A passivation layer is located on the side of the first source / drain layer away from the substrate, and a portion of the passivation layer is filled within the virtual hole.

15. The display panel according to claim 1, wherein, At least a portion of the virtual hole is located in the display area.

16. The display panel according to any one of claims 1-15, wherein, The plurality of pixel driving circuits are arrayed along a first direction and a second direction, the first direction and the second direction intersecting; At least a portion of the structure of the first source / drain layer is connected to the oxide transistor via vias; The display panel also includes: The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes multiple column-oriented extension lines, and the orthogonal projection of the column-oriented extension lines on the substrate extends along the second direction. The virtual area includes a second virtual area, which is located on one or both sides of the display area in the first direction. At least a portion of the column extension lines in the second virtual area are disconnected from the pixel driving circuit, and the at least portion of the column extension lines disconnected from the pixel driving circuit are connected to a regulated signal terminal.

17. The display panel according to claim 16, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit is connected to the first electrode of the light-emitting unit; The display panel further includes a first power line and a second power line, wherein the first power line is used to provide a power signal to the pixel driving circuit, and the second power line is used to provide a power signal to the second electrode of the light-emitting unit; The first power line or the second power line provides the regulated signal terminal.

18. The display panel according to any one of claims 1-17, wherein, The display panel includes multiple pixel driving circuit groups, which are arrayed along a first direction and a second direction, the first direction and the second direction intersecting. The pixel driving circuit group includes a plurality of pixel driving circuits that are adjacent in a first direction. In the same pixel driving circuit group, there is at least one set of two adjacent pixel driving circuits whose orthogonal projections on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along a second direction.

19. The display panel according to any one of claims 1-17, wherein, The pixel driving circuit includes a driving transistor and two capacitors, namely a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The display panel also includes: A first gate layer is located between the substrate and the active layer. The first gate layer includes a first conductive portion and a second conductive portion connected in the same layer. The first conductive portion is used to form a first electrode of the first capacitor, and the second conductive portion is used to form a first electrode of the second capacitor. A second gate layer is located between the first gate and the active layer. The second gate layer includes a sixth conductive portion and a seventh conductive portion. The orthographic projection of the sixth conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap. The sixth conductive portion is used to form the second electrode of the first capacitor. The orthographic projection of the seventh conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate at least partially overlap. The seventh conductive portion is used to form the second electrode of the second capacitor. The orthographic projections of the sixth conductive part and the seventh conductive part on the substrate are distributed along the second direction.

20. The display panel according to any one of claims 1-17, wherein, The pixel driving circuit includes a driving transistor and two capacitors, including a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The display panel also includes: A second gate layer is located between the substrate and the active layer. The second gate layer includes a sixth conductive portion, which is used to form the second electrode of the first capacitor. The active layer further includes a third active portion, which is used to form the channel region of the driving transistor; Wherein, the orthogonal projection of the sixth conductive part on the substrate covers the orthogonal projection of the third active part on the substrate.

21. The display panel according to any one of claims 1-17, wherein, The pixel driving circuit includes one or more first-type transistors, and the one or more first-type transistors include a fifth transistor. The display panel includes multiple first-type signal lines and light-emitting units, and the multiple first-type signal lines include a first power line. The pixel driving circuit further includes a driving transistor, two capacitors, and a sixth transistor. The two capacitors include a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The second terminal of the fifth transistor is connected to the first terminal of the driving transistor, the gate is connected to the third enable signal line, and the first terminal of the fifth transistor in the first pixel driving circuit is connected to the first power supply line. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the fourth enable signal line. The display panel also includes: The second gate layer is located between the substrate and the active layer. The second gate layer includes a sixth conductive portion, a seventh conductive portion, a third enable signal line, and a fourth enable signal line. The sixth conductive portion is used to form the second electrode of the first capacitor, the seventh conductive portion is used to form the second electrode of the second capacitor, a portion of the structure of the third enable signal line is used to form the bottom gate of the fifth transistor, and a portion of the structure of the fourth enable signal line is used to form the bottom gate of the sixth transistor. Wherein, the orthographic projections of the third enable signal line and the fourth enable signal line on the substrate extend along the first direction. In the same pixel driving circuit, the orthographic projections of the sixth conductive part and the seventh conductive part on the substrate are located between the orthographic projections of the third enable signal line and the fourth enable signal line on the substrate.

22. The display panel according to any one of claims 1-17, wherein, The pixel driving circuit includes one or more first-type transistors, and the one or more first-type transistors include a fifth transistor and a seventh transistor. The display panel includes multiple first-type signal lines and light-emitting units, and the multiple first-type signal lines include a first power line and a second initial signal line. The pixel driving circuit also includes a driving transistor and a sixth transistor. The second terminal of the fifth transistor is connected to the first terminal of the driving transistor, the gate is connected to the first enable signal line, and the first terminal of the fifth transistor in the first pixel driving circuit is connected to the first power supply line. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the second enable signal line. The second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, the gate is connected to the first reset signal line, and the first electrode of the seventh transistor in the first pixel driving circuit is connected to the second initial signal line. A portion of the structure of the active layer is used to form the channel regions of the driving transistor, the fifth transistor, the sixth transistor, and the seventh transistor; The display panel also includes: A third gate layer is located between the active layer and the first source / drain layer. The third gate layer includes a first enable signal line, a second enable signal line, a first reset signal line, and an eleventh conductive portion. A portion of the structure of the first enable signal line is used to form the top gate of the fifth transistor, a portion of the structure of the second enable signal line is used to form the top gate of the sixth transistor, a portion of the structure of the first reset signal line is used to form the top gate of the seventh transistor, and the eleventh conductive portion is used to form the top gate of the driving transistor. In the same pixel driving circuit, the orthographic projections of the first enable signal line, the second enable signal line, and the first reset signal line on the substrate extend along a first direction and are sequentially spaced along a second direction. The orthographic projection of the eleventh conductive part on the substrate is located between the orthographic projections of the first enable signal line and the second enable signal line on the substrate. The orthographic projection of the first reset signal line on the substrate is located on the side of the second enable signal line on the substrate away from the orthographic projection of the eleventh conductive part on the substrate.

23. The display panel according to claim 22, wherein, The pixel driving circuit includes one or more first-type transistors, and the one or more first-type transistors include a second transistor and a fourth transistor. The display panel includes multiple first-type signal lines, and the multiple first-type signal lines include a data line and a first initial signal line. The pixel driving circuit also includes a first transistor and two capacitors. The two capacitors include a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the first electrode of the first capacitor. The second terminal of the second transistor is connected to the gate of the driving transistor, and the first terminal of the second transistor in the first pixel driving circuit is connected to the first initial signal line; The second terminal of the fourth transistor is connected to the gate of the driving transistor, and the first terminal of the fourth transistor in the first pixel driving circuit is connected to the data line. The display panel also includes: A third gate layer is located between the active layer and the first source / drain layer. The third gate layer includes an eighth conductive portion, a ninth conductive portion, and a tenth conductive portion. The eighth conductive portion is used to form the top gate of the first transistor, the ninth conductive portion is used to form the top gate of the second transistor, and the tenth conductive portion is used to form the top gate of the fourth transistor. A portion of the structure of the active layer is used to form the channel regions of the first transistor, the second transistor, and the fourth transistor; The first source / drain layer further includes a gate line, a second reset signal line, and a third reset signal line. The gate line is connected to the tenth conductive part through a via, the second reset signal line is connected to the ninth conductive part through a via, and the third reset signal line is connected to the eighth conductive part through a via. The orthogonal projections of the gate line, the second reset signal line, and the third reset signal line on the substrate extend along a first direction. In the same pixel driving circuit, the orthographic projection of the gate line on the substrate is located between the orthographic projection of the first enable signal line on the substrate and the orthographic projection of the eleventh conductive part on the substrate; the orthographic projection of the second reset signal line on the substrate is located between the orthographic projection of the eleventh conductive part on the substrate and the orthographic projection of the second enable signal line on the substrate; and the orthographic projection of the third reset signal line on the substrate is located between the orthographic projection of the second reset signal line on the substrate and the orthographic projection of the second enable signal line on the substrate.

24. The display panel according to any one of claims 1-17, wherein, The pixel driving circuit includes one or more first-type transistors, and the one or more first-type transistors include a second transistor, a fourth transistor, a fifth transistor, and a seventh transistor. The display panel includes multiple first-type signal lines and light-emitting units, and the multiple first-type signal lines include a data line, a first initial signal line, and a first power line. The pixel driving circuit also includes a driving transistor, a first transistor, a sixth transistor, and two capacitors. The two capacitors include a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the first electrode of the first capacitor. The second terminal of the second transistor is connected to the gate of the driving transistor, and the first terminal of the second transistor in the first pixel driving circuit is connected to the first initial signal line; The second terminal of the fourth transistor is connected to the gate of the driving transistor, and the first terminal of the fourth transistor in the first pixel driving circuit is connected to the data line. The second terminal of the fifth transistor is connected to the first terminal of the driving transistor, and the first terminal of the fifth transistor in the first pixel driving circuit is connected to the first power line. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit. The second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, and the first electrode of the seventh transistor in the first pixel driving circuit is connected to the second initial signal line. The active layer includes a first main active portion and a second main active portion. The orthographic projection of the first main active portion on the substrate and the orthographic projection of the second main active portion on the substrate extend along a second direction and are spaced apart in a first direction. The first main active portion includes a first active portion, a second active portion, and a fourth active portion that are sequentially spaced apart along a second direction. The first active portion is used to form the channel region of the first transistor, the second active portion is used to form the channel region of the second transistor, and the fourth active portion is used to form the channel region of the fourth transistor. The second main active portion includes a sixth active portion, a third active portion, and a fifth active portion that are sequentially spaced apart along a second direction. The sixth active portion is used to form the channel region of the sixth transistor, the third active portion is used to form the channel region of the driving transistor, and the fifth active portion is used to form the channel region of the fifth transistor.

25. A display device, wherein, The display device includes the display panel as described in any one of claims 1-24.

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