Array substrate and display panel

Abstract

An array substrate (100), comprising a substrate (101). A first conductive layer (10), a semiconductor layer (50), a second conductive layer (20), a third conductive layer (30), a fourth conductive layer (40), and a thin film transistor (T) are provided sequentially in the direction moving away from the substrate (101). The first conductive layer (10) comprises a first signal line (11) and a first conductive pattern (12). The second conductive layer (20) comprises a second signal line (21) and a second conductive pattern (22), and the orthographic projections of the second conductive pattern (22) and the first conductive pattern (12) on the substrate (101) at least partially overlap. The third conductive layer (30) comprises a third conductive pattern (31), the fourth conductive layer (40) comprises a pixel electrode (41), and the orthographic projections of the pixel electrode (41) and the third conductive pattern (31) on the substrate (101) at least partially overlap. The second conductive layer (20) may further comprise a first electrode (23) and a second electrode (24) of the thin film transistor (T), the first electrode (23) may be electrically connected to the second signal line (21), and the second electrode (24) may be electrically connected to the second conductive pattern (22). The first conductive pattern (12) is electrically insulated from the second electrode (24), and a first capacitor is formed between the first conductive pattern (12) and the second conductive pattern (22). The pixel electrode (41) is electrically connected to the second conductive pattern (22), and a second capacitor is formed between the third conductive pattern (31) and the pixel electrode (41).

Description

Array substrate and display panel Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Electrophoretic displays offer advantages such as low power consumption, portability, eye protection, and the ability to update display content at any time, leading to their increasing application in various fields including education, healthcare, and daily reading. For example, electrophoretic displays may include electronic paper, an ultra-thin and ultra-light display device that provides a display effect close to that of natural paper, thus reducing reading fatigue when used as a reading device. Summary of the Invention

[0003] On one hand, an array substrate is provided. The array substrate includes a substrate, a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. The first conductive layer is disposed on one side of the substrate and includes a first signal line and a first conductive pattern, wherein the first conductive pattern is electrically insulated from the first signal line. The semiconductor layer is disposed on the side of the first conductive layer away from the substrate and includes a plurality of semiconductor patterns. The second conductive layer is disposed on the side of the semiconductor layer away from the substrate and includes a second signal line and a second conductive pattern, wherein the orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first conductive pattern on the substrate. The third conductive layer is disposed on the side of the second conductive layer away from the substrate and includes a third conductive pattern. The fourth conductive layer is disposed on the side of the third conductive layer away from the substrate and includes a pixel electrode. The orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the third conductive pattern on the substrate. The array substrate further includes a thin-film transistor, which includes a gate located on the first conductive layer and electrically connected to the first signal line, the semiconductor pattern, and a first electrode and a second electrode located on the second conductive layer. The first electrode is electrically connected to the second signal line, and the second electrode is electrically connected to the second conductive pattern. The first conductive pattern is electrically insulated from the second electrode and forms a first capacitance with the second conductive pattern. The pixel electrode is electrically connected to the second conductive pattern, and a second capacitance is formed between the third conductive pattern and the pixel electrode.

[0004] In some embodiments, the array substrate further includes a gate insulating layer. The gate insulating layer is disposed between the first conductive layer and the semiconductor layer, and the gate insulating layer covers the first conductive pattern.

[0005] In some embodiments, the first conductive pattern and the second conductive pattern have the same shape as the orthographic projection onto the substrate.

[0006] In some embodiments, the first conductive layer further includes a first connecting line, which is located between two adjacent first conductive patterns along a first direction and connected to the two first conductive patterns; the first direction is the extension direction of the first signal line.

[0007] In some embodiments, the third conductive layer further includes a second connecting line located between two adjacent third conductive patterns along a second direction and connected to the two first conductive patterns; the second direction is the extension direction of the second signal line and intersects the first direction.

[0008] In some embodiments, the array substrate includes a display area and a peripheral area surrounding the display area. The first conductive pattern and the third conductive pattern are configured to transmit the same voltage signal, and the first conductive pattern and the third conductive pattern are electrically connected in the peripheral area.

[0009] In some embodiments, the third conductive layer further includes a transition block, through which the pixel electrode is electrically connected to the second conductive pattern.

[0010] In some embodiments, the array substrate further includes a second insulating layer, a planarization layer, and a third insulating layer. The second insulating layer is disposed between the second conductive layer and the third conductive layer; the planarization layer is disposed between the second insulating layer and the third conductive layer; and the third insulating layer is disposed between the third conductive layer and the fourth conductive layer. The array substrate further includes a first via, a second via, and a third via. The first via penetrates the second insulating layer and exposes the second conductive pattern. The second via penetrates the planarization layer and exposes at least a portion of the first via. The third via penetrates the third insulating layer and exposes at least a portion of the adapter block. The adapter block is electrically connected to the second conductive pattern through the second via and the first via, and the pixel electrode is electrically connected to the adapter block through the third via.

[0011] In some embodiments, the orthographic projection of the second via on the substrate covers the orthographic projection of the first via on the substrate. The orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the second via on the substrate.

[0012] In some embodiments, the orthographic projection of the third conductive pattern on the substrate covers the orthographic projection of the semiconductor pattern on the substrate.

[0013] In some embodiments, at least two of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are made of metallic conductive materials.

[0014] In some embodiments, the materials of the first conductive layer, the second conductive layer, and the third conductive layer all include metallic conductive materials, and the material of the fourth conductive layer includes a transparent conductive material.

[0015] In some embodiments, the thickness of the first conductive layer is And / or, the thickness of the second conductive layer is And / or, the thickness of the third conductive layer is And / or, the thickness of the fourth conductive layer is

[0016] In another aspect, a display panel is provided, which includes the array substrate described in any of the above embodiments. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0018] Figure 1 is a structural diagram of a display panel according to some embodiments;

[0019] Figure 2 is a structural diagram of an array substrate according to some embodiments;

[0020] Figure 3 is a cross-sectional view along section line AA in Figure 2;

[0021] Figure 4 is a structural diagram of the first conductive layer according to some embodiments;

[0022] Figure 5 is a structural diagram of a first conductive layer, a semiconductor layer, and a second conductive layer according to some embodiments;

[0023] Figure 6 is a structural diagram of a third conductive layer and a fourth conductive layer according to some embodiments;

[0024] Figure 7 is another structural diagram of the third and fourth conductive layers according to some embodiments;

[0025] Figure 8 is a structural diagram of the second via and the first via according to some embodiments;

[0026] Figure 9 is a structural diagram of the third via and the second via according to some embodiments;

[0027] Figure 10 is a structural diagram of the semiconductor layer and the third conductive layer according to some embodiments. Detailed Implementation

[0028] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0029] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0030] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0031] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0032] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0033] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0034] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0035] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0036] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0037] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0038] Embodiments of this disclosure provide a display device, wherein the display device 1000 is a product having an image display function. Exemplarily, the display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0039] For example, the display device 1000 can be any product or component with display function, such as electronic paper, television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, display of camera view (e.g., display of rearview camera in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, mixed reality (MR) device, in-vehicle display, flying display, etc.

[0040] In some embodiments, from the perspective of the light emission type of the display device 1000, the display device 1000 may be a liquid crystal display (LCD) or an electrophoretic display device. In one example, the display device provided in the embodiments of this disclosure may be an electrophoretic display device, for example, the display device may be electronic paper.

[0041] In some embodiments, referring to FIG1, the display device 1000 includes a display panel 1100 and a driving circuit board (not shown in the figure). The driving circuit board may include, for example, a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistor voltage divider circuit (generating Vcom), etc. Of course, the driving circuit board may also include other circuit structures, which will not be listed here. The driving circuit board is electrically connected to the display panel 1100 and is used to transmit control signals to the display panel 1100 to drive the display panel 1100 to display images. In addition, the display device 1000 may also include, but is not limited to, a touch structure, an under-display camera, and an under-display fingerprint sensor, enabling the display device 1000 to realize various functions such as touch control, photography, video recording, or fingerprint recognition, which will not be listed here.

[0042] In some embodiments, the display panel 1100 may include an array substrate 100. Referring, Continuing with FIG1, when the display device 1000 is an electrophoretic display device, the display panel 1100 may include an array substrate 100, a cover plate 200 disposed opposite to the array substrate 100, and an electrophoretic layer 300 located between the array substrate 100 and the cover plate 200. Alternatively, when the display device 1000 is a liquid crystal display device, the display panel 1100 may include an array substrate and a color filter substrate disposed opposite to each other, and a liquid crystal layer located between the array substrate and the color filter substrate. The embodiments of this disclosure will now be described exemplarily using an electrophoretic display device as an example.

[0043] As shown in Figure 1, the array substrate 100 may include a substrate 101 and pixel electrodes 41 disposed on the substrate 101, with the pixel electrodes 41 facing the cover plate 200. The cover plate 200 may include a substrate 201 and a common electrode 202 disposed on the substrate 201, with the common electrode 202 facing the array substrate 100. The pixel electrodes 41 and the common electrode 202 are at least partially opposite to each other. The electrophoretic layer 300 may include a plurality of electrophoretic capsules 301, each of which may include a capsule body, an electrophoretic liquid and charged particles located within the capsule body. The charged particles may include at least two of black particles, white particles, and colored particles, including but not limited to yellow particles, cyan particles, red particles, blue particles, and gray particles. When a voltage is applied to the pixel electrodes 41 in the array substrate 100, a voltage difference is formed between the pixel electrodes 41 and the common electrode 202. Under the action of this voltage difference, the charged particles in the electrophoretic capsules 301 move in the electrophoretic liquid to realize the display of the electronic paper.

[0044] For example, when a positive voltage is applied to the common electrode 202 and a negative voltage is applied to the pixel electrode 41, an electric field is generated between the common electrode 202 and the pixel electrode 41. Under the influence of this electric field, white particles accumulate on the side of the common electrode 202 (the side of the cover plate 200), while black particles accumulate on the side of the pixel electrode 41 (the side of the array substrate 100). At this time, under the reflection of natural light, the display panel displays a white image. Conversely, when a negative voltage is applied to the common electrode 202 and a positive voltage is applied to the pixel electrode 41, black particles accumulate on the side of the common electrode 202 (the side of the cover plate 200), while white particles accumulate on the side of the pixel electrode 41 (the side of the array substrate 100). At this time, under the reflection of natural light, the display panel displays a black image. Thus, the display panel can perform different controls on each sub-pixel to achieve the display of text and images.

[0045] In some embodiments, at least one of the white and black particles in each display unit (sub-pixel) can be replaced with other reflective particles of different colors. For example, the white particles can be replaced with particles that can reflect various colors such as red, green, and blue, thereby enabling the electronic paper display to achieve color display under the above control.

[0046] As display panels develop towards higher PPI, the area of ​​each sub-pixel (including but not limited to pixel electrodes and common electrodes) on the array substrate 100 is becoming smaller. Correspondingly, the storage capacitance formed by the pixel electrodes and other conductive structures on the array substrate is becoming smaller. The reduction in storage capacitance is detrimental to maintaining the voltage on the pixel electrodes. How to increase the size of the storage capacitance in each sub-pixel is a technical problem that urgently needs to be solved.

[0047] To address the aforementioned technical problems, referring to Figures 2 and 3, embodiments of this disclosure provide an array substrate 100. The array substrate 100 includes a substrate 101, and a first conductive layer 10, a semiconductor layer 50, a second conductive layer 20, a third conductive layer 30, a fourth conductive layer 40, and a thin-film transistor T disposed on the substrate 101. The first conductive layer 10 is disposed on one side of the substrate 101, the semiconductor layer 50 is disposed on the side of the first conductive layer 10 away from the substrate 101, the second conductive layer 20 is disposed on the side of the semiconductor layer 50 away from the substrate 101, the third conductive layer 30 is disposed on the side of the second conductive layer 20 away from the substrate 101, and the fourth conductive layer 40 is disposed on the side of the third conductive layer 30 away from the substrate 101. That is, the first conductive layer 10, the semiconductor layer 50, the second conductive layer 20, the third conductive layer 30, and the fourth conductive layer 40 are sequentially disposed along a direction away from the substrate 101.

[0048] Referring to Figure 4, the first conductive layer 10 includes a first signal line 11 and a first conductive pattern 12, wherein the first conductive pattern 12 is electrically insulated from the first signal line 11. For example, there is a gap between the first signal line 11 and the first conductive pattern 12. The first conductive layer 10 may also include a gate 14 of a thin-film transistor T1, which is electrically connected to the first signal line 11. Exemplarily, the first signal line 11 may be a scan signal line, and the gate 14 is integrally formed with the first signal line 11.

[0049] Referring to Figure 5, the semiconductor layer 50 includes a plurality of semiconductor patterns 51. The material of the semiconductor layer 50 may include polycrystalline silicon, amorphous silicon, and oxide semiconductors; the embodiments of this disclosure do not specifically limit the material of the semiconductor layer 50. Furthermore, the semiconductor patterns 51 may include semiconductor regions and conductor regions located on both sides of the semiconductor regions. The semiconductor regions refer to the undoped portions of the semiconductor patterns 51, which retain semiconductor properties and can be used to form the channel structure of thin-film transistors. The conductor regions refer to the portions of the semiconductor patterns 51 that have undergone a conductor-enhancing process (such as a doping process) and can be used for electrical connection to the first electrode 23 and the second electrode 24 of the thin-film transistor T. For example, the material of the semiconductor layer 50 may include metal oxide materials and / or metal oxide nitride materials. The metal oxide materials include, but are not limited to, one or more of the following: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth doped oxide (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O.

[0050] Metallic nitride materials include, but are not limited to, zinc nitride, indium nitride, gallium nitride, tin nitride, cadmium nitride, aluminum nitride, germanium nitride, titanium nitride, silicon nitride, or combinations thereof.

[0051] The material of the semiconductor layer 50 can be amorphous, partially crystalline, single-crystal or polycrystalline, and can also be a single-layer or multi-layer structure.

[0052] Referring to Figure 5, the second conductive layer 20 includes a second signal line 21 and a second conductive pattern 22. The second conductive layer 20 may also include a first electrode 23 and a second electrode 24 of a thin-film transistor T. The first electrode 23 may be electrically connected to the second signal line 21, and the second electrode 24 may be electrically connected to the second conductive pattern 22. For example, the first electrode 23 and the second signal line 21 may be integrally disposed, and the second electrode 24 and the second conductive pattern 22 may be integrally disposed. The thin-film transistor T includes a gate 14, a semiconductor pattern 51, a first electrode 23, and a second electrode 24. Exemplarily, the thin-film transistor T is a bottom-gate transistor.

[0053] Referring to Figures 3 and 5, the orthographic projection of the second conductive pattern 22 on the substrate 101 at least partially overlaps with the orthographic projection of the first conductive pattern 12 on the substrate 101. Thus, a first capacitor can be formed between the first conductive pattern 12 and the second conductive pattern 22. Furthermore, the second conductive pattern 22 is directly electrically connected to the second electrode 24, and the first conductive pattern 12 is electrically insulated from the second electrode 24. That is, the first conductive pattern 12 is not electrically connected to the thin-film transistor T. Based on this, it is unnecessary to provide vias in the insulating layer between the first conductive layer 10 and the second conductive layer 20. Therefore, the second conductive pattern 22 does not need to avoid the aforementioned vias, which helps to increase the area of ​​the second conductive pattern 22, thereby increasing the facing area between the second conductive pattern 22 and the first conductive pattern 12, increasing the size of the first capacitor formed by the second conductive pattern 22 and the first conductive pattern 12, and helping to maintain the stability of the voltage on the second conductive pattern 22.

[0054] For example, the orthographic projection of the second conductive pattern 22 on the substrate 101 is within the range of the orthographic projection of the first conductive pattern 12 on the substrate 101.

[0055] Referring to Figures 3 and 6, the third conductive layer 30 includes a third conductive pattern 31. The fourth conductive layer 40 includes a pixel electrode 41, the orthographic projection of which onto the substrate 101 at least partially overlaps with the orthographic projection of which onto the substrate 101, forming a second capacitor between the pixel electrode 41 and the third conductive pattern 31. The pixel electrode 41 is electrically connected to the second conductive pattern 22, thus the second capacitor and the first capacitor are connected in parallel, increasing the total capacitance of the storage capacitor formed by the pixel electrode 41.

[0056] In some embodiments, referring to FIG3, the array substrate 100 further includes a gate insulating layer 61, which is disposed between the first conductive layer 10 and the semiconductor layer 50. The gate insulating layer 61 covers the first conductive pattern 12, that is, the gate insulating layer 61 completely covers the surface of the first conductive pattern 12 away from the substrate 101. Vias may not be provided in the gate insulating layer 61, thus saving a process step of patterning the gate insulating layer 61, thereby simplifying the fabrication process of the array substrate 100 and reducing the manufacturing cost of the array substrate 100.

[0057] In some embodiments, referring to FIG5, the first conductive pattern 12 and the second conductive pattern 22 have the same shape as the orthographic projection on the substrate 101. This can greatly increase the facing area between the first conductive pattern 12 and the second conductive pattern 22, thereby increasing the capacitance of the first capacitor formed by the first conductive pattern 12 and the second conductive pattern 22, which is beneficial to increasing the total capacitance of the storage capacitor formed by the pixel electrode.

[0058] In some embodiments, at least two of the first conductive layer 10, the second conductive layer 20, the third conductive layer 30, and the fourth conductive layer 40 are made of a metallic conductive material. The metallic conductive material has a low resistance and is advantageous for reducing the thickness of the at least two conductive layers made of metallic conductive material.

[0059] The aforementioned conductive metallic materials may include one or more of titanium, aluminum, copper, molybdenum, niobium, nickel, and their alloys, or the conductive metallic materials may also be metallic multilayer structures. Exemplarily, the metallic multilayer structure may be one or a combination of the following: titanium-aluminum-titanium (Ti / Al / Ti) multilayer structure, molybdenum-aluminum (Mo / Al) multilayer structure, molybdenum-aluminum-molybdenum (Mo / Al / Mo) multilayer structure, molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) multilayer structure, molybdenum-niobium-copper (MoNb / Cu) multilayer structure, molybdenum-nickel-titanium-copper (MTD / Cu) multilayer structure, molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb / Cu / MTD) multilayer structure, molybdenum-nickel-titanium-copper-molybdenum-nickel-titanium (MTD / Cu / MTD) multilayer structure, molybdenum-neodymium-copper multilayer structure, MoNb-copper-MoNb multilayer structure, and AlNb-molybdenum-AlNd multilayer structure.

[0060] In one embodiment, the materials of the first conductive layer 10 and the second conductive layer 20 may include a metallic conductive material, which is beneficial for reducing the resistivity of the first conductive layer 10 and the second conductive layer 20, and thus for reducing the resistance and linewidth of the first signal line 11 and the second signal line 21. The metallic conductive material will not be described in detail here, as referred to above. The material of the third conductive layer 30 may include a metallic conductive material or a transparent conductive material; for example, the material of the third conductive layer 30 may include the aforementioned metallic conductive material.

[0061] When the material of the first conductive layer 10 includes a metallic conductive material, the thickness of the first conductive layer 10 can be [missing information]. For example, when the material of the first conductive layer 10 includes a single metal material, the thickness of the first conductive layer 10 can be [missing information]. When the material of the first conductive layer 10 is a metal stack structure, the total thickness of each stack of the first conductive layer 10 can be... For example, the thickness of the first conductive layer 10 can be or For example, the thickness of the first conductive layer 10 can be or And so on, which will not be listed one by one here.

[0062] Similar to the first conductive layer 10, when the materials of the second conductive layer 20 and the third conductive layer 30 include metallic conductive materials, the thickness of the second conductive layer 20 can be [missing information]. And / or, the thickness of the third conductive layer 30 can be For example, the thickness of the second conductive layer 20 can be or The thickness of the third conductive layer 30 can be... or And so on, which will not be listed one by one here.

[0063] The fourth conductive layer 40 is made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). This transparent conductive material exhibits good stability and is not easily oxidized, which helps to improve the stability of the fourth conductive layer 40.

[0064] When the material of the fourth conductive layer 40 includes a transparent conductive material (such as ITO), the thickness of the fourth conductive layer 40 can be [missing information]. For example, the thickness of the fourth conductive layer 40 can be or For example, the thickness of the fourth conductive layer 40 can be or

[0065] In some embodiments, referring to Figures 4 and 7, the first conductive layer 10 further includes a first connecting line 13, which is located between two adjacent first conductive patterns 12 along the first direction X and connected to the two first conductive patterns 12; this facilitates the transmission of voltage signals to the first conductive patterns 12. The first direction X is the extension direction of the first signal line 11.

[0066] For example, the array substrate 100 includes a display area AA and a peripheral area BB surrounding the display area AA. A first connecting line 13 is provided between any two adjacent first conductive patterns 12 along the first direction X. In this way, a row of first conductive patterns 12 can be interconnected into a whole (hereinafter referred to as the first capacitor plate) through the first connecting line 13. For example, if the first capacitor plate extends along the first direction X to the peripheral area BB of the array substrate 100, only one voltage signal needs to be applied to the first capacitor plate in the peripheral area BB to apply the same voltage signal to all the first conductive patterns 12 in that row, thereby facilitating the transmission of voltage signals to the first conductive patterns 12 located in the display area AA.

[0067] In some embodiments, referring to Figures 6 and 7, the third conductive layer 30 further includes a second connecting line 32, which is located between two adjacent third conductive patterns 31 along the second direction Y and connected to the two third conductive patterns 31; this facilitates the transmission of voltage signals to the third conductive patterns 31. The second direction Y is the extension direction of the second signal line 21.

[0068] For example, a second connecting line 32 is provided between any two adjacent third conductive patterns 31 along the second direction Y. In this way, a column of third conductive patterns 31 can be connected to each other as a whole (hereinafter referred to as the second capacitor plate) through the second connecting line 32. For example, the second capacitor plate extends along the second direction Y to the peripheral area BB of the array substrate. Only one voltage signal needs to be applied to the second capacitor plate in the peripheral area BB to apply the same voltage signal to all the third conductive patterns 31 in the column, which is beneficial to transmitting voltage signals to the third conductive patterns 31 located in the display area AA.

[0069] In some embodiments, the first conductive pattern 12 and the third conductive pattern 31 are configured to transmit the same voltage signal, and the first conductive pattern 12 and the third conductive pattern 31 are electrically connected in the peripheral area BB. For example, as shown in FIG7, the peripheral area BB may include a signal bus 102, which is at least partially disposed around the display area AA (e.g., completely surrounding the display area AA). The first capacitor plate formed by the first conductive pattern 12 and the first connecting line 13 is electrically connected to the signal bus 102 at both ends along the first direction X, and the second capacitor plate formed by the third conductive pattern 31 and the second connecting line 32 is electrically connected to the signal bus 102 at both ends along the second direction Y. Thus, the first capacitor plate and the second capacitor plate are arranged in parallel, which helps to reduce the voltage drop on the first capacitor plate and the second capacitor plate, and improves the voltage uniformity of the first conductive pattern 12 and the third conductive pattern 31 at different locations. In the embodiments of this disclosure, the extending directions of the first capacitor plate and the second capacitor plate intersect each other, and the orthographic projection of the first capacitor plate on the substrate 101 intersects with the orthographic projection of the second capacitor plate on the substrate 101 to form a mesh structure, which is beneficial to improving the voltage uniformity of the first conductive pattern 12 and the third conductive pattern 31.

[0070] In some embodiments, referring to Figures 3 and 6, the third conductive layer 30 further includes a transition block 33, through which the pixel electrode 41 is electrically connected to the second conductive pattern 22. Compared to the pixel electrode 41 being directly electrically connected to the second conductive pattern 22, the transition block 33 can reduce the difficulty of connecting the pixel electrode 41 and the second conductive pattern 22, and reduce the risk of short circuit at the connection via of the pixel electrode 41.

[0071] Referring again to Figure 3, the array substrate 100 further includes an insulating layer located between adjacent conductive layers. The array substrate 100 may include a second insulating layer 62, a planarization layer 63, and a third insulating layer 64. The second insulating layer 62 is disposed between the second conductive layer 20 and the third conductive layer 30, and the planarization layer 63 is disposed between the second insulating layer 62 and the third conductive layer 30. That is, the second insulating layer 62 and the planarization layer 63 are located between the second conductive layer 20 and the third conductive layer 30, with the second insulating layer 62 located on the side of the planarization layer 63 closer to the substrate 101.

[0072] The array substrate 100 also includes a first via V1, a second via V2, and a third via V3. The first via V1 penetrates the second insulating layer 62 and exposes at least a portion of the second conductive pattern 22. The second via V2 penetrates the planarization layer 63 and exposes at least a portion of the first via V1, thus also exposing at least a portion of the second conductive pattern 22. The adapter block 33 is electrically connected to the second conductive pattern 22 sequentially through the second via V2 and the first via V1. The third via V3 penetrates the third insulating layer 64, and the pixel electrode 41 can be electrically connected to the adapter block 33 through the third via V3.

[0073] In some embodiments, referring to Figures 3 and 8, the orthographic projection of the second via V2 on the substrate 101 covers the orthographic projection of the first via V1 on the substrate 101, and the second via V2 and the first via V1 form a via. Referring to Figures 3 and 9, the orthographic projection of the third via V3 on the substrate 101 at least partially overlaps with the orthographic projection of the second via V2 on the substrate 101. This helps to reduce the area occupied by the third via V3 and the second via V2, thereby providing more space for the pixel electrode 41 and the third conductive pattern 31, which is beneficial to increasing the capacitance value of the second capacitor formed between the pixel electrode 41 and the third conductive pattern 31.

[0074] In some embodiments, as shown in FIG10, the orthogonal projection of the third conductive pattern 31 on the substrate 101 can cover the orthogonal projection of the semiconductor pattern 51 on the substrate 101. In this way, the third conductive pattern 31 can form a shielding effect on the semiconductor pattern 51, reducing the risk of leakage current in the thin film transistor T.

[0075] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising: Substrate; A first conductive layer is disposed on one side of the substrate and includes a first signal line and a first conductive pattern, wherein the first conductive pattern is electrically insulated from the first signal line. A semiconductor layer, disposed on the side of the first conductive layer away from the substrate, includes a plurality of semiconductor patterns; A second conductive layer is disposed on the side of the semiconductor layer away from the substrate, and includes a second signal line and a second conductive pattern. The orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first conductive pattern on the substrate. A third conductive layer is disposed on the side of the second conductive layer away from the substrate, and includes a third conductive pattern; A fourth conductive layer is disposed on the side of the third conductive layer away from the substrate, and includes a pixel electrode, wherein the orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the third conductive pattern on the substrate. The array substrate further includes a thin-film transistor, which includes: a gate located in the first conductive layer and electrically connected to the first signal line; a semiconductor pattern; and a first electrode and a second electrode located in the second conductive layer; the first electrode is electrically connected to the second signal line, and the second electrode is electrically connected to the second conductive pattern; the first conductive pattern is electrically insulated from the second electrode and forms a first capacitor with the second conductive pattern; the pixel electrode is electrically connected to the second conductive pattern, and a second capacitor is formed between the third conductive pattern and the pixel electrode.

2. The array substrate according to claim 1, further comprising: A gate insulating layer is disposed between the first conductive layer and the semiconductor layer, and the gate insulating layer covers the first conductive pattern.

3. The array substrate according to claim 1 or 2, wherein, The first conductive pattern and the second conductive pattern have the same shape as the orthographic projection on the substrate.

4. The array substrate according to any one of claims 1 to 3, wherein, The first conductive layer further includes a first connecting line, which is located between two adjacent first conductive patterns along a first direction and is connected to the two first conductive patterns; the first direction is the extension direction of the first signal line.

5. The array substrate according to claim 4, wherein, The third conductive layer further includes a second connecting line, which is located between two adjacent third conductive patterns along a second direction and connected to the two first conductive patterns; the second direction is the extension direction of the second signal line and intersects with the first direction.

6. The array substrate according to claim 5, wherein, The array substrate includes a display area and a peripheral area surrounding the display area; The first conductive pattern and the third conductive pattern are configured to transmit the same voltage signal, and the first conductive pattern and the third conductive pattern are electrically connected in the peripheral region.

7. The array substrate according to any one of claims 1 to 6, wherein, The third conductive layer further includes a transition block, through which the pixel electrode is electrically connected to the second conductive pattern.

8. The array substrate according to claim 7, further comprising: A second insulating layer is disposed between the second conductive layer and the third conductive layer; The first via penetrates the second insulating layer and exposes the second conductive pattern; A planarization layer is disposed between the second insulating layer and the third conductive layer; A second via penetrates the planarization layer and exposes at least a portion of the first via; A third insulating layer is disposed between the third conductive layer and the fourth conductive layer; A third via penetrates the third insulating layer and exposes at least a portion of the adapter block; The adapter block is electrically connected to the second conductive pattern through the second via and the first via, and the pixel electrode is electrically connected to the adapter block through the third via.

9. The array substrate according to claim 8, wherein, The orthographic projection of the second via on the substrate covers the orthographic projection of the first via on the substrate; The orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the second via on the substrate.

10. The array substrate according to any one of claims 1 to 9, wherein, The orthographic projection of the third conductive pattern on the substrate covers the orthographic projection of the semiconductor pattern on the substrate.

11. The array substrate according to any one of claims 1 to 9, wherein, The material of at least two of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer includes a metallic conductive material.

12. The array substrate according to claim 11, wherein, The materials of the first conductive layer, the second conductive layer, and the third conductive layer all include metallic conductive materials, and the material of the fourth conductive layer includes a transparent conductive material.

13. The array substrate according to claim 12, wherein, The thickness of the first conductive layer is And / or, The thickness of the second conductive layer is And / or, The thickness of the third conductive layer is And / or, The thickness of the fourth conductive layer is 14. A display panel, comprising: The array substrate as described in any one of claims 1 to 13.

Images