Display apparatus and electronic device

Abstract

The present application provides a display apparatus, comprising multiple stages of gate driving circuits. Each gate driving circuit comprises a first stage transmission circuit and a first output circuit. The first stage transmission circuit comprises a first pull-down control node G, a fourth capacitor, and a ninth transistor. One electrode plate of the fourth capacitor is electrically connected to the first pull-down control node G, and the other electrode plate thereof is electrically connected to a first stage transmission signal output end. The first output circuit comprises a twenty-first transistor; and a gate of the twenty-first transistor is electrically connected to the first pull-down control node G. The present application can reduce the voltage of a portion of a scan signal that assumes a stepped waveform.

Description

Display devices and electronic equipment Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and electronic device. Background Technology

[0002] To extend the lifespan of OLED display panels, frequency division display technology has been applied. However, OLED display panels incorporating frequency division display technology encounter the following technical problems:

[0003] First, the waveform of the scan signal output by the gate drive circuit of the OLED display panel will have a step-like shape. During the continuous illumination of the OLED display panel, the threshold voltage Vth of the transistor in the gate drive circuit of the OLED display panel will shift negatively, causing the voltage of the portion of the output scan signal that appears as a step-like waveform to rise, thereby reducing the brightness of the OLED display panel.

[0004] Secondly, the circuit stability of existing OLED display panels is lower when the frequency division display function is enabled compared to when the frequency division display function is not enabled, which makes the reliability of the frequency division display function of OLED display panels lower. Invention Overview

[0005] The purpose of this application is to provide a display device and electronic device to improve the circuit stability of the display device when the frequency division display function is enabled.

[0006] Embodiments of this application provide a display device, including: a display panel, the display panel including multiple rows of pixels and multiple levels of gate driving circuits, wherein a first-level gate driving circuit includes: a first-level transmission circuit, the first-level transmission circuit including a first pull-down control circuit and a first pull-down circuit, the first pull-down control circuit including a first pull-down control node G and a fourth capacitor, the first pull-down circuit including a ninth transistor, the gate of the ninth transistor being electrically connected to the first pull-down control node G, the source of the ninth transistor being electrically connected to a low-level signal input terminal, the drain of the ninth transistor being electrically connected to a first-level transmission signal output terminal, one plate of the fourth capacitor being electrically connected to the first pull-down control node G, and the other plate of the fourth capacitor being electrically connected to the first-level transmission signal output terminal; and a first output circuit, the first output circuit including a second pull-down circuit, the second pull-down circuit including a twenty-first transistor, the gate of the twenty-first transistor being electrically connected to the first pull-down control node G, the source of the twenty-first transistor being electrically connected to the low-level signal input terminal, and the drain of the twenty-first transistor being electrically connected to a first scan signal output terminal.

[0007] Embodiments of this application also provide an electronic device, including the display device described above. Beneficial effects

[0008] The display device provided in the embodiments of this application, by setting a first pull-down control circuit and a first pull-down circuit in the first stage transmission circuit of the gate driving circuit, wherein the first pull-down control circuit includes a fourth capacitor and the first pull-down circuit includes a ninth transistor, and one plate of the fourth capacitor is electrically connected to the first pull-down control node G, and the other plate is electrically connected to the first stage transmission signal output terminal, can effectively reduce the voltage of the portion of the scan signal output by the gate driving circuit that presents a stepped waveform, thereby improving the display effect of the display device. Specifically, when the signal at the first stage transmission signal output terminal switches from a high potential to a low potential, since one plate of the fourth capacitor is electrically connected to the first pull-down control node G and the other plate is electrically connected to the first stage transmission signal output terminal, the decrease in the signal potential at the first stage transmission signal output terminal will drive the potential of the first pull-down control node G to decrease through the coupling effect of the fourth capacitor. The decrease in the potential of the first pull-down control node G will affect the conduction state of the twenty-first transistor of the second pull-down circuit in the first output circuit, thereby reducing the potential of the scan signal output by the first scan signal output terminal through the twenty-first transistor, and finally achieving the technical effect of reducing the voltage of the portion of the scan signal that presents a stepped waveform.

[0009] Furthermore, the display device provided in the embodiments of this application also improves the output capability of the first-stage transmission circuit by reasonably setting the size parameters of the ninth transistor in the first-stage transmission circuit. Specifically, by setting the channel width of the ninth transistor to be greater than the channel width of the other transistors in the first-stage transmission circuit, and setting the channel width of the ninth transistor to be greater than or equal to 20 micrometers, the stage transmission signal output from the first-stage transmission signal output terminal has sufficient driving capability, thereby avoiding the problem of abnormal widening of the waveform of the stage transmission signal output from the first-stage transmission signal output terminal. The technical solution provided in the embodiments of this application not only ensures the stability of the waveform of the stage transmission signal output from the first-stage transmission signal output terminal, but also further improves the circuit stability when the display device enables the frequency division display function. Attached Figure Description

[0010] Figure 1 is a schematic diagram of a display device provided in an embodiment of this application.

[0011] Figure 2 is a circuit diagram of pixels in a display device provided in an embodiment of this application.

[0012] Figure 3 is a waveform diagram of the scanning signal and the light emission control signal input to the pixel in the display device provided in the embodiment of this application.

[0013] Figure 4 is a schematic diagram showing the effect of the voltage of the portion of the scanning signal that appears as a stepped waveform in the display device provided in the embodiment of this application on the current flowing through the light-emitting device.

[0014] Figure 5 is a circuit diagram of the gate driving circuit in the display device provided in an embodiment of this application.

[0015] Figure 6 is a schematic diagram of the waveforms of the relevant nodes of the gate drive circuit and the signal output terminal of the scan signal in the display device provided in the embodiment of this application. Embodiments of the present invention

[0016] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0017] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple” and similar words mean two or more, unless otherwise expressly specified.

[0018] As shown in Figure 1, the display device provided in the embodiments of this application includes a display panel, a timing controller, a source drive circuit, and a power management chip. The display panel is an organic light-emitting diode (OLED) display panel.

[0019] The display panel includes a display area and a non-display area. The display area has an array of m×n pixels (PX), where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange driving circuits and various signal lines. The display panel also includes multiple scan lines (SCAN), multiple data lines (DATA), and multi-stage gate driving circuits. The multiple scan lines (SCAN) extend along a first direction and are arranged along a second direction, and the multiple data lines (DATA) extend along the second direction and are arranged along the first direction, with the first direction perpendicular to the second direction. The gate driving circuit is located in the non-display area and is electrically connected to the scan lines (SCAN). The source driving circuit is electrically connected to the multiple data lines (DATA) via a flexible circuit board. The timing controller is electrically connected to the gate driving circuit and the source driving circuit.

[0020] The display panel includes an organic light-emitting diode (OLED) array substrate and an encapsulation layer. The OLED array substrate includes a substrate, a buffer layer disposed on the substrate, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, a first metal layer disposed on the gate insulating layer, an interlayer insulating layer disposed on the first metal layer, a second metal layer disposed on the interlayer insulating layer, a planarization layer disposed on the second metal layer, a first electrode layer disposed on the planarization layer, a pixel defining layer disposed on the first electrode layer, an organic light-emitting layer disposed within an opening area defined by the pixel defining layer, and a second electrode layer disposed on the organic light-emitting layer. The first metal layer includes scan lines (SCAN), a gate electrode, etc. The second metal layer includes data lines (DATA), a source electrode, a drain electrode, etc. The encapsulation layer is sealed to the OLED array substrate to prevent moisture and oxygen from penetrating the organic light-emitting layer.

[0021] Each pixel (PX) includes a pixel driving circuit and an organic light-emitting diode (OLED). The pixel driving circuit includes at least two thin-film transistors (TFTs) and a storage capacitor. One TFT acts as a switching transistor, with its gate electrically connected to the corresponding scan line and its source electrically connected to the corresponding data line. The other TFT acts as a driving transistor, with its gate electrically connected to the drain of the switching transistor, its source electrically connected to a first power supply voltage line, and its drain electrically connected to the anode of the OLED. One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end is electrically connected to either the source or drain of the driving transistor. The cathode of the OLED is electrically connected to a second power supply voltage line. When the scan line outputs a high-potential scan signal, the switching transistor is turned on, and the data signal on the data line is written to the gate of the driving transistor and the storage capacitor through the switching transistor. When the scan line outputs a low-potential scan signal, the switching transistor is turned off, the storage capacitor maintains the voltage at the gate of the driving transistor, and the driving transistor generates a driving current corresponding to the gate voltage, driving the OLED to emit light.

[0022] Each gate drive circuit is electrically connected to one scan line. Under the control of the timing controller, the gate drive circuit sequentially outputs scan signals, scanning each row of pixels PX in the display area line by line. Under the control of the timing controller, the source drive circuit generates and outputs data signals based on the image data. The timing controller receives and processes externally input image data and timing signals, generates control signals, and transmits the image data to the source drive circuit. The power management chip provides operating voltages to various parts of the display device, including providing a second power supply voltage VSS for the cathode of the organic light-emitting diode OLED, a first power supply voltage VDD for the first power supply voltage line, and gate drive voltages VGH / VGL for the gate drive circuit, etc.

[0023] The display device provided in the embodiments of this application includes a display panel, which includes multiple rows of pixels. Each pixel includes a pixel driving circuit and an OLED light-emitting device, and the pixel driving circuit is electrically connected to the OLED light-emitting device.

[0024] As shown in Figure 2, the pixel driving circuit includes thin-film transistors Tp1, Tp2, Tp3, Tp4, Tp5, Tp6, Tp7, Tp8, capacitor Cst, and capacitor Cboost.

[0025] Among them, thin-film transistors Tp1, Tp2, Tp5, Tp6, Tp7, and Tp8 are P-type thin-film transistors, while thin-film transistors Tp3 and Tp4 are N-type thin-film transistors.

[0026] The gate of thin-film transistor Tp1 is electrically connected to node Q, the source of thin-film transistor Tp1 is electrically connected to node P, and the drain of thin-film transistor Tp1 is electrically connected to node R. The gate of thin-film transistor Tp2 is electrically connected to the second scan signal input terminal Pscan1, the source of thin-film transistor Tp2 is electrically connected to the data signal input terminal Data, and the drain of thin-film transistor Tp2 is electrically connected to node P. The gate of thin-film transistor Tp3 is electrically connected to the first scan signal input terminal Nscan1, the source of thin-film transistor Tp3 is electrically connected to node R, and the drain of thin-film transistor Tp3 is electrically connected to node Q. The gate of thin-film transistor Tp4 is electrically connected to the third scan signal input terminal Nscan2, the source of thin-film transistor Tp4 is electrically connected to the first reset signal input terminal Vi1, and the drain of thin-film transistor Tp4 is electrically connected to node Q. The gate of thin-film transistor Tp5 is electrically connected to the first light-emitting control signal input terminal EM, the source of thin-film transistor Tp5 is electrically connected to the first power supply signal input terminal VDD, and the drain of thin-film transistor Tp5 is electrically connected to node P. The gate of thin-film transistor Tp6 is electrically connected to the first light-emitting control signal input terminal EM, the source of thin-film transistor Tp6 is electrically connected to node R, and the drain of thin-film transistor Tp6 is electrically connected to node S. The gate of thin-film transistor Tp7 is electrically connected to the fourth scan signal input terminal Pscan2, the source of thin-film transistor Tp7 is electrically connected to the second reset signal input terminal Vi2, and the drain of thin-film transistor Tp7 is electrically connected to node S. The gate of thin-film transistor Tp8 is electrically connected to the fourth scan signal input terminal Pscan2, the source of thin-film transistor Tp8 is electrically connected to the third reset signal input terminal Vi3, and the drain of thin-film transistor Tp8 is electrically connected to node R. One plate of capacitor Cst is electrically connected to node Q, and the other plate of capacitor Cst is electrically connected to the first power supply signal input terminal VDD. One plate of capacitor Cboost is electrically connected to node Q, and the other plate of capacitor Cboost is electrically connected to the second scan signal input terminal Pscan1. The anode of the light-emitting device OLED is electrically connected to node S, and the cathode of the light-emitting device OLED is electrically connected to the second power signal input terminal VSS.

[0027] The signal transmitted at the first scan signal input terminal Nscan1 is used to control the on and off states of the thin-film transistor Tp3. When the signal transmitted at the first scan signal input terminal Nscan1 is at a high potential, the thin-film transistor Tp3 is on; when the signal transmitted at the first scan signal input terminal Nscan1 is at a low potential, the thin-film transistor Tp3 is off. When the signal transmitted at the first scan signal input terminal Nscan1 transitions from a high potential to a low potential, after the data signal writing phase, the waveform of the signal transmitted at the first scan signal input terminal Nscan1 will exhibit a stepped shape, as shown in Figure 3. When the voltage of a portion of the STP in this stepped waveform is too high, it will cause the thin-film transistor Tp3 to fail to turn off completely.

[0028] As shown in Figure 4, during the continuous screen illumination process of the display device, the threshold voltage of the transistor in the gate drive circuit shifts negatively, and the voltage of the part of the STP that presents a stepped waveform in the scanning signal continues to rise, which makes it impossible for the third thin film transistor Tp3 to be completely turned off. This causes the threshold voltage of the first thin film transistor Tp1 to shift, the current flowing through the light-emitting device OLED to change, the brightness of the light-emitting device OLED to decrease, and ultimately the lifespan of the display panel to be reduced.

[0029] The display panel also includes cascaded multi-stage gate driving circuits. Each stage of the gate driving circuit includes a first gate driving sub-circuit and a second gate driving sub-circuit. The first gate driving sub-circuit outputs a first scan signal Nscan1 (Nout2), and the second gate driving sub-circuit outputs a second scan signal Pscan1. As shown in Figure 5, the first gate driving sub-circuit includes a first stage transmission circuit 501 and a first output circuit 502. The first stage transmission circuit 501 and the first output circuit 502 are electrically connected. The first output circuit 502 outputs the first scan signal Nscan1 to a row of pixels, and the first stage transmission circuit 501 outputs a stage transmission signal Nout1 to the first gate driving sub-circuits of other stages of the gate driving circuit. The second gate driving sub-circuit includes a second stage transmission circuit and a second output circuit. The second stage transmission circuit and the second output circuit are electrically connected. The second output circuit outputs the second scan signal Pscan1 to the row of pixels, and the second stage transmission circuit outputs a stage transmission signal to the second gate driving sub-circuits of other stages of the gate driving circuit. The technical solution of the embodiments of this application mainly improves the first gate driving sub-circuit.

[0030] The first-stage transmission circuit 501 includes a first transistor Ts1, a second transistor Ts2, a third transistor Ts3, a fourth transistor Ts4, a fifth transistor Ts5, a sixth transistor Ts6, a seventh transistor Ts7, an eighth transistor Ts8, a ninth transistor Ts9, a tenth transistor Ts10, an eleventh transistor Ts11, a twelfth transistor Ts12, a thirteenth transistor Ts13, a fourteenth transistor Ts14, a fifteenth transistor Ts15, a sixteenth transistor Ts16, a seventeenth transistor Ts17, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4.

[0031] The gate of the first transistor Ts1 is electrically connected to node C, and its source is electrically connected to the high-level signal input terminal VGH. The gate of the second transistor Ts2 is electrically connected to node E, its source is electrically connected to the first clock signal input terminal CK, and its drain is electrically connected to the drain of the first transistor Ts1. The gate of the third transistor Ts3 is electrically connected to the second clock signal input terminal XCK, its source is electrically connected to the stage signal input terminal Nin, and its drain is electrically connected to node D. The gate of the fourth transistor Ts4 is electrically connected to the second clock signal input terminal XCK, its source is electrically connected to the low-level signal input terminal VGL, and its drain is electrically connected to node C. The gate of the fifth transistor Ts5 is electrically connected to node D, its source is electrically connected to the second clock signal input terminal XCK, and its drain is electrically connected to node C. The gate of the sixth transistor Ts6 is electrically connected to node B, the source of the sixth transistor Ts6 is electrically connected to the first clock signal input terminal CK, and the drain of the sixth transistor Ts6 is electrically connected to node A. The gate of the seventh transistor Ts7 is electrically connected to the first clock signal input terminal CK, and the source of the seventh transistor Ts7 is electrically connected to node A. The gate of the eighth transistor Ts8 is electrically connected to node D, the source of the eighth transistor Ts8 is electrically connected to the high-level signal input terminal VGH, and the drain of the eighth transistor Ts8 is electrically connected to node F. The gate of the ninth transistor Ts9 is electrically connected to the first pull-down control node G, the source of the ninth transistor Ts9 is electrically connected to the low-level signal input terminal VGL, and the drain of the ninth transistor Ts9 is electrically connected to the first-stage signal output terminal Nout1. The gate of the tenth transistor Ts10 is electrically connected to node F, the source of the tenth transistor Ts10 is electrically connected to the high-level signal input terminal VGH, and the drain of the tenth transistor Ts10 is electrically connected to the first-stage signal output terminal Nout1. The gate of the eleventh transistor Ts11 is electrically connected to the low-level signal input terminal VGL, the source of the eleventh transistor Ts11 is electrically connected to node C, and the drain of the eleventh transistor Ts11 is electrically connected to node B. The gate of the twelfth transistor Ts12 is electrically connected to the low-level signal input terminal VGL, the source of the twelfth transistor Ts12 is electrically connected to node D, and the drain of the twelfth transistor Ts12 is electrically connected to the first pull-down control node G. The gate of the thirteenth transistor Ts13 is electrically connected to the first control signal input terminal CTRL1, the source of the thirteenth transistor Ts13 is electrically connected to the high-level signal input terminal VGH, and the drain of the thirteenth transistor Ts13 is electrically connected to node D. The gate of the fourteenth transistor Ts14 is electrically connected to the second clock signal input terminal XCK, and the source of the fourteenth transistor Ts14 is electrically connected to the cascade signal input terminal Nin.The gate of the fifteenth transistor Ts15 is electrically connected to the low-level signal input terminal VGL. The source of the fifteenth transistor Ts15 is electrically connected to the drain of the fourteenth transistor Ts14. The drain of the fifteenth transistor Ts15 is electrically connected to node E. The gate of the sixteenth transistor Ts16 is electrically connected to node E. The source of the sixteenth transistor Ts16 is electrically connected to node E. The drain of the sixteenth transistor Ts16 is electrically connected to the first pull-down control node G. The gate of the seventeenth transistor Ts17 is electrically connected to the second control signal input terminal CTRL2. The source of the seventeenth transistor Ts17 is electrically connected to the drain of the seventh transistor Ts7. The drain of the seventeenth transistor Ts17 is electrically connected to node F. One plate of the first capacitor C1 is electrically connected to node E. The other plate of the first capacitor C1 is electrically connected to the drain of the first transistor Ts1. One plate of the second capacitor C2 is electrically connected to node A. The other plate of the second capacitor C2 is electrically connected to node B. One plate of the third capacitor C3 is electrically connected to node F, and the other plate of the third capacitor C3 is electrically connected to the high-level signal input terminal VGH. One plate of the fourth capacitor C4 is electrically connected to the first pull-down control node G, and the other plate of the fourth capacitor C4 is electrically connected to the first-stage signal output terminal Nout1.

[0032] The first output circuit 502 includes an eighteenth transistor Ts18, a nineteenth transistor Ts19, a twentieth transistor Ts20, a twenty-first transistor Ts21, a twenty-second transistor Ts22, a fifth capacitor C5, and a sixth capacitor C6.

[0033] The gate of the eighteenth transistor Ts18 is electrically connected to node I, the source of the eighteenth transistor Ts18 is electrically connected to node F, and the drain of the eighteenth transistor Ts18 is electrically connected to node H. The gate of the nineteenth transistor Ts19 is electrically connected to node D, the source of the nineteenth transistor Ts19 is electrically connected to the high-level signal input terminal VGH, and the drain of the nineteenth transistor Ts19 is electrically connected to node H. The gate of the twentieth transistor Ts20 is electrically connected to node D, the source of the twentieth transistor Ts20 is electrically connected to the first control signal input terminal CTRL1, and the drain of the twentieth transistor Ts20 is electrically connected to the gate of the eighteenth transistor Ts18. The gate of the twenty-first transistor Ts21 is electrically connected to the first pull-down control node G, the source of the twenty-first transistor Ts21 is electrically connected to the low-level signal input terminal VGL, and the drain of the twenty-first transistor Ts21 is electrically connected to the first scan signal output terminal Nout2. The gate of the 22nd transistor Ts22 is electrically connected to node H, the source of the 22nd transistor Ts22 is electrically connected to the high-level signal input terminal VGH, and the drain of the 22nd transistor Ts22 is electrically connected to the first scan signal output terminal Nout2. One plate of the fifth capacitor C5 is electrically connected to node H, and the other plate of the fifth capacitor C5 is electrically connected to the high-level signal input terminal VGH. One plate of the sixth capacitor C6 is electrically connected to the high-level signal input terminal VGH, and the other plate of the sixth capacitor C6 is electrically connected to the gate of the 18th transistor Ts18.

[0034] In this embodiment, the first transistor Ts1 to the twenty-second transistor Ts22 are all P-type thin-film transistors.

[0035] By setting a fourth capacitor C4 between the first pull-down control node G and the first stage signal output terminal Nout1, when the signal of the first stage signal output terminal Nout1 switches from a high potential to a low potential, the fourth capacitor C4 can pull down the potential of the first pull-down control node G, thereby reducing the voltage of the STP portion of the output scan signal that presents a stepped waveform. This ensures the stability of the waveform of the stage signal output by the first stage signal output terminal Nout1 and improves the circuit stability when the display device enables the frequency division display function.

[0036] Figure 6 illustrates the relationship between the waveforms of the signals of node E and the first pull-down control node G in the first-stage transmission circuit 501 of the embodiment of this application and the waveforms of the signals of the corresponding nodes in the comparative example. The solid lines represent the waveforms of the signals of node E and the first pull-down control node G in the first-stage transmission circuit 501 of the embodiment of this application, while the dashed lines represent the waveforms of the signals of the corresponding nodes in the comparative example.

[0037] As can be seen from Figure 6, in the technical solution provided by the embodiments of this application, the rising edges of the waveforms of the signals of nodes E and the first pull-down control node G in the first-stage transmission circuit 501 are in the same time as the rising edges of the waveforms of the corresponding nodes in the comparative example. However, in the technical solution provided by the embodiments of this application, the falling edges of the waveforms of the signals of nodes E and the first pull-down control node G in the first-stage transmission circuit 501 are in advance compared to the falling edges of the waveforms of the corresponding nodes in the comparative example. The pulse width of the waveforms of the signals of nodes E and the first pull-down control node G in the first-stage transmission circuit 501 in the technical solution provided by the embodiments of this application is smaller than the pulse width of the waveforms of the corresponding nodes in the comparative example, thus avoiding the phenomenon of abnormal waveform widening.

[0038] Figure 6 also illustrates the first scan signal output terminal Nout2 of the third-stage gate drive circuit. <3> The first scan signal output terminal Nout2 of the 21st stage gate drive circuit <21> The first scan signal output terminal Nout2 of the 61st stage gate drive circuit <61> The waveform of the output scan signal is related to the waveform of the corresponding level scan signal in the comparative example. The solid line represents the first scan signal output terminal Nout2 of the third-stage gate drive circuit in the technical solution provided in the embodiments of this application. <3> The first scan signal output terminal Nout2 of the 21st stage gate drive circuit <21> The first scan signal output terminal Nout2 of the 61st stage gate drive circuit <61> The waveform of the output scan signal, with the dashed line representing the waveform of the corresponding level of the scan signal in the comparative example.

[0039] As shown in Figure 6, the waveforms of the scan signals output by the first scan signal output terminals of the 3rd, 21st, and 61st stage gate drive circuits in the embodiments of this application all have the following characteristics: the rising edge of the waveform is in time the same as the rising edge of the corresponding stage scan signal waveform in the comparative example, but the falling edge of the waveform is in time earlier than the falling edge of the corresponding stage scan signal waveform in the comparative example. As the number of stages increases (from the 3rd stage to the 21st stage and then to the 61st stage), the pulse width of the scan signal waveform output by each stage gate drive circuit in the embodiments of this application remains basically consistent (the difference in pulse width between any two stages of the gate drive circuit output is less than or equal to 5%), while the pulse width of the scan signal waveform output by each stage gate drive circuit in the comparative example gradually increases with the increase of the number of stages. Specifically, the pulse width difference of level 21 (i.e., the absolute value of the difference between the pulse width of the technical solution of this application and the pulse width of the comparative example) is greater than the pulse width difference of level 3, and the pulse width difference of level 61 is greater than the pulse width difference of level 21.

[0040] As can be seen from the waveform comparison above, the technical solution provided by the embodiments of this application, by setting a fourth capacitor C4 in the first stage transmission circuit, can effectively control the pulse width of the scanning signal output by each stage of the gate driving circuit, avoiding the problem in the comparative example where the pulse width of the scanning signal gradually increases with the number of stages. This technical solution not only ensures that the scanning signal output by each stage of the gate driving circuit has a stable pulse width, but also avoids signal interference between adjacent stages due to excessively large pulse widths of the scanning signal, thereby improving the operational reliability of the gate driving circuit and thus improving the display quality of the display device.

[0041]

[0042] Table 1

[0043] Table 1 compares the operating states of different first gate drive sub-circuits with varying threshold voltage offsets. The horizontal axis of the table represents the threshold voltage offset of the ninth transistor Ts9, ranging from 0 volts to -1.6 volts, with values ​​incremented in 0.2-volt increments. The vertical axis represents the operating states of different first gate drive sub-circuits with varying channel widths W of the ninth transistor Ts9. Specifically, 22T6C represents a first gate drive sub-circuit with 22 transistors and 6 capacitors.

[0044] As shown in Table 1, for the first gate drive sub-circuit of the 22T6C structure, when the channel width W of the ninth transistor Ts9 is 10 micrometers, the gate drive circuit cannot function properly when the threshold voltage offset of the ninth transistor Ts9 is -1.2 volts or less; when the channel width W of the ninth transistor Ts9 increases to 20 micrometers, the gate drive circuit only fails to function properly when the threshold voltage offset of the ninth transistor Ts9 is -1.6 volts; when the channel width W of the ninth transistor Ts9 increases to 40 micrometers, the gate drive circuit can still function properly even when the threshold voltage offset of the ninth transistor Ts9 is -1.6 volts. For the first gate drive sub-circuit of the comparative 22T5C structure, when the channel width W of the ninth transistor Ts9 is 10 micrometers, the gate drive circuit cannot function properly when the threshold voltage offset of the ninth transistor Ts9 is -1.6 volts. By comparison, it can be seen that the first gate driving sub-circuit of the 22T6C structure provided in the embodiments of this application has better working reliability than the first gate driving sub-circuit of the 22T5C structure in the comparative example when the channel width W of the ninth transistor Ts9 is 40 micrometers. This shows that the first gate driving sub-circuit of the 22T6C structure provided in the embodiments of this application has better circuit stability.

[0045] The display device provided in the embodiments of this application can be applied to the field of flexible organic light-emitting diode display technology, and is particularly suitable for display panel products with frequency division display function.

[0046] Embodiments of this application provide a display device, including a display panel. The display panel includes multiple rows of pixels and cascaded multi-level gate driving circuits, wherein a first-level gate driving circuit includes:

[0047] The first-stage transmission circuit 501 includes a first pull-down control circuit and a first pull-down circuit. The first pull-down control circuit includes a first pull-down control node G and a fourth capacitor C4. The first pull-down circuit includes a ninth transistor Ts9. The gate of the ninth transistor Ts9 is electrically connected to the first pull-down control node G, the source of the ninth transistor Ts9 is electrically connected to the low-level signal input terminal VGL, and the drain of the ninth transistor Ts9 is electrically connected to the first-stage transmission signal output terminal Nout1. One plate of the fourth capacitor C4 is electrically connected to the first pull-down control node G, and the other plate of the fourth capacitor C4 is electrically connected to the first-stage transmission signal output terminal Nout1. The first-stage transmission signal output terminal Nout1 is used for output stage transmission signals.

[0048] The gate drive circuit also includes a first output circuit 502, which includes a second pull-down circuit. The second pull-down circuit includes a twenty-first transistor Ts21. The gate of the twenty-first transistor Ts21 is electrically connected to the first pull-down control node G, the source of the twenty-first transistor Ts21 is electrically connected to the low-level signal input terminal VGL, and the drain of the twenty-first transistor Ts21 is electrically connected to the first scan signal output terminal Nout2.

[0049] The connections between the transistors and capacitors in the first-stage transmission circuit 501 constitute the first-stage transmission circuit 501 used to generate the transmission signal. Through the placement of the fourth capacitor C4, the first-stage transmission circuit 501 can influence the potential of the first pull-down control node G through capacitive coupling when the potential of the signal at the first-stage transmission signal output terminal Nout1 changes, thereby controlling the potential of the first scan signal Nscan1.

[0050] The fourth capacitor C4 is used to pull down the potential of the first pull-down control node G during the process of the signal at the first stage signal output terminal Nout1 switching from a high potential to a low potential.

[0051] When the signal at the first-stage signal output terminal Nout1 switches from a high potential to a low potential, since one plate of the fourth capacitor C4 is electrically connected to the first pull-down control node G and the other plate is electrically connected to the first-stage signal output terminal Nout1, the decrease in the potential of the signal at the first-stage signal output terminal Nout1 will cause the potential of the first pull-down control node G to decrease through the coupling effect of the fourth capacitor C4. The decrease in the potential of the first pull-down control node G can affect the conduction state of the transistor electrically connected to the first pull-down control node G, thereby affecting the potential of the scan signal output at the first scan signal output terminal Nout2, ultimately achieving the technical effect of reducing the voltage of the STP portion of the scan signal that presents a stepped waveform.

[0052] The channel width of the ninth transistor Ts9 is greater than the channel width of the other transistors in the first stage of the transistor circuit.

[0053] Specifically, the ninth transistor Ts9 is used to pull the potential of the first-stage signal output terminal Nout1 to a low potential under the control of the potential of the first pull-down control node G. When the channel width of the ninth transistor Ts9 is small, the waveform of the signal at the first-stage signal output terminal Nout1 will exhibit abnormal widening, which will affect the normal operation of the gate drive circuit. Therefore, the channel width of the ninth transistor Ts9 needs to be set within an appropriate range.

[0054] The channel width of the ninth transistor Ts9 is greater than or equal to 20 micrometers. By setting the channel width of the ninth transistor Ts9 to be greater than or equal to 20 micrometers, it can be ensured that the stage transmission signal output from the first stage transmission signal output terminal Nout1 has sufficient driving capability, thereby avoiding the problem of abnormal widening of the waveform of the stage transmission signal output from the first stage transmission signal output terminal Nout1, and thus improving the working stability of the gate drive circuit.

[0055] The channel width of the ninth transistor Ts9 is in the range of 30 micrometers to 50 micrometers. Preferably, the channel width of the ninth transistor Ts9 can be set to 40 micrometers. With this setting, the gate drive circuit can still operate normally even when the threshold voltage of the transistor is negatively offset by -1.6 volts, thereby further improving the reliability of the gate drive circuit. In addition, the channel width of the ninth transistor can also be set to other values ​​in the range of 30 micrometers to 50 micrometers according to actual needs.

[0056] The first-stage transmission circuit 501 also includes a first transistor Ts1, a second transistor Ts2, a third transistor Ts3, a fourth transistor Ts4, a fifth transistor Ts5, a sixth transistor Ts6, a seventh transistor Ts7, an eighth transistor Ts8, a tenth transistor Ts10, an eleventh transistor Ts11, a twelfth transistor Ts12, a thirteenth transistor Ts13, a fourteenth transistor Ts14, a fifteenth transistor Ts15, a sixteenth transistor Ts16, a seventeenth transistor Ts17, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0057] The gate of the first transistor Ts1 is electrically connected to node C, and the source of the first transistor Ts1 is electrically connected to the high-level signal input terminal.

[0058] The gate of the second transistor Ts2 is electrically connected to node E, the source of the second transistor Ts2 is electrically connected to the first clock signal input terminal CK, and the drain of the second transistor Ts2 is electrically connected to the drain of the first transistor Ts2.

[0059] The gate of the third transistor Ts3 is electrically connected to the second clock signal input terminal XCK, the source of the third transistor Ts3 is electrically connected to the stage signal input terminal Nin, and the drain of the third transistor Ts3 is electrically connected to node D.

[0060] The gate of the fourth transistor Ts4 is electrically connected to the second clock signal input terminal XCK, the source of the fourth transistor Ts4 is electrically connected to the low-level signal input terminal VGL, and the drain of the fourth transistor Ts4 is electrically connected to node C.

[0061] The gate of the fifth transistor Ts5 is electrically connected to node D, the source of the fifth transistor Ts5 is electrically connected to the second clock signal input terminal XCK, and the drain of the fifth transistor Ts5 is electrically connected to node C.

[0062] The gate of the sixth transistor Ts6 is electrically connected to node B, the source of the sixth transistor Ts6 is electrically connected to the first clock signal input terminal CK, and the drain of the sixth transistor Ts6 is electrically connected to node A.

[0063] The gate of the seventh transistor Ts7 is electrically connected to the first clock signal input terminal CK, and the source of the seventh transistor Ts7 is electrically connected to node A.

[0064] The gate of the eighth transistor Ts8 is electrically connected to node D, the source of the eighth transistor Ts8 is electrically connected to the high-level signal input terminal VGH, and the drain of the eighth transistor Ts8 is electrically connected to node F.

[0065] The gate of the tenth transistor Ts10 is electrically connected to node F, the source of the tenth transistor Ts10 is electrically connected to the high-level signal input terminal VGH, and the drain of the tenth transistor Ts10 is electrically connected to the first-stage signal output terminal Nout1.

[0066] The gate of the eleventh transistor Ts11 is electrically connected to the low-level signal input terminal VGL, the source of the eleventh transistor Ts11 is electrically connected to node C, and the drain of the eleventh transistor Ts11 is electrically connected to node B.

[0067] The gate of the twelfth transistor Ts12 is electrically connected to the low-level signal input terminal VGL, the source of the twelfth transistor Ts12 is electrically connected to node D, and the drain of the twelfth transistor Ts12 is electrically connected to the first pull-down control node G.

[0068] The gate of the thirteenth transistor Ts13 is electrically connected to the first control signal input terminal CTRL1, the source of the thirteenth transistor Ts13 is electrically connected to the high-level signal input terminal VGH, and the drain of the thirteenth transistor Ts13 is electrically connected to node D.

[0069] The gate of the fourteenth transistor Ts14 is electrically connected to the second clock signal input terminal XCK, and the source of the fourteenth transistor Ts14 is electrically connected to the stage signal input terminal Nin.

[0070] The gate of the fifteenth transistor Ts15 is electrically connected to the low-level signal input terminal VGL, the source of the fifteenth transistor VGL is electrically connected to the drain of the fourteenth transistor Ts14, and the drain of the fifteenth transistor Ts15 is electrically connected to node E.

[0071] The gate of the sixteenth transistor Ts16 is electrically connected to node E, the source of the sixteenth transistor Ts16 is electrically connected to node E, and the drain of the sixteenth transistor Ts16 is electrically connected to the first pull-down control node G.

[0072] The gate of the seventeenth transistor Ts17 is electrically connected to the second control signal input terminal CTRL2, the source of the seventeenth transistor Ts17 is electrically connected to the drain of the seventh transistor Ts7, and the drain of the seventeenth transistor Ts17 is electrically connected to node F.

[0073] One plate of the first capacitor C1 is electrically connected to node E, and the other plate of the first capacitor C1 is electrically connected to the drain of the first transistor Ts1.

[0074] One plate of the second capacitor C2 is electrically connected to node A, and the other plate of the second capacitor C2 is electrically connected to node B.

[0075] One plate of the third capacitor C3 is electrically connected to node F, and the other plate of the third capacitor C3 is electrically connected to the high-level signal input terminal VGH.

[0076] The first output circuit 502 also includes the eighteenth transistor Ts18, the nineteenth transistor Ts19, the twentieth transistor Ts20, the twenty-second transistor Ts22, the fifth capacitor C5, and the sixth capacitor C6.

[0077] The gate of the eighteenth transistor Ts18 is electrically connected to node I, the source of the eighteenth transistor Ts18 is electrically connected to node F, and the drain of the eighteenth transistor Ts18 is electrically connected to node H.

[0078] The gate of the nineteenth transistor Ts19 is electrically connected to node D, the source of the nineteenth transistor Ts19 is electrically connected to the high-level signal input terminal VGH, and the drain of the nineteenth transistor Ts19 is electrically connected to node H.

[0079] The gate of the twentieth transistor Ts20 is electrically connected to node D, the source of the twentieth transistor Ts20 is electrically connected to the first control signal input terminal CTRL 1, and the drain of the twentieth transistor Ts20 is electrically connected to the gate of the eighteenth transistor Ts18.

[0080] The gate of the 22nd transistor Ts22 is electrically connected to node H, the source of the 22nd transistor Ts22 is electrically connected to the high-level signal input terminal VGH, and the drain of the 22nd transistor Ts22 is electrically connected to the first scan signal output terminal Nout2.

[0081] One plate of the fifth capacitor C5 is electrically connected to node H, and the other plate of the fifth capacitor C5 is electrically connected to the high-level signal input terminal VGH.

[0082] One plate of the sixth capacitor C6 is electrically connected to the high-level signal input terminal VGH, and the other plate of the sixth capacitor C6 is electrically connected to the gate of the eighteenth transistor Ts18.

[0083] The first output circuit 502 is used to reduce the potential of the scan signal output from the first scan signal output terminal Nout2 through the twenty-first transistor Ts21 under the control of the potential of the first pull-down control node G.

[0084] Specifically, when the potential of the first pull-down control node G decreases, the conduction capability of the twenty-first transistor 1Ts2 is enhanced, thereby more effectively pulling the potential of the first scan signal output terminal Nout2 down to a low potential. By controlling the potential of the first pull-down control node G through the fourth capacitor C4, the voltage of the step-shaped waveform portion of the scan signal output from the first scan signal output terminal Nout2 can be reduced, thereby improving the lifespan of the display panel.

[0085] Embodiments of this application also provide an electronic device, including the display device described above.

[0086] The display device provided in the embodiments of this application improves the display effect by setting a fourth capacitor C4 in the first stage transmission circuit 501 of the gate driving circuit, and electrically connecting one plate of the fourth capacitor C4 to the first pull-down control node G and the other plate to the first stage transmission signal output terminal Nout1. This effectively reduces the voltage of the step-shaped waveform portion of the scan signal output by the gate driving circuit, thereby improving the display effect of the display device. Specifically, when the signal of the first stage transmission signal output terminal Nout1 switches from a high potential to a low potential, since one plate of the fourth capacitor C4 is electrically connected to the first pull-down control node G and the other plate is electrically connected to the first stage transmission signal output terminal Nout1, the decrease in the signal potential of the first stage transmission signal output terminal Nout1 will drive the potential of the first pull-down control node G to decrease through the coupling effect of the fourth capacitor C4. The decrease in the potential of the first pull-down control node G will affect the conduction state of the transistor in the first output circuit 502 that is electrically connected to the first pull-down control node G, thereby affecting the potential of the scan signal output by the first scan signal output terminal Nout2, and ultimately achieving the technical effect of reducing the voltage of the part of STP that presents a stepped waveform in the scan signal.

[0087] Furthermore, the display device provided in the embodiments of this application also improves the output capability of the first-stage transmission circuit 501 by reasonably setting the size parameters of the transistors in the first-stage transmission circuit 501. Specifically, by setting the channel width of the ninth transistor Ts9 to be greater than or equal to 20 micrometers, the stage transmission signal output by the first-stage transmission signal output terminal Nout1 has sufficient driving capability, thereby avoiding the problem of abnormal widening of the waveform of the stage transmission signal output by the first-stage transmission signal output terminal Nout1. The technical solution provided in the embodiments of this application not only ensures the stability of the waveform of the stage transmission signal output by the first-stage transmission signal output terminal Nout1, but also further improves the circuit stability when the display device enables the frequency division display function.

[0088] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, comprising: The display panel includes multiple rows of pixels and multiple levels of gate driving circuits, wherein the first level of the gate driving circuit includes: The first-stage transmission circuit includes a first pull-down control circuit and a first pull-down circuit. The first pull-down control circuit includes a first pull-down control node G and a fourth capacitor. The first pull-down circuit includes a ninth transistor, the gate of which is electrically connected to the first pull-down control node G, the source of which is electrically connected to a low-level signal input terminal, and the drain of which is electrically connected to the first-stage transmission signal output terminal. One plate of the fourth capacitor is electrically connected to the first pull-down control node G, and the other plate of the fourth capacitor is electrically connected to the first-stage transmission signal output terminal. The first output circuit includes a second pull-down circuit, which includes a twenty-first transistor. The gate of the twenty-first transistor is electrically connected to the first pull-down control node G, the source of the twenty-first transistor is electrically connected to the low-level signal input terminal, and the drain of the twenty-first transistor is electrically connected to the first scan signal output terminal.

2. The display device according to claim 1, wherein The fourth capacitor is used to pull down the potential of the first pull-down control node G during the process of the signal at the first stage signal output terminal switching from a high potential to a low potential.

3. The display device according to claim 1, wherein, The channel width of the ninth transistor is greater than the channel width of the other transistors in the first stage transmission circuit.

4. The display device according to claim 1 or 3, wherein, The channel width of the ninth transistor is greater than or equal to 20 micrometers.

5. The display device of claim 4, wherein, The channel width of the ninth transistor is in the range of 30 micrometers to 50 micrometers.

6. The display device of claim 5, wherein, The channel width of the ninth transistor is 40 micrometers.

7. The display device according to claim 1, wherein The first-stage transmission circuit also includes: The first transistor has its gate electrically connected to node C and its source electrically connected to a high-level signal input terminal. The second transistor has its gate electrically connected to node E, its source electrically connected to the first clock signal input terminal, and its drain electrically connected to the drain of the first transistor. The third transistor has its gate electrically connected to the second clock signal input terminal, its source electrically connected to the stage signal input terminal, and its drain electrically connected to node D. The fourth transistor has its gate electrically connected to the second clock signal input terminal, its source electrically connected to the low-level signal input terminal, and its drain electrically connected to node C. The fifth transistor has its gate electrically connected to node D, its source electrically connected to the second clock signal input terminal, and its drain electrically connected to node C. The sixth transistor has its gate electrically connected to node B, its source electrically connected to the first clock signal input terminal, and its drain electrically connected to node A. The seventh transistor has its gate electrically connected to the first clock signal input terminal and its source electrically connected to node A. The eighth transistor has its gate electrically connected to node D, its source electrically connected to the high-level signal input terminal, and its drain electrically connected to node F. The tenth transistor has its gate electrically connected to node F, its source electrically connected to the high-level signal input terminal, and its drain electrically connected to the first-stage signal output terminal. The eleventh transistor has its gate electrically connected to the low-level signal input terminal, its source electrically connected to node C, and its drain electrically connected to node B. The twelfth transistor has its gate electrically connected to the low-level signal input terminal, its source electrically connected to the node D, and its drain electrically connected to the first pull-down control node G. The thirteenth transistor has its gate electrically connected to the first control signal input terminal, its source electrically connected to the high-level signal input terminal, and its drain electrically connected to node D. The fourteenth transistor, the gate of which is electrically connected to the second clock signal input terminal, and the source of which is electrically connected to the stage signal input terminal; The fifteenth transistor has its gate electrically connected to the low-level signal input terminal, its source electrically connected to the drain of the fourteenth transistor, and its drain electrically connected to node E. The sixteenth transistor has its gate electrically connected to node E, its source electrically connected to node E, and its drain electrically connected to the first pull-down control node G. The seventeenth transistor has its gate electrically connected to the second control signal input terminal, its source electrically connected to the drain of the seventh transistor, and its drain electrically connected to the node F. A first capacitor, one plate of which is electrically connected to node E, and the other plate of which is electrically connected to the drain of the first transistor. A second capacitor, one plate of which is electrically connected to node A, and the other plate of which is electrically connected to node B; The third capacitor has one plate electrically connected to node F and the other plate electrically connected to the high-level signal input terminal.

8. The display device according to claim 7, wherein, The first transistor through the seventeenth transistor are all P-type thin-film transistors.

9. The display device according to claim 1, wherein, The first output circuit also includes: The eighteenth transistor has its gate electrically connected to node I, its source electrically connected to node F, and its drain electrically connected to node H. The nineteenth transistor has its gate electrically connected to node D, its source electrically connected to the high-level signal input terminal, and its drain electrically connected to node H. The twentieth transistor has its gate electrically connected to node D, its source electrically connected to the first control signal input terminal, and its drain electrically connected to the gate of the eighteenth transistor. The gate of the 22nd transistor is electrically connected to the node H, the source of the 22nd transistor is electrically connected to the high-level signal input terminal, and the drain of the 22nd transistor is electrically connected to the first scan signal output terminal. The fifth capacitor has one plate electrically connected to node H and the other plate electrically connected to the high-level signal input terminal. The sixth capacitor has one plate electrically connected to the high-level signal input terminal and the other plate electrically connected to the gate of the eighteenth transistor.

10. The display device of claim 9, wherein, The eighteenth to twenty-second transistors are all P-type thin-film transistors.

11. The display device of claim 9, wherein, The first output circuit is used to reduce the potential of the scan signal output from the first scan signal output terminal by means of the twenty-first transistor under the control of the potential of the first pull-down control node G.

12. The display device according to claim 1, wherein The fourth capacitor is used to reduce the voltage of the portion of the scan signal output from the first scan signal output terminal that exhibits a stepped waveform.

13. The display device according to claim 12, wherein, When the signal at the first stage signal output terminal switches from a high potential to a low potential, the fourth capacitor is used to drive the potential of the first pull-down control node G to drop through capacitive coupling, so as to pull the potential of the first scan signal output terminal to a low potential through the twenty-first transistor.

14. The display device according to claim 1, wherein, The difference in pulse width between the waveforms of the scan signals output by any two gate drive circuits is less than or equal to 5%.

15. An electronic device comprising a display device as described in any one of claims 1-14.

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