Driving method for display panel
By adjusting the duration of the light emission control signal and the anode reset time during the write and hold frames of the display panel, the problem of bright bands running through the bright strip area was solved, and the display effect of the display panel was improved.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO LTD
- Filing Date
- 2024-12-31
- Publication Date
- 2026-07-02
AI Technical Summary
In the low grayscale image of the display panel, the light-emitting device that runs through the bright strip area affects the change of current during the non-light-emitting stage, causing the high-potential signal load to change, affecting the writing of the next frame, and forming multiple bright stripes.
By adjusting the duration of the light emission control signal, different durations of level control are used in the write frame stage and the hold frame stage to reduce the turn-off time of the light emission device in the hold frame stage, and the anode reset time is adaptively adjusted to reduce the load change of the high potential signal.
This effectively reduces the formation of bright bands running under the bright strip, improving the display effect of the display panel.
Smart Images
Figure CN2024144092_02072026_PF_FP_ABST
Abstract
Description
Display panel driving method
[0001] This application claims priority to Chinese patent application No. 202411930354.6, filed on December 25, 2024, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of display technology, and more specifically to a driving method for a display panel. Background Technology
[0003] With the development of display technology, users have increasingly higher requirements for the display effect of display panels. In order to improve the display effect of low grayscale images, related technologies have added a bright strip running through the top of the low grayscale image. Invention Overview
[0004] When the light-emitting device in the pixel driving circuit enters the bright bar area during the non-light-emitting stage, it affects the current change, which in turn causes the load of the high-potential signal to change, affecting the writing of the next frame, resulting in multiple bright bands being projected below the bright bar.
[0005] This application provides a driving method for a display panel, the display panel including a pixel driving circuit, the pixel driving circuit including a light-emitting device; one frame display time of the display panel includes a write frame stage and one or more hold frame stages, in the write frame stage the display panel writes and displays the image, and in the hold frame stage the display panel displays the image;
[0006] The driving method includes:
[0007] When the light emission control signal is at the first level, the light emission device is controlled to turn off; and
[0008] When the light emission control signal is at the second level, the light emission device is turned on.
[0009] In the write frame phase, the duration of the first level of the light emission control signal is a first duration, and in at least one hold frame phase, the duration of the first level of the light emission control signal is a second duration, wherein the first duration and the second duration are different. Attached Figure Description
[0010] Figure 1 is a schematic diagram of a pixel driving circuit;
[0011] Figure 2 is a schematic diagram of the driving timing;
[0012] Figure 3 is a schematic diagram of another driving timing;
[0013] Figure 4 is a flowchart of a display panel driving method provided in an embodiment of this application;
[0014] Figure 5 is a schematic diagram of a driving timing provided in an embodiment of this application;
[0015] Figure 6 is a schematic diagram of another driving timing provided in an embodiment of this application;
[0016] Figure 7 is a schematic diagram of the bright band formation process;
[0017] Figure 8 is a schematic diagram showing the relationship between the voltage change value of a high-potential signal and the duration of the high level of the light emission control signal. Embodiments of the present invention
[0018] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.
[0019] Furthermore, in the embodiments of this application, "multiple" refers to two or more. The terms "first" and "second," etc., in the embodiments of this application are used to distinguish different technical features and do not indicate any order, quantity, or importance.
[0020] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.
[0021] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.
[0022] Please refer to Figure 1, which is a schematic diagram of a pixel driving circuit. This pixel driving circuit may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a third reset transistor T8, a storage capacitor Cst, a boost capacitor Cboost, and a light-emitting device.
[0023] The driving transistor T1 includes a first terminal connected to the first node A, a second terminal connected to the second node B, and a control terminal connected to the third node Q. The switching transistor T2 includes a first terminal connected to the data signal DATA, a second terminal connected to the first node A, and a control terminal connected to the first scan control signal PSCAN. The compensation transistor T3 includes a first terminal connected to the second node B, a second terminal connected to the third node Q, and a control terminal connected to the second scan control signal NSCAN_T3. The first reset transistor T4 includes a first terminal connected to the first reset signal Vi_G, a second terminal connected to the third node Q, and a control terminal connected to the third scan control signal NSCAN_T4. The first light-emitting control transistor T5 includes a first terminal connected to the high-potential signal VDD, a second terminal connected to the first node A, and a control terminal connected to the light-emitting control signal EM. The second light-emitting control transistor T6 includes a first terminal connected to the second node B, a second terminal connected to the fourth node C, and a control terminal connected to the light-emitting control signal EM. The second reset transistor T7 includes a first terminal connected to the second reset signal VI_ANO, a second terminal connected to the fourth node C, and a control terminal connected to the fourth scan control signal PSCAN2. The third reset transistor T8 includes a first terminal connected to the third reset signal VI_T8, a second terminal connected to the first node A, and a control terminal connected to the fourth scan control signal PSCAN2. The storage capacitor Cst includes one end connected to a high-potential signal and the other end connected to the third node Q. The boost capacitor Cboost includes one end connected to the first scan control signal PSCAN and the other end connected to the third node Q. The light-emitting device includes an anode connected to the fourth node C and a cathode connected to a low-potential signal VSS.
[0024] In some embodiments, the control electrode may be the gate, the first electrode may be one of the source or the drain, and the second electrode may be the other of the source or the drain.
[0025] It should be understood that in Figure 1, the switching transistor T2, driving transistor T1, second reset transistor T7, third reset transistor T8, first light-emitting control transistor T5, and second light-emitting control transistor T6 are P-type thin film transistors (PTFTs), and the compensation transistor T3 and first reset transistor T4 are N-type thin film transistors (NTFTs). However, this does not constitute a limitation on the embodiments of this application. In practical applications, each transistor can be arbitrarily set to N-type thin film transistors or P-type thin film transistors in conjunction with the driving timing.
[0026] Please refer to Figure 2, which is a schematic diagram of a driving timing sequence. The driving timing sequence shown in Figure 2 can be used to drive the corresponding devices in the pixel driving circuit shown in Figure 1.
[0027] As shown in Figure 2, the display time of one frame can include one write frame phase and two hold frame phases. The frame can be written and displayed during the write frame phase, and the frame can be displayed during the hold frame phase. That is, no new frame needs to be written during the hold frame phase; instead, display is performed based on the frame written during the write frame phase.
[0028] As shown in Figure 2, one level cycle of the light emission control signal EM corresponds to one write frame phase or one hold frame phase. One level cycle of the light emission control signal EM includes a high-level duration and a low-level duration. If the light emission control signal EM is high, the first light emission control transistor T5 and the second light emission control transistor T6 are turned off, and the light-emitting device does not emit light. If the light emission control signal EM is low, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the current flowing through the driving transistor T1 can pass through the second node B and the fourth node C, thereby driving the light-emitting device to emit light.
[0029] As shown in Figure 2, during the high-level duration of the light-emitting control signal EM, the first scan control signal PSCAN can remain at a low level for a period of time to control the switching transistor T2 to turn on, thereby allowing the data signal DATA to be written to the third node Q. Also as shown in Figure 2, during the high-level duration of the light-emitting control signal EM, the fourth scan control signal PSCAN2 can remain at a low level for a period of time to control the second reset transistor T7 to turn on, thereby resetting the fourth node C. Since the fourth node C is connected to the anode of the light-emitting device, resetting the fourth node C is equivalent to resetting the anode of the light-emitting device.
[0030] Typically, during the write frame phase, the first scan control signal PSCAN is set low before the fourth scan control signal PSCAN2 during the high-level duration of the light-emitting control signal EM. That is, during the write frame phase, the fourth node C is reset after the data signal DATA is written to the third node Q, and then the light-emitting device is driven to emit light. During the hold frame phase, the light-emitting device is driven to emit light after the fourth node C is reset.
[0031] Please refer to Figure 3, which is a schematic diagram of another driving timing. The driving timing shown in Figure 3 can be used to drive the corresponding devices in the pixel driving circuit shown in Figure 1.
[0032] The difference between the embodiment in Figure 3 and the embodiment in Figure 2 is that, in the embodiment in Figure 2, the display time of one frame includes one write frame stage and two hold frame stages, while in the embodiment in Figure 3, the display time of one frame includes one write frame stage and one hold frame stage. For a description of the various signals in the embodiment in Figure 3, please refer to the embodiment in Figure 2, which will not be repeated here.
[0033] Please refer to Figure 4, which is a flowchart of a driving method for a display panel according to an embodiment of this application. The display panel includes a pixel driving circuit, which includes light-emitting devices. For example, the pixel driving circuit can be as shown in Figure 1. One frame display time of the display panel includes a write frame stage and one or more hold frame stages. In the write frame stage, the display panel writes and displays the image, and in the hold frame stage, the display panel displays the image. As shown in Figure 4, the driving method may include the following steps:
[0034] Step 410: When the light emission control signal is at the first level, control the light emission device to turn off;
[0035] Step 420: When the light emission control signal is at the second level, control the light emission device to turn on.
[0036] In this embodiment, the pixel driving circuit includes a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a light-emitting device. The first light-emitting control transistor T5 includes a first terminal connected to a high-potential signal VDD, a second terminal connected to a first node A, and a control terminal connected to a light-emitting control signal EM. The second light-emitting control transistor T6 includes a first terminal connected to a second node B, a second terminal connected to a fourth node C, and a control terminal connected to the light-emitting control signal EM. The light-emitting device includes an anode connected to the fourth node C and a cathode connected to a low-potential signal VSS. The first and second light-emitting control transistors T5 and T6 are turned on or off according to the light-emitting control signal EM. When the light-emitting control signal EM is at a first level, the first and second light-emitting control transistors T5 and T6 are turned off, so the high-potential signal VDD cannot flow into the fourth node C, and the light-emitting device is turned off and does not emit light. When the light-emitting control signal EM is at a second level, the first and second light-emitting control transistors T5 and T6 are turned on, so the high-potential signal VDD can flow through the first node A, the second node B, and the fourth node C, and the light-emitting device is turned on and emits light. Therefore, step 410 above may include: when the light emission control signal EM is at the first level, controlling the first light emission control transistor T5 and the second light emission control transistor T6 to turn off; step 420 above may include: when the light emission control signal EM is at the second level, controlling the first light emission control transistor T5 and the second light emission control transistor T6 to turn on.
[0037] When both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are P-type thin-film transistors, the first level of the light-emitting control signal EM is high, and the second level of the light-emitting control signal EM is low. When both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are N-type thin-film transistors, the first level of the light-emitting control signal EM is low, and the second level of the light-emitting control signal EM is high.
[0038] In this embodiment, the duration of the first level of the light emission control signal EM during the write frame phase is a first duration, and the duration of the first level of the light emission control signal EM during at least one hold frame phase is a second duration. The first duration and the second duration are different. Since the light emission device is turned off when the light emission control signal EM is at the first level, the off-time of the light emission device during the write frame phase is different from the off-time of the light emission device during the hold frame phase.
[0039] In some embodiments, the second duration is less than the first duration. That is, the duration of the first level of the light emission control signal EM during the hold frame phase is less than the duration of the first level of the light emission control signal EM during the write frame phase, thereby the off-time of the light-emitting device during the hold frame phase is less than the off-time of the light-emitting device during the write frame phase. Embodiments of this application reduce the off-time of the light-emitting device during the hold frame phase. Optionally, the second duration is less than or equal to half of the first duration. That is, the off-time of the light-emitting device during the hold frame phase is less than or equal to half of the off-time of the light-emitting device during the write frame phase. Embodiments of this application reduce the off-time of the light-emitting device during the hold frame phase by at least half. Taking a first duration of 60H as an example, meaning the duration of the first level of the light emission control signal EM during the write frame phase is 60H, and the off-time of the light-emitting device during the write frame phase is 60H, then the second duration is less than or equal to 30H. This means the duration of the first level of the light emission control signal EM during the hold frame phase is less than or equal to 30H, and the off-time of the light-emitting device during the hold frame phase is less than or equal to 30H. Here, 1H represents the charging time for one row of pixels in the image.
[0040] In some embodiments, the duration of the second level of the light emission control signal EM during the write frame phase is a third duration, and the duration of the second level of the light emission control signal EM during at least one hold frame phase is a fourth duration, wherein the third duration and the fourth duration are different. Since the light-emitting device is turned on when the light emission control signal EM is at the second level, the on-time of the light-emitting device during the write frame phase is different from the on-time of the light-emitting device during the hold frame phase. Optionally, the sum of the first duration and the third duration during the write frame phase is equal to the sum of the second duration and the fourth duration during a hold frame phase. If the second duration is less than the first duration, the fourth duration is greater than the third duration. Since both the first and second durations are the duration of the first level of the light emission control signal EM, and the third and fourth durations are the duration of the second level of the light emission control signal EM, and one level cycle of the light emission control signal EM corresponds to one write frame phase or one hold frame phase, the duration of one write frame phase and the duration of one hold frame phase are the same in the embodiments of this application. The embodiments of this application reduce the off-time of the light-emitting device during the hold frame phase while increasing the on-time of the light-emitting device during the hold frame phase.
[0041] In some embodiments, the duration of the second level of the light emission control signal EM during the write frame phase is a third duration, and the duration of the second level of the light emission control signal EM during at least one hold frame phase is a fourth duration, with the third duration being the same as the fourth duration. Since the light-emitting device is turned on when the light emission control signal EM is at the second level, the on-time of the light-emitting device during the write frame phase and the on-time of the light-emitting device during the hold frame phase can also be the same. Embodiments of this application may also reduce only the off-time of the light-emitting device during the hold frame phase while maintaining the on-time of the light-emitting device unchanged during the hold frame phase.
[0042] In cases where a single display frame includes multiple hold frame phases, compared to the write frame phase, this embodiment can reduce the duration of the first level of the light emission control signal EM in each hold frame phase, thereby reducing the off-time of the light-emitting device in each hold frame phase; alternatively, the duration of the first level of the light emission control signal EM in some hold frame phases can be reduced, thereby reducing the off-time of the light-emitting device in these hold frame phases, while the off-time of the light-emitting device in other hold frame phases can be consistent with the off-time of the light-emitting device in the write frame phase.
[0043] In some embodiments, a display frame time of the display panel includes a write frame phase and at least two hold frame phases; the duration of the first level of the light emission control signal in each hold frame phase is the second duration. That is, the duration of the first level of the light emission control signal EM in each hold frame phase can be reduced, thereby reducing the off-time of the light-emitting device in each hold frame phase.
[0044] In some embodiments, a display frame duration of the display panel includes a write frame phase and at least two hold frame phases; the duration of a first level of the light-emitting control signal in the first hold frame phase is a second duration. The first hold frame phase is a hold frame phase adjacent to the write frame phase. That is, the duration of the first level of the light-emitting control signal EM in the hold frame phase adjacent to the write frame phase can be reduced, thereby reducing the off-time of the light-emitting device in the hold frame phase adjacent to the write frame phase.
[0045] Based on the scheme that "the duration of the first level of the light emission control signal EM in the first holding frame phase is the second duration," the duration of the first level of the light emission control signal EM in the second holding frame phase can be equal to or different from the duration of the first level of the light emission control signal EM in the write frame phase. This application does not limit this. That is, the duration of the first level of the light emission control signal in the second holding frame phase is the same as or different from the duration of the first level of the light emission control signal in the write frame phase; wherein, the second holding frame phase is a holding frame phase that is not adjacent to the write frame phase.
[0046] In some embodiments, a display frame duration of the display panel includes a write frame phase and at least two hold frame phases; the duration of the first level of the light-emitting control signal in the second hold frame phase is the second duration. The second hold frame phase is a hold frame phase that is not adjacent to the write frame phase. That is, the duration of the first level of the light-emitting control signal EM in the hold frame phase that is not adjacent to the write frame phase can be reduced, thereby reducing the off-time of the light-emitting device in the hold frame phase that is not adjacent to the write frame phase.
[0047] Based on the scheme that "the duration of the first level of the light emission control signal EM in the second holding frame phase is the second duration," the duration of the first level of the light emission control signal EM in the first holding frame phase can be equal to or different from the duration of the first level of the light emission control signal EM in the write frame phase. This application does not limit this. That is, the duration of the first level of the light emission control signal in the first holding frame phase is the same as or different from the duration of the first level of the light emission control signal in the write frame phase; wherein, the first holding frame phase is a holding frame phase adjacent to the write frame phase.
[0048] In some embodiments, the driving method further includes: resetting the anode of the light-emitting device during a first time period in the write frame phase; and resetting the anode of the light-emitting device during a second time period in at least one hold frame phase; wherein the start time of the first time period is separated from the start time of the write frame phase by a first interval, and the start time of the second time period is separated from the start time of the corresponding hold frame phase by a second interval, and the first interval and the second interval are different. To ensure that the anode reset operation is performed during the off-time of the light-emitting device, thereby avoiding affecting the conduction and light emission of the light-emitting device, the embodiments of this application adjust the off-time of the light-emitting device in at least one hold frame phase while also adaptively adjusting the anode reset time of the light-emitting device in at least one hold frame phase. Optionally, the first time period is within the duration of the first level of the light emission control signal in the write frame phase, and the second time period is within the duration of the first level of the light emission control signal in the corresponding hold frame phase.
[0049] In some embodiments, the second duration is shorter than the first duration; the second interval duration is shorter than the first interval duration. That is, when the off-time of the light-emitting device is reduced in at least one hold frame phase, the reset time of the anode of the light-emitting device also needs to be adaptively moved forward.
[0050] In this embodiment, the pixel driving circuit further includes a second reset transistor T7 and a light-emitting device. The second reset transistor T7 includes a first terminal connected to the second reset signal VI_ANO, a second terminal connected to the fourth node C, and a control terminal connected to the fourth scan control signal PSCAN2. The light-emitting device includes an anode terminal connected to the fourth node C and a cathode terminal connected to the low-potential signal VSS. Therefore, resetting the anode terminal of the light-emitting device is also resetting the fourth node C. Thus, resetting the anode terminal of the light-emitting device includes resetting the fourth node C. That is, the driving method further includes: resetting the fourth node C during a first time period in the write frame phase; and resetting the fourth node C during a second time period in at least one hold frame phase.
[0051] When the fourth scan control signal PSCAN2 is at the third level, the second reset transistor T7 is turned on; when the fourth scan control signal PSCAN2 is at the fourth level, the second reset transistor T7 is turned off. When the second reset transistor T7 is turned on, the second reset signal VI_ANO can reach the fourth node C through the second reset transistor T7, thereby resetting the fourth node C. Therefore, the above-mentioned resetting of the fourth node C can be implemented as follows: when the fourth scan control signal PSCAN2 is at the third level, the second reset transistor T7 is turned on, so that the second reset signal VI_ANO flows into the fourth node C. Specifically, during the first time period of the write frame phase, the fourth scan control signal PSCAN2 is at the third level; during the second time period of at least one hold frame phase, the fourth scan control signal PSCAN2 is at the third level. Optionally, when the second reset transistor T7 is a P-type thin-film transistor, the third level of the fourth scan control signal PSCAN2 is low and the fourth level of the fourth scan control signal PSCAN2 is high; when the second reset transistor T7 is an N-type thin-film transistor, the third level of the fourth scan control signal PSCAN2 is high and the fourth level of the fourth scan control signal PSCAN2 is low.
[0052] In summary, the driving method provided in this application provides that the off-time of the light-emitting device in at least one hold frame stage is different from the off-time of the light-emitting device in the write frame stage. This results in different degrees of influence on the current and the load on the high-potential signal when the light-emitting device enters the bright bar area during its off-time, thus avoiding the superposition of multiple bright bands projected below the bright bar. Furthermore, in this application embodiment, the off-time of the light-emitting device in at least one hold frame stage is shorter than the off-time of the light-emitting device in the write frame stage. That is, this application embodiment reduces the off-time of the light-emitting device in at least one hold frame stage, thereby reducing the influence on the current when the light-emitting device enters the bright bar area during its off-time, thus reducing the load change on the high-potential signal, and further reducing the intensity of multiple bright bands projected below the bright bar, improving the display effect of the display panel.
[0053] The driving method provided in the embodiments of this application will be described below with reference to several examples of driving timing.
[0054] Please refer to Figures 5 and 6, which are schematic diagrams of a driving timing sequence provided in an embodiment of this application. The driving timing sequences shown in Figures 5 and 6 can be used to drive the corresponding devices in the pixel driving circuit shown in Figure 1.
[0055] As shown in Figures 5 and 6, the display time of one frame of the display panel can include a write frame phase and one or more hold frame phases. During the write frame phase, the image can be written and displayed; during the hold frame phase, the image can be displayed. One level cycle of the light emission control signal EM corresponds to one write frame phase or one hold frame phase. One level cycle of the light emission control signal EM includes a high-level duration and a low-level duration. Taking the first light emission control transistor T5 and the second light emission control transistor T6 as examples, if the light emission control signal EM is high, the first light emission control transistor T5 and the second light emission control transistor T6 are turned off, and the light-emitting device is off and does not emit light; if the light emission control signal EM is low, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the light-emitting device is on and emits light.
[0056] Taking a P-type thin-film transistor as an example, as shown in Figures 5 and 6, during the write frame stage, while the light emission control signal EM is at a high level, the first scan control signal PSCAN can remain at a low level for a period of time to control the switch transistor T2 to turn on, so that the data signal DATA can be written to the third node Q. That is, the above driving method also includes: during the write frame stage, when the light emission control signal EM is at the first level, controlling the switch transistor T2 to turn on according to the first scan control signal PSCAN, so that the data signal DATA is written to the third node Q.
[0057] Taking the second reset transistor T7 as a P-type thin-film transistor as an example, as shown in Figures 5 and 6, during the write frame stage and the hold frame stage, during the high-level duration of the light emission control signal EM, the fourth scan control signal PSCAN2 can be maintained at a low level for a period of time to control the second reset transistor T7 to conduct, thereby resetting the anode of the light-emitting device. During the write frame stage, during the high-level duration of the light emission control signal EM, the first scan control signal PSCAN can be set low before the fourth scan control signal PSCAN2; that is, during the write frame stage, after the data signal DATA is written to the third node Q, the fourth node C is reset, and then the light-emitting device is driven to emit light.
[0058] As shown in Figure 5, one frame display time includes one write frame phase and two hold frame phases. Compared to the write frame phase, the duration of the high level of the light-emitting control signal EM in each hold frame phase can be shortened, thereby shortening the off-time of the light-emitting device. Simultaneously, the duration of the low level of the light-emitting control signal EM in each hold frame phase is extended, thereby extending the light-emitting time of the light-emitting device. Specifically, the off-time of the light-emitting device can be shortened by at least half. That is, the duration of the high level of the light-emitting control signal EM in the write frame phase is the first duration, and the duration of the high level of the light-emitting control signal EM in the hold frame phase is the second duration, the second duration being less than or equal to half of the first duration.
[0059] As shown in Figure 6, a display frame consists of a write frame phase and a hold frame phase. Compared to the write frame phase, the duration of the high level of the light-emitting device (EM) during the hold frame phase can be shortened, thereby shortening the off-time of the light-emitting device. Simultaneously, the duration of the low level of the light-emitting control signal (EM) during the hold frame phase can be extended, thereby extending the light-emitting duration of the light-emitting device.
[0060] As shown in Figures 5 and 6, for the hold frame stage where the turn-off duration of the light-emitting device is adjusted, the reset time of the anode of the light-emitting device is also moved forward accordingly to ensure that the anode of the light-emitting device is reset within the turn-off time of the light-emitting device.
[0061] As shown in Figure 7, when the light-emitting device enters the bright strip area 710 during its off-time, the load of the high-potential signal VDD changes, causing the voltage of the high-potential signal VDD to increase, making this area bright and forming a bright band. As shown in Figure 8, as the duration of the high level of the light-emitting control signal EM shortens, the change in the load of the high-potential signal VDD gradually decreases, thus reducing the voltage change of the high-potential signal VDD. As shown in Figure 8, when the duration of the high level of the light-emitting control signal EM shortens from 60H (60 unit time) to 30H (30 unit time), the change in the load of the high-potential signal VDD decreases, and the voltage change value of the high-potential signal VDD decreases from 4mV (millivolt) to 1mV. It can be seen that as the duration of the high level of the light-emitting control signal EM shortens, the voltage rise of the high-potential signal VDD decreases, thereby reducing the brightness of this area, mitigating the intensity of the bright band, and improving the display effect.
[0062] It should be understood that the pixel driving circuit described in the embodiments of this application can be as shown in Figure 1. For a description of the pixel driving circuit described in the embodiments of this application, please refer to the embodiment in Figure 1 above.
[0063] For the specific implementation methods of each of the above operations and their corresponding beneficial effects, please refer to the detailed description of the pixel driving circuit, driving timing and display panel driving method above, which will not be repeated here.
[0064] The above provides a detailed description of a display panel driving method provided by the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A driving method for a display panel, the display panel including a pixel driving circuit, the pixel driving circuit including a light-emitting device; a frame display time of the display panel includes a write frame stage and one or more hold frame stages, wherein the display panel writes and displays an image in the write frame stage, and the display panel displays the image in the hold frame stage; in, The driving method includes: When the light emission control signal is at the first level, the light emission device is controlled to turn off; and When the light emission control signal is at the second level, the light emission device is turned on. In the write frame phase, the duration of the first level of the light emission control signal is a first duration, and in at least one hold frame phase, the duration of the first level of the light emission control signal is a second duration, wherein the first duration and the second duration are different.
2. The driving method according to claim 1, wherein, The second duration is less than the first duration.
3. The driving method according to claim 2, wherein, The second duration is less than or equal to half of the first duration.
4. The driving method according to claim 1, wherein, In the write frame phase, the duration of the second level of the light emission control signal is a third duration, and in at least one hold frame phase, the duration of the second level of the light emission control signal is a fourth duration, wherein the third duration is different from the fourth duration.
5. The driving method according to claim 4, wherein, The sum of the first duration and the third duration in the write frame phase is equal to the sum of the second duration and the fourth duration in the hold frame phase.
6. The driving method according to claim 5, wherein, The second duration is less than the first duration; the fourth duration is greater than the third duration.
7. The driving method according to claim 1, wherein, In the write frame phase, the duration of the second level of the light emission control signal is a third duration, and in at least one hold frame phase, the duration of the second level of the light emission control signal is a fourth duration, wherein the third duration is the same as the fourth duration.
8. The driving method according to claim 1, wherein, One frame display time of the display panel includes one write frame phase and at least two hold frame phases; The duration of the first level of the light emission control signal in each of the holding frame phases is the second duration.
9. The driving method according to claim 8, wherein, One frame display time of the display panel includes one write frame phase and at least two hold frame phases; The duration of the first level of the light emission control signal during the first holding frame phase is the second duration; The first holding frame phase is the holding frame phase adjacent to the write frame phase.
10. The driving method according to claim 9, wherein, The duration of the first level of the light emission control signal in the second hold frame phase is the same as or different from the duration of the first level of the light emission control signal in the write frame phase; wherein, the second hold frame phase is a hold frame phase that is not adjacent to the write frame phase.
11. The driving method according to claim 1, wherein, One frame display time of the display panel includes one write frame phase and at least two hold frame phases; The duration of the first level of the light emission control signal during the second holding frame phase is the second duration; The second hold frame phase is a hold frame phase that is not adjacent to the write frame phase.
12. The driving method according to claim 11, wherein, The duration of the first level of the light emission control signal in the first holding frame phase is the same as or different from the duration of the first level of the light emission control signal in the write frame phase; wherein, the first holding frame phase is the holding frame phase adjacent to the write frame phase.
13. The driving method according to claim 1, wherein, The method further includes: During the first time period of the write frame phase, the anode of the light-emitting device is reset; During a second time period of at least one of the holding frame phases, the anode of the light-emitting device is reset; The first time period is separated from the start time of the first time period by a first interval, and the second time period is separated from the start time of the corresponding hold frame phase by a second interval. The first interval and the second interval are different.
14. The driving method according to claim 13, wherein, The first time period is within the duration of the first level of the light emission control signal in the write frame phase, and the second time period is within the duration of the first level of the light emission control signal in the corresponding hold frame phase.
15. The driving method according to claim 14, wherein, The second duration is less than the first duration; the second interval duration is less than the first interval duration.
16. The driving method according to claim 1, wherein, The pixel driving circuit further includes a driving transistor, a switching transistor, a compensation transistor, a first reset transistor, a first light-emitting control transistor, a second light-emitting control transistor, a second reset transistor, and a third reset transistor. The driving transistor includes a first electrode connected to the first node, a second electrode connected to the second node, and a control electrode connected to the third node; The switching transistor includes a first electrode that receives a data signal, a second electrode that is connected to the first node, and a control electrode that receives a first scan control signal. The compensation transistor includes a first electrode connected to the second node, a second electrode connected to the third node, and a control electrode that receives the second scan control signal; The first reset transistor includes a first terminal connected to a first reset signal, a second terminal connected to the third node, and a control terminal connected to a third scan control signal; The first light-emitting control transistor includes a first electrode connected to a high-potential signal, a second electrode connected to the first node, and a control electrode connected to a light-emitting control signal; The second light-emitting control transistor includes a first electrode connected to the second node, a second electrode connected to the fourth node, and a control electrode that receives the light-emitting control signal; The second reset transistor includes a first terminal connected to a second reset signal, a second terminal connected to the fourth node, and a control terminal connected to a fourth scan control signal; The third reset transistor includes a first electrode that receives a third reset signal, a second electrode that is connected to the first node, and a control electrode that receives a fourth scan control signal. The light-emitting device includes an anode connected to the fourth node and a cathode connected to a low-potential signal.
17. The driving method according to claim 16, wherein, The step of controlling the light-emitting device to turn off when the light-emitting control signal is at the first level includes: When the light emission control signal is at the first level, the first light emission control transistor and the second light emission control transistor are controlled to turn off; When the light-emitting control signal is at the second level, controlling the light-emitting device to turn on includes: When the light emission control signal is at the second level, the first light emission control transistor and the second light emission control transistor are turned on.
18. The driving method according to claim 17, wherein, The method further includes: During the first time period of the write frame phase, the fourth node is reset; The fourth node is reset during a second time period of at least one of the holding frame phases; The first time period is within the duration of the first level of the light emission control signal in the write frame phase, and the second time period is within the duration of the first level of the light emission control signal in the corresponding hold frame phase.
19. The driving method according to claim 18, wherein, The resetting of the fourth node includes: When the fourth scan control signal is at the third level, the second reset transistor is turned on so that the second reset signal flows into the fourth node; Specifically, during the first time period of the write frame phase, the fourth scan control signal is the third level; during the second time period of at least one hold frame phase, the fourth scan control signal is the third level.
20. The driving method according to claim 17, wherein, The method further includes: During the write frame stage, when the light emission control signal is at the first level, the switching transistor is turned on according to the first scan control signal so that the data signal is written to the third node.