Direct current comparator bridge and current source self-calibration method therefor

Abstract

The present application relates to the field of measurement apparatuses, and discloses a direct current comparator bridge and a current source self-calibration method therefor. The direct current comparator bridge comprises structures such as main / secondary current sources, main loop integer-turn / fractional-turn adjustable windings, integer-turn / fractional-turn switch matrices, integer-turn / fractional-turn drive modules, a secondary loop fixed-turn winding, a micro-difference compensation module, a modulation module, a demodulation module, a conditioning module, an ADC, and a control module. The main current source and the secondary current source each comprise a reference DAC and a transconductance amplifier. The reference DAC receives a code value from the control module, and outputs a voltage corresponding to the code value to the transconductance amplifier. The transconductance amplifier converts a voltage signal outputted by the reference DAC into a current signal. The control module calculates, on the basis of ADC sampling data, correction values corresponding to the main current source and the secondary current source, and corrects, on the basis of the correction values, the code values received by the main current source and the secondary current source, so as to complete self-calibration of the main current source and the secondary current source, thereby improving the accuracy of output current values of the current sources.

Description

A DC current comparator bridge and its current source calibration method

[0001] This application claims priority to Chinese Patent Application No. 202411942258.3, filed on December 27, 2024, entitled "A DC Current Comparator Bridge and Current Source Calibration Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of measurement device technology, and in particular to a DC current comparator bridge and its current source calibration method. Background Technology

[0003] A DC current comparator is a high-accuracy DC current comparison device, commonly used as a high-accuracy DC current measuring instrument. Furthermore, using a DC current comparator as its core, and in conjunction with a resistor bridge arm, current feedback system, and unbalanced voltage detection system, a DC current comparator bridge for resistance ratio measurement can be constructed. Based on differences in key components and measurement accuracy, DC current comparator bridges are further subdivided into conventional DC current comparator bridges (DCC bridges) and low-temperature DC current comparator bridges (CCC bridges). The measurement accuracy of a DCC bridge is generally 10... -7 ~10 -8 The accuracy of CCC bridge measurements is typically around 10. -9 ~10 -10 The magnitude of the current is measured. The DC current comparator bridge itself has master and slave loop current tracking capabilities, therefore, an accuracy of 10 is generally used. -4 ~10 -5 By using master and slave current sources with magnitude-level accuracy, a current ratio value with even higher accuracy can be obtained, which can meet the requirements of 10. -7 ~10 -8 Measurement of resistance ratio with order-of-magnitude accuracy.

[0004] However, with the development of science and technology and industry, its application areas are expanding. Because a DC current comparator bridge can simultaneously set the current value and measure the resistance value, it can easily achieve resistance scanning measurement with the current load as the independent variable. Therefore, it has been used to measure the load factor of precision resistors. In this application scenario, a mismatch between the accuracy of the current measurement and the accuracy of the resistance measurement has emerged. That is, of the two parameters used to calculate the resistor load factor (current value and resistance value), the accuracy of the current value is significantly lower than the accuracy of the resistance value measurement, thus limiting the accuracy of the final measurement result to the accuracy of the current source. Summary of the Invention

[0005] To address the mismatch between the accuracy of current values ​​and the accuracy of resistance measurements in current current comparator bridges, this application provides a current comparator bridge and its current source calibration method to improve the accuracy of the current source output value.

[0006] To achieve the above objectives, this application provides the following solution.

[0007] In an exemplary embodiment, this application provides a DC current comparator bridge, comprising: a main current source, a slave current source, standard resistor terminals, resistor terminals to be measured, an iron core, an integer-turn adjustable winding of the main circuit, an integer-turn switch matrix, an integer-turn drive module, a fractional-turn adjustable winding of the main circuit, a fractional-turn switch matrix, a fractional-turn drive module, a fixed-turn winding of the slave circuit, a differential compensation module, a modulation module, a demodulation module, a conditioning module, an ADC, and a control module; the modulation module includes a modulation circuit and a dedicated modulation winding; the demodulation module includes a dedicated demodulation winding and a demodulation circuit;

[0008] The control module is connected to the main current source, the slave current source, the integer turns drive module, the fractional turns drive module, the differential compensation module, and the ADC respectively.

[0009] The main current source includes a reference DAC and a transconductance amplifier; the reference DAC receives code values ​​from the control module and outputs the voltage corresponding to the code values ​​to the transconductance amplifier; the transconductance amplifier converts the voltage signal output by the reference DAC into a current signal; the sampling resistor in the transconductance amplifier is switched by a switch to realize current level switching; the slave current source has the same structure as the main current source.

[0010] The standard resistor terminal and the fixed number of turns winding of the slave circuit are connected to the slave circuit where the slave current source is located; the standard resistor terminal is used to connect an external standard resistor, a standard resistor to replace a relay, or a slave circuit standby resistor;

[0011] The terminals of the resistor under test, the main circuit integer-turn adjustable winding, the main circuit fractional-turn adjustable winding, and the differential compensation module are connected in the main circuit where the main current source is located; the terminals of the resistor under test are used to connect an external resistor under test, and the resistor under test can replace a relay or a standby resistor in the main circuit.

[0012] The iron core is used to wind an adjustable winding with an integer number of turns in the main circuit, an adjustable winding with a fractional number of turns in the main circuit, a winding with a fixed number of turns in the slave circuit, a special winding for modulation, and a special winding for demodulation.

[0013] The integer-turn switch matrix is ​​connected to the integer-turn drive module and the main circuit integer-turn adjustable winding, respectively. The integer-turn drive module is used to provide drive signals to the integer-turn switch matrix under the control command of the control module, so as to connect different number of turns of the main circuit integer-turn adjustable winding to the main circuit.

[0014] The fractional-turn switch matrix is ​​connected to the fractional-turn drive module and the main circuit fractional-turn adjustable winding, respectively. The fractional-turn drive module is used to provide drive signals to the fractional-turn switch matrix under the control command of the control module, so as to connect different number of turns of the main circuit fractional-turn adjustable winding to the main circuit.

[0015] The differential compensation module is used to extract the main circuit current from the main circuit and output it to the main circuit fractional-turn adjustable winding after proportional attenuation.

[0016] The modulation circuit is connected to a dedicated modulation winding; the modulation module is used to modulate the residual magnetic flux in the iron core to generate a modulated detection signal.

[0017] The demodulation circuit is connected to a dedicated demodulation winding; the demodulation module is used to demodulate the modulated detection signal into a DC voltage signal.

[0018] The conditioning module is connected to the demodulation circuit and the ADC respectively; the conditioning module is used to filter and amplify the DC voltage signal output by the demodulation module, and output the conditioned voltage signal to the ADC.

[0019] The ADC is used to sample the conditioned voltage signal and send the sampled data to the control module;

[0020] The control module is used to calculate the correction values ​​corresponding to the main current source and the slave current source based on the sampled data, and to correct the code values ​​received by the main current source and the slave current source based on the correction values, thereby completing the self-calibration of the main current source and the slave current source.

[0021] In one exemplary embodiment, the reference DAC employs a single DAC device.

[0022] In one exemplary embodiment, the reference DAC is a composite DAC consisting of dual DACs and a proportional adder; the dual DACs include a first DAC and a second DAC, denoted as DACa and DACb, respectively.

[0023] In one exemplary embodiment, this application also provides a current source calibration method for a DC current comparator bridge, applied to the DC current comparator bridge; the current source calibration method includes:

[0024] Step 1: Switch the integer turns switching matrix so that the number of integer turns in the main circuit's adjustable integer turns winding is equal to the number of fixed turns in the slave circuit's fixed turns winding; switch the fractional turns switching matrix so that the number of fractional turns in the main circuit's adjustable fractional turns winding is 0.

[0025] Step 2: Switch the main current source and the secondary current source to the same current range. Short-circuit the terminals of the resistor under test by replacing the relay with the resistor under test or connect it to the standby resistor of the main circuit. Short-circuit the terminals of the standard resistor by replacing the relay with the standard resistor or connect it to the standby resistor of the secondary circuit.

[0026] Step 3: Denote the reference DAC of the main current source as DAC1 and the reference DAC of the secondary current source as DAC2. Divide the bit length N of DAC1 and DAC2 into high-order bits N. H and low-order N L Two parts: Initialize all N bits of DAC1 and DAC2 to 0;

[0027] Step 4: Refresh the output voltages of DAC1 and DAC2 according to the currently received code value. Driven by the output voltages of DAC1 and DAC2, the main current source and the slave current source output current to the main circuit and the slave circuit respectively.

[0028] Step 5: Read the sampled data using the ADC, and record the reading as D. (i)(j) , where the subscript i represents the high-order bit value of DAC1 and j represents the high-order bit value of DAC2;

[0029] Step 6, if the current Execute step 7; if the current Then the current loop ends, and the process jumps to step 8;

[0030] Step 7: If i = j, increment the code value of DAC1 by 1, i.e., i = i + 1, and keep j unchanged; otherwise, increment the code value of DAC2 by 1, i.e., j = j + 1, and keep i unchanged; then jump to step 4.

[0031] Step 8: After this round of iterations, the ADC has collected a total of [data / data]. Each sampled data point is denoted as...

[0032] Step 9, take The first of the sampled data The sampled data are grouped into pairs according to their sequential order. The difference d between each pair of adjacent sampled data is calculated by subtracting the previous value from the next value in each group. 2,k =D (k+1)(k) -D (k)(k) Where k takes the following values: And k is an integer, and a total of [number] calculations are performed. d 2,k ;

[0033] Step 10, d 2,k Summation, calculation yields

[0034] Step 11, according to d 2,k S2 calculates the DNL error e between adjacent code values ​​in the high-order bits of DAC2. 2,k ;

[0035] Step 12, according to e 2,k Calculate the correction value c for DAC2. 2,k ;

[0036] Step 13, take The last sample data The sampled data are grouped into pairs according to their sequential order. The difference d between each pair of adjacent sampled data is calculated by subtracting the previous value from the next value in each group. 1,k =D (k)(k) -D (k)(k-1) Where k takes the following values: Total calculation d 1,k ;

[0037] Step 14, d 1,k Summation, calculation yields

[0038] Step 15, according to d 1,k The DNL error e between adjacent code values ​​in the high-order bits of DAC1 is calculated using S1. 1,k ;

[0039] Step 16, according to e 1,k Calculate the correction value c for DAC1. 1,k ;

[0040] Step 17: When the DC current comparator bridge is in normal measurement mode, use the correction value c. 1，k and c 2，k Correct the code values ​​received from the main current source and the current source respectively.

[0041] In an exemplary embodiment, step 11, according to d 2,k S2 calculates the DNL error e between adjacent code values ​​in the high-order bits of DAC2. 2,k Specifically, it includes:

[0042] In an exemplary embodiment, step 12, according to e 2,kCalculate the correction value c for DAC2. 2,k Specifically, it includes:

[0043] In an exemplary embodiment, step 15, according to d 1,k The DNL error e between adjacent code values ​​in the high-order bits of DAC1 is calculated using S1. 1，k Specifically, it includes:

[0044] In an exemplary embodiment, step 16, according to e 1，k Calculate the correction value c for DAC1. 1,k Specifically, it includes:

[0045] In an exemplary embodiment, in step 3, the number of bits N of DAC1 and DAC2 is divided into high-order bits N. H and low-order N L Two parts, specifically including:

[0046] When the reference DAC uses a single DAC device, according to the formula Determine the least significant bit N in the number of bits N. L The rest are high-order N H Where INL is the maximum integral nonlinearity error of the reference DAC.

[0047] In an exemplary embodiment, in step 3, the number of bits N of DAC1 and DAC2 is divided into high-order bits N. H and low-order N L Two parts, specifically including:

[0048] When the reference DAC is a composite DAC consisting of dual DACs and a proportional adder, if the resistance ratio of the proportional adder is 1 / 2... m Then the effective number of DACa is taken as the high-order N. H , take m as the lower bit N L The total number of digits is N = N H +N L Reference DAC.

[0049] According to the specific embodiments provided in this application, the following technical effects are disclosed:

[0050] This application provides a DC current comparator bridge and its current source calibration method. By using the control module built into the DC current comparator bridge, the correction values ​​corresponding to the master and slave current sources are calculated based on the ADC sampling data. The correction values ​​are then used to correct the current source output in the conventional measurement mode. This can reduce the nonlinear error of the overall current source output to within 1 LSB, greatly improving the accuracy of the current source output current value.

[0051] Instruction manual illustrations

[0052] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 is a schematic diagram of the basic components of a DC current comparator bridge.

[0054] Figure 2 is a schematic diagram of the current source structure of the reference DAC using a single DAC device;

[0055] Figure 3 is a schematic diagram of the current source structure of the reference DAC using a composite DAC. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0057] To improve the accuracy of the current source in a DC current comparator bridge, this application provides a DC current comparator bridge and a current source calibration method. The method is implemented by a control module built into the DC current comparator bridge, and the current source output in the conventional measurement mode is corrected using self-calibration data (correction value), thereby improving the accuracy of the current parameters in the DC current comparator bridge.

[0058] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0059] As shown in Figure 1, in an exemplary embodiment, the DC current comparator bridge (hereinafter also referred to as the bridge) provided in this application includes: a main current source, a slave current source, a standard resistor terminal block, a resistor under test terminal block, an iron core T, and an adjustable winding W of integer turns in the main circuit. 11 Integer-turn switch matrix, integer-turn drive module, main circuit fractional-turn adjustable winding W 12 The system comprises a fractional-turn switch matrix, a fractional-turn drive module, a fixed-turn winding W2 in the slave circuit, a differential compensation module, a modulation module, a demodulation module, a conditioning module, an ADC, and a control module. The modulation module includes a modulation circuit and a dedicated modulation winding W2. m The demodulation module includes a dedicated demodulation winding W.d And demodulation circuit. In other embodiments, the DC current comparator bridge may further include an unbalanced voltage detection module and / or an optical isolation module.

[0060] The control module is connected to the main current source, the slave current source, the integer-turn drive module, the fractional-turn drive module, the differential compensation module, and the ADC, respectively. In other embodiments, the control module is also connected to the unbalanced voltage detection module and / or the optical isolation module, respectively.

[0061] As shown in Figures 2 and 3, the main current source is primarily composed of a reference DAC (Digital-to-Analog Converter) and a transconductance amplifier. The reference DAC described in this application can be a single DAC device as shown in Figure 2, or a composite DAC consisting of dual DACs and a proportional adder as shown in Figure 3. The dual DACs include a first DAC and a second DAC, denoted as DACa and DACb, respectively. The reference DAC receives control commands and code values ​​from the control module, and outputs a code value corresponding to a voltage V. O The signal is directed to a transconductance amplifier. This transconductance amplifier converts the voltage signal output from the reference DAC into a current signal. The sampling resistor in the transconductance amplifier can be switched via a switch to achieve current level switching. The slave current source has the same structure as the main current source.

[0062] In the exemplary embodiments shown in Figures 2 and 3, the input terminal of the transconductance amplifier uses an operational amplifier Q1 to form a buffer circuit, achieving impedance matching between the preceding and following stages. Capacitors C1 and C2 are connected in parallel with ground in the following stage of the buffer circuit to filter the preceding signal and reduce noise. Operational amplifiers Q2 and Q3, sampling resistors Ra, Rb, and Rc, and resistors R1, R2, R3, and R4 with equal resistance values ​​together form a Holland current source circuit, converting the output voltage of the buffer circuit into current for output. The current output point is the common connection point of the sampling resistors Ra, Rb, and Rc.

[0063] In a transconductance amplifier, the sampling resistors refer to Ra, Rb, and Rc. By controlling the multiplexer switch S0, only one of the sampling resistors, Ra, Rb, or Rc, is connected to the line at any given time. Since the output current is equal to V... in / R, where V in R is the voltage at the input terminal of the sampling resistor, and R is the resistance value of the sampling resistor connected in the circuit among Ra, Rb, or Rc. Therefore, by selecting the resistance values ​​of Ra, Rb, or Rc in decimal form, the current range can be switched by changing the sampling resistor. Of course, in practical applications, transconductance amplifiers are not limited to this one circuit form; other circuit forms can also achieve the function of a transconductance amplifier; and the range selection is not limited to three levels, but can be designed according to requirements.

[0064] The control module can send control commands to the DAC to configure its parameters. For example, it can configure the DAC's output range and polarity. With the DAC parameters pre-configured, the control module sends code values ​​to the DAC, which then converts these code values ​​into voltage for output based on the configured parameters and output characteristics (the conversion formula defined by the device itself).

[0065] In the composite DAC circuit structure shown in Figure 3, the proportional adder consists of an operational amplifier Q4 and four high-precision resistors R5, R6, R7, and R8. The components of the composite DAC circuit structure have the following relationships:

[0066] If we set R5 = R8 and R6 = R7, then we have:

[0067] R5, R6, R7, and R8 represent the resistance values ​​of four high-precision resistors. O The reference DAC output voltage; V a and V b These are the output amplitude voltages of DACa and DACb, respectively.

[0068] Regarding the resistance configuration, if the resistance ratio is... Then there is Where M is a positive integer.

[0069] Generally, DACa and DACb can be selected from DAC devices of the same specifications, having the same output range and resolution. The total output voltage V after combining the two DACs via a proportional adder is then calculated. O This is equivalent to the output amplitude voltage of DACa being attenuated by M times and then synthesized with DACa. It is equivalent to DACa providing the high-order N bits of the total output voltage signal. H DACb provides the low-order N bits of the total output voltage signal. L Compared to a single DAC output, a composite DAC increases adjustable resolution by a factor of M. M converted to binary is 2^M. m m is also a positive integer.

[0070] The structure of the slave current source is the same as that of the master current source. In this application, both the master and slave current sources are objects to be calibrated.

[0071] As shown in Figure 1, when the DC current comparator bridge is in normal measurement mode, the standard resistor terminal is used to connect an external standard resistor R. s That is, the standard resistor terminals are represented by R in Figure 1. s The four circles at both ends indicate whether the standard resistor terminals are connected to R.s The current source of this application has no impact on the calibration method, meaning that the self-calibration process can be completed with the standard resistor terminals left unconnected.

[0072] As shown in Figure 1, the standard resistor terminal block and the fixed-turn winding W2 of the slave circuit are connected in the slave circuit where the slave current source is located. During current source calibration, the standard resistor terminal block is used to connect a standard resistor to replace the relay or the slave circuit standby resistor R. z .

[0073] When the DC current comparator bridge is in normal measurement mode, the terminals of the resistor under test are used to connect the external resistor R. x That is, the terminals of the resistor to be tested are represented by R in Figure 1. x The four circles at both ends indicate whether the terminals of the resistor under test are connected to R. x The current source of this application has no impact on the calibration method, meaning that the self-calibration process can be completed with the terminals of the resistor under test left unconnected.

[0074] As shown in Figure 1, the terminals of the resistor under test and the main circuit integer-turn adjustable winding W 11 The main circuit fractional-turn adjustable winding W 12 The differential compensation module is connected in the main circuit where the main current source is located. During current source self-calibration, the terminals of the resistor under test are used to connect the resistor under test to replace the relay or the main circuit standby resistor R. y .

[0075] The standby resistor refers to the resistor R connected in parallel to the standard resistor R inside the bridge circuit via a relay. s Or the resistor to be measured R x The resistors at the positions, in this embodiment, respectively correspond to the standby resistor R in the slave circuit. z and the standby resistor R of the main circuit y This avoids open-circuit faults in the master and slave circuits when no external resistor is connected. During current source calibration, both the master and slave circuits can be switched to the standby resistor, eliminating the need for an external standard resistor R on the bridge. s and the resistance to be measured R x According to circuit theory, a current source must not be open-circuited. Without a standby resistor, the absence of a standard resistor or the resistor under test will cause the current source to open-circuit, damaging the circuit. A standby resistor ensures that when neither a standard resistor nor the resistor under test is connected, the circuit can switch to standby, preventing the current source from opening. It should be noted that DCCs generally have an internal standby resistor to achieve this operation. If there is no standby resistor, it can be used in the bridge arm resistor (i.e., the standard resistor R). s Or the resistor to be measured R xA relay is installed at both ends and controlled to be short-circuited. In this embodiment, these are referred to as a standard resistor replacement relay and a resistor under test replacement relay, respectively. Specifically, a control signal is sent by the control module to cause the moving contact of the relay to move from R... s Or R x Switch to R on the connection line z Or R y On the connection line. For example, by closing the moving contact S of the relay. 11 S 12 And disconnect R x The terminals of the resistor under test at both ends can switch the main circuit to R. y On the connection line; by closing the moving contact S of the relay. 21 S 22 And disconnect R s The standard resistor terminals at both ends allow switching from the circuit to R. z The connection line. If there is no standby resistor, then move the relay moving contact from R. s Or R x The connection line should be switched to the connection line where the standard resistor replaces the relay or the resistor under test replaces the relay.

[0076] The iron core T is used to wind an adjustable winding W of integer turns for the main circuit. 11 Main circuit fractional-turn adjustable winding W 12 1. Fixed-turn winding W2 from the circuit; 2. Modulation-specific winding W m And demodulation dedicated winding W d In this embodiment, the circuit through which the output current of the main current source flows is called the main circuit, which includes the main current source and the resistor to be measured, R. x Main circuit integer turn adjustable winding W 11 Micro-differential compensation module, main circuit fractional-turn adjustable winding W 12 The circuit through which the current flows from the current source is called the slave circuit, which includes the slave current source, the slave circuit fixed-turn winding W2, and the standard resistor R. s wait.

[0077] Among them, the main circuit integer-turn adjustable winding W 11 This is an adjustable winding with an integer number of turns connected in series in the main circuit. Its function is to adjust the magnetic flux generated by the main circuit current in the iron core T by changing the integer number of turns. Main circuit fractional-turn adjustable winding W 12 The adjustable-turn winding (W1) is connected in series in the output circuit of the differential compensation module. Its function is to fine-tune the magnetic flux generated by the main circuit current in the iron core T by changing the fractional number of turns. The fixed-turn winding (W2) is connected in series in the slave circuit, with a fixed number of turns. Its function is to make the slave circuit current generate magnetic flux in the iron core T. The modulation-specific winding (W1) is also included. mIts function is to generate a modulated magnetic flux signal in the iron core T. The windings W in the main and slave circuits... 11 W 12 The magnetic flux generated by the current in W2 in the iron core T cancels each other out, and the remaining magnetic flux is modulated by the dedicated winding W. m Modulation, in the dedicated demodulation winding W d The induced electromotive force is generated in the middle, and the voltage signal proportional to the residual magnetic flux is restored by the demodulation circuit. After being matched with the input range of the ADC by the conditioning module, the ADC finally collects the signal, digitizes it, and transmits it to the control module as sampling data.

[0078] Main circuit integer turn adjustable winding W 11 A switching matrix is ​​needed to control whether windings with different numbers of turns are connected to the main circuit. The switching matrix typically consists of multiple relays, and a drive module provides the drive signals to the switching matrix. The main circuit has an integer number of turns adjustable winding W. 11 The switch matrix and its driving module are referred to as the integer-turn switch matrix and the integer-turn driving module, respectively. As shown in Figure 1, the integer-turn switch matrix is ​​connected to the integer-turn driving module and the main circuit integer-turn adjustable winding W. 11 The integer-turn drive module is used to provide drive signals to the integer-turn switching matrix under the control commands of the control module, so as to drive the main circuit integer-turn adjustable winding W. 11 Different numbers of turns of windings are connected to the main circuit.

[0079] Similarly, the main circuit fractional-turn adjustable winding W 12 A switching matrix is ​​also needed to control whether windings with different numbers of turns are connected to the main circuit. The switching matrix typically consists of multiple relays, and the drive module provides the drive signals to the switching matrix. The main circuit's fractional-turn adjustable winding W... 12 The switch matrix and its driving module are referred to as the fractional-turn switch matrix and the fractional-turn driving module, respectively. As shown in Figure 1, the fractional-turn switch matrix is ​​connected to the fractional-turn driving module and the main circuit fractional-turn adjustable winding W. 12 The fractional-turn drive module is used to provide drive signals to the fractional-turn switching matrix under the control commands of the control module, so as to drive the main circuit fractional-turn adjustable winding W. 12 Different numbers of turns of windings are connected to the main circuit.

[0080] The differential compensation module is used to extract the main circuit current from the main circuit, attenuate it proportionally, and then output it to the main circuit fractional-turn adjustable winding W. 12 Differential compensation modules can be broadly classified into passive compensator types and active compensator types.

[0081] In the modulation module, the modulation circuit and the dedicated modulation winding W mConnection. The modulation module is used to modulate the residual magnetic flux inside the bridge of the DC current comparator, i.e., in the iron core T, to generate a modulated detection signal.

[0082] In the demodulation module, the demodulation circuit and the dedicated demodulation winding W d Connection; the demodulation module is used to demodulate the detection signal modulated by the DC current comparator bridge into a DC voltage signal.

[0083] The conditioning module is connected to both the demodulation circuit and the ADC. The conditioning module filters and amplifies the DC voltage signal output from the demodulation module, and outputs the conditioned voltage signal to the ADC.

[0084] The ADC (Analog-to-Digital Converter) is used to sample the conditioned voltage signal and send the sampled data to the control module. In the standard measurement mode of the DC current comparator bridge, the sampled data is used for feedback control to enable the slave circuit to track the current in the main circuit. During current source self-calibration, the control module calculates correction values ​​for the main and slave current sources based on the sampled data, and corrects the code values ​​received by the main and slave current sources based on these correction values, thus completing the self-calibration process for the main and slave current sources.

[0085] The control module is typically an embedded processor, such as an ARM or FPGA. In standard measurement mode, it generates and sends control commands for current setting, feedback, and switching. During self-calibration of the current source, the self-calibration process and correction algorithm are stored in the control module. After the user activates the corresponding function, the module automatically completes the calibration process, stores the calibration data, and automatically corrects the current upon exiting self-calibration mode.

[0086] Since the upper and lower parts of the bridge shown in Figure 1 use different power supply systems, an optical isolation module is set up to isolate the control module from all the analog circuits above through optical signals, so as to reduce the interference of the control module to the analog circuits.

[0087] The unbalanced voltage detection module has two inputs, connected to the resistor R to be measured. x and standard resistor R s It is connected to the high-side voltage, and its function is to detect the resistance R to be measured. x and standard resistor R s The unbalanced voltage between them.

[0088] To more clearly illustrate the implementation scheme of this application, the basic components of the DC current comparator bridge have been described above. Most modules of the DC current comparator bridge, such as the differential compensation module, switching matrix, drive module, modulation module, demodulation module, and conditioning module, may be implemented using different technical approaches in specific systems; these are not the focus of this application. However, regardless of the implementation scheme used for these modules, their basic functions can satisfy the implementation of the current source calibration method of this application, ultimately improving the accuracy of the current output in the original system.

[0089] Based on the DC current comparator bridge system structure shown in Figure 1, this application also proposes a current source calibration method, including the following steps 1 to 17.

[0090] Step 1: Switch the integer-turn switch matrix to enable the main circuit integer-turn adjustable winding W 11 The integer number of turns is equal to the fixed number of turns of the fixed-turn winding W2 in the secondary circuit; the fractional-turn switching matrix is ​​switched so that the fractional-turn adjustable winding W in the primary circuit... 12 The fractional number of turns is 0.

[0091] Specifically, the control module sends control commands to switch the main circuit integer-turn adjustable winding W. 11 An integer-turn switching matrix is ​​used to ensure that the integer number of turns is equal to the fixed number of turns of the fixed-turn winding W2 in the slave circuit, while simultaneously switching the fractional-turn adjustable winding W in the main circuit. 12 The fractional-turn switching matrix ensures that the fractional-turn count of the main circuit is 0. The proportional error of the winding turns is much smaller than the calibrated current error. At this time, the main and slave current sources induce magnetic flux in the iron core T through their respective windings and cancel each other out. The remaining magnetic flux is reflected as the output voltage through the modulation and demodulation modules.

[0092] Step 2: Switch the main current source and the secondary current source to the same current range, and short-circuit the terminals of the resistor under test by replacing the relay or connect it to the standby resistor R in the main circuit. y Replace the relay with a standard resistor to short-circuit the terminals or connect it to the standby resistor R in the slave circuit. z .

[0093] It should be noted that since the transconductance amplifier may have different nonlinear characteristics at different settings, it is recommended to perform the current source self-calibration process separately at all settings to obtain more accurate calibration data. In this embodiment, one setting is selected to illustrate the specific self-calibration method.

[0094] The bridge arm resistors (standard resistor R) in the master and slave circuits are connected. s and the resistance to be measured R xBoth belong to the bridge arm resistors. The current terminal of either resistor should be shorted or connected to an internal standby resistor. Note that DCCs typically have an internal standby resistor for this operation; if not, it can be connected to the bridge arm resistor (i.e., the standard resistor R). s Or the resistor to be measured R x Relays are installed at both ends and controlled to short-circuit. This application's method does not use an unbalanced voltage detection module; to prevent saturation due to unbalanced voltage generated during self-calibration, it is disconnected from the bridge circuit at this time.

[0095] Step 3: Denote the reference DAC of the main current source as DAC1 and the reference DAC of the secondary current source as DAC2. Divide the bit length N of DAC1 and DAC2 into high-order bits N. H and low-order N L It consists of two parts, and initializes all N bits of DAC1 and DAC2 to 0.

[0096] There are two ways to divide the reference DAC bit depth N.

[0097] Option 1, when the reference DAC uses the single DAC device shown in Figure 2, according to the formula... Determine the least significant bit N in the number of bits N. L The rest are high-order N H Where INL represents the maximum integral nonlinearity error of the reference DAC. That is, assuming the maximum integral nonlinearity error is INL, then the minimum number of bits greater than the maximum integral nonlinearity error INL is taken as N. L The rest are N H .

[0098] Option 2, when the reference DAC is a composite DAC consisting of dual DACs and a proportional adder, as shown in Figure 3, combines the output voltages of the two DACs (DACa and DACb) through an adder with a 1 / M resistance ratio. The resistance ratio of the proportional adder is set to M = 1 / 2. m Then the effective number of DACa is taken as the high-order N. H , take m as the lower bit N L The total number of digits is N = N H +N L The composite DAC is used as the reference DAC.

[0099] In this embodiment, a 16-bit single DAC device is used for illustration, i.e., N=16, divided into high-order bits N H =14 and the lower digit N L= 2. The number of bits N refers to the binary number of bits in the DAC, a fundamental parameter of the DAC. The high-order bits (or low-order bits) are those with greater weight, and the low-order bits are those with less weight. For example, the decimal number 1234 has four bits: the thousands and hundreds digits are considered high-order bits, and the tens and units digits are low-order bits. The binary representation is similar. The code value is the numerical value represented by the binary code. In scheme 2, DACa and DACb together constitute a composite DAC, where the high-order and low-order bits refer to the high and low-order bits of the composite DAC.

[0100] Step 4: Refresh the output voltages of DAC1 and DAC2 according to the currently received code value. Driven by the output voltages of DAC1 and DAC2, the main current source and the slave current source output current to the main circuit and the slave circuit respectively.

[0101] DAC stands for Digital-to-Analog Converter. "Digital" refers to numerical values ​​represented by binary code, and "analog" refers to the fact that voltage is an analog signal. The basic mode of a DAC is that when a set of binary codes (referred to as code values ​​in this application) is input, the DAC outputs a corresponding voltage. Each time a code value is input to the control module, the DAC output changes accordingly; "refreshing" is a term used to describe this change.

[0102] Step 5: Read the sampled data using the ADC, and record the reading as D. (i)(j) , where the subscript i represents the high-order bit value of DAC1 and j represents the high-order bit value of DAC2;

[0103] In this embodiment, the subscript i represents the high 14-bit code value of the current DAC1, and j represents the high 14-bit code value of the current DAC2; 0≤i,j≤2 14 -1.

[0104] Step 6, if the current Execute step 7; if the current Then the current loop ends, and the process jumps to step 8.

[0105] In this embodiment of the application, 2 14 -1 = 16383. If the current value is 0 ≤ j < 16383, proceed to step 7; if the current value is j = 16383, skip the next step and end the current loop.

[0106] Step 7: If i = j, increment the code value of DAC1 by 1, i.e., i = i + 1, and keep j unchanged; otherwise, increment the code value of DAC2 by 1, i.e., j = j + 1, and keep i unchanged; then jump to step 4.

[0107] The cyclic process changes the code values ​​of DAC1 and DAC2, either by increasing the code value of DAC1 by 1 or by increasing the code value of DAC2 by 1.

[0108] Step 8: After this round of iterations, the ADC has collected a total of [data / data]. Each sampled data point is denoted as...

[0109] During the loop, i and j change alternately. The end of this loop satisfies the termination condition of step 6, and thus, exactly the data is collected. A number.

[0110] Step 9, take The first of the sampled data The sampled data are grouped into pairs according to their sequential order. The difference d between each pair of adjacent sampled data is calculated by subtracting the previous value from the next value in each group. 2,k =D (k+1)(k) -D (k)(k) Where k takes the following values: And k is an integer, and a total of [number] calculations are performed. d 2,k .

[0111] In the same formula, k takes the same value. Here, k is a subscript number used to represent the sampled data obtained in step 8 in a unified form. For example, when k = 0, it is equivalent to d 2,0 =D (1)(0) -D (0)(0) In this embodiment of the application, k takes values ​​from 0 to 16382 in step 9, and a total of 16383 d values ​​are calculated. 2,k .

[0112] Step 10, d 2,k Summation, calculation yields

[0113] Step 11, according to d 2,k S2 calculates the DNL error e between adjacent code values ​​in the high-order bits of DAC2. 2，k ;Specifically,

[0114] In this embodiment of the application, k takes values ​​from 0 to 16382 in step 11, and a total of 16383 e are calculated. 2，k e 2，k This refers to the DNL error between adjacent code values ​​that the high 14 bits of DAC2 can represent. The DNL error value e obtained through self-calibration... 2，k This means that in regular measurements, a low N setting can be used. L = 2 bits are used to correct the DNL error of DAC2, thereby obtaining a more accurate current output.

[0115] DNL (Differential Non-Linearity) error, also known as differential nonlinearity error, is represented using the high 14 bits of the self-calibration process. One unit in the least significant bit of the high 14 bits is equal to four times (2 to the power of 2) one unit in the low 2 bits. In other words, the voltage represented by the low 2 bits is more precise than that represented by the high 14 bits. If the error value represented by the high 14 bits has a decimal part, it can be compensated for more precisely using the low 2 bits.

[0116] Step 12, according to e 2，k Calculate the correction value c for DAC2. 2,k ;Specifically,

[0117] Step 13, take The last sample data The sampled data are grouped into pairs according to their sequential order. The difference d between each pair of adjacent sampled data is calculated by subtracting the previous value from the next value in each group. 1,k =D (k)(k) -D (k)(k-1) Where k takes the following values: Total calculation d 1,k .

[0118] In this embodiment of the application, k takes values ​​from 1 to 16383 in step 13, and a total of 16383 d values ​​are calculated. 1,k Numerical value.

[0119] Step 14, d 1,k Summation, calculation yields

[0120] Step 15, according to d 1,k The DNL error e between adjacent code values ​​in the high-order bits of DAC1 is calculated using S1. 1,k ;Specifically,

[0121] In this embodiment of the application, k takes values ​​from 1 to 16383 in step 14, and a total of 16383 e are calculated. 1,k Numerical value. e 1，k This refers to the DNL error between adjacent code values ​​that the high 14 bits of DAC1 can represent. The meaning is the same as above.

[0122] Step 16, according to e 1,k Calculate the correction value c for DAC1. 1,k ;Specifically,

[0123] The correction value c obtained from self-calibration 1，k and c2，k Stored in the control module for use in regular measurement modes.

[0124] Step 17: When the DC current comparator bridge is in normal measurement mode, use the correction value c. 1，k and c 2，k Correct the code values ​​received from the main current source and the current source respectively.

[0125] When the DC current comparator bridge is in normal measurement mode, after the user sets the test current through the control module, the current value is converted into the corresponding DAC setting code value by the control module. Assuming the user sets the setting code value of a certain current source's corresponding DAC (e.g., DAC1) to D1, the code value is corrected according to steps 17.1 to 17.5 before being output to the reference DAC. The correction process described below will use the corrected value c... 1，k and c 2，k The subscript k is specifically replaced by values ​​such as D1H and D1L.

[0126] Step 17.1: Divide D1 into 14 bits and 2 bits in binary format. The high 14 bits are denoted as D1H and the low 2 bits are denoted as D1L.

[0127] Step 17.2, query c 1，k c in 1，D1H Calculate h = c 1，D1H +D1L. h is a variable set to simplify the expression.

[0128] Step 17.3, if Perform step 17.4;

[0129] If h < 0, then let D1H = D1H-1 Then return to step 17.2 and execute;

[0130] like Let D1H = D1H+1 Then return to step 17.2 to execute.

[0131] Step 17.4: Take D1L = h, and combine it with the current D1H to form the complete corrected code value D11, i.e.

[0132] Step 17.5: The control module sets the code value of DAC1 to D11 and outputs it to control the output voltage of DAC1.

[0133] When the current source reference DAC is a single DAC device, using a 16-bit DAC, the datasheet states that the integral nonlinearity is less than ±2 LSB. It should be noted that the overall nonlinearity error of the current source output also includes the nonlinearity error introduced by the subsequent transconductance amplifier; in this embodiment, this portion is referred to the DAC output as less than ±1 LSB. Therefore, the maximum overall integral nonlinearity error of the current source is ±3 LSB. Following the above method, this application can reduce the overall nonlinearity error of the current source output to within 1 LSB. When the current source reference DAC is a composite DAC, it is equivalent to improving the DAC's resolution, and more accurate data can be obtained through a self-calibration process.

[0134] Following the method described in the above embodiment, the error of the current source in Scheme 1 can be reduced by several times. For even higher accuracy, Scheme 2 can be used. In Scheme 2, the DAC in the current source is composed of two devices, DACa and DACb, combined using a proportional adder. In this embodiment, DACa and DACb are selected as 14-bit DAC devices of the same model, with a nonlinearity error of less than 1 LSB. The resistance ratio M of the proportional adder is set to 1 / 2. m This causes the output voltages of DACa and DACb to be 1 / 2 6 =1 / 64 of the output, then N H =14, N L =m=6, the total effective number of bits for the composite DAC is N=20 bits. It should be noted that in this Scheme 2, only the high 6 bits of DACb are used; the unused low 8 bits are simply set to zero. The subsequent self-calibration and correction procedures are the same as in Scheme 1 and will not be repeated. Using Scheme 2, the nonlinearity error of the overall current source output can be reduced by tens of times, i.e., 1 to 2 orders of magnitude. Scheme 2 improves the effective resolution of the DAC. During error measurement and correction, it can operate with a resolution of less than 1 LSB, thus improving the effect of error correction.

[0135] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A direct current comparator bridge characterized by, include: The system comprises a main current source, a slave current source, standard resistor terminals, resistor terminals under test, an iron core, an integer-turn adjustable winding of the main circuit, an integer-turn switch matrix, an integer-turn drive module, a fractional-turn adjustable winding of the main circuit, a fractional-turn switch matrix, a fractional-turn drive module, a fixed-turn winding of the slave circuit, a differential compensation module, a modulation module, a demodulation module, a conditioning module, an ADC, and a control module; the modulation module includes a modulation circuit and a dedicated modulation winding; the demodulation module includes a dedicated demodulation winding and a demodulation circuit. The control module is connected to the main current source, the slave current source, the integer turns drive module, the fractional turns drive module, the differential compensation module, and the ADC respectively. The main current source includes a reference DAC and a transconductance amplifier; the reference DAC receives code values ​​from the control module and outputs the voltage corresponding to the code values ​​to the transconductance amplifier; the transconductance amplifier converts the voltage signal output by the reference DAC into a current signal; the sampling resistor in the transconductance amplifier is switched by a switch to realize current level switching; the slave current source has the same structure as the main current source. The standard resistor terminal and the fixed number of turns winding of the slave circuit are connected to the slave circuit where the slave current source is located; the standard resistor terminal is used to connect an external standard resistor, a standard resistor to replace a relay, or a slave circuit standby resistor; The terminals of the resistor under test, the main circuit integer-turn adjustable winding, the main circuit fractional-turn adjustable winding, and the differential compensation module are connected in the main circuit where the main current source is located; the terminals of the resistor under test are used to connect an external resistor under test, and the resistor under test can replace a relay or a standby resistor in the main circuit. The iron core is used to wind an adjustable winding with an integer number of turns in the main circuit, an adjustable winding with a fractional number of turns in the main circuit, a winding with a fixed number of turns in the slave circuit, a special winding for modulation, and a special winding for demodulation. The integer-turn switch matrix is ​​connected to the integer-turn drive module and the main circuit integer-turn adjustable winding, respectively. The integer-turn drive module is used to provide drive signals to the integer-turn switch matrix under the control command of the control module, so as to connect different number of turns of the main circuit integer-turn adjustable winding to the main circuit. The fractional-turn switch matrix is ​​connected to the fractional-turn drive module and the main circuit fractional-turn adjustable winding, respectively. The fractional-turn drive module is used to provide drive signals to the fractional-turn switch matrix under the control command of the control module, so as to connect different number of turns of the main circuit fractional-turn adjustable winding to the main circuit. The differential compensation module is used to extract the main circuit current from the main circuit and output it to the main circuit fractional-turn adjustable winding after proportional attenuation. The modulation circuit is connected to a dedicated modulation winding; the modulation module is used to modulate the residual magnetic flux in the iron core to generate a modulated detection signal. The demodulation circuit is connected to a dedicated demodulation winding; the demodulation module is used to demodulate the modulated detection signal into a DC voltage signal. The conditioning module is connected to the demodulation circuit and the ADC respectively; the conditioning module is used to filter and amplify the DC voltage signal output by the demodulation module, and output the conditioned voltage signal to the ADC. The ADC is used to sample the conditioned voltage signal and send the sampled data to the control module; The control module is used to calculate the correction values ​​corresponding to the main current source and the slave current source based on the sampled data, and to correct the code values ​​received by the main current source and the slave current source based on the correction values, thereby completing the self-calibration of the main current source and the slave current source.

2. The DC current comparator bridge according to claim 1, characterized in that, The reference DAC uses a single DAC device.

3. The DC current comparator bridge of claim 1, wherein, The reference DAC is a composite DAC consisting of dual DACs and a proportional adder; the dual DACs include a first DAC and a second DAC, denoted as DACa and DACb, respectively.

4. A current source self-calibration method for a direct current comparator bridge, characterized by, The current source is applied to the DC current comparator bridge according to any one of claims 1-3; the current source calibration method includes: Step 1: Switch the integer turns switching matrix so that the number of integer turns in the main circuit's adjustable integer turns winding is equal to the number of fixed turns in the slave circuit's fixed turns winding; switch the fractional turns switching matrix so that the number of fractional turns in the main circuit's adjustable fractional turns winding is 0. Step 2: Switch the main current source and the secondary current source to the same current range. Short-circuit the terminals of the resistor under test by replacing the relay with the resistor under test or connect it to the standby resistor of the main circuit. Short-circuit the terminals of the standard resistor by replacing the relay with the standard resistor or connect it to the standby resistor of the secondary circuit. Step 3, record the reference DAC of the main current source as DAC1, and the reference DAC of the slave current source as DAC2, divide the bit number N of DAC1 and DAC2 into high bit N H and low bit N L two parts, initialize all N bit values of DAC1 and DAC2 as 0; Step 4: Refresh the output voltages of DAC1 and DAC2 according to the currently received code value. Driven by the output voltages of DAC1 and DAC2, the main current source and the slave current source output current to the main circuit and the slave circuit respectively. Step 5: Read the sampled data using the ADC, and record the reading as D. (i)(j) , where the subscript i represents the high-order bit value of DAC1 and j represents the high-order bit value of DAC2; Step 6, if the current perform step 7; if the current Then the current loop ends, and the process jumps to step 8; Step 7: If i = j, increment the code value of DAC1 by 1, i.e., i = i + 1, and keep j unchanged; otherwise, increment the code value of DAC2 by 1, i.e., j = j + 1, and keep i unchanged; then jump to step 4. Step 8, after the end of this round of cycle, ADC has collected a total of a sample data, denoted as Step 9, take the first The sampled data are grouped into pairs according to their sequential order. The difference d between each pair of adjacent sampled data is calculated by subtracting the previous value from the next value in each group. 2，k =D (k+1)(k) -D (k)(k) Where k takes the following values: and k is an integer, co-computed d 2,k ; Step 10, d 2,k summed, resulting in Step 11, according to d 2,k and S2 to calculate the DNL error e between the high adjacent code values of DAC2 2，k ; Step 12, according to e 2，k Calculating the correction value c of the DAC2 2,k ; Step 13, take post in the sampling data The sampled data are grouped into pairs according to their sequential order. The difference d between each pair of adjacent sampled data is calculated by subtracting the previous value from the next value in each group. 1,k =D (k)(k) -D (k)(k-1) Where k takes the following values: Co-computing d 1,k ; Step 14, to d 1,k sum, calculated Step 15, according to d 1,k and S1 calculate the DNL error e between the high adjacent code values of DAC1 1，k ; Step 16, according to e 1，k Calculating the correction value c of DAC1 1,k ; Step 17. Use the correction value c when the DC current comparator bridge is in the normal measurement mode. 1，k and c 2,k correct the code values received from the master and slave current sources, respectively.

5. The current source self-calibration method of claim 4, wherein, The step 11, according to d 2,k and S2 calculate the DNL error e between the high adjacent code values of DAC2 2,k , specifically comprising:

6. The current source self-calibration method of claim 4, wherein, Step 12, according to e 2,k Calculate the correction value c for DAC2. 2,k Specifically, it includes:

7. The current source calibration method according to claim 4, characterized in that, Step 15, according to d 1,k The DNL error e between adjacent code values ​​in the high-order bits of DAC1 is calculated using S1. 1,k Specifically, it includes:

8. The current source calibration method according to claim 4, characterized in that, Step 16, according to e 1,k Calculate the correction value c for DAC1. 1,k Specifically, it includes:

9. The current source self-calibration method of claim 4, wherein, The step 3 divides the bit number N of DAC1 and DAC2 into high bit N H and low bit N L two parts, specifically comprising: When a single DAC device is used for the reference DAC, the equation Determine the least significant bit N in the number of bits N. L The rest are high-order N H Where INL is the maximum integral nonlinearity error of the reference DAC.

10. The current source self-calibration method of claim 4, wherein, The step 3 divides the bit number N of DAC1 and DAC2 into high bit N H and low bit N L two parts, specifically comprising: When the reference DAC is a composite DAC consisting of dual DACs and a proportional adder, if the resistance ratio of the proportional adder is 1 / 2... m Then the effective number of DACa is taken as the high-order N. H , take m as the lower bit N L The total number of digits is N = N H +N L Reference DAC.

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