Signal envelope detection circuit and chip

Abstract

Embodiments of the present disclosure provide a signal envelope detection circuit and chip. The signal envelope detection circuit comprises: N cascaded first amplification circuits, an input end of a first-stage first amplification circuit being used for receiving a target input signal; M cascaded attenuation circuits, an input end of a first-stage attenuation circuit being used for receiving the target input signal; M second amplification circuits, an input end of each second amplification circuit being correspondingly connected to an output end of one attenuation circuit; and a plurality of rectifiers, an output end of each first amplification circuit and an output end of each second amplification circuit each being connected to an input end of one rectifier. Output ends of all of the rectifiers are connected together and are used for outputting a target output signal. N and M are both integers greater than 1, and amplification multiples of the N first amplification circuits are the same as amplification multiples of the M second amplification circuits. The embodiments of the present disclosure can expand the dynamic range of the signal envelope detection circuit and improve detection accuracy.

Description

A signal envelope detection circuit and chip

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 202411910608.8, filed on December 23, 2024, entitled “A Signal Envelope Detection Circuit and Chip”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of communication technology, and in particular to a signal envelope detection circuit and chip. Background Technology

[0004] In communication systems, signal detection circuits and chips play a crucial role in extracting information and recovering original data to ensure the accuracy and integrity of information during transmission. In radar systems, signal detection circuits and chips are used to detect reflected signals, thereby analyzing key information such as the target's position, velocity, and direction.

[0005] Functionally, signal detection circuits and chips can be categorized into signal envelope detection and RMS detection. Signal envelope detection accurately captures the amplitude envelope of radio frequency signals, thereby extracting useful signal information. The dynamic range of the detectable signal is one of the key performance indicators of a signal envelope detection chip. Expanding the dynamic range of signal envelope detection circuits will facilitate their further application in communication and radar systems, providing stronger support for modern communication and radar technologies. Summary of the Invention

[0006] This disclosure provides a signal envelope detection circuit and chip with a large dynamic range and high linearity.

[0007] In a first aspect, embodiments of this disclosure provide a signal detection circuit, including:

[0008] N cascaded first amplifier circuits, the input terminal of the first stage first amplifier circuit is used to receive the target input signal, and the input terminals of the second to Nth stage first amplifier circuits are used to receive the output signal of the previous stage first amplifier circuit;

[0009] M cascaded attenuation circuits, the input terminal of the first-stage attenuation circuit is used to receive the target input signal, and the input terminals of the second to Mth-stage attenuation circuits are used to receive the output signal of the previous stage attenuation circuit.

[0010] M second amplifier circuits, with the input of each second amplifier circuit connected to the output of the corresponding attenuation circuit;

[0011] Multiple rectifiers are used, with the output of each first amplifier circuit connected to the input of the corresponding rectifier, and the output of each second amplifier circuit connected to the input of the corresponding rectifier; the outputs of all rectifiers are connected together to output the target output signal.

[0012] Where N and M are both integers greater than 1; the amplification factors of the first amplifier circuit and the second amplifier circuit are the same.

[0013] In a second aspect, embodiments of this disclosure provide a signal inclusion detection chip, including the signal envelope detection circuit as described in the first aspect.

[0014] The beneficial effects of this embodiment are as follows: each amplification circuit (first amplification circuit and second amplification circuit) uses the exact same amplification factor, and an attenuation circuit is connected before each second amplification circuit. In this way, each second amplification circuit receives the attenuated signal, which is then amplified and sent to the rectifier. Thus, when facing a high-power input signal, although the output of the amplification link composed of N cascaded first amplification circuits reaches saturation, the signal can be attenuated by the attenuation circuit first, so that the high-power input signal falls into the operating range of the rectifier corresponding to the attenuation circuit. Then, the second amplification circuit and the rectifier convert the high-power part, realize logarithmic conversion, and increase the dynamic range.

[0015] Furthermore, since the attenuation circuit has virtually no impact on linearity, and the first and second amplifier circuits have the same amplification factor, the linearity of the first and second amplifier circuits is the same. This makes the output linearity of the rectifier connected to the first and second amplifier circuits basically consistent, improving the deviation caused by the gain difference and enhancing the detection accuracy.

[0016] Meanwhile, an attenuation circuit is also connected before the first-stage second amplifier circuit. This attenuation circuit can cancel out the amplification factor of the first-stage second amplifier circuit, so that the power of the output signal of the first second amplifier circuit falls within the range of the rectifier, ensuring the integrity of the current splicing. Attached Figure Description

[0017] Figure 1 is a schematic diagram of the composition structure of a signal envelope detection circuit provided in an embodiment of this disclosure;

[0018] Figure 2 is a schematic diagram of the composition structure of a signal envelope detection circuit provided in an embodiment of this disclosure;

[0019] Figure 3 is a schematic diagram of the composition structure of a limiting amplifier provided in an embodiment of this disclosure;

[0020] Figure 4 is a schematic diagram of the composition structure of a limiting amplifier provided in an embodiment of this disclosure;

[0021] Figure 5 is a schematic diagram of the variation curve of the output current of a rectifier stage by the input power according to an embodiment of the present disclosure.

[0022] Figure 6 is a schematic diagram comparing an ideal logarithmic curve and an actual logarithmic curve provided in an embodiment of this disclosure;

[0023] Figure 7 is a schematic diagram comparing the error of an ideal logarithmic curve and the error of an actual logarithmic curve according to an embodiment of this disclosure;

[0024] Figure 8 is a schematic diagram of the composition structure of a signal envelope detection circuit provided in an embodiment of this disclosure;

[0025] Figure 9 is a schematic diagram of the composition structure of a signal envelope detection circuit provided in an embodiment of this disclosure;

[0026] Figure 10 is a schematic diagram of the composition structure of a signal envelope detection circuit provided in an embodiment of this disclosure;

[0027] Figure 11 is a schematic diagram of the composition structure of a signal envelope detection circuit provided in an embodiment of this disclosure;

[0028] Figure 12 is a schematic diagram of the composition structure of a signal envelope detection circuit provided in an embodiment of this disclosure;

[0029] Figure 13 is a schematic diagram of the composition structure of a rectifier provided in an embodiment of this disclosure;

[0030] Figure 14 is a schematic diagram of the variation curve of the output current of a rectifier stage by the input power according to an embodiment of the present disclosure;

[0031] Figure 15 is a comparative schematic diagram of an ideal logarithmic curve and an actual logarithmic curve provided in an embodiment of this disclosure;

[0032] Figure 16 is a schematic diagram comparing the error of an ideal logarithmic curve and the error of an actual logarithmic curve according to an embodiment of this disclosure. Detailed Implementation

[0033] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0035] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0036] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0037] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms used in the embodiments of this disclosure will be explained. The nouns and terms used in the embodiments of this disclosure shall be interpreted as follows:

[0038] milliwatts decibels (dBm);

[0039] decibels (dB);

[0040] Microamperes (μA);

[0041] Ampere (A);

[0042] Volt (V);

[0043] Bipolar Junction Transistor (BJT);

[0044] Power supply voltage (VDD).

[0045] A common structure for signal envelope detection circuits (also referred to as logarithmic envelope detection circuits, detector circuits, detectors, etc.) is a cascaded architecture of limiting amplifiers and rectifiers. As shown in Figure 1, this signal envelope detection circuit includes N cascaded limiting amplifiers (limiting amplifier 1 to limiting amplifier N), N+1 rectifiers (rectifier 1 to rectifier N+1), and a load resistor, where N is a positive integer. The output of each limiting amplifier is connected to the input of a rectifier, and the input of limiting amplifier 1 is also connected to the input of a rectifier. The outputs of the N+1 rectifiers are connected together to output the signal obtained from the envelope detection. Typically, the output signal of the rectifier is a current signal. In Figure 1, the signal envelope detection circuit also includes a load resistor, which converts the current signal into a voltage signal, resulting in the output voltage shown in Figure 1. Both the limiting amplifiers and rectifiers have two-terminal inputs, and the N limiting amplifiers form an amplification link. The lower end of the dynamic range of a signal envelope detection circuit is its sensitivity, and the upper end is its input power limit. How to effectively extend the dynamic range of the signal envelope detection circuit is a problem that needs to be solved.

[0046] Based on Figure 1, as shown in Figure 2, the amplification stage consists of the limiting amplifiers and rectifiers shown in Figure 1. However, in Figure 2, the limiting amplifiers in the amplification stage are represented by A1, and the rectifier numbers are not shown. Furthermore, the number of rectifiers in the amplification stage is the same as the number of limiting amplifiers A1. R DET Indicates the load resistance, V DET The output voltage is represented by V; the output signals of the first to Nth limiting amplifiers A1 are sequentially denoted as V. p1 V p2 ... V pN To improve the upper limit of dynamic range, this embodiment adds an attenuation stage to the amplification link. As shown in Figure 2, the attenuation stage includes multiple attenuation circuits B0, multiple limiting amplifiers A0, and multiple rectifiers. The number of attenuation circuits B0 is one less than the number of limiting amplifiers A0. Assuming that there are a total of M limiting amplifiers A0, where M is a positive integer, the input signals of the 1st to the Mth limiting amplifiers A0 are sequentially denoted as V. att1 V att2 ... V attM The output signals of the first to the Mth limiting amplifiers A0 are sequentially denoted as V. n1 V n2 ... V nM Among them, the first limiting amplifier A0 is a unit limiting amplifier with a gain of 1, which directly receives the input signal V from the signal envelope detection circuit. IN The remaining limiting amplifiers A0 receive the signal attenuated by the attenuation circuit B0. The output of each limiting amplifier A0 is also connected to the input of a rectifier. The outputs of the rectifiers in the amplification stage and the rectifiers in the attenuation stage are connected together, outputting the signal V. DET Therefore, when dealing with high-power signals, if the amplification stage becomes saturated, the envelope of the high-power signal can be detected through the attenuation stage.

[0047] It should be noted that the principle behind the attenuation stage increasing the upper limit of the dynamic range is as follows:

[0048] The limiting amplifier A1 behaves as a linear amplifier within its input range. When the output reaches the designed limiting value, the output remains constant, thus limiting the dynamic range. The signal envelope detection circuit, however, typically has a lower limit to its dynamic range. When the input is below this lower limit, the signal envelope detection circuit outputs its minimum value. When the input is above the lower limit but within the linear operating range, the signal envelope detection circuit converts the input into a logarithmic output. When the input exceeds the linear operating range, the output may still increase with the input, but the relationship is no longer logarithmic. In this case, an attenuation circuit is needed. When the input power exceeds the upper limit of the amplification stage, the attenuation circuit in the attenuation stage attenuates the excess power to detect the attenuated power signal. The rectifier converts the voltage output of the limiting amplifier into current; all currents are summed to complete the splicing.

[0049] For example, suppose the input dynamic range of the signal envelope detection circuit in Figure 2 is 80dBm (-50dBm to 30dBm), and the output current range is 100μA to 900μA. The output current changes linearly with the power in dBm, equivalent to taking the logarithm of the absolute power value. The rectifier's operating range is assumed to be 0 to 10dBm. When the input signal is below 0dBm, the rectifier has no output; when the input signal is above 10dBm, the rectifier output saturates; only when the input signal is between 0 and 10dBm does the rectifier output current change linearly. Therefore, each stage of the limiting amplifier A1 needs to amplify the signal input to the rectifier to the 0 to 10dBm range before it can be detected by the rectifier.

[0050] Assume the amplification stage includes five limiting amplifiers A1, each with a dynamic range of 10dBm, resulting in a total dynamic range of 50dBm (-50dBm to 0dBm) for the entire amplification stage. Each stage has a gain of 10dB. The first limiting amplifier A1 amplifies the current from -10dBm to 0dBm to 10dBm, corresponding to the output current of the first rectifier. The first and second limiting amplifiers A1 amplify the current from -20dBm to -10dBm to 0dBm, corresponding to the output current of the second rectifier. Each rectifier can output a corresponding current; the first to third limiting amplifiers A1 amplify -30dBm to -20dBm to 0 to 10dBm, and the corresponding third rectifier can output a corresponding current; the first to fourth limiting amplifiers A1 amplify -40dBm to -30dBm to 0 to 10dBm, and the corresponding fourth rectifier can output a corresponding current; the first to fifth limiting amplifiers A1 amplify -50dBm to -40dBm to 0 to 10dBm, and the corresponding fifth rectifier can output a corresponding current.

[0051] When the input dynamic range is 0dBm to 30dBm, it exceeds the dynamic range of the amplification stage. Therefore, after the attenuation circuit attenuates the input signal, it falls into the dynamic range of the attenuation stage (the attenuation stage can handle a larger signal power).

[0052] Assuming the attenuation stage includes three limiting amplifiers A0, it also includes two attenuation circuits B0 and three rectifiers. Since the input signal power falls within the rectifier's operating range when it's between 0dBm and 10dBm, the first limiting amplifier A0 in the attenuation stage directly outputs the 0dBm to 10dBm signal at a unity gain (corresponding to a gain of 1) to the corresponding rectifier input. The rectifier then converts this into the corresponding current. In other words, the first limiting amplifier A0 is a single-gain amplifier with a gain of 1. The attenuation stage consists of three circuits: a first attenuator (B0) attenuates 10dBm–20dBm to 0–10dBm, and a second attenuator (A0) outputs a unity-gain output to the corresponding rectifier input, which then converts the current to the corresponding current. The first and second attenuator circuits (B0 and B0) attenuate 20dBm–30dBm to 0dBm–10dBm, and a third attenuator (A0) outputs a unity-gain output to the corresponding rectifier input, which then converts the current to the corresponding current. It is evident that the attenuator (A0) in the attenuation stage is a unity-gain amplifier with a gain of 1, and the attenuation circuit (B0) can be a passive attenuation network.

[0053] Ultimately, the attenuation stage and the amplification stage work together to complete the conversion from -50dBm to 30dBm, and then splice them together to obtain the final output signal. In this example, each stage corresponds to a dynamic range of 10dBm; therefore, the gain of each stage in the amplification stage and the attenuation stage must be 10dB and -10dB, respectively. In the attenuation stage, except for the first limiting amplifier A0, the remaining stages attenuate by 10dB through the attenuation circuit B0, and each limiting amplifier A0 has unity gain.

[0054] Alternatively, in the attenuation stage, the first limiting amplifier A0 has a gain of 0dB (corresponding to a gain factor of 1), and the gain of each subsequent attenuation circuit B0 plus the gain of limiting amplifier A0 equals -10dB. This maintains a consistent structure for limiting amplifier A0 throughout the attenuation stage, with all amplifiers having a gain of 0dB. Therefore, only the attenuation circuit B0 needs to be designed.

[0055] In summary, in the above scheme, the first-stage limiting amplifier A0 in the attenuation stage of the signal envelope detection circuit directly receives the input signal V. IN The current is not passed through the attenuation circuit B0 because it is necessary to achieve complete current splicing.

[0056] Specifically, in a signal envelope detector circuit with attenuation stages, the gain of each limiting amplifier A1 in the amplification stage is uniformly A1 (A1 > 1). The first stage in the attenuation stage is a unity-gain limiting amplifier, meaning the gain of the first-stage limiting amplifier A0 is A0 = 1. The signal is then attenuated stage by stage via attenuation circuit B0, and after attenuation, it is still output to the rectifier via a unity-gain limiting amplifier A0. When the input signal to the rectifier enters its linear region, it begins to respond with a corresponding output current. Ultimately, the output currents of all rectifiers can be pieced together to form a complete logarithmic curve corresponding to different signal power values. It can be understood that increasing the number of limiting amplifier stages in the amplification stage extends the lower limit of the detector's dynamic range, and increasing the number of limiting amplifier stages in the attenuation stage extends the upper limit of the detector's dynamic range.

[0057] The structures of limiting amplifier A1 in the amplification stage and limiting amplifier A0 in the attenuation stage are shown in Figures 3 and 4. Limiting amplifier A1 consists of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor M1, a second transistor M2, and a first wake source I1; limiting amplifier A0 consists of a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a third transistor M3, a fourth transistor M4, and a second wake source I2. Both limiting amplifiers A1 and A0 can be dual-ended input and dual-ended output. IN+ This indicates its positive inverting input signal, V IN- This indicates its inverted input signal, V OUT+ This indicates its positive phase output signal, V OUT- This indicates its inverted output signal, with the first wake source I1 and the second wake source I2 used to provide the wake current. Each transistor can be a BJT.

[0058] As shown in Figures 3 and 4, limiting amplifier A0 and limiting amplifier A1 have the same structure, that is, their circuit topology, the types and quantities of components, and the connection relationships between components are the same. Only the resistance values, current, and other parameters are different, resulting in different gains (while maintaining the same swing). For ease of distinction, the component labels are different in Figures 3 and 4.

[0059] The limiting values ​​of limiting amplifiers A1 and A0 are kept consistent by maintaining the tail current and load resistance (i.e., the resistors connected to the collectors of each BJT: first resistor R1, second resistor R2, fifth resistor R5, and sixth resistor R6). The difference in gain between the two is mainly achieved by changing the resistance values ​​of the negative feedback resistors connected to the emitter stage of each BJT (i.e., third resistor R3, fourth resistor R4, seventh resistor R7, and eighth resistor R8).

[0060] Based on the aforementioned example, Figure 5 illustrates the stage-by-stage output current (I) of the rectifier. DETThe curves (unit: A) show the variation of the input power (Pin, unit: dBm) of the signal envelope detection circuit with the input power of the signal envelope detection circuit. The solid line represents the output of the five amplification stage rectifiers, and the dashed line represents the output of the three attenuation stage rectifiers. Figure 6 shows a comparison of the corresponding ideal logarithmic curve and the actual logarithmic curve. The horizontal axis represents the input power (Pin, unit: dBm) of the signal envelope detection circuit, and the vertical axis represents the output voltage (V) of the signal envelope detection circuit. DET (The unit is V); Figure 7 shows a schematic diagram comparing the error of the corresponding ideal logarithmic curve and the error of the actual logarithmic curve. The horizontal axis is the input power (Pin, in dBm) of the signal envelope detection circuit, and the vertical axis is the dB linear error of the signal envelope detection circuit after subtracting the ideal output from the output, in dB.

[0061] The inventors discovered that because the amplifiers used in the attenuation stage and the amplification stage have different gains, their linearity differs. Generally, a lower amplifier gain results in better linearity, while a higher gain leads to worse linearity. Therefore, the linearity of the attenuation stage is significantly better than that of the amplification stage. Better linearity means that the amplifier can maintain a gain similar to that of a small signal even with a large signal, whereas poor linearity cannot. Thus, the limiting amplifier in the attenuation stage can maintain a high gain even with a high input power pin, resulting in a relatively large current slope at the rectifier output. Conversely, the amplifier in the amplification stage cannot maintain a high gain even with a high input power pin. Therefore, as shown in Figure 5, the output current slope of the rectifier in the amplification stage is lower than that of the rectifier in the attenuation stage, resulting in the concave shape shown in Figure 5. Because of this concave shape in Figure 5, the logarithmic curve and logarithmic curve error of the signal envelope detection circuit also differ significantly from the ideal state, as shown in Figures 6 and 7.

[0062] In the logarithmic envelope detector circuit with attenuation stages described above, the attenuation and amplification stages use limiting amplifiers with different gains (but the same swing). Although the rectifier input voltage exhibits a progressively larger A1-fold relationship for small signals, a splicing dip occurs for large signals due to the difference in linearity between the attenuation and amplification stage limiting amplifiers (generally, the higher the gain, the worse the linearity). This ultimately leads to a large logarithmic error in the actual logarithmic curve, reducing the accuracy of signal detection.

[0063] To extend the dynamic range of the signal envelope detection circuit and ensure the accuracy of signal detection while avoiding dips in current splicing, this disclosure also provides a signal envelope detection circuit. As shown in FIG8, the signal envelope detection circuit 10 includes:

[0064] N cascaded first amplifier circuits 101, the input terminal of the first stage first amplifier circuit 101 is used to receive the target input signal, and the input terminals of the second to Nth stage first amplifier circuits 101 are used to receive the output signal of the previous stage first amplifier circuit 101.

[0065] M cascaded attenuation circuits 102, the input terminal of the first-stage attenuation circuit 102 is used to receive the target input signal, and the input terminals of the second to Mth-stage attenuation circuits 102 are used to receive the output signal of the previous stage attenuation circuit 102.

[0066] M second amplifier circuits 103, the input terminal of each second amplifier circuit 103 is connected to the output terminal of the corresponding attenuation circuit 102; wherein, each second amplifier circuit 103 can correspond to one attenuation circuit 102;

[0067] Multiple rectifiers 104 are provided, with the output terminal of each first amplifier circuit 101 and the output terminal of each second amplifier circuit 103 connected to the input terminal of the corresponding rectifier 104; the output terminals of all rectifiers 104 are connected together to output the target output signal; wherein, each first amplifier circuit 101 can correspond to one rectifier 104, and each second amplifier circuit 103 can correspond to one rectifier 104.

[0068] Where N and M are both integers greater than 1; the amplification factors of the first amplifier circuit 101 and the second amplifier circuit 103 are the same.

[0069] It should be noted that, as shown in Figure 8, only one serial number 101 is shown, and the first-stage first amplifier circuit 101 is denoted as first amplifier circuit 1, the second-stage first amplifier circuit 101 is denoted as first amplifier circuit 2, ..., and the Nth-stage first amplifier circuit 101 is denoted as first amplifier circuit N. The output signal of each first amplifier circuit 101 is denoted as V in sequence. p1 V p2 V p3 ... V pN Only one serial number 102 is shown, and the first-stage attenuation circuit 102 is denoted as attenuation circuit 1, the second-stage attenuation circuit 102 as attenuation circuit 2, ..., the Mth-stage attenuation circuit 102 as attenuation circuit M, and the output signal of each attenuation circuit 102 is denoted as V in sequence. att1 V att2 V att3 ... V attM Only one serial number 103 is shown, and the first-stage second amplifier circuit 103 is denoted as second amplifier circuit 1, the second-stage second amplifier circuit 103 is denoted as second amplifier circuit 2, ..., the Mth-stage second amplifier circuit 103 is denoted as second amplifier circuit M, and the output signal of each second amplifier circuit 103 is denoted as V in sequence. n1 Vn2 V n3 ... V nM .

[0070] It should also be noted that, in order to distinguish it from the input and output signals of the internal components of the circuit, the overall input signal of the signal envelope detection circuit 10 is denoted as the target input signal, and the overall output signal is denoted as the target output signal.

[0071] In this example, the output of each first amplifier circuit 101 is connected to a rectifier 104. In other examples, the input of the first stage first amplifier circuit 101 can also be connected to a rectifier 104, which is not specifically limited. In the signal envelope detection circuit 10 shown in Figure 8, there are N+M rectifiers 104 (only two numbers 104 are shown). The N first amplifier circuits 101 and the connected N rectifiers 104 form an amplification stage, and the N rectifiers 104 in the amplification stage are sequentially labeled as rectifier 1, rectifier 2, ..., rectifier N; the M second amplifier circuits 103 and the connected M attenuation circuits 102 and M rectifiers 104 (rectifiers N+1 to rectifiers N+M) form an attenuation stage.

[0072] Here, both the first amplifier circuit 101 and the second amplifier circuit 103 are limiting amplifiers. The limiting amplifier amplifies the received signal and limits the amplitude of the output signal to a fixed value; hence the name limiting amplifier. Its function is to amplify the signal by a certain factor while limiting the swing. The rectifier 104's main function is to convert the stage-by-stage output signal (AC voltage) of the limiting amplifier into a DC current. It has the characteristic that the output current and its input voltage amplitude are logarithmically related; that is, the rectifier's main function is to convert AC voltage into DC current output.

[0073] It should also be noted that in this embodiment, the amplification factors of the N first amplifier circuits 101 and the M second amplifier circuits 103 are all equal, that is, the gains are all equal, and the swing of the N first amplifier circuits 101 and the M second amplifier circuits 103 is also equal, so that the output current slope of all rectifiers is equal, thereby avoiding the problem of uneven splicing of the output current of rectifier 104; avoiding the situation of depression or protrusion caused by the unequal amplification factors of each amplifier circuit.

[0074] Meanwhile, an attenuation circuit 102 is connected before the first second amplifier circuit 103 to attenuate the signal to cancel out the amplification factor of the second amplifier circuit 103, so that the output of the first second amplifier circuit 103 can fall within the dynamic range of the rectifier N+1, ensuring the integrity of the splicing.

[0075] Since the amplification circuits (first amplification circuit 101 and second amplification circuit 103) of the attenuation stage and the amplification stage in this embodiment of the present disclosure use the same amplification factor (i.e., the same gain), and each second amplification circuit 103 in the attenuation stage is connected to an attenuation circuit 102, each second amplification circuit 103 receives the attenuated signal, amplifies it, and then sends it to the rectifier 104. Thus, when facing a high-power input signal, although the output of the amplification stage reaches saturation, the signal can be attenuated by the attenuation circuit 102 in the attenuation stage, and then converted by the second amplification circuit 103 and the rectifier 104 to achieve logarithmic conversion. Furthermore, since the attenuation circuit 102 has virtually no impact on linearity, and the first amplification circuit 101 and the second amplification circuit 103 have the same gain, the linearity of the first amplification circuit 101 and the second amplification circuit 103 is the same, making the output linearity of the rectifier 104 of the amplification stage and the attenuation stage basically consistent, improving the deviation due to gain difference and improving the detection accuracy.

[0076] In some embodiments, the amplification factor of the first amplifier circuit 101 and the second amplifier circuit 103 is A1, and the amplification factor of the attenuation circuit 102 is 1 / A1; wherein, A1 is greater than 1.

[0077] It should be noted that in this embodiment, the amplification factor A1 of both the first amplifier circuit 101 and the second amplifier circuit 103 is greater than 1, meaning that neither the first amplifier circuit 101 nor the second amplifier circuit 103 is a unity-gain amplifier, but rather has an actual amplification effect on the signal. Meanwhile, to ensure effective detection even with large signal inputs, the input signal of each stage of the second amplifier circuit 103 is attenuated by an attenuation circuit 102 connected to its input terminal, reducing the high-power signal to within the dynamic range of the second amplifier circuit 103, thereby enabling successful detection.

[0078] It should also be noted that, for better splicing, the amplification factor of each attenuation circuit 102 is 1 / A1. Thus, in the signal envelope detection circuit 10 with attenuation stage (or logarithmic envelope detection circuit) provided in this embodiment of the disclosure, the amplification factor of each first amplification circuit 101 in the amplification stage is uniformly A1, and the input terminal of each second amplification circuit 103 in the attenuation stage is connected to the attenuation circuit 102. That is, the input terminal of the first second amplification circuit 103 is also connected to the attenuation circuit 102, rather than directly receiving the target input signal. In the attenuation stage, each stage first attenuates by A1 times (that is, the amplification factor B0 of the attenuation circuit 102 is 1 / A1. Since A1 is greater than 1, 1 / A1 is less than 1, thus achieving attenuation). After attenuation, it is output to the rectifier 104 through a limiting amplifier with an amplification factor of A1 (that is, the second amplification circuit 103, which is consistent with the first amplification circuit 101 in the amplification stage). Ultimately, it is possible to achieve a gain relationship of A1 times for the voltage signal before each rectifier 104, that is (with V... p3 For example:

[0079] V p3 =A1V p2 =A1 2 V p1 =A1 3 V n1 =A1 4 V n2 =A1 5 V n3 When the input signal of rectifier 104 enters its linear region, it will start to respond and output the corresponding current. Finally, the output currents of all rectifiers can be pieced together to form a complete logarithmic curve corresponding to different signal power values.

[0080] Assuming the signal envelope detection circuit has an input dynamic range of 80dBm (-50dBm to 30dBm), the rectifier has an operating range of 0 to 10dBm, and the amplification stage includes five stages of first amplification circuits 101, each with a dynamic range of 10dBm, and the overall dynamic range of the amplification stage is 50dBm (-50dBm to 0dBm), with a gain of 10dB for each stage; the first stage of the first amplification circuit 101 amplifies -10 to 0dBm to 0dBm to 10dBm, and the corresponding rectifier 104 can output a corresponding current; the first stage of the first amplification circuit 101 and the second stage of the first amplification circuit 101 amplify -10 to 0dBm to 0dBm to 10dBm. The amplification from 20dBm to -10dBm to 0 to 10dBm corresponds to the output current of the rectifier 104. The first amplifier circuit 101 of stages 1 to 3 amplifies from -30dBm to -20dBm to 0 to 10dBm, and the corresponding rectifier 104 can output the corresponding current. The first amplifier circuit 101 of stages 1 to 4 amplifies from -40dBm to -30dBm to 0 to 10dBm, and the corresponding rectifier 104 can output the corresponding current. The first amplifier circuit 101 of stages 1 to 5 amplifies from -50dBm to -40dBm to 0 to 10dBm, and the corresponding rectifier 104 can output the corresponding current.

[0081] When the input dynamic range is 0dBm to 30dBm, it exceeds the dynamic range of the amplification stage. Therefore, the attenuation circuit 102 attenuates the input signal, bringing it within the dynamic range of the attenuation stage. Assuming the attenuation stage includes three second amplification circuits 103, it also includes three attenuation circuits B0 and three rectifiers 104. The first-stage attenuation circuit 102 attenuates the 0dBm to 10dBm signal to -10dBm to 0dBm, the first-stage second amplification circuit 102 amplifies it back to 0dBm to 10dBm, and then the rectifier 104 converts it into a corresponding current. The first-stage attenuation circuit 102 and the second-stage attenuation circuit 102 attenuate the 10dBm to 20dBm signal. The attenuation stage reduces the voltage from 20dBm to 30dBm to -10dBm, and the second stage amplifier circuit 102 amplifies it again to 0dBm to 10dBm. Then, the rectifier 104 converts it into the corresponding current. The first to third attenuation circuits attenuate the voltage from 20dBm to 30dBm to -10dBm to 0dBm, and the third stage amplifier circuit 102 amplifies it again to 0dBm to 10dBm. Then, the rectifier 104 converts it into the corresponding current. Finally, the attenuation stage and the amplification stage work together to complete the conversion from -50dBm to 30dBm, and the signals are spliced ​​together to obtain the final target output signal.

[0082] In this way, since the amplification factor and swing of the first amplifier circuit 101 and the second amplifier circuit 103 are equal, the output current slope of all rectifiers 104 is equal, thus avoiding the problem of uneven output current splicing of rectifiers 104. Furthermore, the first second amplifier circuit 103 is connected to an attenuation circuit 102, which attenuates the signal to cancel out the amplification factor of the second amplifier circuit 103, thereby ensuring that the output of the first second amplifier circuit 103 falls within the dynamic range of the rectifier 104, guaranteeing the integrity of the splicing.

[0083] Based on Figure 8, as shown in Figure 9, in some embodiments, each first amplifier circuit 101, each second amplifier circuit 103, and each attenuator circuit 102 is a dual-ended input and dual-ended output; each rectifier 104 is a dual-ended input and single-ended output; the target input signal V IN Including the positive phase input signal V IN+ and inverted input signal V IN- ;

[0084] The positive input terminal (+) of the first amplifier circuit 101 and the first input terminal of the first attenuator circuit 102 are both used to receive the positive input signal V. IN+ The inverting input terminal (-) of the first-stage amplifier circuit 101 and the second input terminal of the first-stage attenuator circuit 102 are both used to receive the inverted input signal V. IN- ;

[0085] The first input terminal of the second to Mth stage attenuation circuit 102 is connected to the first output terminal of the previous stage attenuation circuit 102; the second input terminal of the second to Mth stage attenuation circuit 102 is connected to the second output terminal of the previous stage attenuation circuit 102.

[0086] The non-inverting input terminal of any second amplifier circuit 103 is connected to the first output terminal of the corresponding attenuation circuit 102; the inverting input terminal of any second amplifier circuit 103 is connected to the second output terminal of the corresponding attenuation circuit 102.

[0087] It should be noted that, as shown in Figure 9, for any first-stage amplifier circuit 101 (denoted as the i-th stage, where i is a positive integer greater than or equal to 1 and less than or equal to N), it has differential dual-ended input and output, and its output signal V pi It is the output signal V at its positive output terminal (+). pi+ The output signal V at its inverting output terminal (-) pi- difference.

[0088] For any second amplifier circuit 103 (denoted as the j-th, where j is an integer greater than or equal to 1 and less than or equal to M), which has differential dual-ended input and output, attenuation circuits 1 to attenuation circuit j will convert the inverted input signal V... IN+Attenuated to the first attenuated signal V attj+ The inverted input signal V IN- Attenuated to the second attenuated signal V attj- The input signal V of the second amplifier circuit j attj It is the first attenuated signal V attj+ With the second attenuation signal V attj- The difference is the output signal V of the second amplifier circuit j. nj It is the output signal V at its positive output terminal (+). nj+ The output signal V at the inverting output terminal (-) nj- difference.

[0089] As shown in Figure 9, the logarithm detection circuit 10 may also include a load resistor R. DET It is used to convert the current signals output by all rectifiers 104 into voltage signals, which serve as the target output signal V. DET Furthermore, filters, buffers, output resistors, etc., can be connected after all rectifiers 104 to regulate the target output signal V. DET Filtering and drive enhancement are performed to obtain an output signal with a frequency within a suitable range and strong driving capability.

[0090] Based on Figure 9, as shown in Figure 10, in some embodiments, the attenuation circuit 102 includes a first sub-attenuation circuit s1 and a second sub-attenuation circuit s2; wherein, the input terminal of the first sub-attenuation circuit s1 serves as the first input terminal of the attenuation circuit 102, and the output terminal of the first sub-attenuation circuit s1 serves as the first output terminal of the attenuation circuit 102; the input terminal of the second sub-attenuation circuit s2 serves as the second input terminal of the attenuation circuit 102, and the output terminal of the second sub-attenuation circuit s2 serves as the second output terminal of the attenuation circuit 102.

[0091] In the first-stage attenuation circuit 102, the first sub-attenuation circuit s1 is connected in series with the non-inverting input terminal of the first-stage second amplifier circuit 103 and the non-inverting input signal V. IN+ Between them, the second sub-attenuation circuit s2 is connected in series with the inverting input terminal of the first-stage second amplifier circuit 103 and the inverting input signal V. IN- between;

[0092] In the second to Mth stage attenuation circuits 102, the first sub-attenuation circuit s1 is connected in series between the non-inverting input terminals of two adjacent stages of the second amplifier circuit 103, and the second sub-attenuation circuit s2 is connected in series between the inverting input terminals of two adjacent stages of the second amplifier circuit 103.

[0093] It should be noted that the target input signal V IN Including the positive phase input signal V IN+ and inverted input signal V IN-Correspondingly, M first sub-attenuation circuits s1 form a positive phase attenuation link, used to attenuate the positive phase input signal V. IN+ The signal is attenuated in stages. M second sub-attenuation circuits s2 form an inverting attenuation link, which is used to attenuate the inverted input signal V. IN- The attenuation is performed step by step. The amplification factor of each first sub-attenuation circuit s1 and each second sub-attenuation circuit s2 is 1 / A1.

[0094] Furthermore, in the embodiments of this disclosure, each sub-attenuation circuit can be capacitive or resistive. As shown in FIG11, both the first sub-attenuation circuit s1 and the second sub-attenuation circuit s2 are resistors.

[0095] It should be noted that, as shown in Figure 11, for the resistive attenuation circuit, the first sub-attenuation circuits s1 in attenuation circuits 1 to M are respectively denoted as resistors R11 to RM1, and the second sub-attenuation circuits s2 in attenuation circuits 1 to M are respectively denoted as resistors R12 to RM2. The resistance ratio of each stage is designed according to the required attenuation factor.

[0096] Taking attenuation circuit 1 as an example, the first end of resistor R11 serves as the input end of the first sub-attenuation circuit s1, and the second end of resistor R11 serves as the output end of the first sub-attenuation circuit s1; the first end of resistor R12 serves as the input end of the second sub-attenuation circuit s2, and the second end of resistor R12 serves as the output end of the second sub-attenuation circuit s2.

[0097] It should also be noted that, as shown in Figure 11, in addition to the 2×M resistors, resistors R(M+1)1 and R(M+1)2 are also included. The first terminal of resistor R(M+1)1 is connected to the second terminal of resistor RM1, and the first terminal of resistor R(M+1)2 is connected to the second terminal of resistor RM2. The second terminals of resistors R(M+1)1 and R(M+1)2 are connected to each other to ensure consistent common-mode output voltage across all stages in the attenuation stage. In other words, for the positive-phase attenuation link (resistors R11 to RM1) or the negative-phase attenuation link (resistors R12 to RM2), voltage division is achieved by resistors connected in series in M+1 stages. The number of resistors in the link is one more than the number of resistors in attenuation circuit 102; this is necessary to achieve attenuation. The resistance ratios of resistors R(M+1)1 and R(M+1)2, and the resistors in attenuation circuit 102, are designed according to the required attenuation factor for each stage.

[0098] In this way, the resistor-based attenuation circuit (or attenuator) can achieve a step-by-step attenuation by A1 times, followed by an amplification by A1 times. This allows the voltage signal before each rectifier 104 to exhibit a gain relationship of A1 times, i.e., V p3 =A1V p2 =A1 2 Vp1 =A1 3 V n1 =A1 4 V n2 =A1 5 V n3 Meanwhile, since the attenuation circuit 102 has virtually no impact on linearity, the linearity of the input signal to the rectifier 104 in the attenuation stage is mainly affected by the amplitude limiting amplifier. Since the amplification stage and the attenuation stage use the same amplitude limiting amplifier, they can maintain the same linearity.

[0099] As shown in Figure 12, both the first sub-attenuation circuit s1 and the second sub-attenuation circuit s2 are capacitors. The signal envelope detection circuit 10 also includes M first bias circuits 105. Each first bias circuit 105 is connected to the input terminal of the corresponding second amplifier circuit 103 and is used to provide bias voltage to the second amplifier circuit 103.

[0100] It should be noted that, as shown in Figure 12, for the capacitive attenuation circuit, the first sub-attenuation circuits s1 in attenuation circuits 1 to M are respectively denoted as capacitors C11 to CM1, and the second sub-attenuation circuits s2 in attenuation circuits 1 to M are respectively denoted as capacitors C12 to CM2. The capacitance ratio of all capacitors is designed according to the required attenuation factor for each stage.

[0101] Taking attenuation circuit 1 as an example, the first end of capacitor C11 serves as the input end of the first sub-attenuation circuit s1, and the second end of capacitor C11 serves as the output end of the first sub-attenuation circuit s1; the first end of capacitor C12 serves as the input end of the second sub-attenuation circuit s2, and the second end of capacitor C12 serves as the output end of the second sub-attenuation circuit s2.

[0102] It should also be noted that, as shown in Figure 12, in addition to the 2×M capacitors, capacitors C(M+1)1 and C(M+1)2 are also included. The first terminal of capacitor C(M+1)1 is connected to the second terminal of capacitor CM1, and the first terminal of capacitor C(M+1)2 is connected to the second terminal of capacitor CM2. The second terminals of capacitors C(M+1)1 and C(M+1)2 are either connected to or grounded. In other words, for the positive-phase attenuation link (capacitors C11 to CM1) or the negative-phase attenuation link (capacitors C12 to CM2), voltage division is achieved by capacitors connected in series at M+1 stages. The number of capacitors in the link is one more than the number of attenuation circuits 102; this is necessary to achieve attenuation. The capacitance ratios of capacitors C(M+1)1 and C(M+1)2 and the capacitors in attenuation circuit 102 are designed according to the required attenuation factor for each stage.

[0103] In this way, the capacitor-based attenuation circuit 102 can achieve a step-by-step attenuation by A1 times, followed by an amplification by A1 times, so that the voltage signal before each rectifier 104 exhibits a gain relationship of A1 times, i.e., V p3 =A1V p2 =A1 2 V p1 =A1 3 V n1 =A1 4 V n2 =A1 5 V n3 Meanwhile, since the attenuation circuit 102 has virtually no impact on linearity, the linearity of the input signal to the rectifier 104 in the attenuation stage is mainly affected by the amplitude limiting amplifier. Since the amplification stage and the attenuation stage use the same amplitude limiting amplifier, they can maintain the same linearity.

[0104] It should also be noted that, as shown in Figure 12, for the capacitive attenuation circuit 102, a first bias circuit 105 needs to be set at the input terminal of each second amplifier circuit 103 to provide input bias for the second amplifier circuit 103. However, for the resistive attenuation circuit 102, as shown in Figure 11, the resistor can act as a bias circuit, and no additional bias circuit is required.

[0105] For the second amplifier circuit 103 with dual-ended input, as shown in Figure 12, the first bias circuit 105 includes a first sub-bias circuit b1 and a second sub-bias circuit b2.

[0106] The first sub-bias circuit b1 is connected to the non-inverting input terminal of the second amplifier circuit 103;

[0107] The second sub-bias circuit b2 is connected to the inverting input terminal of the second amplifier circuit 103.

[0108] It should be noted that, taking the first bias circuit 105 connected to the second amplifier circuit 1 as an example, the first sub-bias circuit b1 is used to provide a positive bias for the second amplifier circuit 1, and the second sub-bias circuit b2 is used to provide an inverting bias for the second amplifier circuit 1. Both the first sub-bias circuit b1 and the second sub-bias circuit b2 can be resistors. The first terminal of the first sub-bias circuit b1 is connected to the positive bias voltage V. CM1 The second terminal is connected to the non-inverting input terminal of the second amplifier circuit 1; the first terminal of the second sub-bias circuit b2 is connected to the inverting bias voltage V. CM2 The second terminal is connected to the inverting input terminal of the second amplifier circuit 1.

[0109] It should also be noted that the positive bias voltage V CM1 and inverting bias voltage V CM2The settings can be customized according to actual needs, and no specific value is limited; different positive bias voltages V within the first bias circuit 105... CM1 and inverting bias voltage V CM2 The settings are also based on the needs, and may be the same or different; no specific restrictions are imposed on this.

[0110] In this way, the bias voltage is provided to the second amplifier circuit 103 by using a resistor connection, ensuring that the second amplifier circuit 103 works normally.

[0111] Furthermore, as shown in Figure 11 or Figure 12, the signal envelope detection circuit 10 may also include a second bias circuit 106 for providing a bias voltage to the first stage first amplifier circuit 101. For the dual-ended input first amplifier circuit 101, the second bias circuit 106 includes a third sub-bias circuit b3 and a fourth sub-bias circuit b4;

[0112] The third sub-bias circuit b3 is connected to the non-inverting input terminal of the first stage first amplifier circuit 101;

[0113] The fourth sub-bias circuit b4 is connected to the inverting input of the first stage first amplifier circuit 101.

[0114] It should be noted that the third sub-bias circuit b3 provides a positive bias for the first stage first amplifier circuit 1, and the fourth sub-bias circuit b4 provides an inverting bias for the first stage first amplifier circuit 1. Both the third sub-bias circuit b3 and the fourth sub-bias circuit b4 can be resistors. The first terminal of the third sub-bias circuit b3 is connected to the positive bias voltage V. CM3 The second terminal is connected to the non-inverting input terminal of the first stage first amplifier circuit 1; the first terminal of the fourth sub-bias circuit b4 is connected to the inverting bias voltage V. CM4 The second terminal is connected to the inverting input terminal of the first stage amplifier circuit 1. The non-inverting bias voltage V... CM3 and inverting bias voltage V CM4 It can be set according to actual needs, and there are no restrictions on its specific value.

[0115] In this way, the bias voltage is provided by the resistor connection to the first stage first amplifier circuit 101, ensuring that the amplifier circuit link works normally.

[0116] It should also be noted that in this embodiment, the first amplifier circuit 101 and the second amplifier circuit 103 have the same structure. That is, the first amplifier circuit 101 and the second amplifier circuit 103 are both limiting amplifiers, with the same structure and the same amplification factor. In other words, each first amplifier circuit 101 and each second amplifier circuit 103 are actually identical amplifiers (ignoring unavoidable differences due to manufacturing processes). Their circuit topology, the types and quantities of components, the connection relationships between components, and the parameters of the components are all completely identical. They are simply located in the attenuation stage and the amplification stage, respectively. Their structures can be referred to in Figure 3 or Figure 4. Taking Figure 3 as an example, the limiting amplifier (i.e., the first amplifier circuit 101 / second amplifier circuit 103) includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor M1, a second transistor M2, and a first wake source I1; V IN+ V represents the inverting input signal of the limiting amplifier. IN- V represents the inverting input signal of the limiting amplifier. OUT+ V represents the inverting output signal of the limiting amplifier. OUT- This indicates the inverted output signal of the limiting amplifier;

[0117] The first terminals of both the first resistor R1 and the second resistor R2 receive the supply voltage VDD.

[0118] The base of the first transistor M1 serves as the non-inverting input of the limiting amplifier; the base of the second transistor M2 serves as the inverting input of the limiting amplifier.

[0119] The second terminal of the first resistor R1 is connected to the collector of the first transistor M1 as the inverting output terminal of the limiting amplifier; the second terminal of the second resistor R2 is connected to the collector of the second transistor M2 as the non-inverting output terminal of the limiting amplifier.

[0120] The first end of the third resistor R3 is connected to the emitter of the first transistor M1;

[0121] The first terminal of the fourth resistor R4 is connected to the emitter of the second transistor M2;

[0122] The second end of the third resistor R3 and the second end of the fourth resistor R4 are both connected to the first end of the first wake source I1.

[0123] The second terminal of the first wake source I1 is grounded.

[0124] It should be noted that in the limiting amplifier, the resistors are optional. That is, the limiting amplifier may not include any resistors or may only include a portion of them, depending on the gain requirements of the limiting amplifier.

[0125] The structure of rectifier 104 can be referred to in Figure 13. As shown in Figure 13, rectifier 104 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7; V IN+ This indicates the inverting input signal directly received by the first amplifier circuit 101 / second amplifier circuit 103 connected to the rectifier, V. IN- This indicates the inverted input signal directly received by the first amplifier circuit 101 / second amplifier circuit 103 connected to the rectifier, I. OUT This indicates the output signal (current signal) of the rectifier 104;

[0126] The first terminal of the ninth resistor R9 and the base of the fifth transistor M5 are connected as the first input terminal (or non-inverting input terminal) of the rectifier 104; the first terminal of the tenth resistor R10 and the base of the sixth transistor M6 are connected as the second input terminal (or inverting input terminal) of the rectifier 104.

[0127] The second terminal of the ninth resistor R9, the second terminal of the tenth resistor R10, and the base of the seventh transistor M7 are connected;

[0128] The first terminal of the eleventh resistor R11' receives the supply voltage VDD; the second terminal of the eleventh resistor R11' is connected to the collector of the seventh transistor M7; the emitters of the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all connected to the first terminal of the third wake source I3.

[0129] The second terminal of the third wake source I3 is grounded;

[0130] The collectors of the fifth transistor M5 and the sixth transistor M6 are connected as the output terminals of the rectifier 104, and the output signal is a current signal I. OUT .

[0131] It should be noted that the first transistor M1 to the seventh transistor M7 involved here can all be BJTs. The first wake source I1 to the third wake source I3 are used to provide the wake current.

[0132] Based on the logarithmic envelope detection circuit provided in Figures 8 to 13 above, taking a 5-stage amplification stage and a 3-stage attenuation stage as an example, Figure 14 shows the corresponding output current schematic diagram of the rectifier; Figure 15 is a comparison schematic diagram of the corresponding ideal logarithmic curve and the actual logarithmic curve; Figure 16 is a comparison schematic diagram of the corresponding ideal logarithmic curve error and the actual logarithmic curve error.

[0133] Compared to Figure 5, in Figure 14, since the amplifiers in the attenuation stage and the amplification stage have the same gain, the slope of the rectifier output current is the same, and the dip is significantly improved when spliced. Compared to Figure 6, in Figure 15, the actual logarithmic curve is close to the ideal logarithmic curve; compared to Figure 7, in Figure 16, the error of the actual logarithmic curve is close to the error of the ideal logarithmic curve.

[0134] In summary, the embodiments of this disclosure propose a large dynamic range signal envelope detection circuit architecture. By using the same limiting amplifier in the attenuation stage and the amplification stage, the successive gains, swing, and linearity of the attenuation stage and the amplification stage are consistent. This solves the key problem of logarithmic error caused by uneven splicing of rectifier curves in the amplification stage and the attenuation stage, improves the detection accuracy, and ultimately enables the detection circuit to effectively widen the dynamic range.

[0135] In another embodiment of this disclosure, a logarithmic envelope detection chip is also provided, which includes the logarithmic envelope detection circuit 10 described in any of the foregoing embodiments.

[0136] Thus, since the logarithmic envelope detection circuit 10 is a logarithmic envelope detection circuit with an attenuation stage, and the attenuation stage and amplification stage use limiting amplifiers with the same gain, swing, and linearity, while the attenuation circuit in the attenuation stage has virtually no impact on linearity, the rectifier input voltage exhibits a successive A1-fold relationship on both small and large signals. Ultimately, as shown in Figures 14-16 above, the splicing of the amplification stage and attenuation stage does not result in a dip, but rather maintains the splicing shape of the amplification stage. This ensures that the actual logarithmic curve does not generate additional logarithmic errors due to splicing, thereby improving detection accuracy.

[0137] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0138] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0139] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0140] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0141] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0142] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0143] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A signal envelope detection circuit, characterized in that, include: N cascaded first amplifier circuits, the input terminal of the first stage first amplifier circuit is used to receive the target input signal, and the input terminals of the second to Nth stages first amplifier circuits are used to receive the output signal of the previous stage first amplifier circuit; M cascaded attenuation circuits, the input terminal of the first-stage attenuation circuit is used to receive the target input signal, and the input terminals of the second to Mth-stage attenuation circuits are used to receive the output signal of the previous-stage attenuation circuit; M second amplifier circuits, the input terminal of each second amplifier circuit is connected to the output terminal of the corresponding attenuation circuit; Multiple rectifiers are provided, with the output terminal of each first amplifier circuit connected to the input terminal of the corresponding rectifier, and the output terminal of each second amplifier circuit connected to the input terminal of the corresponding rectifier; the output terminals of all the rectifiers are connected together for outputting the target output signal. Where N and M are both integers greater than 1; the amplification factors of the first amplifier circuit and the second amplifier circuit are the same.

2. The signal envelope detection circuit according to claim 1, characterized in that, The amplification factor of the first amplifier circuit and the second amplifier circuit is A1, and the amplification factor of the attenuation circuit is 1 / A1.

3. A signal envelope detection circuit as claimed in claim 2, characterized in that A1 is greater than 1.

4. The signal envelope detection circuit of claim 1, wherein, Each of the first amplifier circuit, each of the second amplifier circuit, and each of the attenuation circuits is a dual-ended input and a dual-ended output; each of the rectifiers is a dual-ended input and a single-ended output; the target input signal includes a positive-inverting input signal and an inverting input signal. The non-inverting input terminal of the first amplifier circuit in the first stage and the first input terminal of the attenuation circuit in the first stage are both used to receive the non-inverting input signal; the inverting input terminal of the first amplifier circuit in the first stage and the second input terminal of the attenuation circuit in the first stage are both used to receive the inverting input signal. The first input terminal of the attenuation circuits of stages 2 to M is connected to the first output terminal of the attenuation circuit of the previous stage; the second input terminal of the attenuation circuits of stages 2 to M is connected to the second output terminal of the attenuation circuit of the previous stage. The non-inverting input terminal of any of the second amplifier circuits is connected to the first output terminal of the corresponding attenuation circuit; the inverting input terminal of any of the second amplifier circuits is connected to the second output terminal of the corresponding attenuation circuit.

5. The signal envelope detection circuit according to claim 4, characterized in that, The attenuation circuit includes a first sub-attenuation circuit and a second sub-attenuation circuit; In the first stage attenuation circuit, the first sub-attenuation circuit is connected in series between the non-inverting input terminal of the first stage second amplifier circuit and the non-inverting input signal, and the second sub-attenuation circuit is connected in series between the inverting input terminal of the first stage second amplifier circuit and the inverting input signal. In the attenuation circuits of stages 2 to M, the first sub-attenuation circuit is connected in series between the non-inverting input terminals of two adjacent stages of the second amplifier circuit, and the second sub-attenuation circuit is connected in series between the inverting input terminals of two adjacent stages of the second amplifier circuit.

6. The signal envelope detection circuit according to claim 5, characterized in that, Both the first sub-attenuation circuit and the second sub-attenuation circuit are resistors.

7. The signal envelope detection circuit according to claim 5, characterized in that, Both the first sub-attenuation circuit and the second sub-attenuation circuit are capacitors. The signal envelope detection circuit also includes M first bias circuits, each of which is connected to the input terminal of the corresponding second amplifier circuit to provide a bias voltage to the second amplifier circuit.

8. The signal envelope detection circuit according to claim 7, characterized in that, The first bias circuit includes a first sub-bias circuit and a second sub-bias circuit; The first sub-bias circuit is connected to the non-inverting input terminal of the second amplifier circuit; The second sub-bias circuit is connected to the inverting input of the second amplifier circuit.

9. The signal envelope detection circuit according to any one of claims 1 to 8, characterized in that, The first amplifier circuit and the second amplifier circuit have the same structure.

10. The signal envelope detection circuit according to any one of claims 1 to 8, characterized in that, Both the first amplifier circuit and the second amplifier circuit are limiting amplifiers.

11. A signal envelope detection chip, characterized in that, Includes the signal envelope detection circuit as described in any one of claims 1 to 10.

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