Integrated circuit, cross-clock domain data transmission method, electronic device, and storage medium

Abstract

The present application relates to an integrated circuit, a cross-clock domain data transmission method, an electronic device, and a storage medium. The integrated circuit comprises a first clock domain and a second clock domain; the first clock domain comprises a first pointer control module; the second clock domain comprises a second pointer control module; the first pointer control module comprises a first synchronization pointer control module; the first synchronization pointer control module is configured to: in response to the frequency of the first clock signal being greater than that of the second clock signal, on the basis of a second clock phase and a second clock period of the second clock domain, the first clock signal and a first clock phase of the first clock domain, determine a phase relationship between the first clock signal and the second clock signal, and determine a first pointer control signal on the basis of the phase relationship; and in response to the frequency of the first clock signal being smaller than that of the second clock signal, determine that the first pointer control signal is a first value, so that a first read pointer and a first write pointer increase by the first value in each clock period of the first clock signal.

Description

Integrated circuits, cross-clock domain data transmission methods, electronic devices, storage media

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411930853.5, filed on December 25, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to an integrated circuit, a method for data transmission across clock domains, an electronic device, and a non-transitory computer-readable storage medium. Background Technology

[0004] Processors typically use one or more clock signals to synchronize logical operations across their modules, thereby preventing errors such as setup mistakes and race conditions. Different clock signals are used for different parts of the processor, each part being called a clock domain. By using different clock domains, the processor operates different parts at different frequencies and relatively independently of the timing of logical operations. For example, the processor can use clock signals of different frequencies to synchronize different clock domains, thereby improving processing efficiency. Furthermore, the processor can provide different clock signals to different clock domains without synchronizing them, thus simplifying clock management and signal routing at the processor level. Summary of the Invention

[0005] At least one embodiment of this disclosure provides an integrated circuit, including a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal. The first clock signal and the second clock signal are co-source clock signals. The frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal. The first clock domain includes a first pointer control module, and the second clock domain includes a second pointer control module. The first pointer control module is configured to generate a first pointer control signal for the first clock domain, such that a first read pointer and a first write pointer in the first clock domain are adjusted according to the first pointer control signal, wherein the first pointer control signal is used to indicate the update time point of the first read pointer and the first write pointer. The second pointer control module is configured to generate a second pointer control signal for the second clock domain, such that a second read pointer and a second write pointer in the second clock domain are adjusted according to the second pointer control signal, wherein the second pointer control signal is used to indicate the update time point of the second read pointer and the second write pointer. New time point; the integrated circuit further includes a first first-in-first-out (FIFO) buffer and a second FIFO buffer, the first FIFO buffer being configured to perform data transmission from the first clock domain to the second clock domain based on the first write pointer and the second read pointer, and the second FIFO buffer being configured to perform data transmission from the second clock domain to the first clock domain based on the first read pointer and the second write pointer; the first pointer control module includes a first synchronous pointer control module, the first synchronous pointer control module being configured to: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal to a first value, so that the first read pointer and the first write pointer increase the first value in each clock period of the first clock signal.

[0006] For example, in the integrated circuit provided in at least one embodiment of this disclosure, the first synchronization pointer control module and the second pointer control module include the same structure, and both include a first sub-module and a second sub-module. The first sub-module of the first synchronization pointer control module is configured to determine the first clock phase according to the first clock period of the first clock domain, wherein the first clock phase is used to indicate the phase value of each clock period of the first clock signal; the second sub-module of the first synchronization pointer control module is configured to determine the first pointer control signal, wherein, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal having a first value indicates that the rising edge of the second clock signal is located in the current clock period of the first clock signal, and the first pointer control signal having a second value indicates that no rising edge of the second clock signal is located in the current clock period of the first clock signal.

[0007] For example, in an integrated circuit provided in at least one embodiment of this disclosure, the second submodule includes a phase synchronization detection unit, a phase estimation unit, and a phase tracking unit. The phase synchronization detection unit is configured to determine a target clock phase in the second clock signal based on the second clock phase and the first clock signal, wherein the target clock phase is the phase value of a selected clock cycle in the second clock signal. The phase estimation unit is configured to determine a target clock cycle corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock cycle, wherein the target clock phase is located in a phase interval corresponding to the target clock cycle, and the phase interval is determined by the phase value of the target clock cycle and the phase value of the next clock cycle of the target clock cycle. The phase tracking unit is configured to continuously estimate a first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle.

[0008] For example, in an integrated circuit provided in at least one embodiment of this disclosure, the phase synchronization detection unit includes a multi-level flip-flop group and an AND gate. The multi-level flip-flop group is configured to use the first clock signal as a clock to synchronize a transition edge selected in the second clock signal. The AND gate is configured to perform an AND operation between the synchronized transition edge and the phase of the second clock signal to obtain the phase value of the clock period in which the selected transition edge is located as the target clock phase.

[0009] For example, in an integrated circuit provided in at least one embodiment of this disclosure, the phase estimation unit is configured to compare the target clock phase with phase intervals corresponding to a plurality of clock cycles respectively, so as to determine the target clock cycle corresponding to the target clock phase, wherein the plurality of clock cycles are a plurality of clock cycles in the first clock signal before the transition edge after synchronization.

[0010] For example, in an integrated circuit provided in at least one embodiment of this disclosure, the phase estimation unit is further configured to estimate the phase change of the second clock signal as measured by the clock period of the first clock signal.

[0011] For example, in an integrated circuit provided in at least one embodiment of this disclosure, when the phase tracking unit continuously estimates the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock period, it includes performing the following steps: determining a clock phase to be estimated based on the target clock phase and the second clock cycle; in the current clock cycle: determining whether the clock phase to be estimated is located within the phase interval corresponding to the current clock cycle based on the clock phase to be estimated; in response to the clock phase to be estimated being located within the phase interval corresponding to the current clock cycle, determining the first pointer control signal output in the current clock cycle as the first value, and updating the clock phase to be estimated based on the second clock cycle; in response to the clock phase to be estimated not being located within the phase interval corresponding to the current clock cycle, determining the first pointer control signal output in the current clock cycle as the second value.

[0012] For example, in the integrated circuit provided in at least one embodiment of this disclosure, the first read pointer and the first write pointer are adjusted according to the first pointer control signal in each clock cycle of the first clock signal, and the second read pointer and the second write pointer are adjusted according to the second pointer control signal in each clock cycle of the second clock signal; in response to a data write operation generated in the write clock cycle of the first clock domain, a data read operation is performed in the read clock cycle corresponding to the write clock cycle in the second clock signal, wherein, in response to the clock frequency of the first clock signal being greater than the clock frequency of the second clock signal, the rising edge of the second clock signal that differs from the rising edge of the read clock cycle by a+1 second clock cycles is located in the clock cycle preceding the write clock cycle in the first clock signal, and in response to the clock frequency of the first clock signal being less than the clock frequency of the second clock signal, wherein the rising edge that differs from the rising edge of the write clock cycle by a first clock cycle is located in the clock cycle preceding the read clock cycle in the second clock signal, where a is a positive integer.

[0013] For example, in the integrated circuit provided in at least one embodiment of this disclosure, the first pointer control module further includes a first state machine and a first asynchronous pointer control module, and the second pointer control module further includes a second state machine and a second asynchronous pointer control module. The first asynchronous pointer control module and the second asynchronous pointer control module each include multiple levels of flip-flops. The first asynchronous pointer control module and the second asynchronous pointer control module synchronize the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through their respective multiple levels of flip-flops. The first state machine is configured to control the first clock domain to use the first asynchronous pointer control module for cross-clock domain data transmission when a frequency switch occurs, and to control the first clock domain to use the first synchronous pointer control module for cross-clock domain data transmission after the frequency switch is completed and phase estimation is completed. The second state machine is configured to control the second clock domain to use the second asynchronous pointer control module for cross-clock domain data transmission when a frequency switch occurs, and to control the second clock domain to use the second synchronous pointer control module for cross-clock domain data transmission after the frequency switch is completed and phase estimation is completed.

[0014] For example, in the integrated circuit provided in at least one embodiment of this disclosure, the first state machine and the second state machine are further configured to receive a first indication information indicating whether a frequency switching is completed, and a second indication information indicating the frequency magnitude relationship between a first clock signal and a second clock signal. In response to the first indication information indicating that a frequency switching has occurred, the first state machine controls the first clock domain to use the first asynchronous pointer control module to perform cross-clock domain data transmission, and the second state machine controls the second clock domain to use the second asynchronous pointer control module to perform cross-clock domain data transmission. The first state machine and the second state machine are further configured to determine whether a frequency switching is completed and whether phase estimation is completed based on the first indication information and the second indication information.

[0015] For example, in an integrated circuit provided in at least one embodiment of this disclosure, when the first state machine executes the operation of determining whether frequency switching is complete and phase estimation is completed based on the first indication information and the second indication information, it includes the following operations: in response to the first indication information indicating that frequency switching is complete and the second indication information indicating that the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal: the first state machine controls the first synchronization pointer control module to perform phase estimation to obtain the phase relationship and determine the first pointer control signal based on the phase relationship; in response to the first synchronization pointer control module completing phase estimation, it determines that frequency switching is complete and phase estimation is completed; and the first state machine is further configured to perform a synchronization handshake with the second state machine so that the second state machine controls the second clock domain to use the second synchronization pointer control module to perform cross-clock domain data transmission; in response to the first indication information indicating that frequency switching is complete and the second indication information indicating that the clock frequency of the first clock signal is less than the clock frequency of the second clock signal: after completing the synchronization handshake with the second state machine, it determines that frequency switching is complete and phase estimation is completed.

[0016] At least one embodiment of this disclosure provides a cross-clock domain data transmission method applied to a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal. The first clock domain includes a first first-in-first-out (FIFO) buffer, and the second clock domain includes a second FIFO buffer. The first clock signal and the second clock signal are co-source clock signals, and the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal. The data transmission method includes: in the first clock domain, determining a first pointer control signal, and adjusting a first read pointer and a first write pointer of the first clock domain according to the first pointer control signal, wherein the first pointer control signal is used to indicate the update time point of the first read pointer and the first write pointer; in the second clock domain, determining a second pointer control signal, and adjusting a second read pointer and a second write pointer of the second clock domain according to the second pointer control signal, wherein the second pointer control signal is used to indicate... The update times of the second read pointer and the second write pointer; based on the first write pointer and the second read pointer, data transmission from the first clock domain to the second clock domain is performed using the first first-in-first-out buffer, and data transmission from the second clock domain to the first clock domain is performed using the second first-in-first-out buffer based on the first read pointer and the second write pointer; wherein, determining the first pointer control signal includes: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determining the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determining the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determining the first pointer control signal to a first value, so that the first read pointer and the first write pointer increase the first value in each clock period of the first clock signal.

[0017] For example, in the data transmission method provided in at least one embodiment of this disclosure, determining the first pointer control signal further includes: determining the first clock phase according to the first clock period of the first clock domain, wherein the first clock phase is used to indicate the phase value of each clock period of the first clock signal; wherein, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal being a first value indicates that there is a rising edge of the second clock signal in the current clock period of the first clock signal, and the first pointer control signal being a second value indicates that there is no rising edge of the second clock signal in the current clock period.

[0018] For example, in a data transmission method provided in at least one embodiment of this disclosure, determining the phase relationship between the first clock signal and the second clock signal based on the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase, and determining the first pointer control signal based on the phase relationship, includes: determining a target clock phase in the second clock signal based on the second clock phase and the first clock signal, wherein the target clock phase is the phase value of a selected clock period in the second clock signal; determining a target clock period corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock period, wherein the target clock phase is located in a phase interval corresponding to the target clock period, and the phase interval is determined by the phase value of the target clock period and the phase value of the next clock period of the target clock period; and continuously estimating the first pointer control signal output in each current clock period of the first clock signal based on the target clock phase and the target clock period.

[0019] For example, the data transmission method provided in at least one embodiment of this disclosure further includes: when a frequency switch occurs, controlling the first clock domain and the second clock domain to perform cross-clock domain data transmission using asynchronous pointer control logic; after the frequency switch is completed and phase estimation is completed, controlling the first clock domain and the second clock domain to perform cross-clock domain data transmission using synchronous pointer control logic, wherein the asynchronous pointer control logic includes synchronizing the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through multi-level flip-flops, and the synchronous pointer control logic includes obtaining the phase relationship and performing cross-clock domain data transmission based on the phase relationship.

[0020] At least one embodiment of this disclosure provides an electronic device, including: a memory that non-transitoryly stores computer-executable instructions; and a processor configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the cross-clock domain data transmission method according to any embodiment of this disclosure.

[0021] At least one embodiment of this disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the cross-clock domain data transmission method according to any embodiment of this disclosure. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0023] Figure 1 is a schematic diagram of the structure of a multi-core chip system;

[0024] Figure 2 is a schematic block diagram of an integrated circuit provided in at least one embodiment of the present disclosure;

[0025] Figure 3 is a schematic diagram of a clock phase provided in an embodiment of this disclosure;

[0026] Figure 4 is a schematic diagram of the phase relationship between the first clock domain and the second clock domain provided in an embodiment of this disclosure;

[0027] Figure 5 is a schematic diagram of a first synchronization pointer control module provided in an embodiment of this disclosure;

[0028] Figure 6 is a schematic structural diagram of the second sub-module provided in at least one embodiment of this disclosure;

[0029] Figure 7A is a schematic structural diagram of a phase synchronization detection unit provided in an embodiment of this disclosure;

[0030] Figure 7B is a timing diagram of the phase synchronization detection unit shown in Figure 7A provided in an embodiment of this disclosure;

[0031] Figure 8A is a timing diagram of a cross-clock domain data transmission process provided in an embodiment of this disclosure;

[0032] Figure 8B is a timing diagram of a cross-clock domain data transmission process provided in another embodiment of this disclosure;

[0033] Figure 9 is a schematic diagram of state machine state switching provided in an embodiment of this disclosure;

[0034] Figure 10 is a schematic block diagram of a first pointer control module provided in an embodiment of the present disclosure;

[0035] Figure 11 is a schematic flowchart of a cross-clock domain data transmission method provided in at least one embodiment of the present disclosure;

[0036] Figure 12 is a schematic block diagram of an electronic device provided in at least one embodiment of this disclosure; and

[0037] Figure 13 is a schematic diagram of a non-transitory computer-readable storage medium provided in at least one embodiment of the present disclosure. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0040] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and known components have been omitted.

[0041] Figure 1 is a schematic diagram of a multi-core chip system. As shown in Figure 1, this system is a 4-core system-on-a-chip (SoC), comprising four processing cores, three-level caches (L1, L2, and L3 caches) corresponding to each core, an on-chip interconnect network, dynamic random access memory (DRAM), and other intellectual property cores. I-L1$ is a private instruction L1 cache for each core, and D-L1$ is a private data L1 cache for each core. Every two cores share one L2 cache, and all four cores share one L3 cache. The L3 cache and other intellectual property cores (e.g., direct memory access / video / display, etc.) access DRAM via the on-chip interconnect network.

[0042] As shown in Figure 1, high-performance processor chip designs typically involve multiple processing cores sharing the L3 cache. To save power and improve processor performance, DVFS (Dynamic Voltage and Frequency Scaling) technology is often employed. The processing cores operate at different voltages and frequencies under varying load conditions, thus constantly switching frequencies. Because the processing core's frequency changes, the clock frequencies of the processing core and the L3 cache can differ; therefore, the interface signal between the processing core and the L3 cache is an asynchronous clock signal.

[0043] When transmitting data across clock domains, metastability errors may occur. Therefore, signals across clock domains must be processed by cross-clock domain circuits. This technique is known as the synchronization processing technique for asynchronous clock signals.

[0044] These errors can be mitigated by including metastable circuitry (such as sets of flip-flops) between clock domains to enable data transfer. However, such metastable circuitry can increase latency and requires additional circuitry (such as extra entries for buffers) to address control signal delays.

[0045] These errors can be reduced by using an asynchronous first-in-first-out (FIFO) buffer to transfer data across clock domains, but the latency of asynchronous FIFOs is also significant, impacting processor performance. Specifically, asynchronous FIFO circuits determine whether the FIFO is empty or full by comparing the write pointer of one clock domain with the read pointer of another. Therefore, asynchronous FIFOs need to synchronize the read pointer (pointing to the next location in the FIFO to be read) or the write pointer (pointing to the next location in the FIFO to be written) from one clock domain to another. Traditional synchronous circuits use two or more stages of flip-flops (DFFs), and the latency introduced by the synchronous circuit is greater than two clock cycles of the destination clock domain. This is the overall data transmission latency of traditional asynchronous FIFO circuits. For example, when data is transferred from a fast clock to a slow clock, the synchronization delay of the pointer from the fast clock domain to the slow clock domain requires more than two clock cycles of the slow clock domain, resulting in a large data transmission latency.

[0046] Furthermore, as mentioned earlier, high-performance processors often share an L3 cache across multiple processing cores. Processing cores are single-clock-domain digital logic, and their frequencies can be significantly increased with advancements in manufacturing processes and timing optimizations. The cache within the L3 cache is a custom analog circuit with a larger area and longer physical traces, making frequency convergence more difficult for the L3 cache than for the processing core. Therefore, it's possible that in certain high-performance scenarios, the processing core's operating frequency may exceed the L3 cache frequency. Due to the use of DVFS (Dual-Clock Filtering System) technology, it's possible for the processing core's frequency to be higher than the L3 cache frequency, or vice versa. Current cross-clock-domain signal processing typically only supports one frequency relationship, such as only supporting scenarios where the processing core's frequency is lower than the L3 cache frequency, and does not support arbitrary switching between the two clock domains.

[0047] This disclosure provides at least one embodiment of an integrated circuit, a cross-clock domain data transmission method, an electronic device, and a non-transitory computer-readable storage medium.

[0048] In at least one embodiment, the integrated circuit includes a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal. The first clock signal and the second clock signal are co-source clock signals. The frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal. The first clock domain includes a first pointer control module, and the second clock domain includes a second pointer control module. The first pointer control module is configured to generate a first pointer control signal for the first clock domain, such that a first read pointer and a first write pointer in the first clock domain are adjusted according to the first pointer control signal, wherein the first pointer control signal is used to indicate the update time point of the first read pointer and the first write pointer. The second pointer control module is configured to generate a second pointer control signal for the second clock domain, such that a second read pointer and a second write pointer in the second clock domain are adjusted according to the second pointer control signal, wherein the second pointer control signal is used to indicate the update time point of the second read pointer and the first write pointer. The update time of the two write pointers; the integrated circuit also includes a first first-in-first-out (FIFO) buffer and a second FIFO buffer. The first FIFO buffer is configured to perform data transmission from the first clock domain to the second clock domain based on the first write pointer and the second read pointer. The second FIFO buffer is configured to perform data transmission from the second clock domain to the first clock domain based on the first read pointer and the second write pointer. The first pointer control module includes a first synchronous pointer control module, which is configured to: respond to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal based on the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine the first pointer control signal based on the phase relationship; respond to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

[0049] At least one embodiment of this disclosure also provides a cross-clock domain data transmission method, applied to a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal. The first clock domain includes a first first-in-first-out (FIFO) buffer, and the second clock domain includes a second FIFO buffer. The first clock signal and the second clock signal are co-source clock signals, and the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal. The data transmission method includes: in the first clock domain, determining a first pointer control signal, and adjusting a first read pointer and a first write pointer of the first clock domain according to the first pointer control signal, wherein the first pointer control signal is used to indicate the update time point of the first read pointer and the first write pointer; in the second clock domain, determining a second pointer control signal, and adjusting a second read pointer and a second write pointer of the second clock domain according to the second pointer control signal, wherein the second... The pointer control signal is used to indicate the update time points of the second read pointer and the second write pointer; based on the first write pointer and the second read pointer, data transmission from the first clock domain to the second clock domain is performed using a first first-in-first-out buffer, and data transmission from the second clock domain to the first clock domain is performed using a second first-in-first-out buffer based on the first read pointer and the second write pointer; wherein, determining the first pointer control signal includes: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determining the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determining the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determining the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

[0050] The integrated circuit and cross-clock domain data transmission method provided in at least one embodiment of this disclosure can support arbitrary switching of the clock frequencies of two asynchronous clock domains. For example, it can switch from a scenario where the frequency of the first clock domain (e.g., the clock domain of the processing core) is higher than that of the second clock domain (e.g., the clock domain of the L3 cache) to a scenario where the frequency of the first clock domain is lower than that of the second clock domain, and vice versa. Therefore, the integrated circuit provided in at least one embodiment of this disclosure supports DVFS technology, has no limiting requirements on the clock frequency relationship between the two asynchronous clock domains, and is more flexible and has wider applicability.

[0051] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.

[0052] Figure 2 is a schematic block diagram of an integrated circuit provided in at least one embodiment of the present disclosure.

[0053] For example, integrated circuit 100 can be in the form, structure, or function of a chip, processor, etc. Integrated circuit can be any circuit structure that requires cross-clock domain data transmission, and this disclosure does not impose any specific limitations on it.

[0054] As shown in Figure 2, the integrated circuit 100 includes a first clock domain 101 determined based on a first clock signal and a second clock domain 102 determined based on a second clock signal. The first and second clock signals are from the same source, meaning they are obtained by dividing the same clock source, but with different division coefficients. Therefore, the phase relationship between the first and second clock signals can be completely determined by the division coefficients of the two clock domains. Thus, knowing the clock phases of the first and second clock domains allows us to determine at what time the read and write pointers of the fast clock signal increase.

[0055] It should be noted that the integrated circuit 100 may also include a third clock domain, a fourth clock domain, etc., that is, the integrated circuit may include more clock domains. When performing cross-clock domain data transmission, two clock domains controlled by an asynchronous clock are selected from multiple clock domains as the first clock domain and the second clock domain.

[0056] In this disclosure, clock phase is used to indicate the phase value of the clock signal in each clock cycle. For example, this phase value may be a specific value that increases according to a frequency division factor, returns to 0 after reaching an upper limit, and continues to increase.

[0057] Figure 3 is a schematic diagram of a clock phase provided in an embodiment of this disclosure.

[0058] As shown in Figure 3, the first clock signal undergoes a frequency switch at the frequency switching moment in Figure 3, with the division factor increasing from 8 to 12, resulting in a frequency decrease. As shown in Figure 3, before the frequency switch, the first clock cycle is represented by a division factor of 8; after the frequency switch, the first clock cycle is represented by a division factor of 12. The numbers corresponding to each clock cycle in the first clock phase represent the phase value of each clock cycle. The first clock phase starts from 0, increasing by a division factor of 8 in each clock cycle; after the frequency switch, it increases by a division factor of 12 in each clock cycle.

[0059] Of course, the above method is just one example of representing clock phase, and this disclosure is not limited to it. Other similar methods can also be used to represent the phase value of the clock signal in each clock cycle. For example, since this disclosure requires comparison of clock phases, the first clock phase and the second clock phase can be set to have the same numerical range, for example, both can be represented using an 8-bit width.

[0060] For example, in at least one embodiment of this disclosure, the frequency of the first clock signal may be greater than the frequency of the second clock signal, or the frequency of the first clock signal may be less than the clock frequency of the second clock signal. That is, this disclosure does not limit the frequency relationship between the two clock domains.

[0061] As shown in Figure 2, the first clock domain includes a first pointer control module 103, and the second clock domain includes a second pointer control module 104.

[0062] The first pointer control module 103 is configured to generate a first pointer control signal for the first clock domain 101, so that the first read pointer and the first write pointer in the first clock domain 101 are adjusted according to the first pointer control signal.

[0063] For example, the first write pointer adjustment module and the first read pointer adjustment module are used to adjust the first read pointer and the first write pointer according to the first pointer control signal. For example, the first read pointer and the first write pointer can accumulate the currently output first pointer control signal in each clock cycle. Of course, other feasible methods can also be used to adjust the first read pointer and the first write pointer according to the first pointer control signal to reflect the change of the first pointer control signal, and this disclosure does not impose specific limitations.

[0064] The second pointer control module 104 is configured to generate a second pointer control signal for the second clock domain 102, so that the second read pointer and the second write pointer in the second clock domain 102 are adjusted according to the second pointer control signal.

[0065] For example, the second write pointer adjustment module and the second read pointer adjustment module are used to adjust the second read pointer and the second write pointer according to the second pointer control signal. For example, the second read pointer and the second write pointer can accumulate the second pointer control signal in each clock cycle. Of course, other feasible methods can also be used to adjust the second read pointer and the second write pointer according to the second pointer control signal to reflect the change of the second pointer control signal, and this disclosure does not impose specific limitations.

[0066] As shown in Figure 2, the integrated circuit 100 also includes a first first-in-first-out (FIFO) buffer 105 and a second first-in-first-out (FIFO) buffer 106.

[0067] The first first-in-first-out buffer 105 is configured to perform data transfer from the first clock domain to the second clock domain based on the first write pointer and the second read pointer.

[0068] As shown in Figure 2, the first first-in-first-out buffer 105 includes a first buffer and a second read selector. The first buffer is configured to buffer data to be sent to the second clock domain, and the write position of the data is indicated by a first write pointer. The second read selector is configured to select data from the data transmitted from the first buffer in the first clock domain to the second clock domain, based on the second read pointer, at the read address indicated by the second read pointer, and output it. Thus, data transmission from the first clock domain to the second clock domain is completed through the first write pointer and the second read pointer.

[0069] The second first-in-first-out buffer 106 is configured to perform data transfer from the second clock domain to the first clock domain based on the first read pointer and the second write pointer.

[0070] As shown in Figure 2, the second FIFO buffer 106 includes a second buffer and a first read selector. The second buffer is configured to buffer data to be sent to the first clock domain, and the write position of the data is indicated by a second write pointer. The first read selector is configured to select data from the data transmitted from the second buffer in the second clock domain to the first clock domain, based on the first read pointer, at the read address indicated by the first read pointer, and output it. Thus, data transmission from the second clock domain to the first clock domain is completed through the second write pointer and the first read pointer.

[0071] For example, multiple cache entries in the first buffer are connected to multiple channels of the second read selector, and multiple cache entries in the second buffer are connected to multiple channels of the first read selector.

[0072] Of course, integrated circuits may include many other modules, and this disclosure does not impose any specific limitations on this.

[0073] For example, the first pointer control module includes a first synchronous pointer control module, which is configured to: in response to a first clock signal having a frequency greater than that of a second clock signal, determine the phase relationship between the first clock signal and the second clock signal based on the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine a first pointer control signal based on the phase relationship; in response to a first clock signal having a frequency less than that of the second clock signal, determine the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

[0074] For example, the first pointer control signal is used to determine the update time of the first read pointer and the first write pointer. For example, if the frequency of the first clock signal is greater than the frequency of the second clock signal, the first pointer control signal is used to indicate whether there is a rising edge of the second clock signal in the current clock cycle of the first clock signal.

[0075] The first pointer control module and the second pointer control module have similar functions and structures. The difference is that one is used to generate the first pointer control signal, and the other uses similar logic to generate the second pointer control signal.

[0076] For example, the second pointer control module includes a second synchronous pointer control module configured to: in response to the frequency of the second clock signal being greater than the frequency of the first clock signal, determine the phase relationship between the first clock signal and the second clock signal based on the first clock phase and the first clock period of the first clock domain, the second clock signal, and the second clock phase of the second clock domain, and determine the second pointer control signal based on the phase relationship; in response to the frequency of the second clock signal being less than the frequency of the first clock signal, determine the second pointer control signal as a first value, so that the second read pointer and the second write pointer increase by the first value in each clock period of the second clock signal.

[0077] For example, the second pointer control signal is used to determine the update time of the second read pointer and the second write pointer. For example, if the frequency of the second clock signal is greater than the frequency of the first clock signal, the second pointer control signal is used to indicate whether there is a rising edge of the first clock signal in the current clock cycle of the second clock signal.

[0078] The first synchronization pointer control module and the second synchronization pointer control module determine the corresponding pointer control values ​​based on the phase relationship between the first clock signal and the second clock signal.

[0079] Figure 4 is a schematic diagram of the phase relationship between the first clock domain and the second clock domain provided in an embodiment of this disclosure.

[0080] As shown in Figure 4, assuming the first clock signal is divided by 3 and the second clock signal is divided by 5, the phase of the first clock signal in each clock cycle (first clock phase) can be represented as 0-3-6-9-12…, and the phase of the second clock signal in each clock cycle (second clock phase) can be represented as 0-5-10-15…. Based on the phase relationship, it can be determined that, for example, the second rising edge of the second clock signal occurs in the second clock cycle of the first clock signal (cycle1 indicated by the box in Figure 4), and the third rising edge of the second clock signal occurs in the fourth clock cycle of the first clock signal (cycle3 indicated by the box in Figure 4). For example, the second read pointer and the second write pointer of the second clock domain can be set to increment in each clock cycle, while the first read pointer and the first write pointer of the first clock domain only increment in cycles1, 2, 4, etc. (incrementing after the rising edge of the slow clock occurs). This achieves cross-clock domain signal synchronization between the two clock domains, avoiding data loss on asynchronous interfaces.

[0081] In at least one embodiment of this disclosure, the first synchronous pointer control module can determine the phase relationship between the first clock signal and the second clock signal based on the second clock phase, the second clock period, the first clock signal, and the first clock phase when the frequency of the first clock signal is greater than the frequency of the second clock signal, and determine the first pointer control signal based on the phase relationship to estimate the clock phase of the slower clock domain in the faster clock domain; when the frequency of the first clock signal is less than the frequency of the second clock signal, a first value is accumulated in each clock period of the first clock signal, thereby increasing the first read pointer and the first write pointer at each rising edge of the first clock signal. Therefore, even if the frequency changes, the updated phase relationship can be obtained through the first pointer control module, thereby controlling the read pointer and the write pointer. There is no limitation on the frequency relationship between the two asynchronous clock domains, enabling the integrated circuit to support DVFS technology, without limiting frequency changes, providing greater flexibility and wider applicability.

[0082] Similarly, a similar logic can be used to obtain the phase relationship for the second synchronization pointer control module. When a frequency switch occurs, the second read pointer and the second write pointer are determined based on the updated phase relationship. Furthermore, the phase relationship is obtained in the faster clock domain, while in the slower clock domain, only the first value needs to be accumulated in each clock cycle.

[0083] For example, the first synchronization pointer control module and the second synchronization pointer control module have the same structure, and both include a first submodule and a second submodule.

[0084] Figure 5 is a schematic diagram of a first synchronization pointer control module provided in an embodiment of this disclosure.

[0085] The first submodule 1031 of the first synchronization pointer control module is configured to determine the first clock phase according to the first clock period of the first clock domain, wherein the first clock phase is used to indicate the phase value of each clock cycle of the first clock signal.

[0086] For a description of the first clock phase, please refer to the relevant content in Figure 3, which will not be repeated here.

[0087] The second submodule 1032 of the first synchronization pointer control module is configured as follows: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the phase relationship between the first clock signal and the second clock signal is determined according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and the first pointer control signal is determined based on the phase relationship. In response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal being a first value indicates that there is a rising edge of the second clock signal in the current clock period of the first clock signal, and the first pointer control signal being a second value indicates that there is no rising edge of the second clock signal in the current clock period; in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal is determined to be a first value.

[0088] For example, in this disclosure, the clock phase of the slower clock domain is estimated in the faster clock domain. Therefore, when the frequency of the first clock signal is greater than the frequency of the second clock signal, the phase of the slower second clock signal is estimated by the second submodule to determine the phase relationship between the first clock signal and the second clock signal, and the first pointer control signal is determined based on the phase relationship.

[0089] For example, the first pointer control signal can output a first value or a second value in each clock cycle of the first clock signal. If the first value is output, it indicates that the rising edge of the second clock signal is in the current clock cycle, such as cycle1 in Figure 4. If the second value is output, it indicates that the rising edge of the second clock signal is not in the current clock cycle, such as cycle2 in Figure 4. For example, the first value can be 1 and the second value can be 0.

[0090] For example, if the frequency of the first clock signal is greater than the frequency of the second clock signal, then the first value can be output in each clock cycle of the first clock signal. For example, at the rising edge of each slow clock signal, the first read pointer and the first write pointer are incremented by the first value, for example, by 1.

[0091] The second synchronization pointer control module also includes a first submodule and a second submodule.

[0092] For example, the first submodule of the second synchronization pointer control module is configured to determine the second clock phase according to the second clock period of the second clock domain, wherein the second clock phase is used to indicate the phase value of each clock period of the second clock signal.

[0093] For a description of the second clock phase, please refer to the relevant content in Figure 3, which will not be repeated here.

[0094] The second submodule of the second synchronization pointer control module is configured as follows: In response to the frequency of the second clock signal being greater than the frequency of the first clock signal, the phase relationship between the first clock signal and the second clock signal is determined based on the first clock phase and the first clock period of the first clock domain, the second clock signal, and the second clock phase of the second clock domain, and the second pointer control signal is determined based on the phase relationship. In response to the frequency of the second clock signal being greater than the frequency of the first clock signal, the second pointer control signal being a first value indicates that the rising edge of the first clock signal is located in the current clock period of the second clock signal, and the second pointer control signal being a second value indicates that the rising edge of the first clock signal is not located in the current clock period; in response to the frequency of the second clock signal being greater than the frequency of the first clock signal, the second pointer control signal is determined to be a first value.

[0095] Figure 6 is a schematic structural diagram of the second sub-module provided in at least one embodiment of this disclosure.

[0096] The structure and function of the second submodule are described below using the first synchronization pointer control module as an example. The same applies to the second submodule of the second synchronization pointer control module, so it will not be described again here.

[0097] As shown in Figure 6, the second submodule 1032 includes a phase synchronization detection unit, a phase estimation unit, and a phase tracking unit.

[0098] The phase synchronization detection unit is configured to determine a target clock phase in the second clock signal based on the second clock phase and the first clock signal. For example, the target clock phase is the phase value of a selected clock cycle in the second clock signal.

[0099] Figure 7A is a schematic structural diagram of a phase synchronization detection unit provided in an embodiment of this disclosure.

[0100] As shown in Figure 7A, the phase synchronization detection unit includes a multi-stage flip-flop group and an AND gate. The multi-stage flip-flop group is configured to use a first clock signal as the clock and synchronize with a selected transition edge in the second clock signal to transmit the phase transition signal (the selected transition edge) from the slow clock domain to the fast clock domain, avoiding metastability during the synchronization process. The AND gate is configured to perform an AND operation between the synchronized transition edge and the second clock phase to obtain the phase value of the clock period containing the selected transition edge as the target clock phase, which is a phase value in the second clock phase.

[0101] Figure 7B is a timing diagram of the phase synchronization detection unit shown in Figure 7A provided in an embodiment of this disclosure.

[0102] As shown in Figure 7B, the phase value of the clock cycle in which the selected transition edge occurs is phase A. After passing through multiple flip-flop groups, this transition edge is output as a synchronized transition edge. An AND gate performs an AND operation between the synchronized transition edge and the second clock phase to obtain the target clock phase, i.e., phase A.

[0103] It should be noted that in the phase synchronization detection unit, starting from the selected transition edge, the second clock phase remains phase A in subsequent clock cycles to obtain the target clock phase. Then, when the next transition edge is selected and the above process is repeated, the second clock phase is updated to the phase value of that transition edge.

[0104] For example, the phase estimation unit is configured to determine the target clock period corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock period, wherein the target clock phase is located in the phase interval corresponding to the target clock period, and the phase interval is determined by the phase value of the target clock period and the phase value of the next clock period of the target clock period.

[0105] For example, the phase estimation unit is configured to compare the target clock phase with the phase intervals corresponding to multiple clock cycles to determine the target clock cycle corresponding to the target clock phase, wherein the multiple clock cycles are multiple clock cycles in the first clock signal before the transition edge after synchronization.

[0106] For example, taking Figure 7B as an example, multiple clock cycles include four clock cycles before the transition edge after synchronization, including cycles 0, 1, 2, and 3 in Figure 7B. The number of clock cycles selected can be related to the number of stages of the flip-flops in the multi-stage flip-flop group.

[0107] For example, first determine whether the target clock phase is located in the phase interval corresponding to period 0. For example, the phase interval corresponding to period 0 is [phase1, phase1+period1]. Here, Phase1 represents the phase value corresponding to period 0, and period1 is the clock period of the first clock signal, which can be represented by a frequency division coefficient.

[0108] If phase A falls within the phase interval corresponding to period 0, then the target clock period corresponding to the target clock phase is determined to be period 0. If phase A does not fall within the phase interval corresponding to period 0, then it continues to determine whether phase A falls within the phase interval corresponding to period 1. If phase A falls within the phase interval corresponding to period 1, then the target clock period corresponding to the target clock phase is determined to be period 1. If phase A does not fall within the phase interval corresponding to period 1, then it continues to determine whether phase A falls within the phase interval corresponding to period 2, and so on. Therefore, the target clock period corresponding to the target clock phase in the first clock signal can be determined. Simultaneously, the rising edge corresponding to the transition edge in the first clock signal, which is also the rising edge of the target clock period, can also be determined.

[0109] Therefore, in this disclosure, the correspondence between the rising edges of the first clock signal and the second clock signal is indirectly obtained through phase comparison, thereby obtaining the phase relationship. The pointer control signal is obtained through the phase relationship to adjust the read pointer and the write pointer.

[0110] For example, the phase estimation unit is further configured to estimate the phase change of a second clock signal, measured by the clock period of the first clock signal. For example, the phase estimation unit can also estimate target phases in the first clock signal corresponding to multiple clock periods after the target clock period, wherein each target phase is a phase value in the second clock signal.

[0111] For example, taking Figure 7B as an example, assuming the target clock period corresponding to phase A is determined to be period 0, phase A is then added to the second clock period to obtain the phase B to be judged. Phase B is compared with the phase interval corresponding to period 1. If phase B is located within the phase interval corresponding to period 1, the target phase corresponding to period 1 is determined to be phase B. If phase B is not located within the phase interval corresponding to period 1, the target phase corresponding to period 1 is determined to be phase A, and so on. Thus, the phase change of the second clock signal, measured by the clock period of the first clock signal, can be obtained. For example, it can be estimated how many first clock cycles phase A lasted, how many first clock cycles phase B lasted, etc.

[0112] The phase tracking unit is configured to continuously estimate the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock period. For example, the phase tracking unit can continuously determine the first pointer control signal output in each clock cycle after the synchronization transition edge.

[0113] After obtaining the target clock phase and its corresponding target clock period, it is possible to continuously estimate whether the rising edge of the second clock signal falls within the current clock period of the first clock signal based on this correspondence. This method can derive the first pointer control signal in real time with minimal computational resources, without having to repeatedly use the above method to determine the pointer control signal.

[0114] For example, when the phase tracking unit continuously estimates the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock period, it includes performing the following steps: determining the clock phase to be estimated based on the target clock phase and the second clock cycle; in the current clock cycle: determining whether the clock phase to be estimated is located within the phase interval corresponding to the current clock cycle based on the clock phase to be estimated; in response to the clock phase to be estimated being located within the phase interval corresponding to the current clock cycle, determining the first pointer control signal as a first value, and updating the clock phase to be estimated based on the second clock cycle; in response to the clock phase to be estimated not being located within the phase interval corresponding to the current clock cycle, determining the first pointer control signal as a second value.

[0115] For example, the target clock phase is added to the second clock period to obtain the clock phase B to be estimated. For example, if the clock period corresponding to clock phase B has been determined through the above process, clock phase B can be added to the second clock period to obtain the clock phase C to be estimated.

[0116] For example, assuming the current clock cycle is cycle 5 in Figure 7B, for the clock phase C to be estimated, determine whether the clock phase C to be estimated is located in the phase interval corresponding to cycle 5. For example, the phase interval corresponding to cycle 5 is determined by the phase value of cycle 5 and the phase value of the next clock cycle of cycle 5.

[0117] If the clock phase C to be estimated is located in the phase interval corresponding to period 5, the first pointer control signal is determined to be the first value, the second submodule outputs the first value in period 5, indicating that there is a rising edge of the second clock signal in period 5, and the second clock period is added to the clock phase C to be estimated, the clock phase to be estimated is updated to phase D, and the subsequent judgment continues.

[0118] If the clock phase C to be estimated is not located in the phase interval corresponding to period 5, then the first pointer control signal is determined to be the second value, indicating that no rising edge of the second clock signal falls into period 5. The above process continues in the next clock cycle to determine whether the clock phase C to be estimated is located in the phase interval corresponding to the next clock cycle; this will not be elaborated further here.

[0119] Therefore, phase tracking can be performed based on the target clock phase in the second clock signal and the target clock period in the first clock signal corresponding to the target clock phase. This correspondence can be used to determine the update time points of the subsequent read pointer and write pointer. Thus, in subsequent clock cycles, a pointer control signal indicating whether the rising edge of the second clock signal falls into the current clock cycle can be continuously output to continuously update and adjust the read pointer and write pointer.

[0120] In this disclosure, after a frequency switch occurs, the phase relationship between the first clock signal and the second clock signal after the frequency update can be determined based on the above process, thereby determining the update time point of the read pointer and the write pointer. There is no restriction on the frequency relationship between the two clock domains. The clock frequency of the first clock domain can be higher than the clock frequency of the second clock domain, and the clock frequency of the first clock domain can also be lower than the clock frequency of the second clock domain.

[0121] For example, the first read pointer and the first write pointer are adjusted according to the first pointer control signal in each clock cycle of the first clock signal, and the second read pointer and the second write pointer are adjusted according to the second pointer control signal in each clock cycle of the second clock signal.

[0122] In response to a write clock cycle in the first clock domain, a data write operation is performed in the read clock cycle corresponding to the write clock cycle in the second clock signal. For example, the data write operation includes writing data to a first first-in-first-out buffer according to a first write pointer, and the data read operation includes reading the written data according to a second read pointer.

[0123] For example, the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal, and the rising edge of the second clock signal that is a second clock cycle ahead of the rising edge of the read clock cycle is located in the clock cycle preceding the write clock cycle of the first clock signal.

[0124] For example, the clock frequency of the first clock signal is less than the clock frequency of the second clock signal, and the rising edge of the write clock cycle is a clock cycle earlier than the reading clock cycle in the second clock signal.

[0125] For example, 'a' is a positive integer and is related to the depth of the first FIFO buffer. For example, if the depth of the first FIFO buffer is 3, 'a' can be 1.

[0126] In this disclosure, the read pointer and write pointer are adjusted in each clock cycle, and the read pointer and write pointer are in an incrementing cycle. In order to ensure that read and write do not conflict, in at least one embodiment of this disclosure, when a data write operation occurs at a certain rising edge (rising edge m) of the slower clock domain, a data read operation is performed in the read clock cycle of the faster clock signal. The rising edge of the clock cycle that is a slower clock signal different from the rising edge m is located in the clock cycle before the read clock cycle.

[0127] Figure 8A is a timing diagram of a cross-clock domain data transmission process provided in an embodiment of this disclosure.

[0128] As shown in Figure 8A, assuming the frequency of the first clock signal is less than the frequency of the second clock signal, the depth of the first first-in-first-out buffer is 3, the first pointer control signal outputs 1 in each clock cycle, and the first read pointer and the first write pointer increment by 1 in each clock cycle, as shown in Figure 8A, the first read pointer and the first write pointer cycle with 0, 1, 2.

[0129] As shown in Figure 8A, the rising edge 0 of the first clock signal falls within the period 0 of the second clock signal. Therefore, the second pointer control signal 1 is output during period 0 of the second clock signal. During period 1 of the second clock signal, the second read pointer and the second write pointer increment by 1, changing from 2 to 0. The rising edge 1 of the first clock signal falls within the period 2 of the second clock signal. Therefore, the second pointer control signal 1 is output during period 2 of the second clock signal. During period 3 of the second clock signal, the second read pointer and the second write pointer increment by 1, changing from 0 to 1. The rising edge 2 of the first clock signal falls within the period 5 of the second clock signal. Therefore, the second pointer control signal 1 is output during period 5 of the second clock signal. During period 6 of the second clock signal, the second read pointer and the second write pointer increment by 1, changing from 1 to 2. The subsequent processes follow the same pattern and will not be elaborated further here.

[0130] Therefore, as shown in Figure 8A, assuming a data write operation occurs at rising edge 0, the data at position 1 needs to be read out during the second clock cycle 3. Assuming a data write operation occurs at rising edge 1, the data at position 2 needs to be read out during the second clock cycle 6. This avoids data read / write conflicts, and the read and write pointers can change according to the pointer control signal in each clock cycle without considering data write and read requests.

[0131] Furthermore, as shown in Figure 8A, the delay caused by the aforementioned cross-clock domain data transmission is less than two clock cycles of the slow clock domain. Compared with the traditional data transmission method that uses multi-level flip-flops for synchronization, it can reduce the synchronization processing delay of asynchronous clock signals.

[0132] In at least one embodiment of this disclosure, when a data write operation occurs at a rising edge (rising edge n) of a faster clock domain, a data read operation is performed in the read clock cycle of a slower clock signal, wherein the rising edge of the slower clock signal that differs from the rising edge of the read clock cycle by a+1 slower clock cycles is located in the clock cycle preceding the write clock cycle of the faster clock signal.

[0133] Figure 8B is a timing diagram of a cross-clock domain data transmission process provided in another embodiment of this disclosure.

[0134] As shown in Figure 8B, assuming the frequency of the first clock signal is greater than the frequency of the second clock signal, the depth of the first first-in-first-out buffer is 3, the second pointer control signal outputs 1 in each clock cycle, and the second read pointer and the second write pointer increment by 1 in each clock cycle, as shown in Figure 8B. The second read pointer and the second write pointer cycle with 0, 1, and 2.

[0135] As shown in Figure 8B, the rising edge 0 of the second clock signal falls within the period 0 of the first clock signal. Therefore, the first pointer control signal 1 is output during period 0 of the first clock signal. During period 1 of the first clock signal, the first read pointer and the first write pointer increment by 1, changing from 1 to 2. The rising edge 1 of the second clock signal falls within the period 2 of the first clock signal. Therefore, the first pointer control signal 1 is output during period 2 of the first clock signal. During period 3 of the first clock signal, the first read pointer and the first write pointer increment by 1, changing from 2 to 0. The rising edge 2 of the second clock signal falls within the period 5 of the first clock signal. Therefore, the first pointer control signal 1 is output during period 5 of the first clock signal. During period 6 of the first clock signal, the first read pointer and the first write pointer increment by 1, changing from 0 to 1. The subsequent processes follow the same pattern and will not be elaborated further here.

[0136] Therefore, as shown in Figure 8B, assuming a data write operation occurs during the first clock signal cycle 1, the data at write position 2 needs to be read out at the rising edge 2 of the second clock signal. Similarly, assuming a data write operation occurs during the first clock signal cycle 3, the data at write position 0 needs to be read out at the rising edge 3 of the second clock signal. This avoids data read / write conflicts, and the read and write pointers can change according to the pointer control signal in each clock cycle, regardless of data write and read requests.

[0137] As shown in Figure 8B, the delay caused by the above cross-clock domain data transmission is less than two clock cycles of the slow clock domain. Compared with the traditional data transmission method that uses multi-level flip-flops for synchronization (at least due to the synchronizer bringing more than two clock cycles of the destination clock domain), it can reduce the synchronization processing delay of asynchronous clock signals.

[0138] Of course, it should be noted that the above pointer adjustment process is described using the example of a write operation in the first clock domain and a read operation in the second clock domain. The pointer adjustment logic is similar for a write operation in the second clock domain and a read operation in the first clock domain, and will not be repeated here.

[0139] In this disclosure, the clock signal uses a common clock signal, so the phase relationship between the two clock domains can be determined by the frequency division coefficient, thereby determining the update time points of the read pointer and write pointer of the two clock domains and reducing the synchronization processing delay of the asynchronous clock signal.

[0140] As mentioned earlier, high-performance processors employ DVFS technology, where the processing cores use different voltages and frequencies depending on the workload. For example, when a processing core has a low workload, its voltage and frequency can be reduced to a very low level to save power, while when a processing core has a high workload, its voltage and frequency can be increased. Cross-clock data processing is prone to errors during frequency switching. Currently, data transmission is typically stopped during frequency switching, but stopping data transmission during frequency switching will negatively impact the performance of high-performance processors.

[0141] In the integrated circuit provided in at least one embodiment of this disclosure, the first clock domain further includes a first state machine and a first asynchronous pointer control module, and the second clock domain further includes a second state machine and a second asynchronous pointer control module.

[0142] For example, the first asynchronous pointer control module and the second asynchronous pointer control module each include multiple levels of flip-flops. The first asynchronous pointer control module and the second asynchronous pointer control module use their respective multiple levels of flip-flops to synchronize the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains.

[0143] For example, the first and second asynchronous pointer control modules determine whether a first-in-first-out (FIFO) buffer is empty or full by comparing the write pointer of one clock domain with the read pointer of another clock domain. Therefore, the asynchronous pointer control module needs to synchronize the read pointer (pointing to the next location in the FIFO buffer to read data) or the write pointer (pointing to the next location in the FIFO buffer to write data) from one clock domain to another. Unlike synchronous pointer control modules, in asynchronous pointer control modules, pointer synchronization is achieved through a synchronizer, which typically includes multiple flip-flops. These flip-flops stably reflect the pointer value of another clock domain, avoiding metastability issues. When performing pointer comparisons, these stable register values ​​are used instead of directly comparing pointers across clock domains. Although asynchronous pointer control modules may introduce more latency, they can still maintain cross-clock domain data transmission during frequency switching.

[0144] For example, the asynchronous pointer control module can adopt a conventional structure that uses an asynchronous FIFO for cross-clock domain data transmission, which will not be elaborated here.

[0145] For example, the first state machine is configured to control the first clock domain to use the first asynchronous pointer control module to perform cross-clock domain data transmission when a frequency switch occurs, and to control the first clock domain to use the first synchronous pointer control module to perform cross-clock domain data transmission after the frequency switch is completed and the phase estimation is completed.

[0146] The second state machine is configured to control the second clock domain to use the second asynchronous pointer control module to perform cross-clock domain data transmission when a frequency switch occurs, and to control the second clock domain to use the second synchronous pointer control module to perform cross-clock domain data transmission after the frequency switch is completed and the phase estimation is completed.

[0147] Figure 9 is a schematic diagram of state machine state switching provided in an embodiment of this disclosure.

[0148] As shown in Figure 9, when the integrated circuit is reset or initially powered on, it is in the reset state and enters the first state. At this time, the frequency is changing and has not yet stabilized. In the first state, the first asynchronous pointer control module, the second asynchronous pointer control module, the first first-in-first-out buffer, and the second first-in-first-out buffer are used to perform cross-clock domain data transmission.

[0149] After frequency switching and phase estimation are completed, for example when the clock is stable and the first pointer control module or the second pointer control module completes phase estimation and outputs the first pointer control signal or the second pointer control signal, the system enters the second state. At this time, the first synchronous pointer control module, the second synchronous pointer control module, the first first-in-first-out buffer, and the second first-in-first-out buffer are used to perform cross-clock domain data transmission.

[0150] When a frequency switch occurs again, the system exits the second state, enters the third state, and eventually returns to the first state. At this point, the first asynchronous pointer control module, the second asynchronous pointer control module, the first first-in-first-out buffer, and the second first-in-first-out buffer are used to perform cross-clock domain data transmission, and the above process is repeated.

[0151] The first state machine and the second state machine are further configured to receive a first indication information indicating whether a frequency switching is complete, and a second indication information indicating the frequency relationship between the first clock signal and the second clock signal. In response to the first indication information indicating a frequency switching, the first state machine controls the first clock domain to use a first asynchronous pointer control module to perform cross-clock domain data transmission, and the second state machine controls the second clock domain to use a second asynchronous pointer control module to perform cross-clock domain data transmission. The first state machine and the second state machine are further configured to determine whether a frequency switching is complete and whether phase estimation is completed based on the first and second indication information.

[0152] For example, when the first state machine determines whether frequency switching is complete and phase estimation is completed based on the first indication information and the second indication information, it includes the following operations: In response to the first indication information indicating that frequency switching is complete and the second indication information indicating that the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal: the first state machine controls the first synchronization pointer control module to perform phase estimation to obtain a phase relationship and determine the first pointer control signal based on the phase relationship; in response to the first synchronization pointer control module completing phase estimation, it determines that frequency switching is complete and phase estimation is completed, and the first state machine is also configured to perform a synchronization handshake with the second state machine so that the second state machine controls the second clock domain to use the second synchronization pointer control module to perform cross-clock domain data transmission; In response to the first indication information indicating that frequency switching is complete and the second indication information indicating that the clock frequency of the first clock signal is less than the clock frequency of the second clock signal: after completing the synchronization handshake with the second state machine, it determines that frequency switching is complete and phase estimation is completed.

[0153] Figure 10 is a schematic block diagram of a first pointer control module provided in an embodiment of the present disclosure.

[0154] It should be noted that the second pointer control module also has a similar structure, such as including a second state machine, a second asynchronous pointer control module, and a second synchronous pointer control module. The specific details will not be described again.

[0155] As shown in Figure 10, the first state machine receives the first indication information and the second indication information, determines whether the state needs to be switched based on the first indication information and the second indication information, and outputs different control signals to switch between using the first synchronous control module or the first asynchronous pointer control module to generate the first pointer control signal.

[0156] For example, when the chip is reset or the frequency is unstable, the first indication information indicates that the frequency switching has not yet been completed. At this time, it is in the first state, and the first state machine outputs control signal 1. The first pointer control signal output by the first asynchronous pointer control module is used to adjust the first read pointer and the first write pointer. For example, when the first asynchronous pointer control module is used, the first pointer control signal includes a control signal for the first read pointer and a control signal for the first write pointer, which are used to adjust the first read pointer and the first write pointer respectively.

[0157] When the first indication information indicates that the chip frequency switching is complete, the second indication information is used to determine whether the clock frequency of the first clock domain is greater than the clock frequency of the second clock domain.

[0158] If the clock frequency of the first clock domain is greater than the clock frequency of the second clock domain, the first state machine controls the first synchronization pointer control module to perform phase estimation according to the above process, including determining the phase relationship and determining the first pointer control signal based on the phase relationship. The specific process is detailed in the description of the first synchronization pointer control module above and will not be repeated here. After the first synchronization pointer control module completes the phase estimation, it confirms that the frequency switching is complete and the phase estimation is finished, and enters the second state. At this time, the first state machine outputs a control signal of 0, using the first pointer control signal output by the first synchronization pointer control module to adjust the first read pointer and the first write pointer. Furthermore, the first state machine is configured to perform a synchronization handshake with the second state machine, so that the second state machine controls the second clock domain to use the second synchronization pointer control module for cross-clock domain data transmission. For the second synchronization pointer control module, its output second pointer control signal is the first value. Thus, both clock domains enter the synchronization pointer control logic.

[0159] When the first indication information indicates that the chip frequency switching is complete, if the clock frequency of the first clock domain is less than the clock frequency of the second clock domain, the first state machine waits for a handshake signal from the second state machine. At this time, the second state machine controls the second synchronization pointer control module to perform phase estimation according to the above process. Specifically, the second state machine also determines, based on the received first and second indication information, that the frequency switching is complete and the frequency of the second clock signal is greater than the frequency of the first clock signal. The second state machine then controls the second synchronization pointer control module to perform phase estimation, including determining the phase relationship and determining the second pointer control signal based on the phase relationship. After the second synchronization pointer control module completes the phase estimation, it determines that the frequency switching is complete and the phase estimation is finished, and enters the second state. At this time, the second state machine outputs a control signal of 0, using the second pointer control signal output by the second synchronization pointer control module to adjust the second read pointer and the second write pointer. Furthermore, the second state machine is also configured to perform a synchronous handshake with the first state machine. After completing the synchronous handshake with the second state machine, the first state machine determines that the frequency switching is complete and the phase estimation is finished, and controls the first clock domain to use the first synchronization pointer control module for cross-clock domain data transmission. For the first synchronization pointer control module, its output first pointer control signal is a first value. As a result, both clock domains enter the synchronization pointer control logic.

[0160] When the first indication information indicates that the chip frequency has switched again, both the first state machine and the second state machine exit the second state and enter the third state, and finally return to the first state. Both the first state machine and the second state machine output control signal 1 to switch to their respective asynchronous pointer control modules, and continue to use the asynchronous pointer control modules to adjust the read pointer and write pointer until they enter the second state again.

[0161] The integrated circuit provided in at least one embodiment of this disclosure can switch from a synchronous pointer control module to an asynchronous pointer control module during dynamic frequency switching. The asynchronous pointer control module is used to synchronize the clock signal during frequency switching. When the frequency switching is completed and phase estimation has been completed, the synchronous pointer control module can be used again through a synchronous handshake mechanism. This enables data transmission to be maintained during dynamic frequency switching and low-latency cross-clock processing to be maintained after the frequency stabilizes. Data transmission can be performed throughout the entire runtime of the integrated circuit, improving the performance of the processor without pausing data transmission due to frequency switching.

[0162] Figure 11 is a schematic flowchart of a cross-clock domain data transmission method provided in at least one embodiment of the present disclosure.

[0163] For example, this cross-clock domain data transmission method is applied to a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal. The first clock domain includes a first first-in-first-out buffer, and the second clock domain includes a second first-in-first-out buffer. The first clock signal and the second clock signal are clock signals from the same source. The frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal.

[0164] For example, this cross-clock domain data transmission method can be applied to integrated circuits that include different clock domains. For a description of clock domains and integrated circuits, please refer to the relevant sections mentioned above, which will not be repeated here.

[0165] For example, as shown in FIG11, the cross-clock domain data transmission method provided in this embodiment of the present disclosure includes steps S110 to S130.

[0166] In step S110, in the first clock domain, a first pointer control signal is determined, and the first read pointer and the first write pointer of the first clock domain are adjusted according to the first pointer control signal.

[0167] For example, the first pointer control signal is used to indicate the update time of the first read pointer and the first write pointer.

[0168] For details on the process of adjusting the first read pointer and the first write pointer using the first pointer control signal, please refer to the relevant description in the aforementioned integrated circuit. Repeated descriptions will not be repeated here.

[0169] In step S120, in the second clock domain, a second pointer control signal is determined, and the second read pointer and the second write pointer of the second clock domain are adjusted according to the second pointer control signal.

[0170] For example, the second pointer control signal is used to indicate the update time of the second read pointer and the second write pointer.

[0171] For details on adjusting the second read pointer and the second write pointer using the second pointer control signal, please refer to the relevant description in the aforementioned integrated circuit. Repeated descriptions will not be repeated here.

[0172] In step S130, data transmission from the first clock domain to the second clock domain is performed using the first first-in-first-out buffer based on the first write pointer and the second read pointer, and data transmission from the second clock domain to the first clock domain is performed using the second first-in-first-out buffer based on the first read pointer and the second write pointer.

[0173] For example, in some embodiments, determining the first pointer control signal may include: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determining the phase relationship between the first clock signal and the second clock signal based on the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determining the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determining the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

[0174] For example, in some embodiments, determining the second pointer control signal may include: in response to the frequency of the second clock signal being greater than the frequency of the first clock signal, determining the phase relationship between the first clock signal and the second clock signal based on the first clock phase and the first clock period of the first clock domain, the second clock signal, and the second clock phase of the second clock domain, and determining the second pointer control signal based on the phase relationship; in response to the frequency of the second clock signal being less than the frequency of the first clock signal, determining the second pointer control signal to a first value, so that the second read pointer and the second write pointer increase by the first value in each clock period of the second clock signal.

[0175] The method for determining the second pointer control signal is similar to that for determining the first pointer control signal. The following description uses the first pointer control signal as an example to illustrate the process of determining the first pointer control signal. For the process of determining the second pointer control signal, please refer to the process of determining the first pointer control signal and adjust accordingly. It will not be repeated here.

[0176] For example, determining the first pointer control signal may further include: determining a first clock phase based on a first clock period of a first clock domain, wherein the first clock phase is used to indicate the phase value of each clock period of the first clock signal.

[0177] For example, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal being a first value indicates that the rising edge of the second clock signal is located in the current clock cycle of the first clock signal, and the first pointer control signal being a second value indicates that the rising edge of the second clock signal is not located in the current clock cycle.

[0178] For example, determining the phase relationship between the first clock signal and the second clock signal based on the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase, and determining the first pointer control signal based on the phase relationship, may include: determining a target clock phase in the second clock signal based on the second clock phase and the first clock signal, wherein the target clock phase is the phase value of a selected clock period in the second clock signal; determining a target clock period corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock period, wherein the target clock phase is located in the phase interval corresponding to the target clock period, and the phase interval is determined by the phase value of the target clock period and the phase value of the next clock period of the target clock period; and continuously estimating the first pointer control signal output in each current clock period of the first clock signal based on the target clock phase and the target clock period.

[0179] For example, the process of determining the target clock phase can be found in the description of the phase estimation unit mentioned above, and will not be repeated here.

[0180] For example, determining the phase relationship between the first clock signal and the second clock signal based on the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase, and determining the first pointer control signal based on the phase relationship, may further include: estimating the phase change of the second clock signal as measured by the clock period of the first clock signal.

[0181] For details on the specific implementation process of estimating phase changes, please refer to the relevant description of the aforementioned phase estimation unit; it will not be repeated here.

[0182] For example, in some embodiments, continuously estimating the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock period may include: determining the clock phase to be estimated based on the target clock phase and the second clock cycle; in the current clock cycle: determining whether the clock phase to be estimated is located within the phase interval corresponding to the current clock cycle based on the clock phase to be estimated; in response to the clock phase to be estimated being located within the phase interval corresponding to the current clock cycle, determining the first pointer control signal output in the current clock cycle as a first value, and updating the clock phase to be estimated based on the second clock cycle; in response to the clock phase to be estimated not being located within the phase interval corresponding to the current clock cycle, determining the first pointer control signal output in the current clock cycle as a second value.

[0183] For details on the process of continuously estimating the first pointer control signal, please refer to the relevant description of the phase tracking unit mentioned above. Repeated details will not be repeated here.

[0184] For example, the first read pointer and the first write pointer are adjusted according to the first pointer control signal in each clock cycle of the first clock signal, and the second read pointer and the second write pointer are adjusted according to the second pointer control signal in each clock cycle of the second clock signal; a data write operation is generated in response to the write clock cycle in the first clock domain, and a data read operation is performed in the read clock cycle corresponding to the write clock cycle in the second clock signal, wherein the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal, and the rising edge of the second clock signal that differs from the rising edge of the read clock cycle by a+1 second clock cycles is located in the clock cycle preceding the write clock cycle in the first clock signal, and the clock frequency of the first clock signal is less than the clock frequency of the second clock signal, wherein the rising edge that differs from the rising edge of the write clock cycle by a first clock cycle is located in the clock cycle preceding the read clock cycle, where a is a positive integer.

[0185] In this disclosure, after a frequency switch, the phase relationship between the first and second clock signals after the frequency update can be determined based on the above process. This determines the update times for the read and write pointers. There are no restrictions on the frequency relationship between the two clock domains; the clock frequency of the first clock domain can be higher or lower than the clock frequency of the second clock domain. Furthermore, since the clock signals are from the same source, the phase relationship between the two clock domains can be determined using a frequency division factor, thereby determining the update times for the read and write pointers in both clock domains and reducing the synchronization processing delay of asynchronous clock signals.

[0186] For example, in at least one embodiment of this disclosure, the cross-clock domain data transmission method further includes: when a frequency switch occurs, controlling the first clock domain to use asynchronous pointer control logic to perform cross-clock domain data transmission; after the frequency switch is completed and phase estimation is completed, controlling the first clock domain to use synchronous pointer control logic to perform cross-clock domain data transmission, wherein the asynchronous pointer control logic includes synchronizing the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through multi-level flip-flops, and the synchronous pointer control logic includes obtaining the phase relationship and performing cross-clock domain data transmission based on the phase relationship.

[0187] For example, the asynchronous pointer control logic can refer to the aforementioned description of the asynchronous pointer control module, and the asynchronous pointer control logic can implement the relevant functions of the asynchronous pointer control module. Similarly, the synchronous pointer control logic can refer to the aforementioned description of the synchronous pointer control module, and the synchronous pointer control logic can implement the relevant functions of the synchronous pointer control module.

[0188] For example, in some embodiments, controlling the first clock domain to use asynchronous pointer control logic for cross-clock domain data transmission when a frequency switch occurs may include: in response to a received first indication information indicating that a frequency switch has occurred, controlling the first clock domain to use asynchronous pointer control logic for cross-clock domain data transmission.

[0189] For example, in some embodiments, the data transmission method further includes: determining whether frequency switching is complete and phase estimation is completed based on first indication information and second indication information, wherein the second indication information is used to indicate the frequency magnitude relationship between the first clock signal and the second clock signal.

[0190] For example, in some embodiments, determining whether frequency switching is complete and phase estimation is complete based on first indication information and second indication information may include: in response to the first indication information indicating that frequency switching is complete and the second indication information indicating that the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal: performing phase estimation to obtain the phase relationship and determining the first pointer control signal based on the phase relationship; in response to determining the first pointer control signal, determining that frequency switching is complete and phase estimation is complete, and synchronizing the state with the second clock domain so that the second clock domain adjusts the pointer according to the determined second pointer control signal for data transmission across clock domains; in response to the first indication information indicating that frequency switching is complete and the second indication information indicating that the clock frequency of the first clock signal is less than the clock frequency of the second clock signal: after synchronizing the state with the second clock domain, determining that frequency switching is complete and phase estimation is complete, and adjusting the pointer according to the determined first pointer control signal for data transmission across clock domains.

[0191] For a detailed description of the above process, please refer to the relevant content on integrated circuits mentioned above, which will not be repeated here.

[0192] The cross-clock domain data transmission method provided in at least one embodiment of this disclosure can switch the synchronous pointer control module to the asynchronous pointer control module during dynamic frequency switching. The asynchronous pointer control module is used to realize clock signal synchronization during frequency switching. When the frequency switching is completed and the phase estimation has been completed, the synchronous pointer control module can be used again through the synchronous handshake mechanism. This achieves data transmission during dynamic frequency switching and low-latency cross-clock processing after the frequency stabilizes.

[0193] At least one embodiment of this disclosure also provides an electronic device, and FIG12 is a schematic block diagram of an electronic device provided in at least one embodiment of this disclosure.

[0194] For example, as shown in Figure 12, the electronic device includes a processor 201, a communication interface 202, a memory 203, and a communication bus 204. The processor 201, communication interface 202, and memory 203 communicate with each other via the communication bus 204. Components such as the processor 201, communication interface 202, and memory 203 can also communicate with each other via a network connection. This disclosure does not limit the type and function of the network.

[0195] For example, memory 203 is used to store computer-executable instructions non-transitory. When processor 201 executes the computer-executable instructions, the computer-executable instructions are executed by processor 201 to implement the cross-clock domain data transmission method according to any of the above embodiments. For specific implementations and related explanations of each step of the cross-clock domain data transmission method, please refer to the embodiments of the cross-clock domain data transmission method described above, and will not be repeated here.

[0196] For example, the implementation of the cross-clock domain data transmission method by the processor 201 executing the program stored in the memory 203 is the same as the implementation mentioned in the aforementioned embodiment of the cross-clock domain data transmission method, and will not be repeated here.

[0197] For example, the communication bus 204 can be a Peripheral Component Interconnect Standard (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0198] For example, communication interface 202 is used to enable communication between electronic devices and other devices.

[0199] For example, processor 201 can control other components in an electronic device to perform desired functions. Processor 201 can be a central processing unit (CPU), a network processor (NP), or a digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The central processing unit (CPU) can be based on x86 or ARM architectures, etc.

[0200] For example, memory 203 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-executable instructions may be stored on the computer-readable storage medium, and processor 201 may execute the computer-executable instructions to implement various functions of the electronic device. Various application programs and various data may also be stored in the storage medium.

[0201] For example, a detailed description of the process by which an electronic device performs data transmission across clock domains can be found in the relevant descriptions in the embodiments of the data transmission method across clock domains, and will not be repeated here.

[0202] Figure 13 is a schematic diagram of a non-transitory computer-readable storage medium provided in at least one embodiment of the present disclosure. For example, as shown in Figure 13, one or more computer-executable instructions 301 may be stored non-transitory on the storage medium 300. For example, when the computer-executable instructions 301 are executed by a processor, one or more steps of the cross-clock domain data transfer method described above may be performed.

[0203] For example, the storage medium 300 can be used in the aforementioned electronic device. For example, the storage medium 300 may include the memory 203 in the electronic device.

[0204] For example, the description of storage medium 300 can be found in the description of memory in the embodiments of the electronic device, and repeated descriptions will not be repeated here.

[0205] The following points should be noted regarding this disclosure:

[0206] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0207] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0208] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0209] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. An integrated circuit, comprising a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal, wherein the first clock signal and the second clock signal are co-source clock signals, and the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal. The first clock domain includes a first pointer control module, and the second clock domain includes a second pointer control module. The first pointer control module is configured to generate a first pointer control signal for the first clock domain, such that the first read pointer and the first write pointer in the first clock domain are adjusted according to the first pointer control signal, wherein, The first pointer control signal is used to indicate the update time point of the first read pointer and the first write pointer; The second pointer control module is configured to generate a second pointer control signal for the second clock domain, so that the second read pointer and the second write pointer in the second clock domain are adjusted according to the second pointer control signal, wherein the second pointer control signal is used to indicate the update time point of the second read pointer and the second write pointer; The integrated circuit also includes a first first-in-first-out (FIFO) buffer and a second FIFO buffer. The first first-in-first-out buffer is configured to perform data transfer from the first clock domain to the second clock domain based on the first write pointer and the second read pointer. The second first-in-first-out buffer is configured to perform data transfer from the second clock domain to the first clock domain based on the first read pointer and the second write pointer; The first pointer control module includes a first synchronization pointer control module, which is configured as follows: In response to the fact that the frequency of the first clock signal is greater than the frequency of the second clock signal, the phase relationship between the first clock signal and the second clock signal is determined according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and the first pointer control signal is determined based on the phase relationship; In response to the fact that the frequency of the first clock signal is less than the frequency of the second clock signal, the first pointer control signal is determined to be a first value, so that the first read pointer and the first write pointer increase the first value in each clock cycle of the first clock signal.

2. The integrated circuit according to claim 1, wherein, The first synchronization pointer control module and the second pointer control module, which include the second synchronization pointer control module, have the same structure, and both include a first submodule and a second submodule. The first submodule of the first synchronization pointer control module is configured to determine the first clock phase according to the first clock period of the first clock domain, wherein the first clock phase is used to indicate the phase value of each clock period of the first clock signal; The second submodule of the first synchronization pointer control module is configured to determine the first pointer control signal, wherein, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal having a first value indicates that the rising edge of the second clock signal is located in the current clock cycle of the first clock signal, and the first pointer control signal having a second value indicates that no rising edge of the second clock signal is located in the current clock cycle of the first clock signal.

3. The integrated circuit according to claim 2, wherein, The second submodule includes a phase synchronization detection unit, a phase estimation unit, and a phase tracking unit. The phase synchronization detection unit is configured to determine a target clock phase in the second clock signal based on the second clock phase and the first clock signal, wherein the target clock phase is the phase value of a clock cycle selected in the second clock signal; The phase estimation unit is configured to determine the target clock period corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock period, wherein the target clock phase is located in the phase interval corresponding to the target clock period, and the phase interval is determined by the phase value of the target clock period and the phase value of the next clock period of the target clock period; The phase tracking unit is configured to continuously estimate the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock period.

4. The integrated circuit according to claim 3, wherein, The phase synchronization detection unit includes a multi-stage trigger group and an AND gate. The multi-level trigger group is configured to use the first clock signal as the clock to synchronize with a transition edge selected in the second clock signal; The AND gate is configured to perform an AND operation between the synchronized transition edge and the second clock phase to obtain the phase value of the clock cycle in which the selected transition edge is located, as the target clock phase.

5. The integrated circuit according to claim 4, wherein, The phase estimation unit is configured to compare the target clock phase with the phase intervals corresponding to multiple clock cycles to determine the target clock cycle corresponding to the target clock phase, wherein the multiple clock cycles are multiple clock cycles in the first clock signal before the transition edge after synchronization.

6. The integrated circuit according to claim 5, wherein, The phase estimation unit is further configured to estimate the phase change of the second clock signal as measured by the clock period of the first clock signal.

7. The integrated circuit according to any one of claims 3-6, wherein, When the phase tracking unit continuously estimates the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock period, it includes performing the following steps: Based on the target clock phase and the second clock period, the clock phase to be estimated is determined; During the current clock cycle: Based on the clock phase to be estimated, determine whether the clock phase to be estimated is located within the phase interval corresponding to the current clock cycle; In response to the fact that the clock phase to be estimated is located in the phase interval corresponding to the current clock cycle, the first pointer control signal output in the current clock cycle is determined to be the first value, and the clock phase to be estimated is updated based on the second clock cycle; In response to the fact that the clock phase to be estimated is not located in the phase interval corresponding to the current clock cycle, the first pointer control signal output in the current clock cycle is determined to be the second value.

8. The integrated circuit according to any one of claims 1-7, wherein, The first read pointer and the first write pointer are adjusted according to the first pointer control signal in each clock cycle of the first clock signal, and the second read pointer and the second write pointer are adjusted according to the second pointer control signal in each clock cycle of the second clock signal; In response to a data write operation occurring during the write clock cycle in the first clock domain, a data read operation is performed during the read clock cycle corresponding to the write clock cycle in the second clock signal. Wherein, the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal, and the rising edge of the second clock signal that differs from the rising edge of the read clock cycle by a+1 second clock cycles is located in the clock cycle preceding the write clock cycle of the first clock signal. In response to the clock frequency of the first clock signal being less than the clock frequency of the second clock signal, wherein the rising edge of the write clock cycle that differs from the rising edge of the write clock cycle by a first clock cycle is located in the clock cycle preceding the read clock cycle in the second clock signal, where a is a positive integer.

9. The integrated circuit according to any one of claims 1-8, wherein, The first pointer control module further includes a first state machine and a first asynchronous pointer control module, and the second pointer control module further includes a second state machine and a second asynchronous pointer control module. The first asynchronous pointer control module and the second asynchronous pointer control module each include multiple levels of flip-flops. The first asynchronous pointer control module and the second asynchronous pointer control module use their respective multiple levels of flip-flops to synchronize the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains. The first state machine is configured to control the first clock domain to use the first asynchronous pointer control module to perform cross-clock domain data transmission when a frequency switch occurs, and to control the first clock domain to use the first synchronous pointer control module to perform cross-clock domain data transmission after the frequency switch is completed and the phase estimation is completed. The second state machine is configured to control the second clock domain to use the second asynchronous pointer control module to perform cross-clock domain data transmission when a frequency switch occurs, and to control the second clock domain to use the second synchronous pointer control module to perform cross-clock domain data transmission after the frequency switch is completed and the phase estimation is completed.

10. The integrated circuit according to claim 9, wherein, The first state machine and the second state machine are further configured to receive first indication information indicating whether frequency switching is complete, and second indication information indicating the frequency relationship between the first clock signal and the second clock signal. In response to the first indication information indicating a frequency switch, the first state machine controls the first clock domain to use the first asynchronous pointer control module to perform cross-clock domain data transmission, and the second state machine controls the second clock domain to use the second asynchronous pointer control module to perform cross-clock domain data transmission. The first state machine and the second state machine are further configured to determine, based on the first indication information and the second indication information, whether the frequency switching is completed and the phase estimation is completed.

11. The integrated circuit according to claim 10, wherein, When the first state machine determines whether frequency switching is complete and phase estimation is complete based on the first indication information and the second indication information, it includes the following operations: In response to the first indication information indicating that the frequency switching is complete, and the second indication information indicating that the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal: The first state machine controls the first synchronization pointer control module to perform phase estimation to obtain the phase relationship and determine the first pointer control signal based on the phase relationship. In response to the first synchronization pointer control module completing phase estimation, it is determined that frequency switching is complete and phase estimation is finished, and The first state machine is also configured to perform a synchronization handshake with the second state machine, so that the second state machine controls the second clock domain to use the second synchronization pointer control module to perform cross-clock domain data transmission; In response to the first indication indicating that the frequency switching is complete, and the second indication indicating that the clock frequency of the first clock signal is less than the clock frequency of the second clock signal: After completing the synchronization handshake with the second state machine, it is determined that the frequency switching is complete and the phase estimation is completed.

12. A method for data transmission across clock domains, applied to a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal, wherein the first clock domain includes a first first-in-first-out (FIFO) buffer, the second clock domain includes a second FIFO buffer, the first clock signal and the second clock signal are co-source clock signals, and the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal. The data transmission method includes: In the first clock domain, a first pointer control signal is determined, and the first read pointer and the first write pointer of the first clock domain are adjusted according to the first pointer control signal, wherein the first pointer control signal is used to indicate the update time point of the first read pointer and the first write pointer; In the second clock domain, a second pointer control signal is determined, and the second read pointer and the second write pointer of the second clock domain are adjusted according to the second pointer control signal, wherein the second pointer control signal is used to indicate the update time point of the second read pointer and the second write pointer; Based on the first write pointer and the second read pointer, data transmission from the first clock domain to the second clock domain is performed using the first first-in-first-out buffer; and based on the first read pointer and the second write pointer, data transmission from the second clock domain to the first clock domain is performed using the second first-in-first-out buffer. The determination of the first pointer control signal includes: In response to the fact that the frequency of the first clock signal is greater than the frequency of the second clock signal, the phase relationship between the first clock signal and the second clock signal is determined according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and the first pointer control signal is determined based on the phase relationship; In response to the fact that the frequency of the first clock signal is less than the frequency of the second clock signal, the first pointer control signal is determined to be a first value, so that the first read pointer and the first write pointer increase the first value in each clock cycle of the first clock signal.

13. The data transmission method according to claim 12, wherein, Determining the first pointer control signal also includes: The first clock phase is determined based on the first clock period of the first clock domain, wherein the first clock phase is used to indicate the phase value of each clock period of the first clock signal; Wherein, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal being a first value indicates that the rising edge of the second clock signal is located in the current clock cycle of the first clock signal, and the first pointer control signal being a second value indicates that the rising edge of the second clock signal is not located in the current clock cycle.

14. The data transmission method according to claim 12 or 13, wherein, Based on the second clock phase and second clock period of the second clock domain, the first clock signal, and the first clock phase, the phase relationship between the first clock signal and the second clock signal is determined, and the first pointer control signal is determined based on the phase relationship, including: Based on the second clock phase and the first clock signal, a target clock phase in the second clock signal is determined, wherein the target clock phase is the phase value of a clock cycle selected in the second clock signal; Based on the first clock phase and the second clock period, a target clock period corresponding to the target clock phase in the first clock signal is determined, wherein the target clock phase is located in the phase interval corresponding to the target clock period, and the phase interval is determined by the phase value of the target clock period and the phase value of the next clock period of the target clock period; Based on the target clock phase and the target clock period, the first pointer control signal output in each current clock cycle of the first clock signal is continuously estimated.

15. The data transmission method according to any one of claims 12-14, further comprising: During frequency switching, asynchronous pointer control logic is used to transmit data across clock domains between the first and second clock domains. After frequency switching and phase estimation are completed, synchronous pointer control logic is used to transmit data across clock domains between the first and second clock domains. The asynchronous pointer control logic includes synchronizing the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through multi-level flip-flops, and the synchronous pointer control logic includes obtaining the phase relationship and performing cross-clock domain data transmission based on the phase relationship.

16. An electronic device comprising: Memory stores computer-executable instructions non-transiently; The processor is configured to run computer-executable instructions. The computer-executable instructions are executed by the processor to implement the cross-clock domain data transmission method according to any one of claims 12-15.

17. A non-transitory computer-readable storage medium, wherein, The non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement the cross-clock domain data transmission method according to any one of claims 12-15.

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