Through-silicon via structure and manufacturing method therefor

Abstract

The present invention relates to a through-silicon via structure and a manufacturing method therefor. The structure comprises: a bonding layer; a pad arranged above the bonding layer; a first insulating layer arranged above the bonding layer and the pad, wherein a first opening is formed in the first insulating layer; a wafer arranged above the first insulating layer, wherein a through hole is formed in the wafer, and the size of an opening of the through hole is greater than the size of the first opening; a second insulating layer arranged on the upper surface and the side surface of the wafer; and an interconnect structure arranged above the second insulating layer and the pad, wherein the interconnect structure is electrically connected to the pad. In the through-silicon via structure provided by the present invention, a dry film is used as a mask during the windowing of an insulating layer, and the size of an opening of the dry film is controlled, so that the size of an opening of the insulating layer is less than the size of an opening of a through hole, and thus generation of notches during the windowing of the insulating layer is avoided, thereby reducing the difficulty of the windowing process, thus improving the product yield.

Description

A through-silicon via structure and its manufacturing method Technical Field

[0001] This invention relates to the field of packaging technology, and in particular to a through-silicon via (TSV) structure and its manufacturing method. Background Technology

[0002] Mobile device manufacturers' demands for miniaturization, low cost, and high integration have led to requirements regarding the cost, performance, integration level, and functionality of wafer-level packaging (WLP) solutions for related chips. In system-in-package (SiP), to achieve the functionality of the package structure, several types of heterogeneous chips or passive devices are often involved. Through-silicon via (TSV) interconnects based on technologies such as vertical through-hole interconnects (VTOS) represent a promising direction for SiP due to their advantages, including short global interconnects, low latency, low power consumption, high bandwidth, and high integration.

[0003] For 3D integrated circuits, TSV processes are divided into Via-First, Via-Middle, and Via-Last. Via-First process generally refers to processing TSVs on silicon wafers first, and then processing other devices including circuits; Via-Middle process generally refers to forming TSVs between device processing and subsequent interconnect processing; Via-Last process refers to TSVs being processed after all IC factory processes are completed, and can be completed independently by the wafer-level packaging factory.

[0004] Compared to Via-first and Via-Middle processes, Via-Last technology offers advantages such as lower cost and higher modularity, making it a significant strength in 3D interconnect integration. However, existing Via-Last processes also have limitations, such as high process complexity and large via sizes. Regarding process complexity, the uniformity of the Si wafer thickness before the material arrives can easily lead to notches at the bottom of the TSV during TSV etching. When opening windows in the insulating layer, a larger over-etching amount is required to ensure complete opening, which also easily results in notches. Notches can cause TSV insulation problems, affecting product yield. Furthermore, when using Via-Las technology to fabricate vias on small pads, a structure using a large TSV to connect to a small TSV on the same Si wafer layer is necessary to prevent anomalies in the interconnect metal due to metal grain growth during subsequent wafer processing. However, using a large TSV to small TSV connection on a Si substrate presents significant technical challenges, complex process flows, and high costs. Summary of the Invention

[0005] To address some or all of the problems in the prior art, the present invention provides a through-silicon via (TSV) structure, which includes:

[0006] Bonding layer;

[0007] solder pads, the solder pads being disposed on the bonding layer;

[0008] A first insulating layer is disposed on the bonding layer and the pads, and a first opening is provided in the first insulating layer;

[0009] A wafer, wherein the wafer is disposed on the first insulating layer, and a through-hole is disposed in the wafer, wherein the opening size of the through-hole is larger than the size of the first opening;

[0010] A second insulating layer is disposed on the upper surface and side surface of the wafer;

[0011] An interconnect structure is disposed on the second insulating layer and the pads, and the interconnect structure is electrically connected to the pads.

[0012] Furthermore, the through-silicon via structure also includes a carrier wafer;

[0013] The carrier is disposed under the bonding layer, and the carrier is a glass sheet, a silicon sheet, a sapphire sheet, or a metal sheet.

[0014] Furthermore, the material of the bonding layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or organic bonding adhesive.

[0015] Furthermore, the material of the pad includes one or more of copper, nickel, tin, silver, aluminum, or titanium.

[0016] Furthermore, the wafer includes a chip module;

[0017] The chip module contains multiple identical chips, multiple chips of the same type, or multiple chips of different types.

[0018] Furthermore, the opening size of the through hole is 5μm-300μm; and / or

[0019] The size of the first opening is 3μm-270μm.

[0020] Further, the material of the first insulating layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride; and / or

[0021] The material of the second insulating layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride.

[0022] Furthermore, the material of the interconnect structure includes one or more of copper, tungsten, aluminum, silver, or titanium.

[0023] The present invention also provides a method for manufacturing a through-silicon via structure, the method comprising the following steps:

[0024] The wafer is bonded onto the carrier, the bonding layer is disposed on the carrier, the pads are disposed on the bonding layer, and the first insulating layer is disposed on the bonding layer and the pads;

[0025] Photoresist is applied onto the wafer;

[0026] Expose and develop the photoresist;

[0027] Etch the wafer down to the first insulating layer to create a through-hole;

[0028] Remove the photoresist;

[0029] A second insulating layer is deposited, and the dry film is pressed onto the wafer.

[0030] The dry film is exposed and developed, wherein the opening size of the dry film is smaller than the opening size of the through-hole;

[0031] Etch the first insulating layer and the second insulating layer to remove the dry film;

[0032] An interconnect structure is fabricated on the second insulating layer and the pads to form a through-silicon via (TSV) structure.

[0033] Furthermore, the wafer is etched using the Bosch process.

[0034] The technical solution provided by this invention has the following beneficial effects:

[0035] 1. The silicon through-hole structure provided by this invention, based on the existing Via-Last through-hole fabrication, uses a dry film as a windowing mask when opening the insulating layer, and controls the size of the dry film opening to make it smaller than the size of the through-hole opening. This results in the size of the opened insulating layer opening being smaller than the size of the through-hole opening, which can avoid notch generation when opening the insulating layer, reduce the difficulty of the windowing process, and improve product yield.

[0036] 2. The silicon through-hole structure provided by this invention can precisely open windows on the top of small-sized pads by controlling the size of the dry film opening, meeting the fabrication requirements of the Vi a-Last process for small-sized pads. Compared with the large TSV to small TSV structure on the same Si substrate, it has lower cost and simpler process. Attached Figure Description

[0037] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0038] Figure 1 shows a cross-sectional schematic diagram of a through-silicon via structure according to an embodiment of the present invention;

[0039] Figure 2 shows a cross-sectional schematic diagram of a silicon through-hole structure according to another embodiment of the present invention;

[0040] Figure 3 shows a schematic flowchart of a method for manufacturing a through-silicon via (TSV) structure according to an embodiment of the present invention; and

[0041] Figures 4a-4i show schematic cross-sectional views of the process of forming a through-silicon via structure according to an embodiment of the present invention. Detailed Implementation

[0042] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0043] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0044] In this specification, unless otherwise specified, "arranged on," "arranged above," and "arranged on top of" do not exclude the possibility of an intermediate element between them. Furthermore, "arranged on or above" merely indicates the relative positional relationship between two components, and in certain cases, such as when the product orientation is reversed, it can also be converted to "arranged below or under," and vice versa.

[0045] In this specification, unless otherwise specified, "upper surface" and "side surface" are used only to describe surfaces that distinguish the same component. Furthermore, "first," "second," and "third" are used only for distinguishing descriptions and do not imply differences in size.

[0046] In this specification, unless otherwise specified, the quantifiers “one” and “one” do not exclude scenarios involving multiple elements, and the quantifiers “multiple” and “more” refer to one or more elements.

[0047] It should be noted that the embodiments of the present invention describe the method steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0048] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0049] Figure 1 shows a cross-sectional schematic diagram of a through-silicon via (TSV) structure according to one embodiment of the present invention. Figure 2 shows a cross-sectional schematic diagram of a TSV structure according to another embodiment of the present invention. Figure 1 corresponds to the case where the pad 104 is larger, and Figure 2 corresponds to the case where the pad 104 is smaller. As shown in Figures 1 and 2, the TSV structure includes a wafer 101, a first insulating layer 102, a bonding layer 103, a pad 104, a carrier 105, a second insulating layer 108, and an interconnect structure 110. The carrier 105 is disposed below the bonding layer 103. In one embodiment of the present invention, the carrier 105 may be a glass sheet, a silicon sheet, a sapphire sheet, or a metal sheet. The pad 104 is disposed in or above the bonding layer 103. The first insulating layer 102 is disposed above the bonding layer 103 and the pad 104, and a first opening is arranged in the first insulating layer 102, i.e., the position where the first insulating layer 102 is interrupted in the via 107 in the figure. A wafer 101 is disposed on a first insulating layer 102. A via 107 is disposed in the wafer 101, and the opening size of the via 107 is larger than the size of the first opening. A second insulating layer 108 covers the upper surface and side surfaces of the wafer 101, and the second insulating layer 108 is also disposed in areas of the first insulating layer 102 not covered by the wafer 101. An interconnect structure 110 is disposed on the second insulating layer 108 and a pad 104, and the interconnect structure 110 is electrically connected to the pad 104.

[0050] In one embodiment of the present invention, wafer 101 may be a silicon wafer, a sapphire wafer, a silicon carbide wafer, a gallium nitride wafer, or a gallium arsenide wafer.

[0051] In one embodiment of the present invention, the material of the bonding layer 103 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or organic bonding adhesive.

[0052] In one embodiment of the present invention, the material of the pad 104 may include one or more of copper, nickel, tin, silver, aluminum, or titanium.

[0053] In one embodiment of the present invention, wafer 101 includes a chip module in the area without vias 107. The chip module may contain multiple identical chips, multiple chips of the same type, or multiple chips of different types. In one embodiment of the present invention, the chip may be a logic chip such as a CPU, DSP, GPU, or FPGA; a memory chip such as DRAM, Flash, or HBM; or other types of chips such as SoC or sensors (such as MEMS sensors).

[0054] In one embodiment of the present invention, the opening size of the through hole 107 is 5μm-300μm; and / or the size of the first opening is 3μm-270μm.

[0055] In one embodiment of the present invention, the material of the first insulating layer 102 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride; and / or the material of the second insulating layer 108 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride.

[0056] In one embodiment of the present invention, the material of the interconnect structure 110 includes one or more of copper, tungsten, aluminum, silver, or titanium.

[0057] Figure 3 shows a schematic flowchart of a method for manufacturing a through-silicon via (TSV) structure according to an embodiment of the present invention. Figures 4a-4i show cross-sectional schematic diagrams of the process of forming a TSV structure according to an embodiment of the present invention. A method for manufacturing a TSV structure according to the present invention will be described below with reference to Figures 3 and 4a-4i.

[0058] First, wafer 101 is bonded onto carrier 105, as shown in FIG. 4a. Bonding layer 103 is disposed on carrier 105, pads 104 are disposed in or on bonding layer 103, and a first insulating layer 102 is disposed on bonding layer 103 and pads 104. In one embodiment of the present invention, wafer 101 may be a silicon wafer, a sapphire wafer, a silicon carbide wafer, a gallium nitride wafer, or a gallium arsenide wafer. In one embodiment of the present invention, the material of the first insulating layer 102 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride. In one embodiment of the present invention, the material of bonding layer 103 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or organic bonding adhesive. In one embodiment of the present invention, the material of pads 104 may include one or more of copper, nickel, tin, silver, aluminum, or titanium. In one embodiment of the present invention, carrier 105 may be a glass sheet, a silicon wafer, a sapphire sheet, or a metal sheet.

[0059] Next, photoresist 106 is coated onto wafer 101, as shown in Figure 4b. In one embodiment of the present invention, photoresist 106 can be a positive photoresist or a negative photoresist, and photoresist 106 can be coated by spin coating or spray coating.

[0060] Next, the photoresist 106 is exposed and developed to reveal the through-hole pattern, as shown in Figure 4c.

[0061] Next, wafer 101 is etched down to the first insulating layer 102 to create vias 107, as shown in Figure 4d. In one embodiment of the invention, the vias 107 are created using a Bosch process, with SF6 as the etching gas and C4F8 as the passivation gas. In one embodiment of the invention, the opening size of the vias 107 is 5μm-300μm. In one embodiment of the invention, wafer 101 includes a chip module in the area without vias 107. The chip module may contain multiple identical chips, multiple chips of the same type, or multiple chips of different types. In one embodiment of the invention, the chip may be a logic chip such as a CPU, DSP, GPU, or FPGA; a memory chip such as DRAM, Flash, or HBM; or other types of chips such as SoC or sensors (such as MEMS sensors).

[0062] Next, the photoresist 106 is removed, as shown in Figure 4e. In one embodiment of the present invention, dry or wet photoresist removal is used to remove the photoresist 106 on the surface of the wafer 101. The gas used for dry photoresist removal is O2 or O2+CF4, and the chemical used for wet photoresist removal is dimethyl sulfoxide.

[0063] Next, a second insulating layer 108 is deposited, and a dry film 109 is pressed onto the wafer 101, as shown in Figure 4f. The second insulating layer 108 is mainly used for insulating and protecting the upper surface of the wafer and the sidewalls of the vias. In one embodiment of the present invention, the second insulating layer 108 is deposited using a plasma-enhanced chemical vapor deposition (PECVD) process. In one embodiment of the present invention, the material of the second insulating layer 108 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride. The dry film here is a solid photoresist, and pressing the dry film specifically involves softening the dry film under certain temperature and pressure conditions and then bonding it to the wafer surface, such as a temperature of 70-100°C and a pressure of 1-4 kg.

[0064] Next, the dry film 109 is exposed and developed. The opening size of the dry film 109 is smaller than the opening size of the through hole 107, as shown in Figure 4g.

[0065] Next, the first insulating layer 102 and the second insulating layer 108 are etched to remove the dry film 109, as shown in FIG4h. After etching the first insulating layer 102 and the second insulating layer 108, a first opening is formed in the first insulating layer 102. In one embodiment of the present invention, the size of the first opening in the first insulating layer 102 is smaller than the size of the opening in the via 107, and the size of the first opening in the first insulating layer 102 is 3μm-270μm.

[0066] Finally, an interconnect structure 110 is fabricated on the second insulating layer 108 and the pad 104 to form a through-silicon via (TSV) structure, as shown in FIG4i. The interconnect structure 110 is electrically connected to the pad 104, which can lead electrical signals on the pad 104 to the upper surface of the wafer 101. In one embodiment of the present invention, the material of the interconnect structure includes one or more of copper, tungsten, aluminum, silver, or titanium.

[0067] The silicon via (TSV) structure provided by this invention, based on existing Via-Last via fabrication, uses a dry film as a windowing mask during insulating layer windowing. By controlling the size of the dry film opening, ensuring that its size is smaller than the via opening, the size of the opened insulating layer opening is smaller than the via opening. This avoids notch generation during insulating layer windowing, reduces the difficulty of the windowing process, and improves product yield. By controlling the size of the dry film opening, precise windowing can be performed on the top of small-sized pads, meeting the fabrication requirements of small-sized pad Via-Last processes. Compared to the large TSV to small TSV transition structure on the same Si substrate, this method is more cost-effective and has a simpler process.

[0068] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A through-silicon via (TSV) structure, characterized in that, include: Bonding layer; solder pads, the solder pads being disposed on the bonding layer; A first insulating layer is disposed on the bonding layer and the pads, and a first opening is provided in the first insulating layer; A wafer, wherein the wafer is disposed on the first insulating layer, and a through-hole is disposed in the wafer, wherein the opening size of the through-hole is larger than the size of the first opening; A second insulating layer is disposed on the upper surface and side surface of the wafer; An interconnect structure is disposed on the second insulating layer and the pads, and the interconnect structure is electrically connected to the pads.

2. The through-silicon via structure according to claim 1, characterized in that, It also includes a carrier film; The carrier is disposed under the bonding layer, and the carrier is a glass sheet, a silicon sheet, a sapphire sheet, or a metal sheet.

3. The through-silicon via structure according to claim 1, characterized in that, The bonding layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, or organic bonding adhesive.

4. The through-silicon via structure according to claim 1, characterized in that, The material of the pads includes one or more of copper, nickel, tin, silver, aluminum, or titanium.

5. The through-silicon via structure according to claim 1, characterized in that, The wafer includes a chip module; The chip module contains multiple identical chips, multiple chips of the same type, or multiple chips of different types.

6. The through-silicon via structure according to claim 1, characterized in that, The opening size of the through hole is 5μm-300μm; and / or The size of the first opening is 3μm-270μm.

7. The through-silicon via structure according to claim 1, characterized in that, The material of the first insulating layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride; and / or The material of the second insulating layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride.

8. The through-silicon via structure according to claim 1, characterized in that, The interconnect structure is made of one or more of the following materials: copper, tungsten, aluminum, silver, or titanium.

9. A method for manufacturing a through-silicon via (TSV) structure as described in any one of claims 1-8, characterized in that, Includes the following steps: The wafer is bonded onto the carrier, the bonding layer is disposed on the carrier, the pads are disposed on the bonding layer, and the first insulating layer is disposed on the bonding layer and the pads; Photoresist is applied onto the wafer; Expose and develop the photoresist; Etch the wafer down to the first insulating layer to create a through-hole; Remove the photoresist; A second insulating layer is deposited, and the dry film is pressed onto the wafer. The dry film is exposed and developed, wherein the opening size of the dry film is smaller than the opening size of the through-hole; Etch the first insulating layer and the second insulating layer to remove the dry film; An interconnect structure is fabricated on the second insulating layer and the pads to form a through-silicon via (TSV) structure.

10. The method for manufacturing a through-silicon via structure according to claim 9, characterized in that, The wafer was etched using the Bosch process.

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