Semiconductor device and method of manufacturing the same

Abstract

This application relates to a semiconductor device and a method for fabricating the same. The semiconductor device includes: a first substrate, comprising a main body portion and at least one protrusion disposed on the main body portion; at least two second substrates disposed on the main body portion, with a protrusion located between any two adjacent second substrates; at least two isolation regions, corresponding one-to-one within the at least two second substrates; each isolation region enclosing a device region within its corresponding second substrate; at least two first well regions, corresponding one-to-one with the at least two second substrates, each first well region being located within its corresponding device region on the second substrate; and a first conductive structure electrically connected to the first substrate; wherein the first substrate, second substrates, and first well regions are of a first conductivity type, and the doping concentration of the first substrate is greater than the doping concentration of the first well regions; the isolation regions are of a second conductivity type. This application can improve the latch-up effect of semiconductor devices.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In the field of modern integrated circuit manufacturing, with the continuous improvement of device integration and the increasing complexity of functions, isolation technology between devices has become one of the key factors affecting the performance of integrated circuits. Currently, the widely used isolation technologies mainly include STI (Shallow Trench Isolation) and DTI (Deep Trench Isolation), and they are often combined with the high resistance characteristics of PN junctions under reverse bias to achieve effective isolation between array devices.

[0003] However, in practical applications of traditional technologies, conventional isolation schemes have significant drawbacks in NLDMOS (N-type Lateral Double-Diffused Metal-Oxide-Semiconductor) device scenarios. Specifically, they inevitably lead to the formation of a parasitic PNP transistor in the P-well-N-buried layer-P-substrate configuration. During normal transistor operation, if a high voltage appears in the P-well region, this parasitic PNP transistor will be triggered, generating current in the substrate. When this substrate current flows, it raises the substrate potential of adjacent devices. This abnormal potential change may further cause conduction between the P-substrate and the N-buried layer of adjacent devices, ultimately leading to a severe latch-up effect. The latch-up effect not only interferes with the normal operation of the device, causing performance degradation, but may even damage the device, greatly reducing the reliability and stability of integrated circuits and severely restricting the further development of integrated circuits in high-performance, high-reliability applications. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device and its fabrication method to address the above-mentioned problems.

[0005] To achieve the above objectives, in a first aspect, this application provides a semiconductor device, comprising:

[0006] The first substrate includes a main body portion and at least one protrusion provided on the main body portion;

[0007] At least two second substrates are disposed on the main body portion, and a protrusion is provided between any two adjacent second substrates;

[0008] At least two isolation regions are disposed in the at least two second substrates in a one-to-one correspondence; the isolation regions enclose the device regions within the corresponding second substrates.

[0009] At least two first well regions correspond one-to-one with the at least two second substrates, and each first well region is disposed within the device region of the corresponding second substrate;

[0010] A first conductive structure is electrically connected to the first substrate;

[0011] Wherein, the first substrate, the second substrate, and the first well region are of a first conductivity type, and the doping concentration of the first substrate is greater than the doping concentration of the first well region; the isolation region is of a second conductivity type.

[0012] In one embodiment, the doping concentration of the first substrate is greater than that of the second substrate.

[0013] In one embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

[0014] In one embodiment, the second substrate is an epitaxial layer.

[0015] In one embodiment, the semiconductor device further includes a first lead-out region of a first conductivity type, the first lead-out region being disposed within the protrusion and electrically connected to the first conductive structure.

[0016] In one embodiment, the semiconductor device further includes a first doped region of a first conductivity type, the first doped region being disposed within the protrusion, and the first lead-out region being disposed within the first doped region.

[0017] In one embodiment, the isolation region includes a first sub-region and a second sub-region connected to the first sub-region; the second sub-region extends from a side surface of the second substrate away from the main body into the second substrate, and the first sub-region is located on the side of the second sub-region close to the first substrate; the first sub-region and the second sub-region surround to form the device region.

[0018] In one embodiment, the semiconductor device further includes:

[0019] A drain region of the second conductivity type is provided within the second sub-region;

[0020] A source region of the second conductivity type is disposed within the first well region;

[0021] The gate is disposed on the second substrate.

[0022] Secondly, embodiments of this application provide a method for fabricating a semiconductor device, comprising:

[0023] A first substrate is provided; the first substrate includes a main body portion and at least one protrusion disposed on the main body portion;

[0024] At least two second substrates are formed on the first substrate; a protrusion is provided between any two adjacent second substrates.

[0025] At least two isolation regions and at least two first well regions are formed within the second substrate; the at least two isolation regions are disposed in the at least two second substrates in a one-to-one correspondence; the isolation regions enclose device regions within their respective second substrates; the at least two first well regions correspond one-to-one with the at least two second substrates, and each first well region is disposed within the device region of its corresponding second substrate; wherein, the first substrate, the second substrate, and the first well regions are of a first conductivity type, and the doping concentration of the first substrate is greater than the doping concentration of the first well regions; the isolation regions are of a second conductivity type;

[0026] A first conductive structure is formed that is electrically connected to the first substrate.

[0027] In one embodiment, providing the first substrate includes:

[0028] Provide a substrate material layer;

[0029] A mask layer is formed on the substrate material layer to define the thinning region;

[0030] The thinning region is thinned to form the first substrate;

[0031] And / or,

[0032] The formation of at least two second substrates on the first substrate includes:

[0033] An epitaxial layer is formed on the first substrate;

[0034] The epitaxial layer is planarized to form the at least two second substrates.

[0035] The semiconductor device and its fabrication method provided in this application reduce the resistance of the first substrate by making the doping concentration of the first substrate greater than that of the first well region, which is equivalent to setting the first substrate as a highly doped substrate. By including a main body and a protrusion in the first substrate, it is convenient to place a second substrate on the main body, and adjacent second substrates are separated by the protrusion. Cell devices are placed on the second substrate. When the PNP transistor formed by the first well region, isolation region, and first substrate is turned on, the current leaking into the first substrate will preferentially be discharged through the first conductive structure, thereby reducing crosstalk between adjacent cell devices, improving latch-up effect, and increasing the reliability of the semiconductor device. Furthermore, compared to conventional semiconductor devices, under the same leakage current conditions, the semiconductor device provided in this application has a smaller resistance of the first substrate, resulting in a smaller potential difference when the leakage current flows through the same path, thereby effectively reducing the potential rise of adjacent cell devices, improving latch-up effect, and increasing the stability of the semiconductor device. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of this application.

[0038] Figure 2 for Figure 1 A schematic cross-sectional view of the substrate structure of the semiconductor device shown.

[0039] Figure 3 This is a schematic cross-sectional view of another semiconductor device provided in an embodiment of this application.

[0040] Figure 4 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application.

[0041] Figures 5-7 for Figure 4 A schematic diagram of the cross-sectional structure of the device during the fabrication process shown.

[0042] Explanation of reference numerals in the attached figures:

[0043] 10. Semiconductor device; 11. Substrate structure; 111. First substrate; 1111. Main body; 1112. Protrusion; 112. Second substrate; 12. Isolation region; 121. First sub-region; 122. Second sub-region; 13. Device region; 141. First conductive structure; 142. Second conductive structure; 143. Third conductive structure; 144. Fourth conductive structure; 151. First well region; 152. First lead-out region; 153. First doped region; 154. Drain region; 155. Source region; 156. Second lead-out region; 157. Second well region; 16. Gate; 17. Isolation structure; 18. Dielectric layer; 20. Substrate material layer; 30. Mask layer; 40. Epitaxial layer. Detailed Implementation

[0044] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0047] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0049] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the application.

[0050] As described in the background section, traditional isolation techniques have significant drawbacks in NLDMOS device applications. Specifically, they inevitably lead to the formation of parasitic PNP transistors in the P-well-N-buried layer-P-substrate configuration. During normal transistor operation, if a high voltage appears in the P-well region, this parasitic PNP transistor will be triggered, generating current in the substrate. This substrate current flow increases the substrate potential of adjacent devices. This abnormal potential change may further cause conduction between the P-substrate and the N-buried layer of adjacent devices, ultimately leading to a severe latch-up effect. The latch-up effect not only interferes with the normal operation of the device, causing performance degradation, but may even damage the device, significantly reducing the reliability and stability of integrated circuits and severely restricting their further development in high-performance, high-reliability applications. Related technologies utilize the high reverse resistance of the PN junction for isolation schemes to improve the latch-up effect; however, both shallow trench isolation and deep trench isolation carry the risk of parasitic PNP transistors and latch-up effects.

[0051] Furthermore, addressing or optimizing these problems inherent in traditional isolation technologies through conventional methods often requires a large-scale redevelopment and adjustment of the entire integrated circuit manufacturing process. This means consuming significant human, material, and time resources, including redesigning the entire process flow and making comprehensive changes to all subsequent photomasks and related processes. This undoubtedly poses a huge challenge and burden to integrated circuit manufacturers, significantly extending product development cycles, increasing R&D investment, and reducing product market competitiveness.

[0052] In view of at least one of the above-mentioned problems, embodiments of this application provide a semiconductor device and a method for fabricating the same. By making the doping concentration of the first substrate greater than that of the first well region, it is equivalent to setting the first substrate as a highly doped substrate, thereby reducing the resistance value of the first substrate. By making the first substrate include a main body and a protrusion, it is convenient to set a second substrate on the main body, and two adjacent second substrates are separated by the protrusion, wherein cell devices are set on the second substrate. When the PNP transistor formed by the first well region, the isolation region, and the first substrate is turned on, the current leaking into the first substrate will preferentially be discharged from the first conductive structure, thereby reducing crosstalk between adjacent cell devices, improving the latch-up effect, and improving the reliability of the semiconductor device. In addition, compared with conventional semiconductor devices, under the same leakage current conditions, the semiconductor device provided by this application has a smaller resistance value of the first substrate, and the potential difference generated when the leakage current flows through the same path is smaller, thereby effectively reducing the potential rise of adjacent cell devices, improving the latch-up effect, and improving the stability of the semiconductor device. Furthermore, the solution provided in this application embodiment is highly compatible with existing processes, eliminating the need to redevelop an entire process or change all subsequent photomasks and processes. This saves development time and resources, and has the advantage of a short R&D and manufacturing cycle, which helps to enhance the market competitiveness of the product.

[0053] Firstly, referring to Figure 1 and Figure 2 As shown, this application provides a semiconductor device 10, which may be a bipolar junction transistor (BJT) device, a metal-oxide-semiconductor field-effect transistor (MOSFET) device, etc.

[0054] Specifically, the semiconductor device 10 includes a first substrate 111, at least two second substrates 112, at least two isolation regions 12, at least two first well regions 151, and a first conductive structure 141. Further, the first substrate 111 includes a main body portion 1111 and at least one protrusion 1112 disposed on the main body portion 1111. The at least two second substrates 112 are disposed on the main body portion 1111, and a protrusion 1112 is provided between any two adjacent second substrates 112. The at least two isolation regions 12 are correspondingly disposed within the at least two second substrates 112, that is, one isolation region 12 is disposed on a corresponding second substrate 112; each isolation region 12 surrounds and forms a device region 13 within its corresponding second substrate 112. The at least two first well regions 151 correspond one-to-one with the at least two second substrates 112, and each first well region 151 is disposed within the device region 13 of its corresponding second substrate 112; the first conductive structure 141 is electrically connected to the first substrate 111.

[0055] The first substrate 111, the second substrate 112, and the first well region 151 are of the first conductivity type, and the doping concentration of the first substrate 111 is greater than that of the first well region 151; the isolation region 12 is of the second conductivity type.

[0056] It should be noted here that the semiconductor device 10 includes at least two cell devices, and the type of cell device is not limited here. The number of cell devices, the number of second substrates 112, the number of isolation regions 12, and the number of first well regions 151 are all the same. The cell devices are disposed on the second substrate 112, and at least a portion of the structure of the cell device is disposed within the device region 13. It is understood that the first well region 151 is part of the cell device.

[0057] In one embodiment, the semiconductor device 10 includes a substrate structure 11, which includes a first substrate 111 and a second substrate 112. The materials of the first substrate 111 and the second substrate 112 may be monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, low-temperature polycrystalline silicon (LTPS), or other materials known to those skilled in the art.

[0058] In this embodiment, by making the doping concentration of the first substrate 111 greater than that of the first well region 151, it is equivalent to setting the first substrate 111 as a highly doped substrate, thereby reducing the resistance value of the first substrate 111. By making the first substrate 111 include a main body portion 1111 and a protrusion portion 1112, it is convenient to place the second substrate 112 on the main body portion 1111, and two adjacent second substrates 112 are separated by the protrusion portion 1112. When the PNP transistor formed by the first well region 151, the isolation region 12 and the first substrate 111 is turned on, the current leaking into the first substrate 111 will preferentially be discharged from the first conductive structure 141, thereby reducing crosstalk between adjacent cell devices, improving latch-up effect and improving the reliability of semiconductor device 10.

[0059] Furthermore, traditional semiconductor devices use ordinary substrates with low doping concentrations. While these substrates offer advantages such as simple processing and low cost, substrate leakage can cause crosstalk between integrated cell devices, reducing the reliability of the semiconductor device and integrated circuit. Compared to traditional semiconductor devices, under the same leakage conditions, the first substrate 111 of the semiconductor device 10 provided in this application has a lower resistance value, resulting in a smaller potential difference when the leakage current flows through the same path. This effectively reduces the potential rise of adjacent cell devices, improves the latch-up effect, and enhances the reliability of the semiconductor device 10 and the stability of the integrated circuit system.

[0060] Furthermore, the manufacturing process of the semiconductor device 10 provided in this application embodiment is highly compatible with existing processes. It does not require the redevelopment of an entire process or changes to all subsequent photomasks and processes, which can save development time and resources. It has the advantage of a short R&D and manufacturing cycle, which is conducive to improving the market competitiveness of the product.

[0061] In one embodiment, the doping concentration of the first substrate 111 is greater than that of the second substrate 112. In other words, the first substrate 111 is a "dense substrate" compared to the second substrate 112. This reduces the resistance of the first substrate 111, which helps to reduce crosstalk between adjacent cell devices and thus improves the latch-up effect.

[0062] In one embodiment, the first conductivity type is P-type and the second conductivity type is N-type. Specifically, the first substrate 111, the second substrate 112, and the first well region 151 are all P-type, while the isolation region 12 is N-type. This effectively improves the latch-up effect of N-type devices.

[0063] In one embodiment, the second substrate 112 is an epitaxial layer 40, that is, the second substrate 112 is fabricated by an epitaxial process. This helps to reduce the fabrication difficulty of the second substrate 112, thereby reducing manufacturing costs.

[0064] In one embodiment, the semiconductor device 10 further includes a first lead-out region 152 of a first conductivity type. The first lead-out region 152 is disposed within the protrusion 1112 and electrically connected to the first conductive structure 141. For example, the first lead-out region 152 may be a heavily doped region. This benefits, on the one hand, by reducing the electrical connection resistance between the first conductive structure 141 and the first substrate 111; on the other hand, by disposing the first lead-out region 152 within the protrusion 1112, the first conductive structure 141 can be disposed on the front side of the substrate structure 11, thereby facilitating the electrical connection of the first conductive structure 141 to an external circuit.

[0065] Understandably, the first lead-out area 152 extends from the surface of the protrusion 1112 to the interior of the protrusion 1112.

[0066] In one embodiment, such as Figure 3 As shown, the semiconductor device 10 also includes a first doped region 153 of a first conductivity type, which is disposed within the protrusion 1112, and a first lead-out region 152 is disposed within the first doped region 153. It is understood that in conventional semiconductor devices 10, the first lead-out region 152 is typically disposed within the first doped region 153. The embodiment of this application also includes a first doped region 153, indicating that the semiconductor device 10 in this embodiment does not require changes to the subsequent manufacturing processes and versions of conventional semiconductor devices 10 during fabrication, thereby saving development time.

[0067] In one embodiment, the doping concentration of the first doped region 153 is less than the doping concentration of the first lead-out region 152.

[0068] In one embodiment, such as Figure 1 and Figure 3 As shown, the isolation region 12 includes a first sub-region 121 and a second sub-region 122 connected to the first sub-region 121; the second sub-region 122 extends from the surface of the second substrate 112 away from the main body 1111 into the second substrate 112, and the first sub-region 121 is located on the side of the second sub-region 122 close to the first substrate 111; the first sub-region 121 and the second sub-region 122 enclose and form the device region 13. This configuration simplifies the structure of the isolation region 12 and facilitates its fabrication.

[0069] It should be noted that the shape of the orthographic projection of the second sub-region 122 onto the first substrate 111 can be annular.

[0070] In one embodiment, the first sub-region 121 is a buried doped region.

[0071] In one embodiment, the semiconductor device 10 further includes a drain region 154 of a second conductivity type, a source region 155 of a second conductivity type, and a gate 16. The drain region 154 is disposed within a second sub-region 122; the source region 155 is disposed within a first well region 151; and the gate 16 is disposed on a second substrate 112. This effectively incorporates the second sub-region 122 as part of a cellular device, which helps reduce the area occupied by the cellular device, thereby increasing the number of cellular devices per unit area and ultimately improving device performance.

[0072] In one embodiment, the semiconductor device 10 further includes a second lead-out region 156, a second well region 157, a dielectric layer 18, a second conductive structure 142, a third conductive structure 143, a fourth conductive structure 144, and an isolation structure 17. The second lead-out region 156 is disposed within the first well region 151, and the dielectric layer 18 is disposed on the substrate structure 11. The first conductive structure 141, the second conductive structure 142, the third conductive structure 143, and the fourth conductive structure 144 all penetrate the dielectric layer 18. The second conductive structure 142 is electrically connected to the drain region 154, the third conductive structure 143 is electrically connected to the source region 155, and the fourth conductive structure 144 is electrically connected to the second lead-out region 156. The second lead-out region 156 is of a first conductivity type, and the second well region 157 is of a second conductivity type. The isolation structure 17 is disposed between the protrusion 1112 and the second substrate 112.

[0073] Secondly, referring to Figure 4 As shown, this application embodiment provides a method for fabricating a semiconductor device 10, which specifically includes the following steps:

[0074] S100: A first substrate 111 is provided. The first substrate 111 includes a main body portion 1111 and at least one protrusion 1112 provided on the main body portion 1111.

[0075] S200: At least two second substrates 112 are formed on the first substrate 111. A protrusion 1112 is provided between any two adjacent second substrates 112.

[0076] S300: At least two isolation regions 12 and at least two first well regions 151 are formed within the second substrate 112. The at least two isolation regions 12 are disposed in the at least two second substrates 112 in a one-to-one correspondence; each isolation region 12 surrounds a device region 13 within the corresponding second substrate 112; the at least two first well regions 151 correspond to the at least two second substrates 112 in a one-to-one correspondence, and each first well region 151 is disposed within the device region 13 of the corresponding second substrate 112; wherein, the first substrate 111, the second substrate 112, and the first well region 151 are of a first conductivity type, and the doping concentration of the first substrate 111 is greater than the doping concentration of the first well region 151; the isolation region 12 is of a second conductivity type.

[0077] S400: Forming a first conductive structure 141 electrically connected to the first substrate 111.

[0078] The method for fabricating the semiconductor device 10 provided in this application embodiment, by making the doping concentration of the first substrate 111 greater than that of the first well region 151, is equivalent to setting the first substrate 111 as a substrate with a high doping concentration, thereby reducing the resistance value of the first substrate 111. By making the first substrate 111 include a main body portion 1111 and a protrusion portion 1112, it is convenient to set the second substrate 112 on the main body portion 1111, and two adjacent second substrates 112 are separated by the protrusion portion 1112, wherein cell devices are set on the second substrate 112. When the PNP transistor formed by the first well region 151, the isolation region 12 and the first substrate 111 is turned on, the current leaking into the first substrate 111 will preferentially be discharged from the first conductive structure 141, thereby reducing crosstalk between adjacent cell devices, improving latch-up effect and improving the reliability of the semiconductor device 10. Furthermore, traditional semiconductor devices use ordinary substrates with low doping concentrations. While these substrates offer advantages such as simple processing and low cost, substrate leakage can cause crosstalk between integrated cell devices, reducing the reliability of the semiconductor device and integrated circuit. Compared to traditional semiconductor devices, under the same leakage conditions, the first substrate 111 of the semiconductor device 10 provided in this application has a lower resistance value, resulting in a smaller potential difference when the leakage current flows through the same path. This effectively reduces the potential rise of adjacent cell devices, improves the latch-up effect, and enhances the reliability of the semiconductor device 10 and the stability of the integrated circuit system.

[0079] In one embodiment, S100: providing a first substrate 111 specifically includes the following steps:

[0080] S110: Provide a substrate material layer 20. Specifically, provide a substrate material layer 20 of a first conductivity type.

[0081] S120: A mask layer 30 is formed on the substrate material layer 20 to define the thinning region. Specifically, as shown... Figure 5 As shown, a mask layer 30 is formed on the substrate material layer 20. The mask layer 30 covers a portion of the area and exposes another portion. The covered area is the area where the protrusion 1112 is located, and the exposed area is the area where the main body 1111 is located, which is the thinning area. It can be understood that the mask layer 30 can be a photoresist.

[0082] S130: The thinning region is thinned to form a first substrate 111. For example, as... Figure 6 As shown, the substrate material in the thinned region can be etched using a plasma etching process. It is understood that after etching, the mask layer 30 is removed.

[0083] Thus, based on the traditional process, only one additional photolithography step is needed to form the first substrate 111, thereby improving the latch-up effect and crosstalk between cellular devices.

[0084] In one embodiment, S200: forming at least two second substrates 112 on the first substrate 111 specifically includes the following steps:

[0085] S210: An epitaxial layer 40 is formed on the first substrate 111. Specifically, as shown in... Figure 7 As shown, an epitaxial layer 40 is formed on the first substrate 111 using an epitaxial process. This is equivalent to flattening the first substrate 111 through the epitaxial process. For example, the epitaxial layer 40 can be made relatively thick to ensure sufficient process window for subsequent etching processes.

[0086] S220: Planarize the epitaxial layer 40 to form at least two second substrates 112. For example... Figure 2 As shown, the epitaxial layer 40 can be planarized by etching or chemical-mechanical polishing (CMP).

[0087] It should be noted here that the manufacturing process used after S200 can be exactly the same as the traditional manufacturing process. This illustrates that the manufacturing process of the semiconductor device 10 provided in this application embodiment has high compatibility with existing process flows. For existing products, only one additional photolithography step is needed to achieve high-reliability device isolation, making the semiconductor device 10 compatible with a high-voltage operating range and possessing good scalability, which is beneficial for broadening the application scenarios of existing products. Furthermore, there is no need to redevelop an entire process or change all subsequent photolithography and processes, which can save development time and resources, has the advantage of a short R&D and manufacturing cycle, and is conducive to improving the market competitiveness of the product.

[0088] It should be noted that in S300, other structures of the semiconductor device 10 (such as isolation structure 17, gate 16, source region 155, drain region 154, second well region 157, etc.) can also be fabricated simultaneously. In S400, the second conductive structure 142, third conductive structure 143, and fourth conductive structure 144 of the semiconductor device 10 can also be fabricated simultaneously. The embodiments of this application will not be described in detail here.

[0089] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: The first substrate includes a main body portion and at least one protrusion provided on the main body portion; At least two second substrates are disposed on the main body portion, and a protrusion is provided between any two adjacent second substrates; At least two isolation regions are respectively disposed within the at least two second substrates; Each of the isolation regions is formed within the corresponding second substrate to form a device region; At least two first well regions correspond one-to-one with the at least two second substrates, and each first well region is disposed within the device region of the corresponding second substrate; A first conductive structure is electrically connected to the first substrate; Wherein, the first substrate, the second substrate, and the first well region are of a first conductivity type, and the doping concentration of the first substrate is greater than the doping concentration of the first well region; the isolation region is of a second conductivity type.

2. The semiconductor device according to claim 1, characterized in that, The doping concentration of the first substrate is greater than that of the second substrate.

3. The semiconductor device according to claim 1, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type.

4. The semiconductor device according to claim 1, characterized in that, The second substrate is an epitaxial layer.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a first lead-out region of a first conductivity type, the first lead-out region being disposed within the protrusion and electrically connected to the first conductive structure.

6. The semiconductor device according to claim 5, characterized in that, The semiconductor device further includes a first doped region of a first conductivity type, the first doped region being disposed within the protrusion, and the first lead-out region being disposed within the first doped region.

7. The semiconductor device according to claim 1, characterized in that, The isolation region includes a first sub-region and a second sub-region connected to the first sub-region; the second sub-region extends from the side surface of the second substrate away from the main body into the second substrate, and the first sub-region is located on the side of the second sub-region close to the first substrate; the first sub-region and the second sub-region surround to form the device region.

8. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes: A drain region of the second conductivity type is provided within the second sub-region; A source region of the second conductivity type is disposed within the first well region; The gate is disposed on the second substrate.

9. A method for fabricating a semiconductor device, characterized in that, include: A first substrate is provided; the first substrate includes a main body portion and at least one protrusion disposed on the main body portion; At least two second substrates are formed on the first substrate; A protrusion is provided between any two adjacent second substrates; At least two isolation regions and at least two first well regions are formed within the second substrate; The at least two isolation regions are respectively disposed in the at least two second substrates; Each isolation region is formed within a corresponding second substrate to enclose a device region; the at least two first well regions correspond one-to-one with the at least two second substrates, and each first well region is disposed within the device region of the corresponding second substrate; wherein, the first substrate, the second substrate, and the first well region are of a first conductivity type, and the doping concentration of the first substrate is greater than the doping concentration of the first well region; the isolation region is of a second conductivity type; A first conductive structure is formed that is electrically connected to the first substrate.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The provision of the first substrate includes: Provide a substrate material layer; A mask layer is formed on the substrate material layer to define the thinning region; The thinning region is thinned to form the first substrate; And / or, The formation of at least two second substrates on the first substrate includes: An epitaxial layer is formed on the first substrate; The epitaxial layer is planarized to form the at least two second substrates.

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