Detection device, display panel and display apparatus

Abstract

The embodiments of the present disclosure relate to the technical field of display. Provided are a detection device and a display panel, which are used for improving the reliability and stability of detection devices. The detection device comprises a plurality of detection units arranged in an array and a first control signal line. The first control signal line is electrically connected to the detection units. The first control signal line extends in a second direction, and the second direction is a column direction in which the plurality of detection units are arranged in an array. Each detection unit comprises a first transistor and a first capacitor; the first transistor comprises a first active pattern and a first gate, the first active pattern and the first gate overlapping each other in a third direction, and the third direction being the thickness direction of the detection device; the first capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate being electrically connected to the first gate. Part of the first control signal line and the first electrode plates overlap each other in the third direction. The part of the first control signal line that overlaps the first electrode plate is used for forming the second electrode plates. The detection device can be used for fingerprint recognition.

Description

Detection devices and display panels, display devices

[0001] This application claims priority to PCT patent application No. PCT / CN2024 / 141558, filed on December 23, 2024, and PCT patent application No. PCT / CN2024 / 141527, filed on December 23, 2024.

[0002] This application claims priority to Chinese patent application No. 202510376772.3, filed on March 27, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a detection device, display panel, and display apparatus. Background Technology

[0004] In recent years, with the development of technology, electronic products with biometric identification functions have gradually entered people's lives and work. Fingerprints are unique, unchanging features that distinguish one person from another; they consist of ridges and valleys on the surface of the skin at the fingertips. Because of their uniqueness and immutability, fingerprints can be used for personal identification, making fingerprint recognition technology highly valued. Summary of the Invention

[0005] On one hand, a detection device is provided. The detection device includes a plurality of detection units arranged in an array and a first control signal line. The first control signal line is electrically connected to the detection units. The first control signal line extends along a second direction, which is the column direction of the array of multiple detection units.

[0006] The detection unit includes a first transistor and a first capacitor. The first transistor includes a first active pattern and a first gate, which overlap in a third-direction orientation, the thickness direction of the detection device. The first capacitor includes a first electrode and a second electrode, which are electrically connected to the first gate. A portion of a first control signal line overlaps with the first electrode in a third-direction orientation, and the portion of the first control signal line overlapping with the first electrode forms the second electrode.

[0007] In some embodiments, the detection unit further includes a fourth transistor. The fourth transistor is located on one side of the first transistor along a first direction, which is the row direction in which the plurality of detection units are arranged in an array. The fourth transistor includes a fourth active pattern and a fourth gate, which are overlapped in a third direction. The fourth active pattern and the first gate are electrically connected. A first control signal line is located between the first active pattern and the fourth active pattern.

[0008] In some embodiments, the detection unit further includes a first connection portion. Along a first direction, the first connection portion is located on the side of the first electrode plate away from the first gate. The fourth active pattern is electrically connected to the first electrode plate via the first connection portion.

[0009] In some embodiments, the detection unit further includes a fourth transistor. The fourth transistor is located on one side of the first transistor along a first direction, which is the row direction in which the plurality of detection units are arranged in an array. The fourth transistor includes a fourth active pattern and a fourth gate, which are overlapped in a third direction. The fourth active pattern and the first gate are electrically connected. A first control signal line is located on the side of the first active pattern away from the fourth active pattern.

[0010] In some embodiments, the detection unit further includes a second connection portion. The second connection portion is located on the side of the first gate away from the first electrode plate. The fourth active pattern is electrically connected to the first gate through the second connection portion.

[0011] In some embodiments, the detection device further includes a plurality of detection unit groups. Each detection unit group includes two detection units located in adjacent columns of the same row, and the two detection units within the same detection unit group are symmetrically arranged with respect to the virtual line extending along the second direction.

[0012] In some embodiments, the detection device further includes a second control signal line. The second control signal line is electrically connected to at least one column of detection units and extends along a second direction. The second control signal line is located between two detection units within the same group of detection units.

[0013] In some embodiments, two second control signal lines are provided between two detection units in the same detection unit group, and the two detection units are respectively electrically connected to the two second control signal lines.

[0014] In some embodiments, a second control signal line is provided between two detection units in the same detection unit group, and both detection units are electrically connected to the second control signal line.

[0015] In some embodiments, the detection unit further includes a third transistor. The third transistor includes a third active pattern and a third gate, which are disposed overlapping in a third direction. The third gate is electrically connected to a second control signal line.

[0016] In some embodiments, the detection device further includes a third control signal line. The third control signal line extends along a second direction. A third control signal line is provided between two detection units within the same detection unit group, and both detection units are electrically connected to the third control signal line. The third control signal line is located between two adjacent second control signal lines.

[0017] In some embodiments, the detection device further includes a third control signal line. The third control signal line extends along a second direction. Two third control signal lines are provided between two detection units within the same detection unit group, and the two detection units are respectively electrically connected to the two third control signal lines. A second control signal line is located between two adjacent third control signal lines.

[0018] In some embodiments, the detection unit further includes a fourth transistor. The fourth transistor is located on one side of the first transistor along a first direction, which is the row direction in which the plurality of detection units are arranged in an array. The fourth transistor includes a fourth active pattern and a fourth gate, which are overlapped in a third direction. The fourth gate is electrically connected to a third control signal line.

[0019] In some embodiments, the detection unit further includes a piezoelectric transducer. Along a third direction, the piezoelectric transducer is located on one side of the first transistor and the first capacitor.

[0020] In some embodiments, the detection device further includes a substrate, a first conductive layer, and a second conductive layer. The first conductive layer is located on one side of the substrate and includes a first conductive portion, a portion of which is used to form a first gate and a portion of which is used to form a first electrode. The second conductive layer is located on the side of the first conductive layer away from the substrate and includes a first control signal line.

[0021] In some embodiments, a portion of the first conductive portion is further used to form a first connection portion, the first connection portion being located on the side of the first electrode plate away from the first gate. Alternatively, a portion of the first conductive portion is further used to form a second connection portion, the second connection portion being located on the side of the first gate plate away from the first electrode plate.

[0022] In some embodiments, the second conductive layer further includes a second control signal line. And / or, the second conductive layer further includes a third control signal line.

[0023] On the other hand, a display panel is provided. The display panel includes a display substrate and a detection device as described in any of the above embodiments. The detection device is located on the non-display side of the display substrate.

[0024] In some embodiments, the display panel further includes a color filter. The color filter is located on the side of the display substrate away from the detection device.

[0025] In another aspect, a display device is provided. The display device includes a display panel and a driver chip as described in any of the above embodiments. The driver chip is electrically connected to the display panel. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0027] Figure 1 is a plan view of a display device according to some embodiments;

[0028] Figure 2 is a cross-sectional view of a partial area of ​​a display panel according to some embodiments;

[0029] Figure 3 is a plan view of a detection device within a display panel according to some embodiments;

[0030] Figure 4 is a plan view of the detection device in the display panel according to some embodiments;

[0031] Figure 5 is a plan view of the detection device within the display panel according to some embodiments;

[0032] Figure 6 is a structural diagram of a detection device within a display panel according to some embodiments;

[0033] Figure 7 is an equivalent circuit diagram of a detection device in a display panel according to some embodiments;

[0034] Figure 8 is a plan view of a partial region of the first active layer in a detection device according to some embodiments;

[0035] Figure 9 is a plan view of a partial region of the first conductive layer in a detection device according to some embodiments;

[0036] Figure 10 is a plan view of a partial region of the first active layer and the first conductive layer in a detection device according to some embodiments;

[0037] Figure 11 is a partial plan view of a region of the second conductive layer in a detection device according to some embodiments;

[0038] Figure 12 is a partial plan view of a region of the first active layer, the first conductive layer and the second conductive layer in a detection device according to some embodiments;

[0039] Figure 13 is a partial plan view of a region of the second conductive layer in a detection device according to some embodiments;

[0040] Figure 14 is a partial plan view of a region of the first active layer, the first conductive layer and the second conductive layer in a detection device according to some embodiments;

[0041] Figure 15 is the driving timing diagram of the detection device shown in Figure 7;

[0042] Figure 16 is a plan view of a detection device within a display panel according to some embodiments;

[0043] Figure 17 is a plan view of a partial region of the second electrode layer in a detection device according to some embodiments;

[0044] Figure 18 is a plan view of a partial region of the first electrode layer in a detection device according to some embodiments;

[0045] Figure 19 is a plan view of a partial region of the first active layer, the first insulating layer and the first conductive layer in a detection device according to some embodiments;

[0046] Figure 20 is a plan view of a partial region of the first active layer, the first conductive layer, the second insulating layer, and the second conductive layer within a detection device according to some embodiments;

[0047] Figure 21 is a plan view of a partial region of the second conductive layer and the third insulating layer in a detection device according to some embodiments;

[0048] Figure 22 is a plan view of a partial region of the second conductive layer and the fourth insulating layer in a detection device according to some embodiments;

[0049] Figure 23 is a plan view of a partial region of the second conductive layer, the third insulating layer, the fourth insulating layer, and the third conductive layer within a detection device according to some embodiments;

[0050] Figure 24 is a plan view of a partial region of the second conductive layer, third insulating layer, fourth insulating layer, fifth insulating layer and second electrode layer in a detection device according to some embodiments;

[0051] Figure 25 is a plan view of a partial region of the second electrode layer, the piezoelectric material layer, and the first electrode layer within a detection device according to some embodiments. Detailed Implementation

[0052] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0053] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0054] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0055] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0056] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0057] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0058] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0059] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0060] For ease of description below, an XYZ coordinate system is established. The third direction Z represents the thickness direction of the detection device, the XY plane is perpendicular to the Z direction, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0061] It should be noted that, for example, 1 (20) in the accompanying drawings of this disclosure indicates that component 1 belongs to component 20, and other similar reference numerals in the drawings also follow the above description.

[0062] As shown in Figure 1, some embodiments of this disclosure provide a display device 1000.

[0063] Exemplarily, display device 1000 can be any device that displays images, whether moving (e.g., video) or stationary (e.g., still images), and whether text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, Global Positioning System (GPS) receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 illustrates display device 1000 as an example of a mobile phone.

[0064] For example, the display device 1000 may be an electroluminescent display device or a photoluminescent display device. When the display device 1000 is an electroluminescent display device, it may be an organic light-emitting diode (OLED) display device or a quantum dot light-emitting diode (QLED) display device. When the display device 1000 is a photoluminescent display device, it may be a quantum dot photoluminescent display device.

[0065] Alternatively, the display device 1000 may be a micro light-emitting diode (Micro LED) display device or a mini light-emitting diode (Mini LED) display device.

[0066] Alternatively, the display device 1000 may be a thin film transistor liquid crystal display (TFT-LCD) device.

[0067] In some embodiments, referring to FIG1, the display device 1000 may include a display panel 100 and a driver chip (not shown in the figure). The driver chip is electrically connected to the display panel 100 and can be configured to drive the display panel 100 to display an image.

[0068] For example, the driver chip within the display device 1000 may include a source driver IC.

[0069] For example, the driver chip in the display device 1000 can be encapsulated by means of chip on film (COF), chip on glass (COG) or chip on flexible material (COP) and bonded to the display panel 100.

[0070] For example, when the display device 1000 is an electroluminescent display device or a photoluminescent display device, the display panel 100 within the display device 1000 can be an electroluminescent display panel or a photoluminescent display panel.

[0071] When the display device 1000 is a micro LED display device or a sub-millimeter LED display device, the display panel 100 within the display device 1000 can be a micro LED display panel or a sub-millimeter LED display panel.

[0072] When the display device 1000 is a thin-film transistor liquid crystal display device, the display panel 100 within the display device 1000 can be a thin-film transistor liquid crystal display panel.

[0073] The structure of the above-mentioned display panel 100 will be described in detail below.

[0074] In some embodiments, as shown in FIG2, FIG2 is a cross-sectional view of a partial area of ​​a display panel 100 according to some embodiments. The display panel 100 may include a display substrate 10 and a detection device 20. The detection device 20 may be located on the non-display side 10b of the display substrate 10.

[0075] It should be noted that the display side 10a of the display substrate 10 refers to the side of the display substrate 10 where an image can be displayed. The non-display side 10b of the display substrate 10 refers to the side opposite to the display side 10a of the display substrate 10.

[0076] For example, the detection device 20 within the display panel 100 can be used to identify biometric features.

[0077] For example, the detection device 20 can be used to identify biometric features such as fingerprints.

[0078] For example, the detection device 20 within the display panel 100 can be an ultrasonic detection device.

[0079] When the display substrate 10 within the display panel 100 includes a black pixel definition layer (BPDL) and / or a black matrix (BM), since the ultrasonic detection device within the display panel 100 performs the detection function through ultrasonic waves, there is no need for the black pixel definition layer and / or black matrix to optically avoid the detection device 20. This is beneficial to improving the display uniformity of the display substrate 10, and thus to improving the display effect of the display panel 100.

[0080] In some embodiments, referring to FIG2, the display panel 100 may include a color filter 30.

[0081] In the aforementioned display panel 100, the color filter 30 can absorb or reflect light of non-target wavelengths, thereby reducing stray light interference and improving the display effect of the display panel 100.

[0082] For example, referring to Figure 2, the color filter 30 can be directly integrated onto the encapsulation layer within the display substrate 10 using COE (Color Filter On Encapsulation) technology. On the one hand, this shortens the optical path, which helps improve the luminous efficiency of the display panel 100. On the other hand, it eliminates the need for a polarizer within the display panel 100, thereby avoiding interference with black purity and improving the display effect of the display panel 100.

[0083] For example, referring to FIG2, when the display panel 100 includes a display substrate 10 and a detection device 20, and the detection device 20 is located on the non-display side 10b of the display substrate 10, the color filter 30 may be located on the side of the display substrate 10 away from the detection device 20.

[0084] The structure of the above-mentioned detection device 20 will be described in detail below.

[0085] In some embodiments, as shown in Figures 3, 4, and 5, which are plan views of a detection device 20 within a display panel 100 according to some embodiments, the detection device 20 may include a plurality of detection units M arranged in an array.

[0086] For example, please continue to refer to Figures 3, 4 and 5. The multiple detection units M in the detection device 20 can be arranged at intervals along a first direction X and a second direction Y, respectively. The first direction X can be the row direction of the array of multiple detection units M, and the second direction Y can be the column direction of the array of multiple detection units M.

[0087] For example, referring to Figures 3, 4, and 5, the detection device 20 may also include multiple detection unit groups M1. Each detection unit group M1 may include two detection units M located in adjacent columns of the same row, and the two detection units M within the same detection unit group M1 may be symmetrically arranged with respect to the virtual line N1 extending along the second direction Y.

[0088] In some embodiments, as shown in FIG6, FIG6 is a structural diagram of a detection device 20 within a display panel 100 according to some embodiments. The detection unit M within the detection device 20 may include a driving sub-circuit.

[0089] For example, as shown in FIG7, FIG7 is an equivalent circuit diagram of a detection device 20 within a display panel 100 according to some embodiments. The driving sub-circuit within the detection unit M may include a first transistor T1.

[0090] As shown in Figures 8, 9, and 10, Figure 8 is a plan view of a partial region of the first active layer 1 within the detection device 20 according to some embodiments, Figure 9 is a plan view of a partial region of the first conductive layer 2 within the detection device 20 according to some embodiments, and Figure 10 is a plan view of partial regions of the first active layer 1 and the first conductive layer 2 within the detection device 20 according to some embodiments. The first transistor T1 may include a first active pattern T11 and a first gate T12, which are overlapped in a third direction Z, where the third direction Z is the thickness direction of the detection device 20.

[0091] For example, referring to FIG8, the first active pattern T11 in the first transistor T1 may include a first source region T11a, a first drain region T11b, and a first channel region T11c located between the first source region T11a and the first drain region T11b.

[0092] Please continue to refer to Figure 10. Specifically, the above-mentioned "the first active pattern T11 and the first gate T12 in the first transistor T1 overlap in the third direction Z" can be that the first channel region T11c and the first gate T12 in the first active pattern T11 overlap in the third direction Z.

[0093] For example, referring to Figure 7, the first transistor T1 can be a low-temperature polysilicon (LTPS) thin-film transistor. LTPS thin-film transistors have advantages such as high mobility and fast charging. When the first transistor T1 is an LTPS thin-film transistor, the material of the first active pattern T11 within the first transistor T1 can include low-temperature polysilicon (LTPS).

[0094] Alternatively, the first transistor T1 can be an oxide thin-film transistor. Oxide thin-film transistors have advantages such as low leakage current. When the first transistor T1 is an oxide thin-film transistor, the material of the first active pattern T11 within the first transistor T1 can include oxide semiconductor.

[0095] For example, please continue to refer to Figure 7, where the first transistor T1 can be a P-type transistor.

[0096] When the first transistor T1 is a P-type transistor, the turn-on voltage of the first transistor T1 is a low-level voltage (for example, the turn-on voltage of the first transistor T1 can be 0V, -5V or -10V, etc.), and the turn-off voltage of the first transistor T1 is a high-level voltage (for example, the turn-off voltage of the first transistor T1 can be 5V or 10V, etc.).

[0097] Alternatively, the first transistor T1 can be an N-type transistor.

[0098] When the first transistor T1 is an N-type transistor, the turn-on voltage of the first transistor T1 is a high-level voltage (for example, the turn-off voltage of the first transistor T1 can be 5V or 10V, etc.), and the turn-off voltage of the first transistor T1 is a low-level voltage (for example, the turn-on voltage of the first transistor T1 can be 0V, -5V or -10V, etc.).

[0099] In some embodiments, please continue to refer to FIG6, the detection unit M within the detection device 20 may also include a readout sub-circuit.

[0100] For example, referring to Figure 7, the readout sub-circuit within the detection unit M may include a second transistor T2.

[0101] Please refer to Figures 8, 9 and 10. The second transistor T2 may include a second active pattern T21 and a second gate T22, which are arranged to overlap in the third direction Z.

[0102] For example, referring to Figure 8, the second active pattern T21 within the second transistor T2 may include a second source region T21a, a second drain region T21b, and a second channel region T21c located between the second source region T21a and the second drain region T21b.

[0103] Please continue to refer to Figure 10. Specifically, the above-mentioned "the second active pattern T21 and the second gate T22 in the second transistor T2 overlap in the third direction Z" can be that the second channel region T21c and the second gate T22 in the second active pattern T21 overlap in the third direction Z.

[0104] For example, referring to FIG7, the second transistor T2 can be a low-temperature polycrystalline silicon thin-film transistor. In the case that the second transistor T2 is a low-temperature polycrystalline silicon thin-film transistor, the material of the second active pattern T21 within the second transistor T2 can include low-temperature polycrystalline silicon.

[0105] Alternatively, the second transistor T2 can be an oxide thin-film transistor. In the case that the second transistor T2 is an oxide thin-film transistor, the material of the second active pattern T21 within the second transistor T2 can include an oxide semiconductor.

[0106] For example, please continue to refer to Figure 7, the second transistor T2 can be an N-type transistor or a P-type transistor.

[0107] For example, please continue to refer to FIG10. In the case that the detection unit M in the detection device 20 includes a driving sub-circuit and the driving sub-circuit includes a first transistor T1, the second transistor T2 may be located on one side of the first transistor T1 along the second direction Y.

[0108] In some embodiments, please continue to refer to FIG6, the detection unit M within the detection device 20 may further include a first control circuit.

[0109] For example, referring to Figure 7, the first control circuit within the detection unit M may include a third transistor T3.

[0110] Please refer to Figures 8, 9 and 10. The third transistor T3 may include a third active pattern T31 and a third gate T32, which are arranged to overlap in the third direction Z.

[0111] For example, referring to Figure 8, the third active pattern T31 in the third transistor T3 may include a third source region T31a, a third drain region T31b, and a third channel region T31c located between the third source region T31a and the third drain region T31b.

[0112] Please refer to Figure 10. Specifically, the above-mentioned "the third active pattern T31 and the third gate T32 in the third transistor T3 overlap in the third direction Z" can be that the third channel region T31c and the third gate T32 in the third active pattern T31 overlap in the third direction Z.

[0113] For example, referring to Figure 7, the third transistor T3 can be a low-temperature polycrystalline silicon thin-film transistor. When the third transistor T3 is a low-temperature polycrystalline silicon thin-film transistor, the material of the third active pattern T31 within the third transistor T3 can include low-temperature polycrystalline silicon.

[0114] Alternatively, the third transistor T3 can be an oxide thin-film transistor. In the case that the third transistor T3 is an oxide thin-film transistor, the material of the third active pattern T31 within the third transistor T3 can include oxide semiconductor.

[0115] For example, please continue to refer to Figure 7, where the third transistor T3 can be an N-type transistor or a P-type transistor.

[0116] For example, referring to FIG10, in the case where the detection unit M in the detection device 20 includes a readout sub-circuit and the readout sub-circuit includes a second transistor T2, the third transistor T3 may be located on one side of the second transistor T2 along the first direction X.

[0117] In some embodiments, please continue to refer to FIG6, the detection unit M within the detection device 20 may also include a second control circuit.

[0118] For example, referring to Figure 7, the second control circuit within the detection unit M may include a fourth transistor T4.

[0119] Please refer to Figures 8, 9 and 10. The fourth transistor T4 may include a fourth active pattern T41 and a fourth gate T42, which are arranged to overlap in the third direction Z.

[0120] For example, referring to Figure 8, the fourth active pattern T41 in the fourth transistor T4 may include a fourth source region T41a, a fourth drain region T41b, and a fourth channel region T41c located between the fourth source region T41a and the fourth drain region T41b.

[0121] Please continue to refer to Figure 10. Specifically, the above-mentioned "the fourth active pattern T41 and the fourth gate T42 in the fourth transistor T4 overlap in the third direction Z" can be that the fourth channel region T41c and the fourth gate T42 in the fourth active pattern T41 overlap in the third direction Z.

[0122] For example, referring to Figure 7, the fourth transistor T4 can be a low-temperature polycrystalline silicon thin-film transistor. In the case that the fourth transistor T4 is a low-temperature polycrystalline silicon thin-film transistor, the material of the fourth active pattern T41 within the fourth transistor T4 can include low-temperature polycrystalline silicon.

[0123] Alternatively, the fourth transistor T4 can be an oxide thin-film transistor. In the case that the fourth transistor T4 is an oxide thin-film transistor, the material of the fourth active pattern T41 within the fourth transistor T4 can include oxide semiconductor.

[0124] For example, please continue to refer to Figure 7, where the fourth transistor T4 can be an N-type transistor or a P-type transistor.

[0125] For example, please continue to refer to FIG10. In the case that the detection unit M in the detection device 20 includes a driving sub-circuit and the driving sub-circuit includes a first transistor T1, the fourth transistor T4 may be located on one side of the first transistor T1 along the first direction X.

[0126] For example, please continue to refer to FIG10. In the case that the detection unit M in the detection device 20 includes a first control circuit and the first control circuit includes a third transistor T3, the fourth transistor T4 may be located on one side of the third transistor T3 along the second direction Y.

[0127] In some embodiments, please continue to refer to FIG6, the detection unit M within the detection device 20 may also include a voltage regulator circuit.

[0128] For example, referring to Figure 7, the voltage regulator circuit within the detection unit M may include a first capacitor C1.

[0129] As shown in Figures 11 and 12, and in conjunction with Figure 9, Figure 11 is a plan view of a partial region of the second conductive layer 3 within the detection device 20 according to some embodiments, and Figure 12 is a plan view of a partial region of the first active layer 1, the first conductive layer 2, and the second conductive layer 3 within the detection device 20 according to some embodiments. The first capacitor C1 may include a first electrode C11 and a second electrode C12.

[0130] In some embodiments, referring to Figures 6 and 7, the detection unit M within the detection device 20 may further include a piezoelectric transducer C2. The piezoelectric transducer C2 includes a first electrode C21 and a second electrode C22, and a piezoelectric material layer C23 located between the first electrode C21 and the second electrode C22.

[0131] For example, please continue to refer to Figures 6 and 7, the first electrode C21 of the piezoelectric transducer C2 can be electrically connected to the transmitting signal terminal Tx.

[0132] The working principle of the piezoelectric transducer C2 is as follows: a first signal is applied to the first electrode C21 of the piezoelectric transducer C2 through the transmitting signal terminal Tx. The piezoelectric material layer C23 of the piezoelectric transducer C2 is excited by the voltage to generate the piezoelectric effect, which causes the piezoelectric material layer C23 of the piezoelectric transducer C2 to generate mechanical vibration, thereby emitting ultrasonic waves outward.

[0133] When the detection device 20 is used to identify fingerprints, the ultrasonic waves emitted by the piezoelectric transducer C2 in the detection device 20 are reflected after contacting the finger. Since the finger has valleys and ridges, the vibration intensity of the ultrasonic waves reflected from different positions of the finger (e.g., the valleys and ridges of the finger) is different. At this time, a second signal is applied to the first electrode C21 of the piezoelectric transducer C2 through the transmitting signal terminal Tx. The piezoelectric material layer C23 of the piezoelectric transducer C2 is affected by the reflected ultrasonic waves, generating a positive piezoelectric effect and generating an AC signal on the second electrode C22 of the piezoelectric transducer C2.

[0134] For example, please continue to refer to Figures 6 and 7. The first signal applied to the first electrode C21 of the piezoelectric transducer C2 through the transmitting signal terminal Tx can be an AC voltage signal.

[0135] For example, the first signal can be a square wave AC signal. Or, the first signal can be a sinusoidal AC signal.

[0136] For example, please continue to refer to Figures 6 and 7. The frequency of the first signal applied to the first electrode C21 of the piezoelectric transducer C2 through the transmitting signal terminal Tx can be greater than or equal to 100 kHz and less than or equal to 20 MHz.

[0137] For example, please continue to refer to Figures 6 and 7. The materials of the first electrode C21 and the second electrode C22 of the piezoelectric transducer C2 can both include at least one of metals and metal oxides.

[0138] For example, please continue to refer to Figures 6 and 7. When the materials of the first electrode C21 and the second electrode C22 of the piezoelectric transducer C2 include metals, the materials of the first electrode C21 and the second electrode C22 of the piezoelectric transducer C2 can both include at least one of platinum (Pt), iridium (Ir), gold (Au), aluminum (Al), copper (Cu), titanium (Ti) and stainless steel.

[0139] For example, please continue to refer to Figures 6 and 7. When the materials of the first electrode C21 and the second electrode C22 of the piezoelectric transducer C2 include metal oxides, the materials of the first electrode C21 and the second electrode C22 of the piezoelectric transducer C2 can both include at least one of indium tin oxide (ITO) and fluorine-doped tin oxide.

[0140] For example, referring to Figures 6 and 7, the material of the piezoelectric material layer C23 of the piezoelectric transducer C2 may include at least one of polyvinylidene fluoride (PVDF) and aluminum nitride (AlN).

[0141] For example, referring to Figures 6 and 7, the material of the piezoelectric material layer C23 of the piezoelectric transducer C2 may include polydifluoroethylene.

[0142] For example, please continue to refer to Figures 6 and 7. The material of the piezoelectric material layer C23 of the piezoelectric transducer C2 may include aluminum nitride.

[0143] For example, referring to Figures 6 and 7, the material of the piezoelectric material layer C23 of the piezoelectric transducer C2 may include polyvinylidene fluoride and aluminum nitride.

[0144] In some embodiments, please continue to refer to Figures 11, 12, 13, and 14. Figure 13 is a plan view of a partial region of the second conductive layer 3 within the detection device 20 according to some embodiments, and Figure 14 is a plan view of a partial region of the first active layer 1, the first conductive layer 2, and the second conductive layer 3 within the detection device 20 according to some embodiments. The detection device 20 may further include a first control signal line Gate1. The first control signal line Gate1 extends along a second direction Y.

[0145] Please refer to Figures 3, 4 and 5. The first control signal line Gate1 can be electrically connected to the detection unit M inside the detection device 20.

[0146] For example, please continue to refer to FIG12 and in conjunction with FIG7, the detection unit M in the detection device 20 includes a driving sub-circuit and a second control circuit. The driving sub-circuit includes a first transistor T1 and the second control circuit includes a fourth transistor T4. When the fourth transistor T4 is located on one side of the first transistor T1 along the first direction X, the first control signal line Gate1 can be located between the first transistor T1 and the fourth transistor T4 in the same detection unit M.

[0147] For example, referring to Figure 12, when the first transistor T1 includes a first active pattern T11 and the fourth transistor T4 includes a fourth active pattern T41, the first control signal line Gate1 can be located between the first active pattern T11 of the first transistor T1 and the fourth active pattern T41 of the fourth transistor T4 within the same detection unit M.

[0148] Alternatively, please continue to refer to Figure 14 and in conjunction with Figure 7. The detection unit M in the detection device 20 includes a driving sub-circuit and a second control circuit. The driving sub-circuit includes a first transistor T1, and the second control circuit includes a fourth transistor T4. When the fourth transistor T4 is located on one side of the first transistor T1 along the first direction X, the first control signal line Gate1 can be located on the side of the first transistor T1 in the same detection unit M that is away from the fourth transistor T4.

[0149] For example, referring to Figure 14, when the first transistor T1 includes a first active pattern T11 and the fourth transistor T4 includes a fourth active pattern T41, the first control signal line Gate1 can be located on the side of the first active pattern T11 of the first transistor T1 within the same detection unit M that is away from the fourth active pattern T41 of the fourth transistor T4.

[0150] In some embodiments, referring further to Figures 11, 12, 13, and 14, the detection device 20 may also include a second control signal line Gate2. The second control signal line Gate2 extends along a second direction Y.

[0151] Please refer to Figures 3, 4 and 5. The second control signal line Gate2 can be electrically connected to at least one detection unit M.

[0152] Please refer to Figures 3, 4, 5, 11, 12, 13 and 14. When the detection device 20 includes multiple detection unit groups M1, each detection unit group M1 includes two detection units M located in adjacent columns in the same row, and the two detection units M in the same detection unit group M1 are symmetrically arranged with respect to the virtual line N1 extending along the second direction Y, the second control signal line Gate2 can be located between the two detection units M in the same detection unit group M1.

[0153] For example, referring to Figures 11 and 12, and in conjunction with Figure 3, two second control signal lines (Gate2) can be provided between two detection units M within the same detection unit group M1, and the two detection units M are respectively electrically connected to the two second control signal lines (Gate2). That is, when two second control signal lines (Gate2) are provided between two detection units M within the same detection unit group M1, one detection unit M within the same detection unit group M1 is electrically connected to one of the two second control signal lines (Gate2), and the other detection unit M is electrically connected to the other second control signal line (Gate2).

[0154] Alternatively, please refer to Figures 13 and 14, and in conjunction with Figures 4 and 5. A second control signal line (Gate2) can be provided between two detection units M within the same detection unit group M1, and both detection units M are electrically connected to this second control signal line (Gate2). That is, when a second control signal line (Gate2) is provided between two detection units M within the same detection unit group M1, both detection units M within the same detection unit group M1 are electrically connected to the same second control signal line (Gate2).

[0155] In some embodiments, referring further to Figures 11, 12, 13, and 14, the detection device 20 may also include a third control signal line Gate3. The third control signal line Gate3 extends along the second direction Y.

[0156] Please refer to Figures 3, 4 and 5. The third control signal line Gate3 can be electrically connected to at least one detection unit M.

[0157] Please continue to refer to Figures 3, 4, 5, 11, 12, 13 and 14. When the detection device 20 includes multiple detection unit groups M1, each detection unit group M1 includes two detection units M located in adjacent columns in the same row, and the two detection units M in the same detection unit group M1 are symmetrically arranged with respect to the virtual line N1 extending along the second direction Y, the third control signal line Gate3 can be located between the two detection units M in the same detection unit group M1.

[0158] For example, referring to Figures 11 and 12, and in conjunction with Figure 3, a third control signal line Gate3 can be provided between two detection units M within the same detection unit group M1, and both detection units M are electrically connected to the same third control signal line Gate3. That is, when a third control signal line Gate3 is provided between two detection units M within the same detection unit group M1, the two detection units M within the same detection unit group M1 are electrically connected to the same third control signal line Gate3.

[0159] Alternatively, referring to Figures 13 and 14, and in conjunction with Figures 4 and 5, two third control signal lines (Gate3) can be provided between two detection units M within the same detection unit group M1, and the two detection units M are respectively electrically connected to the two third control signal lines (Gate3). That is, when two third control signal lines (Gate3) are provided between two detection units M within the same detection unit group M1, one detection unit M within the same detection unit group M1 is electrically connected to one of the two third control signal lines (Gate3), and the other detection unit M is electrically connected to the other third control signal line (Gate3).

[0160] For example, please continue to refer to Figures 11 and 12, and in conjunction with Figure 3, in the case where the detection device 20 includes a second control signal line Gate2 and a third control signal line Gate3, and two detection units M in the same detection unit group M1 are provided with two second control signal lines Gate2 and one third control signal line Gate3, and the two detection units M are respectively electrically connected to the two second control signal lines Gate2, and both detection units M are electrically connected to the third control signal line Gate3, the third control signal line Gate3 can be located between two adjacent second control signal lines Gate2.

[0161] In the aforementioned detection device 20, the third control signal line Gate3 is located between two adjacent second control signal lines Gate2. On the one hand, the electric field formed between the two second control signal lines Gate2 and the third control signal line Gate3 on opposite sides of the third control signal line Gate3 can be symmetrically distributed, so that the electric field effect of the two second control signal lines Gate2 on the third control signal line Gate3 on opposite sides of the third control signal line Gate3 can be balanced, which is beneficial to reducing the coupling capacitance of the third control signal line Gate3, thereby improving the signal transmission efficiency of the third control signal line Gate3, and thus improving the stability and reliability of the detection device 20.

[0162] On the other hand, the physical barrier effect of the second control signal line Gate2 can weaken the coupling effect between other components in the detection device 20 (e.g., the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the first capacitor C1) and the third control signal line Gate3. This is beneficial to further reduce the coupling capacitance of the third control signal line Gate3, and thus to further improve the signal transmission efficiency of the third control signal line Gate3, thereby further improving the stability and reliability of the detection device 20.

[0163] Alternatively, please continue to refer to Figures 13 and 14, and in conjunction with Figures 4 and 5. In the case where the detection device 20 includes a second control signal line Gate2 and a third control signal line Gate3, and two detection units M within the same detection unit group M1 are provided with one second control signal line Gate2 and two third control signal lines Gate3, and both detection units M are electrically connected to one second control signal line Gate2, and the two detection units M are respectively electrically connected to two third control signal lines Gate3, the second control signal line Gate2 can be located between two adjacent third control signal lines Gate3.

[0164] In the aforementioned detection device 20, the second control signal line Gate2 is located between two adjacent third control signal lines Gate3. On the one hand, the electric field formed between the two third control signal lines Gate3 on opposite sides of the second control signal line Gate2 can be symmetrically distributed, so that the electric field effect of the two third control signal lines Gate3 on opposite sides of the second control signal line Gate2 can be balanced. This is beneficial to reducing the coupling capacitance of the second control signal line Gate2, thereby improving the signal transmission efficiency of the second control signal line Gate2, and thus improving the stability and reliability of the detection device 20.

[0165] On the other hand, the physical barrier effect of the third control signal line Gate3 can weaken the coupling effect between other components in the detection device 20 (e.g., the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the first capacitor C1) and the second control signal line Gate2. This is beneficial to further reduce the coupling capacitance of the second control signal line Gate2, and thus to further improve the signal transmission efficiency of the second control signal line Gate2, thereby further improving the stability and reliability of the detection device 20.

[0166] In some embodiments, referring further to Figures 9, 10, 12, and 14, the detection device 20 may also include a constant voltage signal line AP. The constant voltage signal line AP extends along a first direction X.

[0167] Please refer to Figures 3, 4 and 5. The constant voltage signal line AP can be electrically connected to at least one row of detection units M.

[0168] For example, the constant voltage signal line AP can be electrically connected to a line detection unit M.

[0169] Alternatively, please refer to Figures 9, 10, 12, and 14, and in conjunction with Figures 3, 4, and 5. The constant voltage signal line AP can be electrically connected to two rows of detection units M. That is, each constant voltage signal line AP corresponds to two rows of detection units M (i.e., multiple detection units M arranged along the first direction X).

[0170] For example, please continue to refer to Figures 9, 10, 12 and 14, and in conjunction with Figures 3, 4 and 5, the constant voltage signal line AP can be located between two adjacent rows of detection units M.

[0171] For example, please continue to refer to Figures 9, 10, 12 and 14. The constant voltage signal line AP can be used to transmit high-level signals, and the signal transmitted by the constant voltage signal line AP can be a DC signal.

[0172] In some embodiments, referring further to Figures 9, 10, 12, and 14, the detection device 20 may also include a signal readout line Read. The signal readout line Read extends along a first direction X.

[0173] Please refer to Figures 3, 4 and 5. The Read signal reading line can be electrically connected to at least one row of detection units M.

[0174] For example, please continue to refer to Figures 9, 10, 12, and 14, and in conjunction with Figures 3, 4, and 5, the signal read lines Read can be electrically connected to a row detection unit M. That is, each signal read line Read corresponds to a row detection unit M.

[0175] Alternatively, the signal read line Read can be electrically connected to the two-line detection unit M.

[0176] For example, please continue to refer to Figures 9, 10, 12 and 14, and in conjunction with Figures 3, 4 and 5, the signal read line Read can be located between two adjacent rows of detection units M.

[0177] For example, please continue to refer to Figures 9, 10, 12 and 14, and in conjunction with Figures 3, 4 and 5, when the detection device 20 includes a constant voltage signal line AP, the constant voltage signal line AP is located between two adjacent rows of detection units M, and the constant voltage signal line AP and the two rows of detection units M are electrically connected, along the second direction Y, the signal read line Read can be located on the side of the detection unit M that is electrically connected to the constant voltage signal line AP away from the constant voltage signal line AP.

[0178] In some embodiments, referring to Figures 9, 10, 11, 12, 13 and 14, the detection device 20 may also include a bias voltage line BIAS.

[0179] Please refer to Figures 3, 4 and 5. The bias voltage line BIAS can be electrically connected to at least one row of detection units M.

[0180] For example, referring to Figures 9, 10, 12, and 14, the bias voltage line BIAS may include a first sub-bias voltage line BIAS2. The first sub-bias voltage line BIAS2 extends along a first direction X.

[0181] For example, please continue to refer to Figures 9, 10, 12, and 14, and in conjunction with Figures 3, 4, and 5, when the bias voltage line BIAS includes a first sub-bias voltage line BIAS2, the first sub-bias voltage line BIAS2 can be electrically connected to a row of detection units M. That is, each first sub-bias voltage line BIAS2 corresponds to a row of detection units M.

[0182] Alternatively, the first sub-bias voltage line BIAS2 can be electrically connected to the two rows of detection units M.

[0183] For example, please continue to refer to Figures 9, 10, 12 and 14, and in conjunction with Figures 3, 4 and 5, in the case where the bias voltage line BIAS includes a first sub-bias voltage line BIAS2, the first sub-bias voltage line BIAS2 can be located between two adjacent rows of detection units M.

[0184] For example, please continue to refer to Figures 9, 10, 12 and 14, and in conjunction with Figures 3, 4 and 5, when the detection device 20 includes a constant voltage signal line AP, the constant voltage signal line AP is located between two adjacent rows of detection units M, and the constant voltage signal line AP and the two rows of detection units M are electrically connected, along the second direction Y, the first sub-bias voltage line BIAS2 can be located on the side of the detection unit M that is electrically connected to the constant voltage signal line AP away from the constant voltage signal line AP.

[0185] For example, in a detection device 20 that includes a constant voltage signal line AP and a signal readout line Read, where the constant voltage signal line AP is located between two adjacent rows of detection units M along the second direction Y, and the signal readout line Read is located on the side of the detection unit M electrically connected to the constant voltage signal line AP that is away from the constant voltage signal line AP, the first sub-bias voltage line BIAS2 can be located on the side of the signal readout line Read that is away from the constant voltage signal line AP. That is, the signal readout line Read can be closer to the constant voltage signal line AP than the first sub-bias voltage line BIAS2.

[0186] For example, referring to Figures 11, 12, 13, and 14, the bias voltage line BIAS may further include a second sub-bias voltage line BIAS1. The second sub-bias voltage line BIAS1 extends along a second direction Y.

[0187] For example, please continue to refer to Figures 12 and 14, and in conjunction with Figures 3, 4 and 5, when the bias voltage line BIAS includes a first sub-bias voltage line BIAS2, and the first sub-bias voltage line BIAS2 extends along the first direction X, the second sub-bias voltage line BIAS1 can be electrically connected to the first sub-bias voltage line BIAS2.

[0188] In the aforementioned detection device 20, the bias voltage line BIAS within the detection device 20 includes a first sub-bias voltage line BIAS2 and a second sub-bias voltage line BIAS1. The first sub-bias voltage line BIAS2 extends along a first direction X, and the second sub-bias voltage line BIAS1 extends along a second direction Y. Since the first direction X is the row direction of the array of multiple detection units M, and the second direction Y is the column direction of the array of multiple detection units M, the first direction X and the second direction Y intersect. The first sub-bias voltage line BIAS2 extending along the first direction X and the second sub-bias voltage line BIAS1 extending along the second direction Y can jointly form a mesh structure, which makes the consistency of the bias signals received by the multiple detection units M within the detection device 20 higher, which is beneficial to improving the detection accuracy of the detection device 20.

[0189] For example, please continue to refer to Figures 11, 12, 13 and 14. When the detection device 20 includes a plurality of detection unit groups M1, each detection unit group M1 includes two detection units M located in adjacent columns in the same row, and the two detection units M in the same detection unit group M1 are symmetrically arranged with respect to the virtual line N1 extending along the second direction Y, the second sub-bias voltage line BIAS1 can be located between two adjacent detection unit groups M1 along the first direction X.

[0190] For example, please continue to refer to Figures 9, 10, 12 and 14. The bias voltage line BIAS can be used to transmit a low-level signal, and the signal transmitted by the bias voltage line BIAS can be a DC signal.

[0191] In some embodiments, please continue to refer to FIG6. When the detection device 20 includes a first control signal line Gate1, a second control signal line Gate, a third control signal line Gate3, a constant voltage signal line AP, a signal reading line Read, a bias voltage line BIAS, and a detection unit M, and the detection unit M includes a driving sub-circuit, a reading sub-circuit, a first control circuit, a second control circuit, a voltage regulating sub-circuit, and a piezoelectric transducer C2, the driving sub-circuit can be electrically connected to the constant voltage signal line AP, the first node N1, and the second node N2 respectively, and is configured to provide a signal to the second node N2 under the control of the signals of the constant voltage signal line AP and the first node N1.

[0192] The voltage regulator circuit can be electrically connected to the first node N1 and the first control signal line Gate1 respectively, and is configured to store the voltage difference between the signal of the first node N1 and the signal of the first control signal line Gate1.

[0193] The read sub-circuit can be electrically connected to the first control signal line Gate1, the signal read line Read, and the second node N2, respectively, and is configured to provide the signal of the second node N2 to the signal read line Read under the control of the signal of the first control signal line Gate1.

[0194] The first control circuit can be electrically connected to the second control signal line Gate2, the bias voltage line BIAS, and the third node N3 respectively, and is configured to provide the bias voltage line BIAS signal to the third node N3 under the control of the signal of the second control signal line Gate2.

[0195] The second control circuit can be electrically connected to the third control signal line Gate3, the first node N1 and the third node N3 respectively, and is configured to provide the signal of the third node N3 to the first node N1 under the control of the signal of the third control signal line Gate3.

[0196] The piezoelectric transducer C2 can be electrically connected to the third node N3 and the transmitting signal terminal Tx respectively. It is configured to emit ultrasonic waves under the control of the signal from the transmitting signal terminal Tx, and convert the ultrasonic wave signal reflected by the object to be identified (e.g., a fingerprint) into an electrical signal and transmit it to the third node N3.

[0197] In the aforementioned detection device 20, the voltage regulator circuit can improve the stability of the signal at the first node N1, thereby improving the detection accuracy of the detection device 20 (e.g., the fingerprint recognition accuracy of the detection device 20), which is beneficial to improving the reliability of the detection device 20.

[0198] For example, referring to Figures 7, 12, and 14, and in conjunction with Figures 3, 4, and 5, the driving sub-circuit within the detection unit M includes a first transistor T1, the reading sub-circuit includes a second transistor T2, the second control circuit includes a fourth transistor T4, and the voltage regulating sub-circuit includes a first capacitor C1. The first transistor T1 includes a first active pattern T11 and a first gate T12; the second transistor T2 includes a second active pattern T21 and a second gate T22; the fourth transistor T4 includes a fourth active pattern T41 and a fourth gate T42; and the first capacitor C1 includes a first plate C11 and a second plate C12. In this case, the first active pattern T11 of the first transistor T1 can be electrically connected to the constant voltage signal line AP and the second active pattern T21 of the second transistor T2, respectively. The first gate T12 of the first transistor T1 can be electrically connected to the fourth active pattern T41 of the fourth transistor T4 and the first plate C11 of the first capacitor C1.

[0199] The second active pattern T21 of the second transistor T2 can be electrically connected to the signal read line Read and the first active pattern T11 of the first transistor T1, respectively. The second gate T22 of the second transistor T2 can be electrically connected to the first control signal line Gate1.

[0200] The fourth active pattern T41 of the fourth transistor T4 can be electrically connected to the first gate T12 of the first transistor T1 and the first plate C11 of the first capacitor C1. The fourth gate T42 of the fourth transistor T4 can be electrically connected to the third control signal line Gate3.

[0201] The first plate C11 of the first capacitor C1 can be electrically connected to the first gate T12 of the first transistor T1 and the fourth active pattern T41 of the fourth transistor T4. The second plate C12 of the first capacitor C1 can be electrically connected to the first control signal line Gate1.

[0202] For example, referring to Figures 12 and 14, and in conjunction with Figures 9, 11, and 13, when the second plate C12 of the first capacitor C1 and the first control signal line Gate1 are electrically connected, a portion of the first control signal line Gate1 within the detection device 20 can overlap with the first plate C11 of the first capacitor C1 in the third direction Z. The portion of the first control signal line Gate1 that overlaps with the first plate C11 of the first capacitor C1 can be used to form the second plate C12 of the first capacitor C1.

[0203] In the aforementioned detection device 20, the portion of the first control signal line Gate1 that overlaps with the first plate C11 of the first capacitor C1 forms the second plate C12 of the first capacitor C1. This reduces parasitic capacitance within the detection device 20, thereby lowering its power consumption. Furthermore, it reduces the wiring density of the detection device 20, which helps reduce the risk of crosstalk between adjacent signal lines, thus improving the reliability and stability of the detection device 20. Additionally, adjusting the resistance of the first control signal line Gate1 simultaneously with adjusting the capacitance of the first capacitor C1 allows for coordinated adjustment of both resistance and capacitance. This optimizes the characteristic impedance of the first control signal line Gate1, reduces signal reflection, and further enhances the reliability and stability of the detection device 20.

[0204] Please continue referring to Figures 9 and 12. When the first control signal line Gate1 within the detection device 20 is located between the first active pattern T11 of the first transistor T1 and the fourth active pattern T41 of the fourth transistor T4 within the same detection unit M, the detection unit M may further include a first connection portion 21. Along the first direction X, the first connection portion 21 may be located on the side of the first plate C11 of the first capacitor C1 away from the first gate T12 of the first transistor T1.

[0205] Please refer to Figure 12 and Figure 9. Specifically, the above-mentioned "electrical connection between the fourth active pattern T41 of the fourth transistor T4 and the first plate C11 of the first capacitor C1" can be that the fourth active pattern T41 of the fourth transistor T4 is electrically connected to the first plate C11 of the first capacitor C1 through the first connection part 21.

[0206] Alternatively, referring to Figure 14, if the first control signal line Gate1 within the detection device 20 is located on the side of the first active pattern T11 of the first transistor T1 within the same detection unit M that is far from the fourth active pattern T41 of the fourth transistor T4, the detection unit M may further include a second connection portion 22. The second connection portion 22 may be located on the side of the first gate T12 of the first transistor T1 that is far from the first plate C11 of the first capacitor C1.

[0207] Specifically, the above-mentioned "the fourth active pattern T41 of the fourth transistor T4 and the first gate T12 of the first transistor T1 are electrically connected" can be that the fourth active pattern T41 of the fourth transistor T4 is electrically connected to the first gate T12 of the first transistor T1 through the second connection portion 22.

[0208] For example, referring to Figures 7, 12, and 14, and in conjunction with Figures 3, 4, and 5, in the detection unit M, the first control circuit includes a third transistor T3, and the second control circuit includes a fourth transistor T4. The third transistor T3 includes a third active pattern T31 and a third gate T32, and the fourth transistor T4 includes a fourth active pattern T41 and a fourth gate T42. In this case, the third active pattern T31 of the third transistor T3 can be electrically connected to the bias voltage line BIAS and the fourth active pattern T41 of the fourth transistor T4, respectively. The third gate T32 of the third transistor T3 can be electrically connected to the second control signal line Gate2.

[0209] The fourth active pattern T41 of the fourth transistor T4 can also be electrically connected to the second electrode C22 of the piezoelectric transducer C2.

[0210] The driving method of the above-mentioned detection device 20 will be described in detail below.

[0211] In some embodiments, as shown in FIG15, FIG15 is a driving timing diagram of the detection device 20 shown in FIG7. AP is the signal timing of the constant voltage signal line AP, Gate1 is the signal timing of the first control signal line Gate1, Gate2 is the signal timing of the second control signal line Gate2, Gate3 is the signal timing of the third control signal line Gate3, BIAS is the signal timing of the bias voltage line BIAS, Tx is the signal timing of the transmit signal terminal Tx, N1 is the signal timing of node N1, N3 is the signal timing of node N3, and Read represents the intensity of the driving current input by the first transistor T1 to the signal readout line Read through the constant voltage signal line AP under the action of the signal of the first node N1.

[0212] It should be noted that the signal timing of the constant voltage signal line AP, the first control signal line Gate1, the second control signal line Gate2, the third control signal line Gate3, the bias voltage line BIAS, the signal timing of the transmit signal terminal Tx, the signal timing of node N1, and the signal timing of node N3 in Figure 15 are only illustrated by taking the example that the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 in the detection device 20 are all N-type transistors, to illustrate the driving timing of the detection device 20 shown in Figure 7.

[0213] Please refer to Figure 15 and, in conjunction with Figure 7, the driving method of the detection device 20 may include a reset phase t1, an information acquisition phase t2, and an information reading phase t3.

[0214] During the reset phase t1, the second control signal line Gate2 and the third control signal line Gate3 output high-level signals, and the third transistor T3 and the fourth transistor T4 are in the conducting state. The bias voltage line BIAS writes a reset signal to the first node N1 and the third node N3 to initialize the signals of the first node N1 and the third node N3, thereby clearing the original voltages of the first node N1 and the third node N3.

[0215] During the information acquisition phase t2, the second control signal line Gate2 outputs a low-level signal, the third control signal line Gate3 outputs a high-level signal, the third transistor T3 is in the off state, and the fourth transistor T4 is in the on state. The signals of the first node N1 and the third node N3 are maintained as the bias voltage line BIAS signals of the previous stage under the action of the first capacitor C1.

[0216] A first signal is provided to the transmitting signal terminal Tx. In this stage, the signal of the first electrode C21 of the piezoelectric transducer C2 is the first signal, and the signal of the second electrode C22 of the piezoelectric transducer C2 is a constant voltage signal. Under the piezoelectric effect of the piezoelectric material layer C23 of the piezoelectric transducer C2, the piezoelectric transducer C2 generates an ultrasonic signal and emits it outward. Then, a second signal is provided to the transmitting signal terminal Tx. The second signal is a constant voltage signal. At this time, the signal of the first electrode C21 of the piezoelectric transducer C2 is the second signal, and the piezoelectric material layer C23 of the piezoelectric transducer C2 receives the ultrasonic signal reflected by the fingerprint to be tested. Under the piezoelectric effect of the piezoelectric material layer C23 of the piezoelectric transducer C2, the second electrode C22 of the piezoelectric transducer C2 generates an AC signal. The AC signal generated by the second electrode C22 of the piezoelectric transducer C2 is transmitted to the third node N3. Since the fourth transistor T4 is turned on, the signal of the third node N3 is written into the first node N1, realizing the conversion between the ultrasonic signal and the electrical signal.

[0217] During the information reading phase t3, the constant voltage signal line AP outputs a high-level signal, and the first control signal line Gate1 outputs a high-level signal. Under the action of the signal from the first node N1, the first transistor T1 uses the constant voltage signal line AP to input a drive current to the signal reading line Read.

[0218] Among them, the voltage of the AC signal generated on the second electrode C22 of the piezoelectric transducer C2 by the ultrasonic signal reflected on the fingerprint valley is relatively small, and the current read by the signal reading line Read is also relatively small. The voltage of the AC signal generated on the second electrode C22 of the piezoelectric transducer C2 by the ultrasonic signal reflected on the fingerprint ridge is relatively large, and the current read by the signal reading line Read is also relatively large. This allows the detection device 20 to determine whether the position corresponding to the piezoelectric transducer C2 is a fingerprint ridge or a fingerprint valley based on the magnitude of the current on the signal reading line Read. This enables the multiple detection units M arranged in the array to judge the fingerprint image.

[0219] The first control signal line Gate1, the second control signal line Gate, the third control signal line Gate3, the constant voltage signal line AP, the signal reading line Read, the bias voltage line BIAS, and the detection unit M (e.g., the driving sub-circuit, reading sub-circuit, first control circuit, second control circuit, voltage regulator sub-circuit, and piezoelectric transducer C2 within the detection unit M) can be located within the film structure of the detection device 20. The film structure of the detection device 20 will be described in detail below.

[0220] In some embodiments, please continue to refer to Figures 3, 4 and 5, the detection device 20 may include a substrate 4.

[0221] For example, referring to Figures 3, 4, and 5, substrate 4 can be a rigid substrate. For instance, the material of substrate 4 may include one or more of glass and polymethyl methacrylate (PMMA).

[0222] Alternatively, substrate 4 may be a flexible substrate. For example, the material of substrate 4 may include one or more of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyimide (PI).

[0223] In some embodiments, referring to Figures 3, 4, and 5, the detection device 20 may further include a first active layer 1. The first active layer 1 may be located on one side of the substrate 4.

[0224] For example, please continue to refer to FIG8 and in conjunction with FIG7, when the detection unit M in the detection device 20 includes a driving sub-circuit and the driving sub-circuit includes a first transistor T1, the first active pattern T11 in the first transistor T1 may be located in the first active layer 1.

[0225] For example, please continue to refer to FIG8 and in conjunction with FIG7, when the detection unit M in the detection device 20 includes a readout sub-circuit and the readout sub-circuit includes a second transistor T2, the second active pattern T21 in the second transistor T2 may be located in the first active layer 1.

[0226] For example, please continue to refer to FIG8 and in conjunction with FIG7, when the detection unit M in the detection device 20 includes a first control circuit and the first control circuit includes a third transistor T3, the third active pattern T31 in the third transistor T3 may be located in the first active layer 1.

[0227] For example, please continue to refer to FIG8 and in conjunction with FIG7, when the detection unit M in the detection device 20 includes a second control circuit and the second control circuit includes a fourth transistor T4, the fourth active pattern T41 in the fourth transistor T4 can be located in the first active layer 1.

[0228] For example, please continue to refer to FIG8, the material of the first active layer 1 may include one or more of amorphous silicon (a-Si), low temperature polycrystalline silicon (LTPS), amorphous oxide semiconductor (a-Oxide), and low temperature polycrystalline oxide (LTPO).

[0229] In some embodiments, referring to Figures 3, 4, and 5, the detection device 20 may further include a first conductive layer 2. The first conductive layer 2 may be located on one side of the substrate 4.

[0230] For example, please continue to refer to Figures 3, 4 and 5. When the detection device 20 includes a first active layer 1, the first conductive layer 2 may be located on the side of the first active layer 1 away from the substrate 4.

[0231] For example, referring to FIG9 and in conjunction with FIG7, when the detection device 20 includes a constant voltage signal line AP, the constant voltage signal line AP may be located in the first conductive layer 2.

[0232] For example, referring to FIG9 and in conjunction with FIG7, in the case where the detection device 20 includes a signal readout line Read, the signal readout line Read may be located in the first conductive layer 2.

[0233] For example, please continue to refer to FIG9 and in conjunction with FIG7, in the case where the detection device 20 includes a bias voltage line BIAS and the bias voltage line BIAS includes a first sub-bias voltage line BIAS2, the first sub-bias voltage line BIAS2 may be located in the first conductive layer 2.

[0234] For example, please continue to refer to FIG9 and in conjunction with FIG7, when the detection unit M in the detection device 20 includes a driving sub-circuit and the driving sub-circuit includes a first transistor T1, the first gate T12 in the first transistor T1 may be located in the first conductive layer 2.

[0235] For example, please continue to refer to FIG9 and in conjunction with FIG7, when the detection unit M in the detection device 20 includes a readout sub-circuit and the readout sub-circuit includes a second transistor T2, the second gate T22 in the second transistor T2 may be located in the first conductive layer 2.

[0236] For example, please continue to refer to FIG9 and in conjunction with FIG7, when the detection unit M in the detection device 20 includes a first control circuit and the first control circuit includes a third transistor T3, the third gate T32 in the third transistor T3 may be located in the first conductive layer 2.

[0237] For example, please continue to refer to FIG9 and in conjunction with FIG7, when the detection unit M in the detection device 20 includes a second control circuit and the second control circuit includes a fourth transistor T4, the fourth gate T42 in the fourth transistor T4 may be located in the first conductive layer 2.

[0238] For example, please continue to refer to FIG9 and in conjunction with FIG7, when the detection unit M in the detection device 20 includes a voltage regulator circuit and the voltage regulator circuit includes a first capacitor C1, the first plate C11 of the first capacitor C1 can be located in the first conductive layer 2.

[0239] For example, referring to Figures 9, 12, and 14, when both the first gate T12 in the first transistor T1 and the first plate C11 of the first capacitor C1 are located in the first conductive layer 2, the first conductive layer 2 may further include a first conductive portion 2a. A portion of the first conductive portion 2a may be used to form the first gate T12 in the first transistor T1, and a portion may be used to form the first plate C11 of the first capacitor C1.

[0240] For example, referring to Figures 9 and 12, when the detection unit M includes the first connection portion 21, a portion of the first conductive portion 2a can also be used to form the first connection portion 21.

[0241] For example, referring to FIG14, when the detection unit M includes a second connection portion 22, a portion of the first conductive portion 2a can also be used to form the second connection portion 22.

[0242] For example, referring to Figure 9, the material of the first conductive layer 2 may include one or more of molybdenum (MO), titanium (Ti), aluminum (Al), and copper (Cu).

[0243] In some embodiments, referring to Figures 3, 4, and 5, the detection device 20 may further include a second conductive layer 3. The second conductive layer 3 may be located on one side of the substrate 4.

[0244] For example, please continue to refer to Figures 3, 4 and 5. When the detection device 20 includes a first conductive layer 2, the second conductive layer 3 may be located on the side of the first conductive layer 2 away from the substrate 4.

[0245] For example, please continue to refer to Figures 11, 12, 13 and 14, and in conjunction with Figure 7, in the case where the detection device 20 includes a first control signal line Gate1, the first control signal line Gate1 may be located in the second conductive layer 3.

[0246] For example, please continue to refer to Figures 11, 12, 13 and 14, and in conjunction with Figure 7, in the case where the detection device 20 includes a second control signal line Gate2, the second control signal line Gate2 may be located in the second conductive layer 3.

[0247] For example, please continue to refer to Figures 11, 12, 13 and 14, and in conjunction with Figure 7, in the case where the detection device 20 includes a third control signal line Gate 3, the third control signal line Gate 3 may be located in the second conductive layer 3.

[0248] For example, please continue to refer to Figures 11, 12, 13 and 14, and in conjunction with Figure 7, in the case where the detection device 20 includes a bias voltage line BIAS, and the bias voltage line BIAS includes a second sub-bias voltage line BIAS1, the second sub-bias voltage line BIAS1 may be located in the second conductive layer 3.

[0249] For example, referring to Figures 11 and 13, the material of the second conductive layer 3 may include one or more of molybdenum (MO), titanium (Ti), aluminum (Al), and copper (Cu).

[0250] In some embodiments, as shown in Figures 16, 17, and 18, Figure 16 is a plan view of a detection device 20 within a display panel 100 according to some embodiments, Figure 17 is a plan view of a partial region of a second electrode layer 5 within the detection device 20 according to some embodiments, and Figure 18 is a plan view of a partial region of a first electrode layer 6 within the detection device 20 according to some embodiments. The detection device 20 may further include a first electrode layer 6 and a second electrode layer 5. The first electrode layer 6 may be located on the side of the second electrode layer 5 away from the substrate 4.

[0251] For example, please continue to refer to Figure 17, the second electrode C22 of the piezoelectric transducer C2 can be located in the second electrode layer 5.

[0252] For example, please continue to refer to Figure 18, the first electrode C21 of the piezoelectric transducer C2 can be located in the first electrode layer 6.

[0253] For example, referring to Figures 16, 17 and 18, and in conjunction with Figures 12 and 14, along the third direction Z, the piezoelectric transducer C2 can be located on one side of the first transistor T1 and the first capacitor C1.

[0254] In some embodiments, as shown in FIG19, FIG19 is a plan view of a partial region of the first active layer 1, the first insulating layer 81, and the first conductive layer 2 within a detection device 20 according to some embodiments. When the detection device 20 includes the first active layer 1 and the first conductive layer 2, the detection device 20 may further include the first insulating layer 81. The first insulating layer 81 is located between the first active layer 1 and the first conductive layer 2.

[0255] For example, referring to Figure 19, the material of the first insulating layer 81 may include one or more (two or more) of silicon nitride (Si3N4), silicon oxide (SiO2) and silicon oxynitride (SiON).

[0256] In some embodiments, as shown in FIG20, FIG20 is a plan view of a partial region of a first active layer 1, a first conductive layer 2, a second insulating layer 82, and a second conductive layer 3 within a detection device 20 according to some embodiments. When the detection device 20 includes a first conductive layer 2 and a second conductive layer 3, the detection device 20 may further include a second insulating layer 82. The second insulating layer 82 is located between the first conductive layer 2 and the second conductive layer 3.

[0257] For example, referring to FIG20 and in conjunction with FIG7 and FIG19, when the detection device 20 includes a detection unit M and a constant voltage signal line AP, the detection unit M includes a driving sub-circuit, and the first active pattern T11 of the first transistor T1 in the driving sub-circuit is electrically connected to the constant voltage signal line AP, the detection device 20 may further include a first transition pattern F1. The first transition pattern F1 can be electrically connected to the first active pattern T11 of the first transistor T1 through a first via Q1, and the first transition pattern F1 can be electrically connected to the constant voltage signal line AP through a second via Q2, so that the first active pattern T11 of the first transistor T1 can be electrically connected to the constant voltage signal line AP through the first transition pattern F1.

[0258] For example, referring to Figure 20, when the detection device 20 includes a second conductive layer 3, the first transition pattern F1 can be located on the second conductive layer 3.

[0259] Please continue to refer to Figure 20 and, in conjunction with Figure 19, when the detection device 20 includes a first active layer 1, a first insulating layer 81, a first conductive layer 2, a second insulating layer 82, and a second conductive layer 3 stacked sequentially, and the first active pattern T11 of the first transistor T1 is located in the first active layer 1 and the constant voltage signal line AP is located in the first conductive layer 2, the first via Q1 can penetrate the first insulating layer 81 and the second insulating layer 82, so that the first transition pattern F1 located in the second conductive layer 3 can be electrically connected to the first active pattern T11 of the first transistor T1 located in the first active layer 1 through the first via Q1.

[0260] The second via Q2 can penetrate the second insulating layer 82, so that the first transition pattern F1 located in the second conductive layer 3 can be electrically connected to the constant voltage signal line AP located in the first conductive layer 2 through the second via Q2.

[0261] For example, referring to FIG20 and in conjunction with FIG7 and FIG19, when the detection device 20 includes a detection unit M and a signal readout line Read, the detection unit M includes a readout sub-circuit, and the second active pattern T21 of the second transistor T2 in the readout sub-circuit is electrically connected to the signal readout line Read, the detection device 20 may further include a second transition pattern F2. The second transition pattern F2 can be electrically connected to the second active pattern T21 of the second transistor T2 through a third via Q3, and the second transition pattern F2 can be electrically connected to the signal readout line Read through a fourth via Q4, so that the second active pattern T21 of the second transistor T2 can be electrically connected to the signal readout line Read through the second transition pattern F2.

[0262] For example, referring to Figure 20, when the detection device 20 includes a second conductive layer 3, the second transition pattern F2 can be located on the second conductive layer 3.

[0263] Please continue referring to Figure 20 and, in conjunction with Figure 19, when the detection device 20 includes a first active layer 1, a first insulating layer 81, a first conductive layer 2, a second insulating layer 82, and a second conductive layer 3 stacked sequentially, and the second active pattern T21 of the second transistor T2 is located in the first active layer 1 and the signal readout line Read is located in the first conductive layer 2, the third via Q3 can penetrate the first insulating layer 81 and the second insulating layer 82, so that the second transition pattern F2 located in the second conductive layer 3 can be electrically connected to the second active pattern T21 of the second transistor T2 located in the first active layer 1 through the third via Q3.

[0264] The fourth via Q4 can penetrate the second insulating layer 82 so that the second transition pattern F2 located on the second conductive layer 3 can be electrically connected to the signal read line Read located on the first conductive layer 2 through the fourth via Q4.

[0265] For example, please continue to refer to FIG20, and in conjunction with FIG7 and FIG19, when the detection device 20 includes a detection unit M and a first control signal line Gate1, the detection unit M includes a readout sub-circuit, and the second gate T22 of the second transistor T2 in the readout sub-circuit is electrically connected to the first control signal line Gate1, the second gate T22 of the second transistor T2 can be electrically connected to the first control signal line Gate1 through the fifth via Q5.

[0266] For example, referring to Figure 20, when the detection device 20 includes a first conductive layer 2, a second insulating layer 82, and a second conductive layer 3 stacked sequentially, and the second gate T22 of the second transistor T2 is located in the first conductive layer 2 and the first control signal line Gate1 is located in the second conductive layer 3, the fifth via Q5 can penetrate the second insulating layer 82 so that the second gate T22 of the second transistor T2 located in the first conductive layer 2 can be electrically connected to the first control signal line Gate1 located in the second conductive layer 3 through the fifth via Q5.

[0267] For example, referring to FIG20 and in conjunction with FIG7 and FIG19, when the detection device 20 includes a detection unit M and a bias voltage line BIAS, the detection unit M includes a first control circuit, and the third active pattern T31 of the third transistor T3 in the first control circuit is electrically connected to the bias voltage line BIAS, the detection device 20 may further include a third transition pattern F3. The third transition pattern F3 can be electrically connected to the third active pattern T31 of the third transistor T3 through a sixth via Q6, and the third transition pattern F3 can be electrically connected to the bias voltage line BIAS through a seventh via Q7, so that the third active pattern T31 of the third transistor T3 can be electrically connected to the bias voltage line BIAS through the third transition pattern F3.

[0268] When the bias voltage line BIAS within the detection device 20 includes the first sub-bias voltage line BIAS2, the aforementioned "the third transition pattern F3 is electrically connected to the third active pattern T31 of the third transistor T3 through the sixth via Q6, and the third transition pattern F3 is electrically connected to the bias voltage line BIAS through the seventh via Q7, so that the third active pattern T31 of the third transistor T3 is electrically connected to the bias voltage line BIAS through the third transition pattern F3" can specifically be that the third transition pattern F3 is electrically connected to the third active pattern T31 of the third transistor T3 through the sixth via Q6, and the third transition pattern F3 is electrically connected to the first sub-bias voltage line BIAS2 within the bias voltage line BIAS through the seventh via Q7, so that the third active pattern T31 of the third transistor T3 can be electrically connected to the first sub-bias voltage line BIAS2 within the bias voltage line BIAS through the third transition pattern F3.

[0269] For example, referring to Figure 20, when the detection device 20 includes a second conductive layer 3, the third transition pattern F3 can be located on the second conductive layer 3.

[0270] Please continue referring to Figure 20 and, in conjunction with Figure 19, when the detection device 20 includes a first active layer 1, a first insulating layer 81, a first conductive layer 2, a second insulating layer 82, and a second conductive layer 3 stacked sequentially, and the third active pattern T31 of the third transistor T3 is located in the first active layer 1, and the first sub-bias voltage line BIAS2 within the bias voltage line BIAS is located in the first conductive layer 2, the sixth via Q6 can penetrate the first insulating layer 81 and the second insulating layer 82, so that the third transition pattern F3 located in the second conductive layer 3 can be electrically connected to the third active pattern T31 of the third transistor T3 located in the first active layer 1 through the sixth via Q6.

[0271] The seventh via Q7 can penetrate the second insulating layer 82 so that the third transition pattern F3 located in the second conductive layer 3 can be electrically connected to the first sub-bias voltage line BIAS2 located in the first conductive layer 2 through the seventh via Q7.

[0272] For example, please continue to refer to FIG20, and in conjunction with FIG7 and FIG19, when the detection device 20 includes a detection unit M and a second control signal line Gate2, the detection unit M includes a first control circuit, and the third gate T32 of the third transistor T3 in the first control circuit is electrically connected to the second control signal line Gate2, the third gate T32 of the third transistor T3 can be electrically connected to the second control signal line Gate2 through the eighth via Q8.

[0273] For example, referring to Figure 20, when the detection device 20 includes a first conductive layer 2, a second insulating layer 82, and a second conductive layer 3 stacked sequentially, and the third gate T32 of the third transistor T3 is located in the first conductive layer 2 and the second control signal line Gate2 is located in the second conductive layer 3, the eighth via Q8 can penetrate the second insulating layer 82 so that the third gate T32 of the third transistor T3 located in the first conductive layer 2 can be electrically connected to the second control signal line Gate2 located in the second conductive layer 3 through the eighth via Q8.

[0274] For example, referring to FIG20 and in conjunction with FIG7 and FIG19, when the detection device 20 includes a detection unit M, the detection unit M includes a second control circuit and a voltage regulator sub-circuit, the second control circuit includes a fourth transistor T4, the voltage regulator sub-circuit includes a first capacitor C1, and the first plate C11 of the first capacitor C1 is electrically connected to the fourth active pattern T41 of the fourth transistor T4, the detection device 20 may further include a fourth transition pattern F4. The fourth transition pattern F4 can be electrically connected to the fourth active pattern T41 of the fourth transistor T4 through a ninth via Q9, and the fourth transition pattern F4 can be electrically connected to the first plate C11 of the first capacitor C1 through a tenth via Q10, so that the fourth active pattern T41 of the fourth transistor T4 can be electrically connected to the first plate C11 of the first capacitor C1 through the fourth transition pattern F4.

[0275] For example, referring to Figure 20, when the detection device 20 includes a second conductive layer 3, the fourth transition pattern F4 can be located on the second conductive layer 3.

[0276] Please continue referring to Figure 20 and, in conjunction with Figure 19, when the detection device 20 includes a first active layer 1, a first insulating layer 81, a first conductive layer 2, a second insulating layer 82, and a second conductive layer 3 stacked sequentially, and the fourth active pattern T41 of the fourth transistor T4 is located in the first active layer 1, and the first plate C11 of the first capacitor C1 is located in the first conductive layer 2, the ninth via Q9 can penetrate the first insulating layer 81 and the second insulating layer 82, so that the fourth transition pattern F4 located in the second conductive layer 3 can be electrically connected to the fourth active pattern T41 of the fourth transistor T4 located in the first active layer 1 through the ninth via Q9.

[0277] The tenth via Q10 can penetrate the second insulating layer 82 so that the fourth transition pattern F4 located in the second conductive layer 3 can be electrically connected to the first plate C11 of the first capacitor C1 located in the first conductive layer 2 through the tenth via Q10.

[0278] For example, please continue to refer to FIG20, and in conjunction with FIG7 and FIG19, when the detection device 20 includes a detection unit M and a third control signal line Gate3, the detection unit M includes a second control circuit, and the fourth gate T42 of the fourth transistor T4 in the second control circuit is electrically connected to the third control signal line Gate3, the fourth gate T42 of the fourth transistor T4 can be electrically connected to the third control signal line Gate3 through the eleventh via Q11.

[0279] For example, referring to Figure 20, when the detection device 20 includes a first conductive layer 2, a second insulating layer 82, and a second conductive layer 3 stacked sequentially, and the fourth gate T42 of the fourth transistor T4 is located in the first conductive layer 2 and the third control signal line Gate3 is located in the second conductive layer 3, the eleventh via Q11 can penetrate the second insulating layer 82 so that the fourth gate T42 of the fourth transistor T4 located in the first conductive layer 2 can be electrically connected to the third control signal line Gate3 located in the second conductive layer 3 through the eleventh via Q11.

[0280] For example, please continue to refer to FIG20, and in conjunction with FIG7 and FIG19, when the detection device 20 includes a bias voltage line BIAS, the bias voltage line BIAS includes a first sub-bias voltage line BIAS2 extending along a first direction X and a second sub-bias voltage line BIAS1 extending along a second direction Y, and the first sub-bias voltage line BIAS2 and the second sub-bias voltage line BIAS1 are electrically connected, the first sub-bias voltage line BIAS2 can be electrically connected to the second sub-bias voltage line BIAS1 through the twelfth via Q12.

[0281] For example, referring to Figure 20, in a detection device 20 comprising a first conductive layer 2, a second insulating layer 82, and a second conductive layer 3 stacked sequentially, with the first sub-bias voltage line BIAS2 located on the first conductive layer 2 and the second sub-bias voltage line BIAS1 located on the second conductive layer 3, the twelfth via Q12 can penetrate the second insulating layer 82. This allows the first sub-bias voltage line BIAS2 located on the first conductive layer 2 to be electrically connected to the second sub-bias voltage line BIAS1 located on the second conductive layer 3 via Q12. Consequently, the bias signal can be transmitted through the mesh structure formed by the first sub-bias voltage line BIAS2 extending along the first direction X and the second sub-bias voltage line BIAS1 extending along the second direction Y. This results in higher consistency of the bias signals received by the multiple detection units M within the detection device 20, which is beneficial for improving the detection accuracy of the detection device 20.

[0282] For example, referring to FIG20 and in conjunction with FIG7 and FIG19, when the detection device 20 includes a detection unit M, the detection unit M includes a second control circuit, and the second control circuit includes a fourth transistor T4, the detection device 20 may further include a fifth transition pattern F5. The fifth transition pattern F5 and the fourth active pattern T41 of the fourth transistor T4 are electrically connected.

[0283] For example, referring to Figure 20, when the detection device 20 includes a second conductive layer 3, the fifth transition pattern F5 can be located on the second conductive layer 3.

[0284] Please continue to refer to Figure 20 and, in conjunction with Figure 19, when the detection device 20 includes a first active layer 1, a first insulating layer 81, a first conductive layer 2, a second insulating layer 82, and a second conductive layer 3 stacked sequentially, and the fourth active pattern T41 of the fourth transistor T4 is located in the first active layer 1 and the fifth transition pattern F5 is located in the second conductive layer 3, the fifth transition pattern F5 can be electrically connected to the fourth active pattern T41 of the fourth transistor T4 through the thirteenth via Q13.

[0285] The thirteenth via Q13 can penetrate the first insulating layer 81 and the second insulating layer 82, so that the fifth transition pattern F5 located in the second conductive layer 3 can be electrically connected to the fourth active pattern T41 of the fourth transistor T4 located in the first active layer 1 through the thirteenth via Q13.

[0286] For example, referring to Figure 20, the material of the second insulating layer 82 may include one or more (two or more) of silicon nitride (Si3N4), silicon oxide (SiO2) and silicon oxynitride (SiON).

[0287] In some embodiments, as shown in FIG21 and in conjunction with FIG20, FIG21 is a plan view of a partial region of the second conductive layer 3 and the third insulating layer 83 within the detection device 20 according to some embodiments. When the detection device 20 includes the first conductive layer 2 and the second conductive layer 3, the detection device 20 may further include the third insulating layer 83. The third insulating layer 83 is located on the side of the second conductive layer 3 away from the first conductive layer 2.

[0288] For example, referring to Figure 21, the material of the third insulating layer 83 may include one or more (two or more) of silicon nitride (Si3N4), silicon oxide (SiO2) and silicon oxynitride (SiON).

[0289] In some embodiments, as shown in FIG22 and in conjunction with FIG20, FIG22 is a plan view of a partial region of the second conductive layer 3 and the fourth insulating layer 84 within the detection device 20 according to some embodiments. When the detection device 20 includes the first conductive layer 2 and the second conductive layer 3, the detection device 20 may further include the fourth insulating layer 84. The fourth insulating layer 84 is located on the side of the second conductive layer 3 away from the first conductive layer 2.

[0290] For example, referring to FIG22 and in conjunction with FIG21, when the detection device 20 includes a third insulating layer 83, the fourth insulating layer 84 may be located on the side of the third insulating layer 83 away from the second conductive layer 3. That is, the third insulating layer 83 may be located between the fourth insulating layer 84 and the second conductive layer 3.

[0291] For example, referring to Figure 22, the material of the fourth insulating layer 84 may include one or more (two or more) of polyimide (PI) and epoxy resin.

[0292] In some embodiments, as shown in FIG23 and in conjunction with FIG20, FIG23 is a plan view of a partial region of the second conductive layer 3, the third insulating layer 83, the fourth insulating layer 84, and the third conductive layer 9 within the detection device 20 according to some embodiments. When the detection device 20 includes the first conductive layer 2 and the second conductive layer 3, the detection device 20 may further include the third conductive layer 9. The third conductive layer 9 is located on the side of the second conductive layer 3 away from the first conductive layer 2.

[0293] For example, referring to FIG23 and in conjunction with FIG21, when the detection device 20 includes a third insulating layer 83, the third insulating layer 83 may be located between the third conductive layer 9 and the second conductive layer 3.

[0294] For example, referring to FIG23 and in conjunction with FIG22, when the detection device 20 includes a fourth insulating layer 84, the fourth insulating layer 84 may be located between the third conductive layer 9 and the second conductive layer 3.

[0295] For example, referring to FIG23, in the case where the detection device 20 includes the fifth adapter pattern F5, the detection device 20 may also include a sixth adapter pattern F6. The sixth adapter pattern F6 and the fifth adapter pattern F5 are electrically connected.

[0296] For example, referring to Figure 23, when the detection device 20 includes a third conductive layer 9, the sixth transition pattern F6 can be located on the third conductive layer 9.

[0297] Please refer to Figure 23, and in conjunction with Figures 21 and 22, when the detection device 20 includes a second conductive layer 3, a third insulating layer 83, a fourth insulating layer 84 and a third conductive layer 9 stacked in sequence, and the fifth transition pattern F5 is located in the second conductive layer 3, the sixth transition pattern F6 can be electrically connected to the fifth transition pattern F5 through the fourteenth via Q14.

[0298] Please continue to refer to Figure 23, and in conjunction with Figures 21 and 22. When the detection device 20 includes a third insulating layer 83 and / or a fourth insulating layer 84, and the third insulating layer 83 and / or the fourth insulating layer 84 is located between the third conductive layer 9 and the second conductive layer 3, the fourteenth via Q14 can penetrate the third insulating layer 83 and / or the fourth insulating layer 84, so that the fifth transition pattern F5 located in the second conductive layer 3 can be electrically connected to the sixth transition pattern F6 located in the third conductive layer 9 through the fourteenth via Q14.

[0299] Please continue to refer to Figure 23, and in conjunction with Figure 20, it can be understood that when the fifth transition pattern F5 and the fourth active pattern T41 of the fourth transistor T4 are electrically connected, by making the sixth transition pattern F6 and the fifth transition pattern F5 electrically connected, the sixth transition pattern F6 and the fourth active pattern T41 of the fourth transistor T4 can be electrically connected.

[0300] For example, referring to Figure 23, the material of the third conductive layer 9 may include one or more of molybdenum (MO), titanium (Ti), aluminum (Al), and copper (Cu).

[0301] In some embodiments, as shown in FIG24 and in conjunction with FIG23, FIG24 is a plan view of a partial region of the second conductive layer 3, the third insulating layer 83, the fourth insulating layer 84, the third conductive layer 9, the fifth insulating layer 85, and the second electrode layer 5 within the detection device 20 according to some embodiments. When the detection device 20 includes the second conductive layer 3, the third conductive layer 9, and the second electrode layer 5, the detection device 20 may further include the fifth insulating layer 85. The fifth insulating layer 85 is located on the side of the third conductive layer 9 away from the second conductive layer 3 and is located between the third conductive layer 9 and the second electrode layer 5.

[0302] For example, please continue to refer to FIG24, and in conjunction with FIG7, FIG19, FIG20 and FIG23, when the detection device 20 includes a detection unit M, the detection unit M includes a piezoelectric transducer C2 and a second control circuit, the fourth active pattern T41 of the fourth transistor T4 in the second control circuit is electrically connected to the second electrode C22 of the piezoelectric transducer C2, and the fifth transition pattern F5 in the detection device 20 is electrically connected to the fourth active pattern T41 of the fourth transistor T4, and the sixth transition pattern F6 is electrically connected to the fifth transition pattern F5, the second electrode C22 of the piezoelectric transducer C2 can be electrically connected to the sixth transition pattern F6, so that the second electrode C22 of the piezoelectric transducer C2 and the fourth active pattern T41 of the fourth transistor T4 can be electrically connected through the sixth transition pattern F6 and the fifth transition pattern F5.

[0303] For example, referring to Figure 24, when the detection device 20 includes a third conductive layer 9, a fifth insulating layer 85 and a second electrode layer 5 stacked in sequence, and the second electrode C22 of the piezoelectric transducer C2 is located on the second electrode layer 5 and the sixth transition pattern F6 is located on the third conductive layer 9, the second electrode C22 of the piezoelectric transducer C2 can be electrically connected through the fifteenth via Q15 and the sixth transition pattern F6.

[0304] The fifteenth via Q15 can penetrate the fifth insulating layer 85 so that the second electrode C22 of the piezoelectric transducer C2 located in the second electrode layer 5 can be electrically connected to the sixth transition pattern F6 located in the third conductive layer 9 through the fifteenth via Q15.

[0305] For example, referring to Figure 24, the material of the fifth insulating layer 85 may include one or more (two or more) of polyimide (PI) and epoxy resin.

[0306] In some embodiments, as shown in FIG25, FIG25 is a plan view of a partial region of the second electrode layer 5, the piezoelectric material layer C23, and the first electrode layer 6 within the detection device 20 according to some embodiments. The detection unit M within the detection device 20 includes a piezoelectric transducer C2, which includes a first electrode C21 and a second electrode C22, and a piezoelectric material layer C23 located between the first electrode C21 and the second electrode C22. When the second electrode C22 of the piezoelectric transducer C2 is located in the second electrode layer 5 and the first electrode C21 of the piezoelectric transducer C2 is located in the first electrode layer 6, the piezoelectric material layer C23 of the piezoelectric transducer C2 may be located between the second electrode layer 5 and the first electrode layer 6.

[0307] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A detection device, comprising: Multiple detection units arranged in an array; The first control signal line is electrically connected to the detection unit; The first control signal line extends along a second direction, which is the column direction in which the plurality of detection unit arrays are arranged; The detection unit includes: The first transistor includes a first active pattern and a first gate; the first active pattern and the first gate are disposed overlapping in a third direction, wherein the third direction is the thickness direction of the detection device; The first capacitor includes a first plate and a second plate; the first plate and the first gate are electrically connected. A portion of the first control signal line and the first electrode plate are arranged to overlap in the third direction, and the portion of the first control signal line that overlaps with the first electrode plate is used to form the second electrode plate.

2. The detection device according to claim 1, wherein, The detection unit further includes a fourth transistor; the fourth transistor is located on one side of the first transistor along a first direction, the first direction being the row direction in which the array of multiple detection units is arranged. The fourth transistor includes a fourth active pattern and a fourth gate, the fourth active pattern and the fourth gate being disposed overlapping in the third direction; the fourth active pattern and the first gate are electrically connected; The first control signal line is located between the first active pattern and the fourth active pattern.

3. The detection device of claim 2, wherein, The detection unit further includes a first connecting portion; along the first direction, the first connecting portion is located on the side of the first electrode plate away from the first gate. The fourth active pattern is electrically connected to the first electrode plate through the first connecting part.

4. The detection device of claim 1, wherein, The detection unit further includes a fourth transistor; the fourth transistor is located on one side of the first transistor along a first direction, the first direction being the row direction in which the array of multiple detection units is arranged. The fourth transistor includes a fourth active pattern and a fourth gate, the fourth active pattern and the fourth gate being disposed overlapping in the third direction; the fourth active pattern and the first gate are electrically connected; The first control signal line is located on the side of the first active pattern that is away from the fourth active pattern.

5. The detection device of claim 4, wherein, The detection unit further includes a second connection portion, which is located on the side of the first gate away from the first electrode plate; The fourth active pattern is electrically connected to the first gate through the second connection portion.

6. The detection device according to any one of claims 1 to 5, wherein, The detection device further includes multiple detection unit groups, each of the detection unit groups including two detection units located in adjacent columns in the same row, and the two detection units in the same detection unit group are symmetrically arranged with respect to the virtual line extending along the second direction.

7. The detection device of claim 6, wherein, The detection device further includes a second control signal line; the second control signal line is electrically connected to at least one column of the detection units, and the second control signal line extends along the second direction; The second control signal line is located between two detection units within the same detection unit group.

8. The detection device of claim 7, wherein, Two second control signal lines are provided between two detection units within the same detection unit group, and the two detection units are respectively electrically connected to the two second control signal lines.

9. The detection device of claim 7, wherein, A second control signal line is provided between two detection units within the same detection unit group, and both detection units are electrically connected to the second control signal line.

10. The detection device of claim 7, wherein, The detection unit further includes a third transistor; the third transistor includes a third active pattern and a third gate, the third active pattern and the third gate being disposed overlapping in the third direction; The third gate and the second control signal line are electrically connected.

11. The detection device of claim 8, wherein, The detection device further includes a third control signal line; the third control signal line extends along the second direction; A third control signal line is provided between two detection units within the same detection unit group, and both detection units are electrically connected to the third control signal line. The third control signal line is located between two adjacent second control signal lines.

12. The detection device of claim 9, wherein, The detection device further includes a third control signal line; the third control signal line extends along the second direction; Two third control signal lines are provided between two detection units within the same detection unit group, and the two detection units are respectively electrically connected to the two third control signal lines. The second control signal line is located between two adjacent third control signal lines.

13. The detection device according to claim 11 or 12, wherein, The detection unit further includes a fourth transistor; the fourth transistor is located on one side of the first transistor along a first direction, the first direction being the row direction in which the array of multiple detection units is arranged. The fourth transistor includes a fourth active pattern and a fourth gate, which are arranged to overlap in the third direction; the fourth gate is electrically connected to the third control signal line.

14. The detection device according to any one of claims 1 to 13, wherein, The detection unit also includes a piezoelectric transducer; Along the third direction, the piezoelectric transducer is located on one side of the first transistor and the first capacitor.

15. The detection device according to any one of claims 1 to 14, wherein, The detection device also includes: Substrate; A first conductive layer is located on one side of the substrate; the first conductive layer includes a first conductive portion, a portion of which is used to form the first gate and a portion of which is used to form the first electrode plate; A second conductive layer is located on the side of the first conductive layer away from the substrate; the second conductive layer includes the first control signal line.

16. The detection device of claim 15, wherein, A portion of the first conductive portion is also used to form a first connection portion, the first connection portion being located on the side of the first electrode plate away from the first gate; or, A portion of the first conductive portion is also used to form a second connection portion, the second connection portion being located on the side of the first gate away from the first electrode plate.

17. The detection device according to claim 15 or 16, wherein, The second conductive layer further includes a second control signal line; and / or, The second conductive layer also includes a third control signal line.

18. A display panel, comprising: Display substrate; The detection device as described in any one of claims 1-17 is located on the non-display side of the display substrate.

19. The display panel of claim 18, wherein, The display panel also includes a color filter located on the side of the display substrate away from the detection device.

20. A display device, comprising: The display panel as described in claim 18 or 19; The driver chip is electrically connected to the display panel.

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