Encoding or decoding method and communication apparatus

Abstract

The present application provides a channel encoding or decoding method and a communication apparatus, which enable generation of a new inserted row based on an adjacent row of a base matrix in NR, or generation of a new inserted row based on a certain row in the base matrix in NR, thereby lifting the base matrix in NR. The lifted base matrix can be flexibly adjusted according to an application scenario, thereby being applicable to different application scenarios and being capable of supporting scenarios with lower code rate requirements. In addition, because this prevents decoding stalls caused by non-orthogonal rows in a base matrix in NR, decoding latency is also reduced. At the same time, this also maintains a favorable decoding structure and decoding threshold of the base matrix, and supports lower-complexity decoding and HARQ retransmission.

Description

Encoding or decoding methods and communication devices

[0001] This application claims priority to Chinese patent application filed on December 27, 2024, with application number 202411984986.0 and entitled "Method for Encoding or Decoding and Communication Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of channel coding, and more specifically, to a method for channel coding or decoding and a communication apparatus. Background Technology

[0003] Low-density parity-check (LDPC) codes are channel coding schemes that closely approximate the Shannon limit, offering advantages such as high performance and low complexity. Mainstream LDPC applications employ a quasi-cyclic (QC) structure. In new radio (NR) systems, LDPC base graphs (BGs) include BG1 and BG2, both sharing a common matrix structure. The base graph can also be written in matrix form, called the base matrix. Based on the base matrix and its boost value, the base matrix can be extended into a complete parity-check matrix for encoding or decoding.

[0004] The lowest bit rate currently supported by NR LDPC is 1 / 5, which cannot meet the communication needs in scenarios with lower bit rates. Summary of the Invention

[0005] This application provides an encoding or decoding method and a communication device that can support communication needs in scenarios with lower bit rates. Furthermore, it can reduce decoding latency.

[0006] Firstly, an encoding method is provided, which can be executed by a communication device or a module applied to the communication device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the communication device). The communication device is also referred to as an encoding device. The method includes: obtaining a first base matrix, the first base matrix including one or more newly added rows, wherein the values ​​of elements in the first newly added row of the one or more newly added rows are determined based on the values ​​of elements in the first row and / or the second row of the first base matrix, the first row being the row preceding the first newly added row, and the second row being the row following the first newly added row; or, the values ​​of elements in the first newly added row of the one or more newly added rows are determined based on the values ​​of elements in the y-th row of the first base matrix, the y-th row being any row in the first base matrix other than the one or more newly added rows, where y is a non-negative integer; determining a first matrix based on the first base matrix and the translation values ​​corresponding to the elements in the first base matrix; encoding based on the first matrix to obtain an encoded bit sequence; and outputting the encoded bit sequence.

[0007] In the technical solution of this application, the first basis matrix can be obtained by extending BG1 or BG2 of NR. The newly inserted rows make the basis matrix, which originally did not have the property of adjacent rows being orthogonal, have the property of adjacent rows being orthogonal after expansion. While maintaining the good matrix structure and decoding threshold of the original basis matrix, it can support a lower code rate. In addition, it can improve the decoding wait problem caused by the non-orthogonal rows of the original basis matrix, thereby reducing decoding latency.

[0008] Secondly, a decoding method is provided, which can be executed by a communication device or a module applied to the communication device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the communication device). The communication device is also called a decoding device. The method includes: obtaining a first base matrix, the first base matrix including one or more newly added rows, wherein the values ​​of the elements in the first newly added row of the one or more newly added rows are determined based on the values ​​of the elements in the first row and / or the second row of the first base matrix, the first row being the row preceding the first newly added row, and the second row being the row following the first newly added row; or, the values ​​of the elements in the first newly added row of the one or more newly added rows are determined based on the values ​​of the elements in the y-th row of the first base matrix, the y-th row being any row in the first base matrix other than the one or more newly added rows, where y is a non-negative integer; determining a first matrix based on the first base matrix and the translation values ​​corresponding to the elements in the first base matrix; decoding a received value sequence based on the first matrix to obtain a decoded bit sequence; and outputting the decoded bit sequence.

[0009] The second aspect is the decoding method corresponding to the encoding method in the first aspect. The technical effects can be found in the explanation of the first aspect.

[0010] In some implementations of the first or second aspect, the first basis matrix is ​​obtained based on an extension of a second basis matrix, which includes a base map BG1 or BG2 in the new wireless NR.

[0011] In this implementation, by extending the original base matrix, the base matrix can be flexibly adjusted for different application scenarios. This allows for adaptation to more application scenarios, such as those with low bitrate requirements, while maintaining the original base matrix's matrix structure and hardware implementation. Furthermore, extending the original base matrix not only improves its performance but also allows for the continued use of its recording method, resulting in minimal hardware modifications and low hardware implementation complexity.

[0012] In some implementations of the first or second aspect, the row index of the first newly added row is i, the position (i,j) of the j-th column of the first newly added row is 0, and the element at the j-th column of at least one of the first and second rows is 1, where j is a non-negative integer.

[0013] In some implementations of the first or second aspect, the first newly added row includes position (i, q), wherein: the element at position (i, q) is 1, the element at position (i-1, q-1) is 1 and / or the element at position (i-1, q+1) is 1; or, the element at position (i, q) is 1, the element at position (i+1, q-1) is 1 and / or the element at position (i+1, q+1) is 1; q and j are not equal.

[0014] In the above implementation, the original base matrix is ​​expanded by generating new rows based on adjacent rows, which can support a lower code rate while maintaining a good matrix structure and decoding threshold.

[0015] In some implementations of the first or second aspect, the number of elements with a value of 1 in the first newly added row, except for the position (i,j), is determined based on the number of non-zero elements in the first or second row.

[0016] In some implementations of the first or second aspect, the positions in the first newly added row, excluding the position (i,j), include position (i,r), where r is a non-negative integer. Whether the element at position (i,r) is 1 is determined based on the column weight of the r-th column of the first base matrix corresponding to position (i,r) and the first column weight. The first column weight is the column weight of the r-th column of the second base matrix at the first code rate. The first code rate is the target code rate, which is one of the code rates supported by the first base matrix. The second base matrix is ​​NR BG2.

[0017] In some implementations of the first or second aspect, the first base matrix includes p punched columns, and the value of the element of the first newly added row at the position of the first punched column in the p punched columns is determined according to any one of the following: the row index of the first newly added row in the first base matrix; the value of the element of the first row and the second row at the position of the first punched column.

[0018] In some implementations of the first or second aspect, the first new row is the nth row in ascending order of row index among the one or more new rows, the element at the nth (mod p) column of the first new row is 1, and the elements at the other punched columns of the first new row are 0, where n is an integer.

[0019] In some implementations of the first or second aspect, the y-th row of the first basis matrix corresponds to the h-th row of the second basis matrix, the positions of non-zero elements in the h-th row of the second basis matrix correspond to a first position set, the positions of non-zero elements in the first newly added row correspond to a second position set, and the second position set is a subset of the first position set, or the first position set is a subset of the second position set.

[0020] This implementation can simultaneously support either a subset of the non-zero element column indices of the rows in the original base matrix, or a subset of the non-zero element column indices of the rows in the original base matrix, thereby improving the performance of low-complexity decoding. For example, by selecting a subset of rows from the original base matrix to generate new rows, the positions and number of non-zero elements in the new rows can be determined based on the region of the selected rows in the original base matrix, which can more broadly support low-complexity decoding and hybrid automatic repeat request (HARQ).

[0021] In some implementations of the first or second aspect, the second set of positions is a subset of the first set of positions, the number of non-zero elements in the h-th row of the second base matrix is ​​x, and the number of non-zero elements in the first newly added row is a, where a is less than x. The a non-zero elements are distributed in the first newly added row in one of the following ways: a positions in ascending order of column index; or a positions in descending order of column index; or a positions in ascending (or descending) order of column index with adjacent index differences greater than 1.

[0022] In some implementations of the first or second aspect, the h-th row of the second base matrix corresponds to a row in the row region corresponding to the information column region of the BG1 or BG2 of the NR.

[0023] In this implementation, the new row in the first basis matrix is ​​generated based on a row in the original basis matrix (i.e., the second basis matrix). If the selected row from the original basis matrix is ​​a row in the row region corresponding to the A region of NR BG1 or BG2, then the position of the non-zero element in the new row in the first basis matrix is ​​a subset of the positions of all non-zero elements in the selected row of the original basis matrix.

[0024] In some implementations of the first or second aspect, the first set of positions is a subset of the second set of positions, the number of non-zero elements in the h-th row of the second base matrix is ​​x, the number of non-zero elements in the first newly added row is b, b is greater than x, the positions of the b non-zero elements in the first newly added row include at least the positions of all non-zero elements in the h-th row of the second base matrix, and the first newly added row is not adjacent to the y-th row of the first base matrix.

[0025] In some implementations of the first or second aspect, the h-th row of the second base matrix corresponds to a row in the row region corresponding to the incremental redundancy region of BG1 or BG2 of the NR.

[0026] In this implementation, the new row in the first basis matrix is ​​generated based on a row in the original basis matrix (i.e., the second basis matrix). If the selected row from the original basis matrix is ​​a row in the row region corresponding to the D region or E region of NR BG1 or BG2, then the positions of the non-zero elements in the new row in the first basis matrix include at least the positions of all the non-zero elements in the selected row of the original basis matrix.

[0027] In some implementations of the first or second aspect, the first newly added row includes a first position, and the translation value corresponding to the first position is related to one or more of the translation value of the nearest non-zero element to the first position, a preset constant, the row index corresponding to the first position, or the column index corresponding to the first position.

[0028] In some implementations of the first or second aspect, the translation value corresponding to the first position is determined based on the following: SV i,e =k+w i,e , or SV i,e =mod(k+w) i,e Z C ), where k is the translation value of the non-zero element in the first base matrix that is closest to the first position, and w i,e The preset constant, or w i,e It is a constant related to the row index i and / or column index e of the first position (i,e), where e is any one of the column indices corresponding to the first base matrix.

[0029] In some implementations of the first or second aspect, the first newly added row includes a first position, the first position corresponds to the e-th column, and the translation value corresponding to the first position is related to one or more of the translation value of the h-th row of the second basis matrix corresponding to the e-th column, a preset constant, the row index corresponding to the first position, or the column index corresponding to the first position.

[0030] In some implementations of the first or second aspect, the translation value corresponding to the first position is determined based on the following: SV i,e =k i′ +w i,e Where i′ is the row index of the h-th row of the second basis matrix, the first position corresponds to the e-th column, and k i′ w is the translation value corresponding to the position in the h-th row and e-th column of the second basis matrix. i,e The preset constant, or w i,e It is a constant related to the row index i and / or column index e of the first position (i,e), where e is any one of the column indices corresponding to the first base matrix.

[0031] Among the above implementation methods, several different ways to obtain the translation value corresponding to the non-zero position in the newly added row are given.

[0032] In some implementations of the first or second aspect, the translation values ​​corresponding to the non-zero elements in the first newly added row are read from a translation value list, which includes translation values ​​corresponding to the non-zero positions in BG1 or BG2 in the NR, and translation values ​​corresponding to the non-zero positions in each of the one or more newly added rows.

[0033] In this implementation, the method of obtaining translation values ​​is compatible with the NR standard. The translation values ​​corresponding to the non-zero positions in the newly added row are recorded together with the translation values ​​corresponding to the non-zero positions in the original base matrix in the translation value list of the new design.

[0034] The above implementation methods provide ways to obtain the translation values ​​corresponding to the non-zero positions of newly added rows in the base matrix. While realizing the adjustment of newly added rows, they are compatible with the matrix generation methods in the standard.

[0035] Thirdly, a communication device is provided, which has the function of implementing the method in the first aspect or any possible implementation of the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0036] Fourthly, a communication device is provided, which has the function of implementing the method in the second aspect or any possible implementation of the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0037] Fifthly, a communication device is provided, comprising at least one processor configured to cause the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor is coupled to at least one memory for storing computer programs or instructions, and the at least one processor is configured to call and run the computer program or instructions from the at least one memory, causing the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor may be included in the communication device or may be configured outside the communication device. Optionally, the communication device further includes the at least one memory. Optionally, the communication device further includes at least one communication interface. As an example, the communication interface may include an input interface and / or an output interface, or may be an interface circuit.

[0038] Sixthly, a communication device is provided, comprising a communication interface and a circuit. The communication interface is configured to receive a signal to be processed and transmit the signal to the circuit. The circuit is configured to process the signal to perform a method as described in the first aspect or any possible implementation thereof; or to perform a method as described in the second aspect or any possible implementation thereof. Optionally, the communication interface is further configured to output a signal processed by the circuit. Optionally, the signal may include information and / or data. Optionally, the communication device may be a chip (e.g., a baseband chip) or a chip system.

[0039] A seventh aspect provides a computer-readable storage medium storing computer program code or instructions that, when executed on a computer, cause the method of the first aspect or any possible implementation thereof to be implemented; or, the method of the second aspect or any possible implementation thereof to be implemented.

[0040] Eighthly, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented; or, as in the second aspect or any possible implementation thereof, the method to be implemented.

[0041] A ninth aspect provides a wireless communication system, including a communication device as described in the third aspect and a communication device as described in the fourth aspect. Attached Figure Description

[0042] Figure 1 is a schematic diagram of the basis matrix structure of NR LDPC.

[0043] Figure 2 is a schematic diagram of the incremental redundancy region of the basis matrix of LDPC.

[0044] Figure 3 shows an example of a communication system applicable to the technical solution of this application.

[0045] Figure 4 is a schematic diagram of the basic process of wireless communication.

[0046] Figure 5 is a schematic flowchart of the channel coding or decoding method 200 provided in this application.

[0047] Figure 6 shows a local example of the first basis matrix obtained based on the NR BG2 extension.

[0048] Figure 7 is a simulation diagram comparing the thresholds of NR's BG2 and the extended BG2 provided in this application.

[0049] Figure 8 shows a local example of the first basis matrix obtained based on the NR BG2 extension.

[0050] Figure 9 is a schematic diagram of the encoding chain flow or decoding chain flow based on the technical solution of this application.

[0051] Figure 10 is a schematic structural diagram of the communication device 1000 provided in this application.

[0052] Figure 11 is a schematic structural diagram of another communication device provided in this application.

[0053] Figure 12 is a schematic structural diagram of the chip provided in this application. Detailed Implementation

[0054] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0055] First, the relevant technologies involved in the embodiments of this application will be introduced.

[0056] In practice, quasi-cyclic LDPC (QC-LDPC) is represented using a base graph (BG), also known as a basis matrix, where elements are either 1 or 0. The 1s in the base matrix are expanded to form a cyclic displacement matrix, and the 0s are expanded to form a zero matrix of the corresponding size. This expansion yields the check matrix. The model of the QC-LDPC base graph is BG = (X, Y, F), where X corresponds to the variables, Y corresponds to the check equation, and F represents the edge relationships. The expansion factor is Z. c After QC expansion, we obtain the Tanner graph, which is a bipartite graph G = (V, C, E), where V is the variable node, C is the check node, and E is its edge relationship, corresponding to the number of columns in the check matrix N = |V| = Z. c |X|, the number of rows in the parity check matrix M = |C| = Z c The number of non-zero elements in the parity-check matrix is ​​|E| = Z|F|. The basis matrix can also be represented as H. BG Based on the basis matrix H BG and the increase value Z c (lifting size) can be used to transform the basis matrix H BG Expanded into a complete parity-check matrix for encoding or decoding. Z c It can also be called the expansion factor, lifting factor, expansion value, expansion coefficient, or lifting size, etc. The lifting process involves adjusting the basis matrix H... BG The element in the middle is promoted to a Z. c ×Z c A square matrix. The 0s in the basis matrix are promoted to Z. c ×Z c The 0-matrix and 1-matrix are promoted to an identity matrix by a circular shift (to the right) P. i,j The matrix P i,j Let be the shifting value (SV) corresponding to the i-th row and j-th column of the base matrix. Circular shift refers to the following form:

[0057] Taking a 4x4 identity matrix as an example, the results after cyclically shifting it by 0, 1, and 3 times are shown below:

[0058] If the circular shift is zero times, the resulting matrix is:

[0059] If the cyclic shift is performed once, the resulting matrix is:

[0060] If the cyclic shift is performed 3 times, the resulting matrix is:

[0061] In new radio (NR), the standard-described LDPC parity check matrix has two corresponding BGs: BG1 and BG2. BG1 and BG2 share a common matrix structure, as shown in Figure 1.

[0062] Figure 1 shows a schematic diagram of the base matrix structure of NR LDPC. As shown in Figure 1, the base matrix includes regions A to E. Region A corresponds to the high-bitrate information column region; region B corresponds to the high-bitrate core check region; region C corresponds to the 0 matrix, which is an all-zero region; region D is the incremental redundancy region of the matrix, corresponding to the low-bitrate matrix; and region E is a raptor-like region, which is an identity matrix structure. As mentioned above, the elements in the base matrix are either 1 or 0. A 0 element indicates an empty element, and a 1 element indicates an edge in the base graph, or an association between the corresponding check and the corresponding variable. Furthermore, the entire matrix shown in Figure 1 is designed for the lowest bitrate. When different bitrates need to be supported, the upper left portion of the matrix is ​​used, as shown in Figure 2.

[0063] Figure 2 shows a schematic diagram of the LDPC base matrix. As shown in Figure 2, region E of the base matrix adopts a Raptor-like structure, which can be gradually extended to low bitrates through a high-bitrate core matrix. Regions A and B constitute the highest bitrate matrix. Region A of BG1 has 22 columns, region B has 4 columns, and 2 punched columns, supporting a bitrate of 22 / (22+4-2)=11 / 12≈0.917. Additional punched parity bits support bitrates slightly higher than this. When a lower bitrate is needed, a row and a column are added as the matrix region to be used, up to the lowest bitrate. The different dashed boxes in Figure 2 represent matrix regions truncated based on different bitrates.

[0064] Basis matrix H BG The expansion is based on a list of lifting sizes and a list of shifting values ​​that correspond one-to-one with the rows of lifting sizes.

[0065] Table 1 is an example of a list of lift dimensions (denoted as Z) for LDPC.

[0066] Table 1: sets of LDPC lifting size Z

[0067] As shown in Table 1, the j-th row of the lifting size list Where a j ∈{2,3,5,7,9,11,13,15}, max(k j The lift size is ∈ {7,7,6,5,5,5,4,4}; the row index of the lift size corresponds one-to-one with the column index of the shift value, that is, the lift size in each row of the lifting size list corresponds to a set of shift values. During rate matching, the lift size is determined first, and then the corresponding shift values ​​are selected to construct the check matrix.

[0068] Table 2 is a schematic diagram of the list of edge connections and translation values ​​for the BG1 section in NR. As shown in Table 2, after selecting a lift value from the lift value list shown in Table 1, the index i corresponding to that lift value can be determined. LS According to index i LS This allows us to determine the translation values ​​corresponding to non-zero elements at different positions in the basis matrix. Taking Table 1 as an example, if the lift value is 96, the corresponding i... LS =1, based on i LS By querying the BG1 partial edge list in Table 2, we can determine that the element in row 0, column 0 of the base matrix corresponds to a translation value of 307; the element in row 0, column 1 corresponds to a translation value of 19; the element in row 0, column 2 corresponds to a translation value of 50, and so on. Table 2 only shows the translation values ​​corresponding to some non-zero elements in row 0 of BG1 as examples.

[0069] Table 2

[0070] A parity-check matrix (PCM) is typically represented by H. The PCM H can be represented by a Tanner graph, with a one-to-one correspondence between the Tanner graph and the PCM H. The Tanner graph consists of two types of vertices: one type represents codeword bits, called variable nodes, each corresponding to a column in the PCM H; the other type consists of check nodes, representing check constraints, each corresponding to a row in the PCM H. For a PCM H of size m rows and n columns, the Tanner graph contains n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the PCM H, and the m check nodes correspond to the m rows of the PCM H. The connections between the two types of nodes correspond to the values ​​of elements in the PCM H. If there is a connection between the i-th check node and the j-th variable node, the element (i, j) in the PCM H has a value of 1; otherwise, the corresponding element is 0. The connection between variable nodes and check nodes is also called an edge. The existence of a connection between the validation node and the variable node can also be described as: the validation node and the variable node are connected or have an edge. The connection between the validation node and the variable node can include either the presence of an edge or the absence of an edge.

[0071] As mentioned in the background section, current LDPC base matrix applications suffer from decoding latency and cannot support application scenarios requiring lower code rates. Therefore, this application provides an encoding or decoding scheme that can reduce decoding latency and, moreover, support application scenarios requiring lower code rates.

[0072] The technical solutions of this application can be applied to various existing and future communication systems, including but not limited to: satellite communication systems, fifth-generation (5G) systems or new radio (NR) systems, long-term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, and future communication systems. Furthermore, they can also be applied to sidelink (SL) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems, or other communication systems, etc., which are not limited herein.

[0073] Figure 3 illustrates an example of a communication system applicable to the technical solution of this application. As shown in Figure 3, the communication system may include one or more transmitters and one or more receivers. Optionally, one of the transmitters and receivers may be a terminal device, and the other may be a network device. The channel coding or decoding method provided in this application is applicable to communication between the network device and the terminal device shown in Figure 3, i.e., uplink communication or downlink communication. For example, in downlink communication, the transmitter in this embodiment is a network device, and the receiver is a terminal device; in uplink communication, the transmitter is a terminal device, and the receiver is a network device.

[0074] For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. In the embodiments of this application, the terminal device may be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as a handheld device with wireless connectivity, in-vehicle equipment, etc. The terminal device in the embodiments of this application may be a mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. Optionally, the UE may be used as a base station. For example, the UE may act as a scheduling entity, providing sidelink signals between UEs in V2X or SL, etc.

[0075] In this embodiment, the device used to implement the functions of the terminal device can be the terminal device itself, or any device capable of supporting the terminal device in implementing the corresponding functions, such as a chip, processor, circuit, hardware, and / or software combination. This device is located on the terminal side and can be configured within or used in conjunction with the terminal device. The chip system can consist of chips or include chips and other discrete components. In this embodiment, the terminal device is used as an example to illustrate the device for implementing the corresponding functions of the terminal device.

[0076] The network device in this application embodiment may include a device for communicating with a terminal device. This network device may include an access network device or a radio access network device; for example, the network device may be a base station. In this application embodiment, the access network device may refer to a radio access network (RAN) node (or device) that connects the terminal device to the wireless network. A base station can broadly encompass, or be replaced by, various names such as: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, a device performing base station functions in D2D, V2X, and M2M communications, a network device (e.g., a base station) in a future communication network, or a device performing network device functions. A base station can support networks using the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0077] Base stations can be fixed or mobile. For example, a helicopter or drone can be configured to act as a mobile base station, and one or more cells can move depending on the location of the mobile base station. In other examples, a helicopter or drone can be configured as a device to communicate with another base station.

[0078] In some deployments, the network device in this application embodiment may be a device including a CU, or a DU, or a device including both CU and DU, or a control plane CU node (central unit-control plane (CU-CP)) and a user plane CU node (central unit-user plane (CU-UP)) and a DU node. For example, the network device may include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0079] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0080] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open radio access network (ORAN / O-RAN) system, CU can also be called an open CU (open CU, O-CU), and DU can also be called an open DU (open DU, O-DU). CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0081] In this embodiment, the device used to implement the functions of the network device can be the network device itself; it can also be a device capable of supporting the network device in implementing the corresponding functions, such as a chip, processor, circuit, hardware, and / or software combination. This device is located on the network side and can be configured within or used in conjunction with the network device. In this embodiment, only the network device is used as an example to illustrate the implementation of the corresponding functions of the network device.

[0082] Figure 4 illustrates the basic process of wireless communication. As shown in Figure 4, at the signal transmitting end, the signal source sequentially undergoes source coding, channel coding, and modulation before being transmitted. At the signal receiving end, the received signal undergoes demodulation, channel decoding, and source recovery before outputting the destination signal. Among these processes, channel coding and decoding are one of the core technologies in the field of wireless communication.

[0083] The channel coding or decoding methods provided in this application can be used in dedicated network devices or general-purpose devices, and can be applied to the various network devices (e.g., base stations) and the various terminal devices mentioned above. Specifically, the channel coding scheme is mainly implemented by the channel coding unit (e.g., encoder or device that supports the coding device to perform the corresponding function) in these devices; the channel decoding scheme is mainly implemented by the channel decoding unit (e.g., decoder or device that supports the decoding device to perform the corresponding function) in these devices.

[0084] Optionally, the functions of the encoding or decoding device can be implemented by application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or by software (e.g., computer program code or instructions in memory), or by a combination of both, without limitation.

[0085] The lowest bitrate currently supported by NR LDPC is 1 / 5, which cannot meet the communication requirements in extremely low bitrate scenarios. In addition, some elements in adjacent rows of NR's BG2 overlap, causing rows to wait during iterative decoding, increasing decoding latency.

[0086] This application addresses the issues of decoding delay and lack of support for lower code rates in the current NR basis matrix. While facilitating hardware implementation and maintaining the main structure of the NR basis matrix (e.g., NR BG1 or BG2), the basis matrix of LDPC is extended.

[0087] The channel coding or channel decoding methods provided in this application are described in detail below.

[0088] Technical terms such as code length, information length, and code rate are used in the embodiments of this application and will be explained uniformly here.

[0089] 1) Information length: This can refer to the number of information bits to be sent, which may or may not include parity bits;

[0090] 2) Code length: refers to the length of the transmitted bits, which can be the number of transmitted bits corresponding to the modulated symbol;

[0091] 3) Code rate: This can refer to the ratio of the number of information bits to the number of transmitted bits.

[0092] The values ​​of the above three parameters can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained or calculated by the transceiver. As a more specific example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bits; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS) table.

[0093] The technical solution of this application can be applicable to a specific scenario, such as enhanced mobile broadband plus (eMBB+) scenario, high throughput scenario or satellite communication, etc., or it can be applicable to multiple communication scenarios defined by the protocol, such as ultra-reliable and low-latency communication (URLLC) scenario, massive machine type communication (mMTC) scenario, etc.

[0094] Figure 5 is a schematic flowchart of the channel coding or decoding method 200 provided in this application. Method 200 relates to an encoding method, which can be implemented by a transmitting-side device (also called an encoding-side device) performing steps 210-240. The transmitting-side device can be a transmitting device or an apparatus applied to a transmitting device (e.g., a chip, processor, or circuit), and is not limited thereto. Optionally, method 200 also relates to a decoding method, which can be implemented by a receiving-side device (also called a decoding-side device) performing steps 250-280. The decoding-side device can be a decoding device or an apparatus applied to a decoding device (e.g., a chip, processor, or circuit).

[0095] 210. The transmitting device obtains the first base matrix.

[0096] The first base matrix includes one or more newly added rows, and the values ​​of the elements in these rows can be determined in the following two ways.

[0097] In this embodiment, the first basis matrix can be obtained by extending the second basis matrix. For example, the second basis matrix can be BG1 or BG2 in NR. In this implementation, the aforementioned one or more new rows refer to rows added to the first basis matrix compared to the second basis matrix; or, in other words, one or more new rows are added to the second basis matrix to obtain the first basis matrix. The newly added row or multiple rows are one or more new rows in the first basis matrix. Alternatively, "new rows" can also be called "inserted rows," that is, one or more rows are inserted into the second basis matrix to obtain the first basis matrix.

[0098] Implementation Method 1

[0099] The values ​​of the elements in the first newly added row of the one or more newly added rows are determined based on the values ​​of the elements in the first row and / or the second row of the first base matrix. The first row is the row preceding the first newly added row, and the second row is the row following the first newly added row. The first newly added row is any row among the one or more newly added rows. It can be understood that when the first base matrix includes a newly added row, that newly added row is the first newly added row.

[0100] In implementation method 1, a new insertion row is generated based on two adjacent rows in the second base matrix. In the first base matrix, any new row (i.e., the insertion row) is determined based on the values ​​of the elements in the row preceding and / or following the insertion row.

[0101] The second basis matrix is ​​the original basis matrix, and the first basis matrix is ​​the extended basis matrix.

[0102] In the following embodiment, it is assumed that the first newly added row corresponds to row index i in the first base matrix.

[0103] In other words, in implementation method 1, the value of the element in the first newly added row is mainly determined by the position of the non-zero elements in the two rows before and after the first newly added row, or by the degree of the variable node and the degree of the check node.

[0104] Assume the number of non-zero elements in the i-th row of the second basis matrix (corresponding to the degree of the check node or the row weight of the i-th row) is DC. i The number of non-zero elements in column e (corresponding to the degree of the variable node or the column weight of column e) is DV e Then, any element in any newly added row of the first basis matrix can be obtained by any of the following methods 1 to 3.

[0105] Method 1

[0106] For the element at position (i, e) in the newly added row #1, where e is a non-negative integer, the value of the element at position (i, e) can be determined according to the following priority:

[0107] Priority 1: If e = 0 or 1, sum the first and second columns of the first i-1 rows respectively. If the sum of the first column is greater than the sum of the second column, set position (i,0) to 0 (for the case where e = 0) and position (i,1) to 1 (for the case where e = 1); otherwise, set position (i,0) to 1 (for the case where e = 0) and position (i,1) to 0 (for the case where e = 1).

[0108] Priority 2: If at least one of the positions (i-1,e) or (i+1,e) is 1, then the position (i,e) is 0;

[0109] Priority 3: Determine the value of position (i,e) based on the values ​​of positions (i-1,e-1), (i-1,e+1), (i+1,e-1), or (i+1,e+1). For example, if at least one of the four positions has a value of 1, then position (i,e) is set to 1.

[0110] Priority 4: Positions not covered by the principles of priorities 1 to 3 above are assigned a value of 0.

[0111] In one example, if the element in column j of either the row before or after the newly added row #1 is 1, then the element at position (i, e) in the newly added row #1 is set to 0, where e is a non-negative integer. For the remaining positions in the newly added row #1, if the element at a certain position in the preceding row (i.e., row i-1) is 1, then the lower right or lower left corner of that position is set to 1; or if the element at a certain position in the following row (i.e., row i+1) is 1, then the upper left or upper right corner of that position is set to 1.

[0112] Method 2

[0113] For the position (i, e) in the newly added row #1, where e is a non-negative integer, the value of the element at that position can be determined according to the following priority:

[0114] Priority 1: If e = 0 or 1, sum the first and second columns of the first i-1 rows respectively. If the sum of the first column is greater than the sum of the second column, set position (i,0) to 0 (for the case where e = 0) and position (i,1) to 1 (for the case where e = 1); otherwise, set position (i,0) to 1 (for the case where e = 0) and position (i,1) to 0 (for the case where e = 1).

[0115] Priority 2: If at least one of the positions (i-1,e) or (i+1,e) is 1, then the position (i,e) is 0;

[0116] Priority 3: If e > 2, in ascending order of e, if the element at position (i, e) is set to 1 such that the difference between the sum of the elements in the first i rows and e columns of the first basis matrix and the sum of the elements in the first i rows and e columns of the second basis matrix does not exceed 1, then the element at position (i, e) is set to 1; otherwise, it is set to 0. This continues until the number of positions equal to 1 in the i-th row of the second basis matrix (where e > 2) is equal to the number of positions equal to 1 in the i-th row of the first basis matrix (where e > 2).

[0117] Optionally, priority 3 can also be described as follows: Positions other than those whose values ​​are determined based on priority 1 and / or priority 2 are called remaining positions, and any one of these remaining positions is denoted as (i, r), where r is a non-negative integer. Whether the element at position (i, r) is 1 is determined based on the column weight of the r-th column corresponding to position (i, r) and the first column weight. The first column weight is the column weight of the r-th column of the second base matrix at the first code rate. The first code rate is one of the code rates supported by the first base matrix, or it can refer to the target code rate. That is, the value of the element at position (i, r) is determined based on the column weight of the r-th column of the first base matrix at the target code rate and the column weight of the r-th column of the second base matrix at the same code rate.

[0118] Priority 4: Positions not covered by the principles of priorities 1 to 3 above are assigned a value of 0.

[0119] Method 3

[0120] For position (i, e) in the newly added row #1, if any row before or after the newly added row #1 has an element in column e that is 1, then the element at position (i, e) in the newly added row #1 is 0, where e is a non-negative integer. Furthermore, the first base matrix includes p punched columns. The value of the element in the first punched column of the newly added row #1 is determined by any one of the following: the row index of the newly added row #1, and the values ​​of the elements in the first and second rows at their respective positions in the first punched columns. Additionally, the positions of the newly added row #1 in all punched columns except the first punched column are 0.

[0121] As an example, the newly added row #1 is the nth row in the order of the row index in ascending order among the above one or more newly added rows. That is, the newly added row #1 is the nth inserted row. The element at the nth (mod p) column position of the newly added row #1 is 1, and the elements at the other punched columns of the newly added row #1 are 0.

[0122] In this application, position (i,e) refers to any position in the newly added row (corresponding to row index i). Positions (i,j), (i,q), and (i,r) in other embodiments are specific examples of position (i,e) in the newly added row. For example, position (i,j) can refer to the position in the newly added row that has a value of 0, position (i,q) can refer to the position in the newly added row that has a value of 1, and position (i,r) can be any of the remaining positions in method 2 of implementation method 1, except for the positions whose values ​​are determined based on priority 1 and / or priority 2.

[0123] Figure 6 shows a local example of the first basis matrix obtained based on NR BG2 extension. Rows marked in yellow are newly added rows, where the positions marked in pink have a value of 1, and the remaining positions have a value of 0. Alternatively, rows marked with arrows in Figure 6 are newly added rows. In these newly added rows, the positions filled with dark color have a value of 1, and the remaining positions filled with light color have a value of 0.

[0124] The example shown in Figure 6 is an extended example. In a real implementation, it is not necessary to add a new row between all adjacent rows in the second basis matrix. Instead, the position of the new row can be determined according to the specific application scenario or the indication of the new row.

[0125] In one example, when the required bitrate for the application scenario is lower than the minimum bitrate designed for the NR base matrix (e.g., NR BG2), at least Method 1 or Method 2 described above should be used to adjust the NR base matrix. More specifically, Method 3 should be used to adjust the punched columns when transmitting operations involving puncturing. More specifically, as another example, when using NR BG1 and the required bitrate for the application scenario is less than 1 / 3, or when using NR BG2 and the required bitrate for the application scenario is less than 1 / 5, Method 1 or Method 2 should be used in combination with Method 3 for adjustment.

[0126] In another example, if the second basis matrix is ​​NR BG2, then new rows are added preferentially between rows 5 and 9 of the second basis matrix.

[0127] In implementation method 1, by inserting new rows into the basis matrix of NR, the basis matrix, which originally lacked the property of orthogonality between adjacent rows, becomes a row-orthogonal basis matrix, thus reducing decoding latency. Furthermore, it preserves the coding structure and hybrid automatic repeat request (HARQ) characteristics of the original basis matrix without significantly impacting the thresholding performance of the original basis matrix. Additionally, it supports application scenarios with lower bit rates.

[0128] Figure 7 shows a simulation comparison of the thresholds for NR's BG2 and the extended BG2 provided in this application. The horizontal axis represents the code rate, and the vertical axis represents the SNR threshold. It can be seen that, compared to NR BG2, the first basis matrix provided in this application, such as the extended BG2 in the example, can support lower code rates.

[0129] Implementation Method 2

[0130] The value of an element in the first newly added row of the one or more newly added rows is determined based on the value of the element in the y-th row of the first base matrix. The y-th row is any row in the first base matrix other than the one or more newly added rows, and y is a non-negative integer.

[0131] In implementation method 2, the values ​​of the elements in the new row are determined based on the values ​​of the elements in the y-th row of the first basis matrix. The first basis matrix is ​​obtained by extending the second basis matrix, and the y-th row of the first basis matrix corresponds to the h-th row of the second basis matrix. Therefore, it can also be said that the h-th row is first selected from the second basis matrix, and the position and number of non-zero elements in the first new row are determined based on at least one of the position and number of non-zero elements in the h-th row of the second basis matrix.

[0132] As mentioned above, the elements in a basis matrix are either 0 or 1. Therefore, a non-zero element in a basis matrix refers to the element "1" in that basis matrix, and a zero element in a basis matrix refers to the element "0" in that basis matrix.

[0133] In one example, the position of the non-zero element in the y-th row of the first basis matrix corresponds to the first position set. That is, the non-zero element in the h-th row of the second basis matrix corresponds to the first position set. The position of the non-zero element in the first new row of the above one or more new rows corresponds to the second position set, which is a subset of the first position set.

[0134] As an example, let x be the number of non-zero elements in the y-th row of the first basis matrix, and let a be the number of non-zero elements in the first newly added row, where a is less than x. These a non-zero elements are distributed in the first newly added row in one of the following ways:

[0135] The 'a' positions in ascending order of the column index; or,

[0136] The a positions of the column index in descending order; or,

[0137] The a positions of the column index in ascending order (or descending order) where the difference between adjacent indexes is greater than 1.

[0138] As an example, Where m is greater than 0 and less than 1. This indicates rounding down to the nearest integer.

[0139] In other words, the h-th row is selected from the second base matrix, where the h-th row of the second base matrix has x non-zero elements. Based on the number of non-zero elements in the h-th row of the original base matrix, a new row (i.e., an insertion row) is generated, and the number of non-zero elements in the new row is less than the number of non-zero elements in the h-th row of the original base matrix. Furthermore, the non-zero elements in the new row can be distributed in order (i.e., in ascending order of column indices), in reverse order (i.e., in ascending order of column indices), or at intervals.

[0140] In one example, row h of the second basis matrix is ​​one row in the set of rows corresponding to the BG1 or BG2 information column regions of NR. The positions of non-zero elements in the first newly added row of the first basis matrix are a subset of the positions of non-zero elements in row h of the second basis matrix. As mentioned above, row h of the second basis matrix corresponds to row y of the first basis matrix. Therefore, it can also be said that the positions of non-zero elements in the first newly added row of the first basis matrix are a subset of the positions of all non-zero elements in row y of the first basis matrix.

[0141] As another example, let x be the number of non-zero elements in the h-th row of the second basis matrix, and b be the number of non-zero elements in the first newly added row, where b is an integer greater than x. The h-th row of the second basis matrix corresponds to the y-th row of the first basis matrix. Therefore, it can also be said that the positions of the non-zero elements in the y-th row of the first basis matrix are a subset of the positions of the non-zero elements in the first newly added row of the first basis matrix. Furthermore, the first newly added row and the y-th row of the first basis matrix are not adjacent.

[0142] In one example, the h-th row of the second basis matrix is ​​one of the rows in the set of rows corresponding to the D and E regions of BG1 or BG2 in NR, for example, called the t-th row. The positions of the non-zero elements in the t-th row are a subset of the positions of the non-zero elements in the first newly added row of the first basis matrix.

[0143] Figure 8 shows a local example of the first basis matrix obtained based on NR BG2 extension. Rows marked in yellow are new rows, with the pink-marked positions having a value of 1 and the remaining positions having a value of 0. Alternatively, rows marked with arrows in Figure 8 are new rows. In these new rows, the dark-filled positions have a value of 1, and the remaining light-filled positions have a value of 0.

[0144] In implementation method 2, by adding new rows to the original basis matrix (e.g., NR BG1 or BG2), the basis matrix that originally did not have the property of adjacent rows being orthogonal becomes a basis matrix with orthogonal rows, which can reduce decoding latency. In addition, the coding structure and HARQ characteristics of the original basis matrix can be maintained, and application scenarios with lower code rates can be supported.

[0145] As an example, the above implementation method 1 is applicable to extending NR BG1, and implementation method 2 is applicable to extending NR BG1 or BG2, respectively obtaining new basis matrices, namely the first basis matrix in the embodiments of this application.

[0146] 220. The transmitting device determines the first matrix based on the first base matrix and the translation values ​​corresponding to the elements in the first base matrix.

[0147] In step 220, the transmitting side device is based on the boost factor Z c The translation values ​​corresponding to each non-zero element in the first basis matrix are used to expand the first basis matrix to obtain the parity check matrix, i.e., the first matrix, which is used for encoding.

[0148] As described above, the first basis matrix may include a second basis matrix (i.e., the original basis matrix) and one or more newly added rows. This application provides a method for obtaining the translation values ​​of these one or more newly added rows. For elements in the first basis matrix other than these one or more newly added rows, the translation values ​​of the corresponding positions in the second basis matrix can be kept unchanged. For details, refer to the method for determining the translation values ​​of non-zero positions in NR BG1 or BG2 in the 3GPP technical specification (TS) 38.212.

[0149] Similarly, let's take one of the newly added rows as an example. The shift value corresponding to the element in the newly added row can also be determined by any of the following methods a to d.

[0150] Method a

[0151] In one example, the first newly added row (e.g., base matrix #1) includes a first position, denoted as (i, e). The first position can represent any position in the first newly added row, and e represents any column index in the corresponding base matrix. The shift value corresponding to the first position is related to one or more of the following: the shift value of the non-zero element in the first base matrix that is closest to the first position, a preset constant, the row index corresponding to the first position, and / or the column index corresponding to the first position.

[0152] As an example, the translation value corresponding to the first position in the first newly added row is determined based on the following formula: SV i,e =k+w i,e Or, SV i,e =mod(k+w) i,e Z C ),

[0153] Where k is the translation value of the non-zero element closest to the first position in the first basis matrix, and w i,e It is a preset constant, or a constant related to the row index i and / or column index e of the first position (i,e).

[0154] Method b

[0155] In another example, the first newly added row includes a first position, and the translation value corresponding to the first position is related to one or more of the following: the translation value corresponding to the h-th row and e-th column of the second base matrix, a preset constant, the row index corresponding to the first position, and / or the column index corresponding to the first position.

[0156] As an example, the translation value corresponding to the first position in the first newly added row is determined based on the following method: SV i,e =k i′ +w i,e ,

[0157] Where i′ is the row index of the h-th row of the second basis matrix, the first position corresponds to the e-th column of the first basis matrix, and k i′ w represents the translation value corresponding to the position in the h-th row and e-th column of the second basis matrix. i,e For a preset constant, or w i,b It is a constant related to the row index i and / or column index e of the first position (i,e), where e is any one of the column indices corresponding to the first base matrix.

[0158] In methods a and b, the translation values ​​corresponding to the elements in the newly added rows of the first basis matrix are calculated. Alternatively, the translation values ​​of the elements in the newly added rows of the first basis matrix can also be obtained using method c or method d.

[0159] Method c

[0160] Pre-store the list of shift values ​​#1, adding identifiers to distinguish whether the current row needs to use them. In one possible implementation, for positions where an increase is needed, add "(+)" after them, and increment the index of subsequent rows with an index greater than that row by 1. If raptor-like nodes are involved, this is indicated by adding "(+)" to the corresponding column position, and incrementing the index of subsequent columns with an index greater than that column by 1.

[0161] As an example, the translation value list #1 can be shown in Table 3.

[0162] Table 3

[0163] In one possible implementation, if the application scenario is identified as requiring a lower bit rate, such as satellite communication or ultra-high reliability, the rows marked with (+) in Table 3 are read and executed. In other application scenarios, the rows marked with (+) are skipped when reading Table 3.

[0164] For example, "5(+)" after row index 5 indicates inserting a new row after the 5th row of the original base matrix, that is, inserting a new row between the 5th and 6th rows of the original base matrix. Under different promotion values ​​(i.e., i... LS The values ​​of (0 to 7) represent the shift values ​​of the newly added row at column indices 1, 4, 6, 8, and 16, respectively. These shift values ​​can be determined by looking up Table 3. For example, if the newly added row is at column index 1, the shift value corresponding to index i... LS For values ​​from 0 to 7, the shift values ​​are 154, 128, 1, 122, 108, 46, 6, and 136, respectively. The shift values ​​corresponding to the positions of non-zero elements in other newly added rows are determined in the same way. Furthermore, to avoid disrupting the raptor-like structure of region E of the first base matrix, when the inserted new row is located in the row region of the original base matrix's raptor-like region (also the row region corresponding to region D or region E), the column index corresponding to the raptor-like node is incremented by 1. Columns before the raptor-like node are unaffected. In other words, a new column is added before the raptor-like node, and the index of the column after this new column is incremented by 1, thus ensuring that the column region after the new column remains an identity matrix.

[0165] In method c, the rows marked with (+) in Table 3 are optional. The rows marked with (+) can be read only in scenarios with low bitrate requirements or other settings. In other scenarios, the rows marked with (+) are ignored and read. In this case, it is equivalent to reading the base matrix to be used from the original base matrix.

[0166] In one example, when reading the base matrix to be used from Table 3, the method of reading Table 3 can be selected according to the current application scenario. For example, in a low bitrate requirement scenario, the base matrix to be used is obtained by reading the rows in Table 3 that contain (+) rows. This method is more suitable for low bitrate scenarios and has better performance. When the current application scenario is something other than a low bitrate requirement scenario, the base matrix to be used can be read either by reading the rows in Table 3 that contain (+) rows or by reading the rows in Table 3 that do not contain (+) rows. For example, if the base matrix to be used has 6 rows, in a low bitrate requirement scenario, the first 5 rows and 5 (+) rows of Table 3 can be read, for a total of 6 rows. In other scenarios, the first 5 rows and 5 (+) rows of Table 3 can be read, for a total of 6 rows. Alternatively, the first 6 rows of Table 3 can be read, and the 5 (+) rows can be skipped, reading the 6th row of the original base matrix, which also reads 6 rows to obtain the base matrix to be used. In this embodiment of the application, the low bitrate requirement scenario is only an example, and it can also be other application scenarios.

[0167] Based on method c, minor modifications can be made to the recording method of the original base matrix to support more application scenarios, such as those requiring lower bitrates.

[0168] Method d

[0169] A pre-stored translation value list #2 is provided. This translation value list #2 includes the translation values ​​corresponding to the positions of non-zero elements in the original base matrix and the translation values ​​corresponding to the positions of non-zero elements in the newly added rows. In other words, the translation value list #2 is designed based on the first base matrix provided in this application. The row and column indices in the first base matrix include not only the rows and columns in the original base matrix, but also the newly inserted rows and the corresponding columns added in the case of raptor-like nodes. Then, the row and column indices are uniformly numbered, and the translation value list #2 is designed based on this.

[0170] In mode d, the transmitting and receiving sides pre-store a translation value list #2. During encoding or decoding, a matrix of the appropriate size is extracted from this list. The translation value corresponding to the position of the non-zero element in the extracted matrix can be determined based on the translation value recorded in the translation value list #2.

[0171] By using any of the methods a to d mentioned above, the LDPC base matrix becomes more scalable, thus adapting to more application scenarios, such as scenarios with lower bitrate requirements than those supported by NR BG1 or BG2.

[0172] Through steps 210 to 220 above, the transmitting device can obtain the expanded basis matrix (i.e., the first basis matrix), and expand the first basis matrix based on the lifting factor and the translation values ​​of the elements in the first basis matrix to obtain the parity matrix, denoted as the first matrix.

[0173] 230. The transmitting device encodes based on the first matrix to obtain the encoded bit sequence.

[0174] 240. The transmitting device outputs the encoded bit sequence.

[0175] The transmitting side encodes based on the parity check matrix, and the process of obtaining the encoded bit sequence will not be described in detail.

[0176] Optionally, if the transmitting device is the transmitting device itself, step 240 may refer to the transmitting device sending an encoded bit sequence to the receiving device; or, if the transmitting device is a device applied to the transmitting device, such as a circuit or chip, step 240 may refer to the device applied to the transmitting device outputting an encoded bit sequence, such as the circuit or chip outputting the encoded bit sequence obtained through a communication interface.

[0177] In the technical solution of this application, the extended base matrix has stronger compatibility with different application scenarios, such as supporting application scenarios with lower bit rates. At the same time, due to the control of a limited range of modifications, it can be compatible with NR BG1 or BG2 schemes, supporting lower bit rates and reducing decoding latency while maintaining the performance of NR BG1 or BG2.

[0178] Optionally, method 200 may also include methods on the decoding side, such as steps 240-250.

[0179] 250. The receiving side device acquires the received value sequence.

[0180] Similar to step 240, if the receiving device is the receiving device itself, step 250 may refer to the receiving device receiving a sequence of received values ​​from the transmitting device, such as a log-likelihood ratio (LLR) sequence; or, if the receiving device is a device applied to the receiving device, such as a circuit or chip, step 250 may refer to the device applied to the receiving device acquiring the sequence of received values, such as a circuit or chip receiving the sequence of received values ​​through a communication interface to perform subsequent decoding processes.

[0181] 260. The receiving device determines the first matrix based on the first base matrix and the translation values ​​corresponding to the elements in the first base matrix.

[0182] Steps 250 to 260 can be referred to in the descriptions of steps 210 to 220 above, and will not be repeated here.

[0183] 270. The receiving device decodes the received value sequence based on the first matrix to obtain the decoded bit sequence.

[0184] 280. The receiving device outputs the decoded bit sequence.

[0185] The embodiments of this application do not limit the order in which the steps in method 200 are executed. The order shown in Figure 5 is only for the purpose of describing the scheme, and other execution orders are also possible. For example, step 250 can be executed before or after step 260, or simultaneously with it; as another example, step 260 can be executed before or after any of steps 210 to 240, or simultaneously with any of them, all of which are feasible.

[0186] The process of decoding based on the parity check matrix (i.e., the first matrix) by the receiving device will not be described in detail in this application.

[0187] The above describes the overall process of encoding or decoding. When encoding or decoding based on this technical solution, the process can also be as shown in Figure 6.

[0188] Figure 9 is a schematic diagram of the encoding chain flow or decoding chain flow based on the technical solution of this application.

[0189] Both the transmitting and receiving devices can store information such as:

[0190] 1) The basis matrix of LDPC, such as BG1 or BG2 of NR, or the first basis matrix in the embodiments of this application;

[0191] It is understandable that storing NR BG1 or BG2, or storing the first basis matrix, depends on the different implementation methods.

[0192] 2) Promotion Size List: The promotion size list can be as shown in Table 1, which includes the promotion size and the row index corresponding to each promotion size set, also known as the promotion size identifier (ID), such as i in Table 1. LS ;

[0193] 3) Translation value list: The translation value of the non-zero position in the base matrix can be determined from the translation value list based on the ID of the lifting dimension; as an example, the translation value list can be a list of translation values ​​corresponding to the position of each non-zero element in the new row calculated according to the formula in method a or method b above, or as translation value list #1 in method c, or as translation value list #2 in method d.

[0194] Optionally, when using method d, the base matrix stored by the transmitting or receiving device can be the first base matrix, and the translation value list is as shown in translation value list #2 in method d. Combined with the lift size list, the transmitting or receiving device can determine the parity check matrix for encoding or decoding.

[0195] Optionally, when any of the methods a to c are used, the base matrix stored by the transmitting or receiving device can be NR BG1 or BG2, and the translation value list can be the translation value corresponding to the position of each non-zero element in the newly added row determined according to the corresponding method of method a to c. In addition, the following nested sequence is also stored.

[0196] 4) Nested sequences: used to record the priority order of newly added rows in the base matrix;

[0197] For example, the nested sequence is {5, 6, ..., 16}, which contains 12 row indices. If it is not necessary to insert all 12 rows, for example, if only 3 rows need to be inserted, rows can be inserted according to the priority of the records in the nested sequence. For example, new rows can be inserted below rows 5, 6, and 7 of the second base matrix.

[0198] Based on the above information, the transmitting or receiving device can determine different base matrices based on different application scenarios, and expand the determined base matrices to obtain a parity check matrix for encoding or decoding.

[0199] Taking the transmitting device as an example, the encoding chain process may include:

[0200] ① The transmitting device selects the base matrix (here referring to NR BG1 or BG2) based on one or more of the following: target code length K, code rate R, or application scenario;

[0201] ② The transmitting device determines whether to expand the selected base matrix;

[0202] If the selected basis matrix is ​​expanded, proceed to step ③ below; otherwise, proceed to step ④.

[0203] ③ The transmitting device expands the selected base matrix to obtain the expanded base matrix, such as the first base matrix or base matrix #1 in the above embodiment;

[0204] ④ Determine the translation value corresponding to each position in the basis matrix #a based on the basis matrix #a (if no expansion is performed, the basis matrix #a is NR BG1 or BG2; or if expansion is performed, the basis matrix #a is the expanded basis matrix, i.e. the first basis matrix) and the lifting factor.

[0205] ⑤ The transmitting device obtains the parity check matrix based on the base matrix #a, the lifting factor, and the shift value corresponding to each position in the base matrix #a, and completes the encoding.

[0206] On the receiving device side, steps ① to ④ are the same as those performed by the transmitting device; the difference is that in step ⑤, the receiving device decodes the parity check matrix after obtaining it.

[0207] It can be understood that when the base matrix #a is NR BG1 or BG2, the translation value of each position in NR BG1 or BG2 is determined based on the lifting value list; when the base matrix #a is the first base matrix, the translation value corresponding to the non-zero position in the original base matrix and the translation value corresponding to the non-zero position in the newly added row are determined based on the lifting value list.

[0208] It is understandable that, given that NR BG1 or BG2 meets the requirements of the current application scenario, in the above encoding chain process, the transmitting or receiving device can choose not to expand the base matrix in step ②, but instead boost the selected NR BG1 or BG2 to obtain a parity check matrix for encoding or decoding. In some application scenarios, the transmitting or receiving device can choose to expand the selected base matrix in step ②. For example, if the transmitting or receiving device selected NR BG2 in step ①, but the minimum bit rate of NR BG2 still cannot support the extremely low bit rate requirements of the current scenario, the transmitting or receiving device can choose to expand NR BG2 to obtain the first base matrix. Then, the first base matrix is ​​boosted to obtain the parity check matrix for encoding or decoding.

[0209] The basis matrix provided in this application supports lower code rates while maintaining a good basis matrix structure and decoding threshold, avoiding decoding delays caused by non-orthogonal rows in NR BG1 or BG2, thereby reducing latency. Furthermore, the technical solution of this application supports flexible adjustments to NR BG1 or BG2, adapting to more application scenarios while maintaining the recording method and hardware implementation of NR BG1 or BG2.

[0210] The above is a detailed description of the channel coding or decoding method provided in this application. The following describes the communication device provided in this application.

[0211] Figure 10 is a schematic structural diagram of the communication device 1000 provided in this application. The communication device 1000 can be a transmitting-side device, or a device applied to the transmitting-side device that can realize the corresponding functions of the transmitting-side device in the method embodiments of this application, such as a chip, processor, or circuit. Alternatively, the communication device 1000 can be a receiving-side device, or a device applied to the receiving-side device that can realize the corresponding functions of the receiving-side device in the method embodiments of this application, such as a chip, processor, or circuit.

[0212] Optionally, the communication device 1000 includes a processing module 1001, which may be a processor, a processing board, a processing unit, or a processing device, etc. When the communication device 1000 is a transmitting-side device or a device applied to a transmitting-side device, the processing module 1001 is used to: obtain a first basis matrix; determine a first matrix based on the first basis matrix and the translation values ​​corresponding to the elements in the first basis matrix; and encode based on the first matrix to obtain an encoded bit sequence, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here. When the communication device 1000 is a receiving-side device or a device applied to a receiving-side device, the processing module 1001 is used to: obtain a first basis matrix; determine a first matrix based on the first basis matrix and the translation values ​​corresponding to the elements in the first basis matrix; and decode the received value sequence based on the first matrix to obtain a decoded bit sequence, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here.

[0213] Optionally, the communication device 1000 further includes a communication module 1002, which may also be referred to as a transceiver module, transceiver, transceiver unit, or transceiver device, etc., for performing receiving (or input) and / or sending (or output) operations. For example, when the communication device 1000 is a transmitting-side device or a device applied to a transmitting-side device, the communication module 1002 can be used to acquire a bit sequence to be encoded and transmit the bit sequence to be encoded to the processing module 1001; and output the encoded bit sequence obtained by the processing module 1001. When the communication device 1000 is a receiving-side device or a device applied to a receiving-side device, the communication module 1002 can be used to receive a received value sequence and send the received value sequence to the processing module 1001; and output the decoded bit sequence obtained by the processing module 1001 decoding the received value sequence. Furthermore, it should be noted that the aforementioned communication module and / or processing module can be implemented through virtual modules. For example, the processing module can be implemented through a software functional unit or a virtual device, and the communication module can be implemented through a software function or a virtual device. Alternatively, the processing module or communication module can also be implemented by a physical device, such as a chip / circuit (e.g., an integrated circuit or logic circuit). The communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or circuit (e.g., an integrated circuit, logic circuit).

[0214] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware, as software functional modules, or a combination of hardware and software.

[0215] Figure 11 is a schematic structural diagram of another communication device provided in this application. The communication device 1100 can be used to implement the functions of any communication device (e.g., a transmitting device or a receiving device) in the communication system described in the foregoing examples. The communication device 1100 may include at least one processor 1110. Optionally, the processor 1110 (or processing device) is coupled to a memory, which may be located within the communication device, integrated with the processor, or located outside the communication device. For example, the communication device 1100 may also include at least one memory 1120. The memory 1120 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 1110 may execute the computer programs, instructions, or data stored in the memory 1120 to perform the corresponding functions of the transmitting device or receiving device in any of the above embodiments.

[0216] Optionally, the communication device 1100 may further include a communication interface 1130, through which the communication device 1100 can interact with other devices. For example, the communication interface 1130 may be a transceiver, circuit, bus, module, pin, or other type of communication interface. When the communication device 1100 is a chip-type device or circuit, the communication interface 1130 in the device 1100 may also be an input / output circuit, capable of inputting information (or receiving information) and / or outputting information (or sending information). The processor may be an integrated circuit or logic circuit, etc., and the processor can determine the output information based on the input information.

[0217] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 1110 may operate in conjunction with the memory 1120 and the communication interface 1130. This application does not limit the connection medium between the processor 1110, the memory 1120, and the communication interface 1130.

[0218] Figure 12 is a schematic structural diagram of the chip provided in this application. The chip 30 includes a circuit 31 and a communication interface 32. The circuit 31 can be a logic circuit, an integrated circuit, etc., and the communication interface 32 can also be called an input / output circuit, input / output interface, interface circuit, etc., which can input information (or receive information) or output information (or send information). The chip 30 can execute the methods executed by the transmitting-side device or the receiving-side device in the various embodiments of this application.

[0219] In addition, this application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause operations and / or processes performed by a transmitting-side device or a receiving-side device in the various method embodiments of this application to be executed.

[0220] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending-side device or the receiving-side device in the various method embodiments of this application are executed.

[0221] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by a transmitting-side device or a receiving-side device in any method embodiment are executed. Further, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may also include the memory.

[0222] This application provides a communication system, including the transmitting-side device and the receiving-side device in the above method embodiments.

[0223] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0224] The processor in this application embodiment has signal processing capabilities and can be a central processing unit (CPU), or a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. It can implement or execute the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly embodied in the execution of the hardware processor, or executed by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0225] In the embodiments of this application, the memory can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). The memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0226] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0227] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0228] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0229] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0230] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

Claims

1. A method of encoding, characterized by, include: Obtain a first base matrix, which includes one or more newly added rows. The value of the element in the first newly added row is determined based on the value of the element in the first row and / or the second row of the first base matrix. The first row is the row before the first newly added row, and the second row is the row after the first newly added row. Alternatively, the value of an element in the first newly added row of the one or more newly added rows is determined based on the value of an element in the y-th row of the first base matrix, where the y-th row is any row in the first base matrix other than the one or more newly added rows, and y is a non-negative integer. The first matrix is ​​determined based on the first basis matrix and the translation values ​​corresponding to the elements in the first basis matrix; Encode the first matrix to obtain an encoded bit sequence; as well as Output the encoded bit sequence.

2. The method of claim 1, wherein, The first basis matrix is ​​obtained based on an extension of the second basis matrix, which includes either basis map BG1 or BG2 in the new wireless NR.

3. The method of claim 2, wherein, The row index of the first newly added row is i, the position (i,j) of the j-th column of the first newly added row is 0, and the element at the j-th column of at least one of the first row and the second row is 1, where j is a non-negative integer.

4. The method of claim 3, wherein, The first newly added row includes the position (i, q), where: The element at position (i, q) is 1, the element at position (i-1, q-1) is 1, and / or the element at position (i-1, q+1) is 1; or, The element at position (i, q) is 1, the element at position (i+1, q-1) is 1 and / or the element at position (i+1, q+1) is 1; q and j are not equal.

5. The method of claim 3, wherein, The number of elements with a value of 1 in the first newly added row, except for the position (i,j), is determined based on the number of non-zero elements in the first row or the second row.

6. The method of claim 5, wherein, The first newly added row includes positions (i, r) in addition to the positions (i, j), where r is a non-negative integer. Whether the element at position (i, r) is 1 is determined by the column weight of the r-th column of the first base matrix corresponding to position (i, r) and the first column weight. The first column weight is the column weight of the r-th column of the second base matrix at the first code rate. The first code rate is the target code rate, and the second base matrix is ​​BG2 in NR.

7. The method according to claim 3, characterized in that, The first base matrix comprises p punched columns, and the value of the element at the position of the first punched column in the first of the p punched columns is determined according to any one of the following: The row index of the first newly added row in the first base matrix; The values ​​of the elements in the first row and the second row at the positions in the first punch column.

8. The method according to claim 7, characterized in that, The first newly added row is the nth row in the one or more newly added rows according to the row index in ascending order. The element at the nth (mod p) column of the first newly added row is 1, and the element at the other punched columns of the first newly added row is 0. n is an integer.

9. The method according to claim 3, characterized in that, The y-th row of the first basis matrix corresponds to the h-th row of the second basis matrix. The positions of the non-zero elements in the h-th row of the second basis matrix correspond to the first position set. The positions of the non-zero elements in the first newly added row correspond to the second position set. The second position set is a subset of the first position set, or the first position set is a subset of the second position set.

10. The method according to claim 9, characterized in that, The second set of positions is a subset of the first set of positions. The number of non-zero elements in the h-th row of the second base matrix is ​​x, and the number of non-zero elements in the first newly added row is a, where a is less than x. The a non-zero elements are distributed in the first newly added row in one of the following ways: The 'a' positions in ascending order of the column index; or, The a positions of the column index in descending order; or, The column indexes are in ascending order and adjacent column indexes differ by more than 1 at position a; or, The column indexes are ordered from largest to smallest, and the a positions of adjacent column indexes differ by more than 1.

11. The method according to claim 10, characterized in that, The h-th row of the second base matrix corresponds to a row in the row region corresponding to the information column region of BG1 or BG2 of the NR.

12. The method according to claim 3, characterized in that, The first set of positions is a subset of the second set of positions. The number of non-zero elements in the h-th row of the second base matrix is ​​x. The number of non-zero elements in the first newly added row is b, where b is greater than x. The positions of the b non-zero elements in the first newly added row include at least the positions of all non-zero elements in the h-th row of the second base matrix. The first newly added row is not adjacent to the y-th row of the first base matrix.

13. The method according to claim 12, characterized in that, The h-th row of the second base matrix corresponds to one row in the row region corresponding to the incremental redundancy region of BG1 or BG2 of the NR.

14. The method according to any one of claims 2-8, characterized in that, The first newly added row includes a first position, and the translation value corresponding to the first position is related to one or more of the following: the translation value of the nearest non-zero element to the first position, a preset constant, the row index corresponding to the first position, or the column index corresponding to the first position.

15. The method according to claim 14, characterized in that, The translation value corresponding to the first position is determined based on the following method: SV i,e = k + w i,e ; or, SV i,e = mod(k + w i,e , Z C ), wherein k is a translation value of a non-zero element in the first basis matrix closest to the first position, w i,e is the preset constant, or w i,e is a constant related to the row index i and / or the column index e of the first position (i, e), and e is any one of the column indices corresponding to the first basis matrix.

16. The method according to any one of claims 9-13, characterized in that, The first newly added row includes a first position, which corresponds to the e-th column. The translation value corresponding to the first position is related to one or more of the translation value of the h-th row of the second base matrix corresponding to the e-th column, a preset constant, the row index corresponding to the first position, or the column index corresponding to the first position.

17. The method according to claim 16, characterized in that, The translation value corresponding to the first position is determined based on the following manner: SV i,e = k i′ + w i,e , Where i′ is the row index of the h-th row of the second basis matrix, the first position corresponds to the e-th column, and k i′ w is the translation value corresponding to the position in the h-th row and e-th column of the second basis matrix. i,e The preset constant, or w i,e It is a constant related to the row index i and / or column index e of the first position (i,e), where e is any one of the column indices corresponding to the first base matrix.

18. A decoding method, characterized in that, include: Obtain a first base matrix, which includes one or more newly added rows. The value of the element in the first newly added row is determined based on the value of the element in the first row and / or the second row of the first base matrix. The first row is the row before the first newly added row, and the second row is the row after the first newly added row. Alternatively, the value of an element in the first newly added row of the one or more newly added rows is determined based on the value of an element in the y-th row of the first base matrix, where the y-th row is any row in the first base matrix other than the one or more newly added rows, and y is a non-negative integer. The first matrix is ​​determined based on the first basis matrix and the translation values ​​corresponding to the elements in the first basis matrix; Based on the first matrix, the received value sequence is decoded to obtain the decoded bit sequence; as well as, Output the decoded bit sequence.

19. The method according to claim 18, characterized in that, The first basis matrix is ​​obtained based on an extension of the second basis matrix, which includes either basis map BG1 or BG2 in the new wireless NR.

20. The method according to claim 19, characterized in that, The row index of the first newly added row is i, the position (i,j) of the j-th column of the first newly added row is 0, and the element at the j-th column of at least one of the first row and the second row is 1, where j is a non-negative integer.

21. The method according to claim 20, characterized in that, The first newly added row includes the position (i, q), where: The element at position (i, q) is 1, the element at position (i-1, q-1) is 1, and / or the element at position (i-1, q+1) is 1; or, The element at position (i, q) is 1, the element at position (i+1, q-1) is 1 and / or the element at position (i+1, q+1) is 1; q and j are not equal.

22. The method according to claim 20, characterized in that, The number of elements with a value of 1 in the first newly added row, except for the position (i,j), is determined based on the number of non-zero elements in the first row or the second row.

23. The method according to claim 22, characterized in that, The first newly added row includes positions (i, r) in addition to the positions (i, j), where r is a non-negative integer. Whether the element at position (i, r) is 1 is determined by the column weight of the r-th column of the first base matrix corresponding to position (i, r) and the first column weight. The first column weight is the column weight of the r-th column of the second base matrix at the first code rate. The first code rate is the target code rate, and the second base matrix is ​​BG2 in NR.

24. The method according to claim 20, characterized in that, The first base matrix comprises p punched columns, and the value of the element at the position of the first punched column in the first of the p punched columns is determined according to any one of the following: The row index of the first newly added row in the first base matrix; The values ​​of the elements in the first row and the second row at the positions in the first punch column.

25. The method according to claim 24, characterized in that, The first newly added row is the nth row in the one or more newly added rows according to the row index in ascending order. The element at the nth (mod p) column of the first newly added row is 1, and the element at the other punched columns of the first newly added row is 0. n is an integer.

26. The method according to claim 20, characterized in that, The y-th row of the first basis matrix corresponds to the h-th row of the second basis matrix. The positions of the non-zero elements in the h-th row of the second basis matrix correspond to the first position set. The positions of the non-zero elements in the first newly added row correspond to the second position set. The second position set is a subset of the first position set, or the first position set is a subset of the second position set.

27. The method according to claim 26, characterized in that, The second set of positions is a subset of the first set of positions. The number of non-zero elements in the h-th row of the second base matrix is ​​x, and the number of non-zero elements in the first newly added row is a, where a is less than x. The a non-zero elements are distributed in the first newly added row in one of the following ways: The 'a' positions in ascending order of the column index; or, The a positions of the column index in descending order; or, The column indexes are in ascending order and adjacent column indexes differ by more than 1 at position a; or, The column indexes are ordered from largest to smallest, and the a positions of adjacent column indexes differ by more than 1.

28. The method according to claim 27, characterized in that, The h-th row of the second base matrix corresponds to a row in the row region corresponding to the information column region of BG1 or BG2 of the NR.

29. The method according to claim 20, characterized in that, The first set of positions is a subset of the second set of positions. The number of non-zero elements in the h-th row of the second base matrix is ​​x. The number of non-zero elements in the first newly added row is b, where b is greater than x. The positions of the b non-zero elements in the first newly added row include at least the positions of all non-zero elements in the h-th row of the second base matrix. The first newly added row is not adjacent to the y-th row of the first base matrix.

30. The method according to claim 29, characterized in that, The h-th row of the second base matrix corresponds to one row in the row region corresponding to the incremental redundancy region of BG1 or BG2 of the NR.

31. The method according to any one of claims 19-25, characterized in that, The first newly added row includes a first position, and the translation value corresponding to the first position is related to one or more of the following: the translation value of the nearest non-zero element to the first position, a preset constant, the row index corresponding to the first position, or the column index corresponding to the first position.

32. The method according to claim 31, characterized in that, The translation value corresponding to the first position is determined based on the following method: SV i,e = k + w i,e ; or, SV i,e = mod(k + w i,e , Z C ), wherein k is a translation value of a non-zero element in the first basis matrix closest to the first position, w i,e is the preset constant, or w i,e is a constant related to the row index i and / or the column index e of the first position (i, e), and e is any one of the column indices corresponding to the first basis matrix.

33. The method according to any one of claims 26-30, characterized in that, The first newly added row includes a first position, which corresponds to the e-th column. The translation value corresponding to the first position is related to one or more of the translation value of the h-th row of the second base matrix corresponding to the e-th column, a preset constant, the row index corresponding to the first position, or the column index corresponding to the first position.

34. The method according to claim 33, characterized in that, The translation value corresponding to the first position is determined based on the following method: SV i,e = k i′ + w i,e , wherein i' is a row index of the h-th row of the second base matrix, the first position corresponds to the e-th column, k i′ is a translation value corresponding to the position of the h-th row and the e-th column of the second base matrix, w i,e is a preset constant, or w i,e is a constant related to the row index i and / or the column index e of the first position (i, e), and e is any one of the column indexes corresponding to the first base matrix.

35. An encoding device, characterized in that, include: Processing module, used for: Obtain a first base matrix, which includes one or more newly added rows. The value of the element in the first newly added row is determined based on the value of the element in the first row and / or the second row of the first base matrix. The first row is the row before the first newly added row, and the second row is the row after the first newly added row. Alternatively, the value of an element in the first newly added row of the one or more newly added rows is determined based on the value of an element in the y-th row of the first base matrix, where the y-th row is any row in the first base matrix other than the one or more newly added rows, and y is a non-negative integer. The first matrix is ​​determined based on the first basis matrix and the translation values ​​corresponding to the elements in the first basis matrix; Encode the first matrix to obtain an encoded bit sequence; as well as A communication module is used to output the encoded bit sequence.

36. A decoding device, characterized in that, include: Processing module, used for: Obtain a first base matrix, which includes one or more newly added rows. The value of the element in the first newly added row is determined based on the value of the element in the first row and / or the second row of the first base matrix. The first row is the row before the first newly added row, and the second row is the row after the first newly added row. Alternatively, the value of an element in the first newly added row of the one or more newly added rows is determined based on the value of an element in the y-th row of the first base matrix, where the y-th row is any row in the first base matrix other than the one or more newly added rows, and y is a non-negative integer. The first matrix is ​​determined based on the first basis matrix and the translation values ​​corresponding to the elements in the first basis matrix; Based on the first matrix, the received value sequence is decoded to obtain the decoded bit sequence; as well as, A communication module is used to output the decoded bit sequence.

37. A communication device, characterized in that, The method includes a communication interface and a circuit. The communication interface is used to acquire information required to perform the method as described in any one of claims 1-17 and send the information to the circuit, which is used to perform the method as described in any one of claims 1-17 based on the received information. Alternatively, the communication interface is used to acquire information required to perform the method as described in any one of claims 18-34 and send the information to the circuit, which is used to perform the method as described in any one of claims 18-34 based on the received information.

38. A communication device, characterized in that, It includes modules or units for performing the method as described in any one of claims 1-17, or modules or units for performing the method as described in any one of claims 18-34.

39. A communication device, characterized in that, The device includes a processor coupled to a memory, the processor being configured to execute a computer program or instructions stored in the memory to cause the communication device to perform the method as described in any one of claims 1-17, or to cause the communication device to perform the method as described in any one of claims 18-34.

40. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, implement the method as described in any one of claims 1-17, or implement the method as described in any one of claims 18-34.

41. A computer program product, characterized in that, Includes a computer program or instructions for performing the method as described in any one of claims 1-17, or includes a computer program or instructions for performing the method as described in any one of claims 18-34.

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