Encoding method, decoding method, communication apparatus, and communication system

Abstract

The present application relates to the technical field of communications, and discloses an encoding method, a decoding method, a communication apparatus, and a communication system. On the basis of the method, a bit sequence is segmented on the basis of a first number of segments, wherein the first number of segments is M times a second number of segments. By expanding the number of segments, the code length of each segmented code block can be reduced, thereby facilitating improvement of error correction and error detection performance, and further improving LDPC decoding performance.

Description

An encoding method, a decoding method, a communication device, and a communication system.

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411981762.4, filed on December 26, 2024, entitled "An Encoding Method, Decoding Method, Communication Device and Communication System", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to an encoding method, a decoding method, a communication device, and a communication system. Background Technology

[0004] For business scenarios with large data volumes and high throughput requirements (such as mixed reality, virtual reality, cloud gaming, etc.), the amount of data to be decoded is large, and the requirements for decoding throughput are high. In order to support the decoding of a large number of information bits and achieve high decoding throughput, low-density parity check (LDPC) coding often uses a base matrix with a high code rate combined with a large lifting value for encoding.

[0005] Currently, the standard method is to double the boost value to support the encoding of longer information bit sequences. For example, the boost value is doubled from the standard-defined 288 to 576, thereby doubling the code length of LDPC to support the encoding of longer information bit sequences.

[0006] However, directly doubling the increment value may introduce bad LDPC structures, thus affecting the decoding performance of LDPC. Summary of the Invention

[0007] This application provides an encoding method, a decoding method, a communication device, and a communication system for improving the decoding performance of LDPC.

[0008] In a first aspect, embodiments of this application provide an encoding method, which can be executed by a first communication device. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, etc.), a component in the communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: determining a first segment number C1 based on a first threshold and a first condition, wherein the first segment number is M times a second segment number C2, where M is an integer greater than 1; the second segment number is related to the first threshold, which is the maximum number of encoded information bits, or the first threshold is related to the maximum length of the output of the distributed matcher; segmenting a first bit sequence according to the first segment number to obtain C1 code blocks; performing channel coding on the C1 code blocks to obtain an encoded second bit sequence; and outputting the second bit sequence.

[0009] Based on the above scheme, the bit sequence is segmented based on a first number of segments, which is M times the second number of segments. By increasing the number of segments, the code length of each segmented code block can be reduced, which helps to improve error correction and detection performance, and thus improves the decoding performance of LDPC.

[0010] Secondly, embodiments of this application provide a decoding method, which can be executed by a second communication device. Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, a network device, etc.), a component in the communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the communication device. The method includes: acquiring a first sequence to be decoded; determining a first number of segments C1 according to a first threshold and a first condition, wherein the first number of segments is M times the number of second segments C2, where M is an integer greater than 1, and the number of second segments is related to the first threshold, which is the maximum number of encoded information bits, or the first threshold is related to the maximum length of the output of the distributed matcher; segmenting the first sequence to be decoded according to the first number of segments to obtain C1 second sequences to be decoded; and performing channel decoding on the C1 second sequences to be decoded to obtain a decoded bit sequence.

[0011] Based on the above scheme, the bit sequence is segmented based on a first number of segments, which is M times the second number of segments. By increasing the number of segments, the code length of each segmented code block can be reduced, which helps to improve error correction and detection performance, and thus improves the decoding performance of LDPC.

[0012] When the first threshold is related to the maximum length of the output of the distribution matcher, since the first segmentation number is determined based on the first threshold, the length of each code block after segmentation does not exceed the first threshold, or the length of each code block after cascading a CRC does not exceed the first threshold. Therefore, after inputting each segmented code block to the distribution matcher, the distribution matcher does not need to perform further segmentation, which can improve the encoding speed and reduce the complexity of the encoder.

[0013] Based on the first or second aspect mentioned above, there are one or more possible implementation methods as follows:

[0014] In one possible implementation, determining the number of the first segments based on the first threshold and the first condition includes: determining the number of the second segments based on the first threshold; and determining the number of the first segments based on the first condition and the number of the second segments.

[0015] Based on the above scheme, when the first threshold is the maximum number of encoded information bits, the second segment number is first determined according to the first threshold to maintain compatibility with the existing protocol. Then, it is determined whether the first condition is met. If it is met, the first segment number is further determined according to the second segment number; otherwise, the second segment number is used. Therefore, this scheme is compatible with the existing protocol and requires minimal modification to the protocol.

[0016] In one possible implementation, the first condition includes one or more of the following:

[0017] The bitrate is greater than or equal to the bitrate threshold.

[0018] The boost values ​​used in the code block encoding belong to a first set, which is a subset of the boost value set; or,

[0019] In a high throughput scenario.

[0020] Based on the above scheme, when the first condition includes a code rate greater than or equal to a code rate threshold, better error correction performance can be provided in the high code rate range. When the first condition includes that the boost value used for code block encoding belongs to the first set, a more refined segmentation method can be provided, thereby improving encoding and decoding performance. When the first condition includes being in a high-throughput scenario, better encoding and decoding performance can be achieved in high-throughput scenarios.

[0021] In one possible implementation, the bit rate threshold is equal to 22 / 23.5.

[0022] Based on the above scheme, better error correction performance can be achieved in the high bit rate range, thereby improving decoding performance.

[0023] In one possible implementation, the promotion value in the first set is a positive integer multiple of X, where X takes the value 9, 11, or 13.

[0024] Based on the above scheme, the number of segments is determined by the boost value used. This method is more accurate and can better cover various code rates and code lengths, thus helping to accurately determine the number of segments and improve decoding performance.

[0025] In one possible implementation, the high-throughput scenario is defined as meeting one or more of the following conditions:

[0026] The index of the buffer status report (BSR) in the medium access control control element (MAC CE) is greater than or equal to the second threshold value;

[0027] The cache size value indicated by the index in the cache status report in MAC CE is greater than or equal to the third threshold value;

[0028] The number of code block groups (CBGs) is greater than or equal to the fourth threshold value;

[0029] The size of the transport block is greater than or equal to the fifth threshold value;

[0030] The number of the second segment is greater than or equal to the sixth threshold value;

[0031] The index of the modulation and coding scheme (MCS) is greater than or equal to the seventh threshold value;

[0032] The modulation order is greater than or equal to the eighth threshold value;

[0033] The spectral efficiency is greater than or equal to the ninth threshold.

[0034] Enable probabilistic shaping;

[0035] The operating frequency band is greater than or equal to the tenth threshold value;

[0036] The number of streams in a multiple input and multiple output (MIMO) system is greater than or equal to the eleventh threshold.

[0037] The required delay is less than or equal to the twelfth threshold value;

[0038] The required block error rate (BLER) is greater than or equal to the thirteenth threshold.

[0039] The maximum number of iterations for the decoding algorithm is less than or equal to the fourteenth threshold.

[0040] Enable limited buffer rate matching (LBRM);

[0041] The terminal's capabilities meet the preset conditions;

[0042] In an enhanced mobile broadband (eMBB) scenario; or,

[0043] The current work period is included in the preset work period.

[0044] In one possible implementation, the maximum number of encoded information bits is Y times 3840 or Y times 8448, where Y is an integer greater than 1.

[0045] Based on the above scheme, the maximum number of encoded information bits is increased to Y times 3840 or Y times 8448, which is the existing maximum number of encoded information bits. This allows for accurate determination of whether to segment the transmission block for transmission blocks with large information bits, reducing the additional overhead caused by unnecessary segmentation.

[0046] In one possible implementation, the C1 code blocks correspond to P code lengths and Q code rates, where P is an integer greater than or equal to 1 and Q is an integer greater than or equal to 1.

[0047] Based on the above solution, higher throughput can be supported, adapting to the needs of high-throughput application scenarios.

[0048] In one possible implementation, the C1 code blocks include multiple sets of code blocks, each set of code blocks contains M code blocks, the M code blocks in each set of code blocks correspond to the same code block cyclic redundancy check code, and the number of sets of code blocks is equal to the number of the second segment.

[0049] Based on the above scheme, multiple code blocks share a single cyclic redundancy check (CRC) code, which reduces the overhead of CRC bits in the message. The number of message bits that the decoder needs to decode is reduced, thus providing better error correction capability.

[0050] In one possible implementation, if the length of the C1 code blocks is less than the fifteenth threshold, then the M code blocks in each group of code blocks correspond to the same code block cyclic redundancy check code.

[0051] Based on the above scheme, when the number of message bits is small, the overhead of the required cyclic redundancy check bits is low. Therefore, when the code block length is less than the 15-threshold threshold, there is no need to add cyclic redundancy check bits to each code block. This reduces the overhead of cyclic redundancy check bits in the message, and the number of message bits that the decoder needs to decode is reduced, thereby obtaining better error correction performance.

[0052] In one possible implementation, each of the M code blocks is concatenated with a sub-block cyclic redundancy check (CRC) code.

[0053] Based on the above scheme, the false alarm rate is reduced by adding more cyclic redundancy check bits, thus achieving better error detection capability.

[0054] In one possible implementation, if the length of the C1 code blocks is greater than the fifteenth threshold, then the M code blocks in each group of code blocks correspond to the same code block cyclic redundancy check code, and each of the M code blocks is concatenated with a sub-code block cyclic redundancy check code.

[0055] Based on the above scheme, when the number of message bits is large, more cyclic redundancy check (CRC) bits need to be added to reduce the false alarm rate, thereby obtaining better error detection capability. Therefore, for longer code blocks, i.e., code block lengths greater than the fifteenth threshold, CRC bits can be added to each code block, which can provide better error detection capability.

[0056] Thirdly, embodiments of this application provide an encoding method, which can be executed by a first communication device. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: determining a number of segments (C) based on a first threshold, the first threshold being related to the maximum length of the output of the distributed matcher; segmenting a first bit sequence according to the number of segments to obtain C code blocks; performing channel coding on the C code blocks to obtain an encoded second bit sequence; and outputting the second bit sequence.

[0057] Based on the above scheme, since the number of segments is determined based on the first threshold, the length of each code block after segmentation does not exceed the first threshold, or the length of each code block after cascading with a CRC does not exceed the first threshold. The first threshold is related to the maximum length of the output of the distributed matcher. Therefore, after inputting each segmented code block into the distributed matcher, the distributed matcher does not need to perform further segmentation, which can improve the speed of encoding and decoding and reduce the complexity of the encoder and decoder.

[0058] In one possible implementation, the first bit sequence is a bit sequence obtained by concatenating the transport block and the transport block cyclic redundancy check code.

[0059] In one possible implementation, Where C represents the segment number, B represents the number of bits in the first bit sequence, and N... thr This represents the first threshold, where L represents the number of bits of the cyclic redundancy check (CRC) code contained in the C code blocks. This indicates rounding up to the nearest integer.

[0060] Fourthly, embodiments of this application provide a decoding method, which can be executed by a second communication device. Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, network device, etc.), a component within that communication device (e.g., a processor, chip, or chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: acquiring a first sequence to be decoded; determining a number of segments (C) based on a first threshold, the first threshold being related to the maximum length of the output of the distributed matcher; segmenting the first sequence to be decoded according to the number of segments to obtain C second sequences to be decoded; and performing channel decoding on the C second sequences to be decoded to obtain a decoded bit sequence.

[0061] Based on the above scheme, since the number of segments is determined based on the first threshold, the length of each code block after segmentation does not exceed the first threshold, or the length of each code block after cascading with a CRC does not exceed the first threshold. The first threshold is related to the maximum length of the output of the distributed matcher. Therefore, after inputting each segmented code block into the distributed matcher, the distributed matcher does not need to perform further segmentation, which can improve the speed of encoding and decoding and reduce the complexity of the encoder and decoder.

[0062] Fifthly, this application provides a communication device that has the functions described in the first and / or third aspects. For example, the communication device includes modules, units, or means corresponding to the operations described in the first and / or third aspects. The functions, units, or means can be implemented by software, or by hardware, or by hardware executing corresponding software.

[0063] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit may correspond to the operations involved in the first and / or third aspects described above.

[0064] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store necessary computer programs or instructions for implementing the functions described in the first and / or third aspects above. The processor can execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the first and / or third aspects above, when executed.

[0065] In one possible design, the communication device includes a processor and a memory, the memory of which may store necessary computer programs or instructions for implementing the functions involved in the first and / or third aspects described above. The processor may execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the first and / or third aspects described above.

[0066] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute the methods in any possible design or implementation of the first and / or third aspects described above. Optionally, the communication device further includes a memory for storing computer programs or instructions that, when executed by the processor, implement the methods in any possible design or implementation of the first and / or third aspects described above.

[0067] Understandably, the processor in the fifth aspect can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor or separated from it. In specific implementations, the memory can be integrated with the processor on the same chip or disposed on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0068] Sixthly, this application provides a communication device that performs the functions described in the second and / or fourth aspects above. For example, the communication device includes modules, units, or means corresponding to the operations described in the second and / or fourth aspects above. The functions, units, or means can be implemented by software, or by hardware, or by hardware executing corresponding software.

[0069] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit may correspond to the operations involved in the second and / or fourth aspects described above.

[0070] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store necessary computer programs or instructions for implementing the functions described in the second and / or fourth aspects above. The processor can execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the second and / or fourth aspects above, when executed.

[0071] In one possible design, the communication device includes a processor and a memory, the memory of which may store necessary computer programs or instructions for implementing the functions involved in the second and / or fourth aspects described above. The processor may execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the second and / or fourth aspects described above.

[0072] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute the methods in any possible design or implementation of the second and / or fourth aspects described above. Optionally, the communication device further includes a memory for storing computer programs or instructions that, when executed by the processor, implement the methods in any possible design or implementation of the second and / or fourth aspects described above.

[0073] Understandably, the processor in the sixth aspect can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor or separated from it. In specific implementations, the memory can be integrated with the processor on the same chip or disposed on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0074] In a seventh aspect, this application provides a communication system, which may include a first communication device and a second communication device; wherein the first communication device is used to perform the method described in the first aspect or any possible implementation of the first aspect, and the second communication device is used to perform the method described in the second aspect or any possible implementation of the second aspect.

[0075] Eighthly, this application provides a communication system, which may include a first communication device and a second communication device; wherein the first communication device is used to perform the method described in the third aspect or any possible implementation of the third aspect, and the second communication device is used to perform the method described in the fourth aspect or any possible implementation of the fourth aspect.

[0076] Ninthly, this application provides a computer-readable storage medium storing a computer program (or computer-readable instructions) in which, when a computer reads and executes some or all of the computer-readable instructions, the method in any of the possible designs of the first to fourth aspects described above is executed.

[0077] For example, a computer-readable storage medium can be any available medium that a computer can access. This includes, but is not limited to, non-transient computer-readable media, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage, magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer.

[0078] In a tenth aspect, this application provides a computer program product that, when read and executed by a computer, causes any of the possible designs in the first to fourth aspects described above to be performed.

[0079] In one aspect, this application provides a chip (or chip system) including a processor coupled to a memory storing a computer program; the processor is configured to invoke part or all of the computer program in the memory, such that any of the possible designs in the first to fourth aspects described above are executed. Attached Figure Description

[0080] Figure 1 is a schematic diagram of the architecture of the communication system applicable to the embodiments of this application;

[0081] Figure 2 is a schematic diagram of a processing flow of information source and information sink according to an embodiment of this application;

[0082] Figure 3 is a schematic diagram of another processing flow of the information source and the information sink in an embodiment of this application;

[0083] Figure 4 is an example diagram of a cyclic shift matrix according to an embodiment of this application;

[0084] Figure 5 is a schematic diagram of the structure of the base matrix in an embodiment of this application;

[0085] Figure 6 is a schematic diagram of the encoding chain in an embodiment of this application;

[0086] Figure 7 is a flowchart illustrating the encoding method provided in an embodiment of this application;

[0087] Figure 8 is an example diagram of secondary segmentation according to an embodiment of this application;

[0088] Figure 9 is another example of secondary segmentation in an embodiment of this application;

[0089] Figure 10 is a simulation diagram of the solution in this application;

[0090] Figure 11 is a flowchart illustrating the decoding method provided in an embodiment of this application;

[0091] Figure 12 is a flowchart illustrating the encoding method provided in an embodiment of this application;

[0092] Figure 13 is a schematic diagram of the encoding chain in an embodiment of this application;

[0093] Figure 14 is a flowchart illustrating the decoding method provided in an embodiment of this application;

[0094] Figure 15 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0095] Figure 16 is a schematic diagram of another communication device provided in an embodiment of this application. Detailed Implementation

[0096] In the embodiments of this application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0097] The technical solutions of this application can be applied to various wireless communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), short-range wireless communication systems (such as sidelink, wireless fidelity, Wi-Fi, Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, 4th generation (4G) mobile communication systems (such as Long Term Evolution (LTE) systems), LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, 5th generation (5G) mobile communication systems (such as New Radio (NR) systems), Future Communication Systems, or other similar communication systems, without limitation. This application describes the communication system shown in Figure 1 as an example. When applying the technical solution of this application to other communication systems, the devices, components, modules, etc. in the embodiment can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0098] Figure 1 is a schematic diagram of the architecture of the communication system applied in the embodiments of this application. As shown in Figure 1, the communication system includes an access network 100. Optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as 110a and 110b in Figure 1, and may also include at least one terminal device, such as 120a-120j in Figure 1. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop computer, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example, the mobile phones in Figure 1 are 120a, 120e, 120f and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can access micro-station 110b, connect to laptop 120g and printer 120h. Mobile phone 120j can control drone 120i.

[0099] (1) Network equipment

[0100] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device in a radio access network (RAN) that provides wireless communication capabilities to terminal devices; this is called RAN equipment. The RAN can be an access network within the 3rd Generation Partnership Project (3GPP), such as 4G, 5G, or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network combining two or more of these.

[0101] RAN equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc.

[0102] RAN equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) and packet data convergence protocol (PDCP) of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the radio link control (RLC) layer and medium access control (MAC) layer of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. The CU and DU can be set up separately, or they can be included in the same network element, such as in the baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the CU (or CU-CP, CU-UP), DU, and RU units in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. RAN equipment can be a macro base station (as shown in Figure 1, 110a), a micro base station or an indoor station (as shown in Figure 1, 110b), or a relay node or donor node, etc. The embodiments of this application do not limit the specific technology or equipment form used in the network equipment.

[0103] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0104] (2) Terminal equipment

[0105] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. They can be widely used in various scenarios, such as D2D communication, V2X communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. Terminal devices can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicle devices (such as vehicle units, in-vehicle modules, in-vehicle chips, on-board units (OBUs) or telematics boxes (T-BOXs), etc.), drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, satellite terminals, Internet of Things (IoT) terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability UE (REDCAP UE), etc. In the embodiments of this application, the device used to implement the functions of the terminal device can be the terminal device itself, or a device capable of supporting the terminal device in implementing that function, such as a chip system or a combination of devices or components capable of implementing the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form used in the terminal device.

[0106] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal device, or by a device containing the functions of the terminal device.

[0107] Network devices and terminal devices can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices.

[0108] The roles of network devices and terminal devices can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device. That is, 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol. In this case, relative to 110a, 120i is also a network device. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. 110a and 110b in Figure 1 can be called communication devices with network device functions, and 120a-120j in Figure 1 can be called communication devices with terminal device functions.

[0109] Network devices and terminal devices, network devices and network devices, and terminal devices can communicate through licensed spectrum, unlicensed spectrum, or both simultaneously, without limitation.

[0110] The network architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0111] The following is an explanation of the relevant terms used in the embodiments of this application. Unless otherwise specified, these explanations are provided to support the meaning of the relevant terms and to make the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0112] (1) Channel coding and channel decoding

[0113] Figure 2 illustrates a processing flow diagram for the source and sink. As shown in Figure 2, the transmitting end (i.e., the source) obtains the bit sequence to be encoded (i.e., the information bit sequence) through source encoding, and then performs channel encoding on the bit sequence to be encoded to obtain the encoded bit sequence. Correspondingly, after the receiving end (i.e., the sink) obtains the symbol sequence to be decoded, it performs channel decoding on the symbol sequence to be decoded to obtain the information bit sequence, and then performs source recovery on the information bit sequence to obtain useful information.

[0114] Since source coding does not consider interference resistance, if the bit sequence output from source coding is directly transmitted through the channel, noise interference in the channel will cause bit errors, reducing communication reliability. Therefore, channel coding, which encodes the bit sequence output from source coding again, can improve communication reliability. Channel decoding is the inverse process of channel coding.

[0115] There are various channel coding methods, such as polar coding or LDPC coding. Polar codes were selected as the control channel coding method in the 5G standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity, and have the advantages of good decoding performance and low complexity. LDPC codes were selected as the data channel coding method in the 5G standard. LDPC codes are linear block codes with a sparse parity-check matrix, which not only have good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure.

[0116] (2) Modulation and demodulation

[0117] As shown in Figure 2, the transmitting end can also map the encoded bit sequence to the modulation symbol sequence, and then transmit the modulation symbol sequence; correspondingly, the receiving end can receive the modulation symbol sequence and obtain the symbol sequence to be decoded by demodulation.

[0118] Modulation refers to the process by which the transmitting end maps the encoded bit sequence to a constellation based on a constellation diagram to obtain a modulated symbol sequence. Demodulation is the reverse process of modulation. Common modulation methods include quadrature amplitude modulation (QAM) and amplitude shift keying (ASK) modulation.

[0119] (3) Probability shaping

[0120] Higher-order modulation refers to mapping multiple bits to the same channel symbol, thereby further improving spectral efficiency. Common higher-order modulation schemes include 16QAM, 64QAM, and 256AM.

[0121] Probabilistic shaping is a common "shaping" technique. A typical flowchart is shown in Figure 3, which illustrates another processing flow between the source and destination. The main difference between Figure 3 and Figure 2 is that in Figure 3, the transmitting end needs to perform probabilistic shaping (or distribution matching), and the receiving end needs to perform deprobabilistic shaping (or dedistribution matching). As shown in Figure 3, by cascading a precoder before channel coding, the information bit sequence is mapped (or "shaped") to a bit sequence that follows a specific distribution. Therefore, the precoder is also called a distribution matcher (DM). Then, during channel coding, systematic coding is used so that the sequence satisfying the specific distribution ultimately appears directly in the coded sequence, thus shaping the final modulation symbol. In this application, probabilistic shaping can also be simply referred to as shaping; this will be used consistently here and will not be elaborated further later.

[0122] For example, for 500 information bits, 100 information bits are not probabilistically shaped, and the other 400 information bits are probabilistically shaped to obtain a bit sequence that follows a specific distribution, which includes 512 bits; then, channel coding is performed on the 100 information bits and the shaped 512 bits.

[0123] (4) LDPC code

[0124] LDPC codes can be represented using a basis matrix, where elements are either 0 or 1. Expanding the basis matrix by adding 1s results in a Zc*Zc cyclic shift matrix, and expanding by adding 0s results in a Zc*Zc zero matrix. This expansion yields a parity-check matrix, which can be used for encoding or decoding. Zc can be referred to as the lift value, lift factor, lift size, expansion factor, expansion value, or expansion coefficient. The basis matrix can be represented as H. BG BG is an abbreviation for base graph.

[0125] For example, if the element in the i-th row and j-th column of the basis matrix has a value of 1, then it corresponds to a shifting value (SV), which can be represented by P. i,j This represents the shift value corresponding to the i-th row and j-th column. A shift value can be used to calculate the corresponding number of cyclic shifts.

[0126] Taking Zc=4 as an example, the matrix obtained by cyclically shifting the 4*4 identity matrix to the right by 1, 2, 3, and 0 times respectively is shown in Figure 4. That is, the number of cyclic shifts are 1, 2, 3, and 0 respectively.

[0127] Currently, the 3GPP TS 38.212 protocol defines various values ​​for the lift size (Zc) as shown in Table 1.

[0128] Table 1

[0129] Referring to Table 1, the values ​​of the lifting dimension Zc can be... Where j represents the j-th row in Table 1, j = 0, 1, 2, 3, 4, 5, 6, 7, a0, a1, a2, a3, a 4, a 5, a6 and a7 are 2, 3, 5, 7, 9, 11, 13, and 15 respectively. k j The value of traverses from 0 to max(k) j ), where max(k0), max(k1), max(k2), max(k3), max(k4), max(k5), max(k6), and max(k7) are 7, 7, 6, 5, 5, 5, 4, and 4, respectively.

[0130] For example, if j = 0, then a0 = 2, and k0 iterates through 0 to 7, so the value of Zc can be 2*2. 0 ,2*2 1 ,2*2 2 ,2*2 3 ,2*2 4 ,2*2 5 ,2*2 6 ,2*2 7 That is, 2, 4, 8, 16, 32, 64, 128, 256. The cases where j takes values ​​from 1 to 7 are similar and will not be elaborated further.

[0131] The protocol also stipulates that each row of Zc in Table 1 corresponds to a set of SV. When constructing the parity check matrix, the size of Zc is first determined, then the set of SV corresponding to that Zc is determined, and then the parity check matrix is ​​constructed based on Zc and SV.

[0132] Table 2 below shows some examples of a set of SVs defined in the 3GPP 212 protocol.

[0133] Table 2

[0134] Table 2 shows the basis matrix H. BG The translation values ​​SV corresponding to the elements with a value of 1 in row 0 i,j The set index i in Table 2 LS That is, the set index i in Table 1 LS Furthermore, the basis matrix H BGThe cyclic shift value corresponding to each element with a value of 1 in row 0 can be obtained by taking the modulo of Zc using the corresponding translation value.

[0135] It should be noted that Table 2 only shows the translation values ​​corresponding to each element in row 0. In practice, it also includes the translation values ​​corresponding to each element in other rows (such as row 1, row 2, etc.).

[0136] Referring to Table 2, when Zc takes the values ​​2, 4, 8, 16, 32, 64, 128, or 256, then i LS =0, basis matrix H BG The SV values ​​of the elements with a value of 1 in row 0 are 250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0. Assuming Zc = 4, then the basis matrix H... BG The cyclic shift counts corresponding to the elements with a value of 1 in row 0 are 250 mod 4, 69 mod 4, 226 mod 4, 159 mod 4, 100 mod 4, 10 mod 4, 59 mod 4, 229 mod 4, 110 mod 4, 191 mod 4, 9 mod 4, 195 mod 4, 23 mod 4, 190 mod 4, 35 mod 4, 239 mod 4, 31 mod 4, 1 mod 4, 0 mod 4, which are 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0. This means that the 4x4 identity matrix is ​​cyclically shifted 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0 times to obtain the basis matrix H. BG The elements in row 0 that have a value of 1 correspond to a 4x4 matrix. For the basis matrix H... BG If the elements in row 0 have a value of 0, then update them to a zero matrix of size 4*4.

[0137] Similarly, for other values ​​of Zc, there are corresponding translation values ​​and cyclic shift counts, as detailed in Table 2.

[0138] Similarly, for the basis matrix H BG The rows other than row 0 are also determined using a similar method to determine the corresponding Zc*Zc matrix.

[0139] In this embodiment, the lifting and translation operations of the LDPC code are described as follows: For a given lifting size Zc, from the basis matrix H... BG Upgraded to the parity check matrix H, specifically, the basis matrix H BG t in i,j (where t) i,j=1) will be replaced with a Zc×Zc matrix I(P) i,j ), where I(P i,j ) is a cyclic shift of the identity matrix I of Zc×Zc by P i,j One (either left or right circular shift is possible) or circular shift P i,j A matrix of degree mod Zc, P i,j The translation value corresponding to the i-th row and j-th column; basis matrix H BG The zeros in H will be replaced with a Zc×Zc matrix of all zeros. It can be seen that the purpose of lifting is to improve the basis matrix H. BG To transform it into a larger parity check matrix H, the translation aims to shift each H... BG The identity matrix corresponding to the non-zero elements is cyclically shifted into a predefined matrix.

[0140] The structure of the base matrix adopted in NR is shown in Figure 5, and is briefly described below: Part A corresponds to the high bitrate information column region, Part B corresponds to the high bitrate core verification region, Part C is a 0 matrix, Region D is the incremental redundancy part of the matrix, corresponding to the low bitrate matrix, and Part E is the incremental redundancy region, which is an identity matrix structure.

[0141] Specifically, when the basis matrix is ​​BG1, it is a matrix with 46 rows and 68 columns. When the basis matrix is ​​BG2, it is a matrix with 42 rows and 52 columns.

[0142] (5) Rate matching

[0143] Rate matching refers to removing some bits from the encoded bit sequence without transmitting them, or repeating some bits.

[0144] The rate matching method will be further explained in three categories below.

[0145] Punching: Punching refers to directly creating holes in certain bit positions within the encoded bit sequence without transmitting them, thus generating bit sequences of arbitrary length. On the decoding side, since there is no information at the corresponding punctured positions, the log-likelihood ratio (LLR) of the corresponding bit is set to 0.

[0146] Shortening: Shortening involves fixing certain bit positions in the encoded bit sequence so that they do not need to be transmitted. On the decoding side, since the corresponding "shortened" positions are known at the receiver (usually 0), the LLR of the corresponding bit is set to infinity.

[0147] Repetition: "Repetition" refers to obtaining a longer bit sequence by repeatedly sending a portion of the encoded bit sequence.

[0148] For rate matching in NR LDPC, a puncturing rate matching method can be used for the first two columns of the NR BG, meaning that the information bits corresponding to the first two columns of the NR LDPC base map are not transmitted; for the information columns other than the first two columns of the NR BG, a shortening rate matching method is used, meaning that if the boost value multiplied by the number of information columns is greater than the actual number of information bits, then the information columns other than the first two columns of the NR BG are shortened; if the code rate is very low, a repetitive transmission rate matching method can be used.

[0149] (6) Encoding chain

[0150] An encoding chain consists of multiple operations performed by the sending end when encoding the information bits to be sent.

[0151] Figure 6 is a schematic diagram of the encoding chain. The encoding chain includes the following operations:

[0152] (a) Generate a transport block (TB) of A bits from the MAC layer, using... It means that, among them, This transport block is also called the payload bit sequence or payload sequence.

[0153] (b) TB-Cyclic Redundancy Check (CRC) Attachment Module Perform CRC encoding, which is also... Concatenating P bits of TB-CRC code yields a bit sequence of length B = A + P. in, For example, P equals 16 or 24, etc.

[0154] (c) The code block segmentation and code block CRC attachment module... The code blocks are segmented to obtain C segments of payload code blocks that do not contain CB-CRC codes. Then, CRC encoding is performed on each of these C segments, i.e., CB-CRC codes are concatenated to obtain C segments of code blocks with a length of K. in,

[0155] Currently, the segmentation of LDPC codes in the NR standard is mainly based on the maximum number of coded information bits K supported by the LDPC base map. cb The transport block (TB) is segmented. Specifically, firstly, a base map BG is selected for encoding based on the TB size A and the code rate R. If A ≤ 292, or A ≤ 3824 and R ≤ 2 / 3, or R ≤ 1 / 4, then BG2 is selected as the base map for LDPC encoding; otherwise, BG1 is selected. If BG1 is selected, then according to K... cb =8448 segments TB. If BG2 is selected, then according to K cb =3840 segments were used to divide TB.

[0156] Since segmentation of the Test Block (TB) affects its error correction performance, it is necessary to ensure that the error correction capabilities of each segmented codeword are as similar as possible, and to prevent any poorly performing codeblocks from becoming bottlenecks in TB performance. The segmentation process defined in the current protocol is described as follows:

[0157] Where B represents the bit sequence following the P-bit TB-CRC code concatenated from a transport block consisting of A bits. The number of bits, i.e., B = A + P. C represents the number of code blocks after segmentation. K cb This represents the maximum number of encoded information bits in each code block after segmentation. L represents the number of CB-CRC bits concatenated in each segmented code block. B′ represents the total number of bits in the C segmented code blocks. This indicates rounding up to the nearest integer.

[0158] (d) The channel coding module Perform channel coding and output C segments, each with a code length of N. m The channel-coded codeword, N m This is the length of the mother code of the channel-coded codeword. The channel coding method can be low-density parity check (LDPC) coding or polar coding, etc.

[0159] (e) The rate matching module matches each segment of length N. m The channel-coded codewords are rate-matched, and the rate-matching method can be any of the following: puncturing, shortening, or repetition. The codeword length after rate matching is from N... m If the rate matching method is punching or shortening, then E is less than N. m If the rate matching mode is repetitive, then E is greater than or equal to N. m After rate matching, a rate-matched code block of length E will be obtained, consisting of segment C. in,

[0160] (f) The bit interleaving module performs bit interleaving on the C-segment rate-matched code blocks to obtain interleaved C-segment code blocks. in,

[0161] (g) The code block concatenation module concatenates the interleaved code blocks of segment C to obtain a bit sequence of length G. in G represents the total number of encoded bits that need to be transmitted, and G = C * E.

[0162] (h) The modulation and resource element mapping module modulates the concatenated bit sequence into quadrature amplitude modulation (QAM) symbols and then maps them onto physical time-frequency resources for transmission.

[0163] The operations performed by the TB-CRC addition module, as well as the code block segmentation and code block CRC addition module, can be understood as part of the source coding shown in Figures 2 and 3. The operations performed by the rate matching module, bit interleaving module, and code block concatenation module can be understood as the operations between channel coding and modulation shown in Figures 2 and 3.

[0164] For business scenarios with large data volumes and high throughput requirements (such as mixed reality, virtual reality, cloud gaming, etc.), the amount of data to be decoded is large, and the requirements for decoding throughput are high. In order to support the decoding of a large number of information bits and achieve high decoding throughput, LDPC encoding often uses a base matrix with a high code rate combined with a large boost value for encoding.

[0165] Currently, the standard lifting value is typically doubled to support the encoding of longer information bit sequences. For example, the lifting value is doubled from the standard-defined 288 to 576, thereby doubling the code length of LDPC to support the encoding of longer information bit sequences.

[0166] However, directly doubling the increment value may introduce bad LDPC structures, thus affecting the decoding performance of LDPC.

[0167] To address the aforementioned issues, this application provides corresponding solutions.

[0168] The methods provided in the embodiments of this application are described in detail below. The methods provided in the embodiments of this application involve a first communication device and / or a second communication device. The first communication device is a signal transmitter, and the second communication device is a signal receiver. Unless otherwise specified, the term "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. Similarly, the term "second communication device" in this application can refer to a communication device (e.g., a terminal device, a network device, a decoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. For example, the first communication device may be a network device, and the second communication device may be a terminal device; or, the first communication device may be a terminal device, and the second communication device may be a network device.

[0169] Figure 7 is a flowchart illustrating an encoding method provided in an embodiment of this application. This method is an implementation method on the encoding side, and includes the following steps:

[0170] Step 701: The first communication device determines the first segment number (C1) based on the first threshold and the first condition.

[0171] In one implementation, the first threshold is the maximum number of encoded information bits. For example, for LDPC base map 1, the maximum number of encoded information bits is 8848 or a multiple of 8448, where Y is an integer greater than 1. For another example, for LDPC base map 2, the maximum number of encoded information bits is a multiple of 3840 or a multiple of 3840, where Y is an integer greater than 1.

[0172] In another implementation, the first threshold is related to the maximum length of the distributed matcher's output. For example, the first threshold is equal to the maximum length of the distributed matcher's output, or equal to the maximum length of the distributed matcher's output minus 1, and so on. The function of the distributed matcher can be found in the preceding description. Since the first segmentation number is determined based on the first threshold, the length of each segmented code block does not exceed the first threshold, or the length of each code block concatenated with a CRC does not exceed the first threshold. Since the first threshold is related to the maximum length of the distributed matcher's output, after inputting the segmented code blocks to the distributed matcher, the distributed matcher does not need to perform further segmentation, which improves encoding speed and reduces encoder complexity.

[0173] Where the number of the first segment C1 is M times the number of the second segment C2, where M is an integer greater than 1, and the number of the second segment is related to the first threshold. For example, the number of the second segment is equal to... Where B represents the bit sequence following the P-bit TB-CRC code concatenated from a transport block consisting of A bits. The number of bits, L represents the number of bits in the CB-CRC code.

[0174] As one implementation method, step 701 can specifically be: the first communication device determines the second number of segments based on the first threshold, and then determines the first number of segments based on the first condition and the second number of segments. Specifically, determining the first number of segments based on the first condition and the second number of segments means determining the first number of segments based on the second number of segments while satisfying the first condition.

[0175] As one implementation method, the first condition includes one or more of the following:

[0176] (1) The bit rate is greater than or equal to the bit rate threshold.

[0177] Here, the code rate can be the effective code rate, that is, the code rate corresponding to the transport block, which is equal to A / N, where A represents the number of bits in the transport block and N represents the code length; or the code rate can be the bit sequence after concatenating P bits of TB-CRC code in the transport block. The corresponding bitrate, that is, the bitrate is equal to B / N, where B represents The number of bits, where N represents the code length.

[0178] For example, the bit rate threshold values ​​are 22 / 23.5, 22 / 24, 22 / 25, 22 / 26, 948 / 1024, 910 / 1024, and 873 / 1024.

[0179] (2) The boost values ​​used in the code block encoding belong to the first set, which is a subset of the boost value set.

[0180] The lift set refers to the complete set of all possible lift values.

[0181] For example, the promotion values ​​in the first set are positive integer multiples of X, where X takes the values ​​9, 11, or 13. That is, the promotion values ​​in the first set include 9*i, 11*i, and 13*i, where i = 1, 2, 3, 4, ...

[0182] (3) In a high throughput scenario.

[0183] For example, a high-throughput scenario is defined as one or more of the following conditions being met:

[0184] a) The cache status report index (BSR index) in MAC CE is greater than or equal to the second threshold value.

[0185] For example, for Short BSR and Short Truncated BSR MAC-CE, the second threshold value can be 31.

[0186] For example, for long BSR and long truncated BSR MAC-CE, the second threshold value can be 153 or 154, etc.

[0187] MAC CE buffer status reports can be obtained by the terminal device reporting to the network device. The second threshold value corresponds to the BSR index. In MAC-CE with short BSR and short truncated BSR, the buffer size value corresponding to BSR index = 31 is 150,000 bytes, or 1,200,000 bits. Segmented according to LDPC BG1 encoding, this yields more than 140 code blocks. This number of code blocks often corresponds to the data volume in high-throughput scenarios, and therefore can be used to determine whether it is a high-throughput scenario. In MAC-CE with long BSR and long truncated BSR, the buffer size value corresponding to BSR index = 154 is 160793 bytes, or 1286344 bits, and the buffer size value corresponding to BSR index = 153 is 150992 bytes, or 1207936 bits. Segmented according to LDPC BG1 encoding, the number of corresponding code blocks exceeds 140 blocks, thus reaching the data volume required for high-throughput scenarios and can be used to determine whether a scenario is high-throughput. b) The cache size value indicated by the index in the cache status report in MAC CE is greater than or equal to the third threshold value.

[0188] For example, for Short BSR and Short Truncated BSR MAC-CE, the third threshold value can be 1,200,000 bits.

[0189] For example, for Long BSR and Long Truncated BSR MAC-CE, the third threshold value can be 1207936 or 1286344 bits.

[0190] For example, for conditions a) and b), the network device determines whether it is a high-throughput scenario based on the MAC CE reported by the terminal. If it is a high-throughput scenario, the network device determines the number of the first segment based on the number of the second segment when sending downlink data; after the terminal reports the MAC CE, it determines the number of the first segment based on the number of the second segment when transmitting uplink data based on the uplink scheduling of the network device. c) The number of CBGs is greater than or equal to the fourth threshold value.

[0191] For example, the fourth threshold value is 6, and so on.

[0192] For example, the maximum code block group (maxCodeBlockGroupPerTransportBlock) in the physical uplink shared channel (PUSCH) code block group transmission / physical downlink shared channel (PDSCH) code block group transmission (PUSCH-CodeBlockGroupTransmission / PDSCH-CodeBlockGroupTransmission) indicated by the network side can be used to indicate the number of CBGs.

[0193] d) The size of the transport block is greater than or equal to the fifth threshold value.

[0194] For example, the fifth threshold value is 1,267,200 bits or 1,689,600 bits.

[0195] e) The number of the second segment is greater than or equal to the sixth threshold value.

[0196] For example, the sixth threshold value can be 100, 140, or 150, etc.

[0197] In high-throughput scenarios, the amount of data transmitted between the first and second communication devices is generally large, and the corresponding number of code blocks (segments) is also large. For example, no less than 100 code blocks can be used, such as 140 or 150 code blocks.

[0198] f) The index of the MCS is greater than or equal to the seventh threshold value.

[0199] For example, the seventh threshold value can be 19, 20, 21, 22, 23, 24, 25, 26, 27 or 28.

[0200] In high-throughput scenarios, network devices often schedule modulation and coding schemes (MCSs) with high spectral efficiency, such as requiring a spectral efficiency greater than 5. The correspondence between the MCS index and spectral efficiency defined in the current protocol is shown in Table 3. Assuming a high-throughput scenario requires a spectral efficiency greater than 5, the MCS index needs to be greater than or equal to 19.

[0201] Table 3

[0202] g). The modulation order (Q_m) is greater than or equal to the eighth threshold.

[0203] For example, the eighth threshold value can be 8, 10, or 12. Among them, 8 corresponds to QAM256, 10 corresponds to QAM1024, and 12 corresponds to QAM4096.

[0204] In high-throughput scenarios, higher modulation orders are often scheduled. For example, the modulation order can be 256QAM, 1024QAM, or 4096QAM.

[0205] h) The spectral efficiency is greater than or equal to the ninth threshold.

[0206] For example, the ninth threshold value can be 6, 7, 7.5 or 8.

[0207] In high-throughput scenarios, MCSs with high spectral efficiency are often scheduled. For example, high spectral efficiency can refer to a spectral efficiency value greater than or equal to 6.

[0208] i) Enable probabilistic shaping.

[0209] To achieve higher spectral efficiency, high throughput may also employ probabilistic shaping technology. When a terminal device enables or supports probabilistic shaping, it can report this capability or whether probabilistic shaping is enabled to the network device, which will then send a probabilistically shaped signal to the terminal device.

[0210] In the uplink scenario, the first communication device (e.g., a terminal device) can carry an indication of whether probabilistic shaping is currently enabled in the uplink control information (UCI). If the second communication device (e.g., a network device) detects the indication in the UCI that probabilistic shaping is being used, then probabilistic shaping is used for decoding.

[0211] In the downlink scenario, the first communication device (e.g., network device) can carry an indication of whether to use probability shaping in the downlink control information (DCI). If the second communication device (e.g., terminal device) detects the indication of using probability shaping in the DCI, then probability shaping is used for demodulation.

[0212] j) The operating frequency band is greater than or equal to the tenth threshold value.

[0213] For example, the tenth threshold value is 24GHz or 24.25GHz.

[0214] In high-throughput scenarios, communication bandwidth is often very wide, and the broadband operating frequency band will not be too low. For example, it can be greater than or equal to 24GHz, such as 24.25GHz. The terminal device can send the supported operating frequency band as capability information to the network device, and the network device communicates with the terminal device in the corresponding frequency band.

[0215] k) The number of streams in a MIMO is greater than or equal to the eleventh threshold.

[0216] For example, the eleventh threshold value can be 4, 5, 6 or 12.

[0217] In high-throughput scenarios, the number of MIMO flows is often large. Terminal devices can report the number of MIMO flows to network devices through RRC or MAC CE. The typical value of the number of MIMO flows can be greater than or equal to 4.

[0218] l) The required delay is less than or equal to the twelfth threshold value.

[0219] For example, the twelfth threshold value can be 1ms or 0.5ms.

[0220] High-throughput scenarios often have high requirements for transmit and receive latency, such as transmit and receive latency of less than 1ms.

[0221] m). The required block error rate is greater than or equal to the thirteenth threshold.

[0222] For example, the thirteenth threshold value is 10. -2 Or 10 -3 .

[0223] In high-throughput scenarios, the block error rate is often not low, for example, not less than 0.001.

[0224] n). The maximum number of iterations for the decoding algorithm is less than or equal to the fourteenth threshold.

[0225] For example, the fourteenth threshold value can be 5, 6, 7, 8, 9 or 10.

[0226] In high-throughput scenarios, LDPC encoding can be used for data encoding. In order to achieve high throughput, LDPC encoding usually does not use a high number of iteration rounds. For example, the number of iteration rounds will not exceed 10 rounds.

[0227] o). Enable LBRM.

[0228] In high-throughput scenarios, the amount of data is often very large. For the receiving end (i.e., the second communication device), with limited buffer capacity, it may be necessary to enable LBRM to receive the data.

[0229] p). The terminal's capabilities meet the preset conditions.

[0230] The terminal's capabilities meet preset conditions, which may include one or more of the following: the maximum decoding length supported by the terminal is greater than a preset threshold, the highest bit rate supported by the terminal is greater than a preset threshold, or the service type requested by the terminal is a preset service type.

[0231] For example, if the first communication device is an access network device and the second communication device is a terminal, the terminal can report the maximum decoding length it supports to the access network device via signaling. The access network device can determine whether the maximum decoding length supported by the terminal is greater than a preset threshold. If it is greater than the preset threshold, it is determined that the terminal is in a high-throughput scenario.

[0232] For example, if the first communication device is an access network device and the second communication device is a terminal, the terminal can report its maximum supported bit rate to the access network device via signaling. The access network device can determine whether the terminal's maximum supported bit rate is greater than a preset threshold. If it is greater than the preset threshold, it is determined that the terminal is in a high-throughput scenario.

[0233] For example, the first communication device is an access network device, and the second communication device is a terminal. The access network device determines that the service type requested by the terminal is a preset service type (such as hybrid virtual reality service or cloud gaming service).

[0234] q). In an eMBB scenario.

[0235] r). The current working period is included in the preset working period.

[0236] Step 702: The first communication device segments the first bit sequence according to the first segment number to obtain C1 code blocks.

[0237] For example, the first bit sequence is a bit sequence obtained by concatenating a transport block (TB) and a transport block cyclic redundancy check (TB-CRC) code.

[0238] In one possible implementation, C1 code blocks correspond to P code lengths and Q code rates, where P is an integer greater than or equal to 1 and Q is an integer greater than or equal to 1. For example, P = Q = 2. The code rates of the first C1-1 code blocks in the C1 code block are the same and greater than the code rate of the C1th code block, and the code length of the first C1-1 code blocks is greater than the code length of the C1th code block. This method can minimize or eliminate rate matching, thereby improving decoding throughput.

[0239] As one implementation method, the C1 code blocks include multiple sets of code blocks, each set containing M code blocks. Each set of code blocks corresponds to the same code block cyclic redundancy check (CB-CRC) code, and the number of sets of code blocks is equal to the number of the second segments. For example, referring to the example in Figure 8, a TB-CRC code consisting of A bits concatenated with P bits is used to obtain a bit sequence of length B = A + P. Then the bit sequence The first segmentation yields C2 bit sequences, and a CB-CRC is concatenated to each bit sequence, resulting in C2 code blocks. C2 is the number of the second segmentation. Then, each code block is segmented a second time to obtain M code blocks, ultimately resulting in C1 code blocks, where C1 = M * C2. The diagram uses M = 2 as an example. It can be seen that after the two segmentations, every M code blocks correspond to one CB-CRC. Some or more of these M code blocks contain the CB-CRC, while others do not. Based on this implementation method, multiple code blocks share a single CB-CRC, reducing the overhead of CRC bits in the message. This reduces the number of message bits the decoder needs to decode, thus providing better error correction capabilities.

[0240] As another implementation method, based on the segmentation method described above, a new CRC can be concatenated to each code block after two segmentations, called sub-code block-CRC (SCB-CRC). For example, in the example of Figure 8, each code block (or sub-code block) after two segmentations can be concatenated with an SCB-CRC to obtain C1 code blocks as shown in Figure 9. Based on this implementation method, the false alarm rate is reduced by adding more cyclic redundancy check bits, thus achieving better error detection capability.

[0241] As one implementation method, if the length of each of the C1 code blocks (i.e., each code block after secondary segmentation) is less than the fifteenth threshold, then SCB-CRC is not concatenated for that code block. If the length of each of the C1 code blocks (i.e., each code block after secondary segmentation) is greater than the fifteenth threshold, then SCB-CRC is concatenated for that code block. If the length of each of the C1 code blocks (i.e., each code block after secondary segmentation) is equal to the fifteenth threshold, then SUB-CRC can be concatenated for that code block, or SCB-CRC can be omitted. Based on this implementation method, a balance can be achieved between error correction and error detection capabilities, resulting in good error correction and detection capabilities.

[0242] Step 703: The first communication device performs channel coding on C1 code blocks to obtain the encoded second bit sequence.

[0243] Here, the second bit sequence refers to the bit sequence obtained by concatenating the channel-coded code blocks from the C1 code blocks. Taking the example in Figure 8, the C1 code blocks are channel-coded to obtain C1 encoded bit sequences, and then these C1 encoded bit sequences are concatenated to obtain the second bit sequence.

[0244] Here, the channel coding can be, for example, LDPC channel coding.

[0245] Step 704: The first communication device outputs the second bit sequence.

[0246] The output here refers to the encoder in the first communication device outputting the second bit sequence to other devices, such as a rate matcher, interleaver, or modem; or it can refer to the first communication device outputting the second bit sequence to other devices, such as a transceiver; or the output here can refer to transmission over the air interface.

[0247] Based on the above scheme, the bit sequence is segmented based on a first number of segments, which is M times the second number of segments. By increasing the number of segments, the code length of each segmented code block can be reduced, which helps to improve error correction and detection performance, and thus improves the decoding performance of LDPC.

[0248] Figure 10 is a simulation diagram of the scheme in this application. The horizontal axis represents the signal-to-noise ratio (SNR), and the vertical axis represents the block error ratio (BLER), with an effective code rate of 22 / 23.5 as an example. The dashed curve represents the decoding performance when a 2x boost is used. The solid curve represents the decoding performance when the number of segments is increased without using a 2x boost. It can be seen that to achieve the same BLER, the scheme in this application has a smaller SNR than the scheme using a 2x boost, meaning it requires less transmission power and therefore has a significant gain. (BLER is set to 10.) -2 For example, the SNR of the proposed solution has a gain of 0.5 dB compared to the solution using a 2x boost value.

[0249] As an example, the following provides a specific implementation method for determining the number of the first segment and the number of the second segment in the embodiment of Figure 7 above.

[0250] Example 1

[0251] Where B represents the bit sequence following the P-bit TB-CRC code concatenated from a transport block consisting of A bits. The number of bits in the first bit sequence (i.e., B = A + P). K' represents the first threshold. L represents the number of bits in the CB-CRC concatenation of each segment after the first segmentation. This indicates rounding up. R represents the bitrate. thr This represents the bitrate threshold. The number of the second segment is equal to... The number of segments in the first segment is equal to twice the number of segments in the second segment.

[0252] In Example 1, if the current scheduled code rate is high, exceeding the preset code rate threshold, each segmented code block is further divided into two code blocks, also known as sub-code blocks. These two shorter sub-code blocks are then encoded into two LDPC short codes. This example can provide better error correction performance in high code rate ranges.

[0253] Example 2

[0254] Where B represents the bit sequence following the P-bit TB-CRC code concatenated from a transport block consisting of A bits. The number of bits in the first bit sequence (i.e., B = A + P). K' represents the first threshold. L represents the number of bits in the CB-CRC concatenation of each segment after the first segmentation. This indicates rounding up. SV represents the boost value used, and SET represents the first set mentioned above, which consists of multiples of 9, 11, and 13. The second segment number is equal to... The number of segments in the first segment is equal to twice the number of segments in the second segment.

[0255] For Example 2, after obtaining C2 code blocks in the first segmentation, it is determined whether to further divide each code block after the first segmentation into multiple smaller code blocks (or sub-code blocks) based on the boost value used by the current code block. This determination method is more refined and can better cover more code rate and code length scenarios, thus achieving better performance.

[0256] Example 3

[0257] The meaning of the parameters in this example is similar to that in Examples 1 and 2. The condition for determining whether a second segmentation is needed in Example 3 is a combination of the conditions in Example 1 and Example 2, that is, when R ≥ R thr And if SV∈SET, then the second segmentation means that each code block after the first segmentation is further divided into 2 code blocks.

[0258] In Example 3, the conditions for further segmentation are more stringent; segmentation only occurs when both the bit rate and boost value meet the corresponding conditions. This example enables precise segmentation, which helps improve decoding performance.

[0259] Figure 11 is a flowchart illustrating a decoding method provided in an embodiment of this application. This method is an implementation method on the decoding side, and includes the following steps:

[0260] Step 1101: The second communication device acquires the first sequence to be decoded.

[0261] For example, the second communication device receives the first sequence to be decoded from the first communication device, or receives the information to be decoded from the first communication device and demodulates the information to be decoded to obtain the first sequence to be decoded.

[0262] Step 1102: The second communication device determines the first segment number (C1) based on the first threshold and the first condition.

[0263] The number of segments in the first segment is M times the number of segments in the second segment, where M is an integer greater than 1. The number of segments in the second segment is related to the first threshold, which is either the maximum number of encoded information bits or the maximum length of the output of the distributed matcher.

[0264] Step 1103: The second communication device segments the first sequence to be decoded according to the first segment number to obtain C1 second sequences to be decoded.

[0265] The specific implementation methods of steps 1102 and 1103 are the same as steps 701 and 702 in the embodiment of Figure 7 above, and can be referred to the foregoing description.

[0266] Step 1104: The second communication device performs channel decoding on C1 second sequences to be decoded to obtain the decoded bit sequences.

[0267] For example, channel decoding could be LDPC channel decoding.

[0268] The decoded bit sequence can be an information bit sequence.

[0269] Based on the above scheme, the bit sequence is segmented based on a first number of segments, which is M times the second number of segments. By increasing the number of segments, the code length of each segmented code block can be reduced, which helps to improve error correction and detection performance, and thus improves the decoding performance of LDPC.

[0270] Figure 12 is a flowchart illustrating an encoding method provided in an embodiment of this application. This method is an implementation method on the encoding side, and includes the following steps:

[0271] Step 1201: The first communication device determines the number of segments (C) according to the first threshold.

[0272] The first threshold is related to the maximum length of the distributed matcher's output. For example, the first threshold may be equal to the maximum length of the distributed matcher's output, or equal to the maximum length of the distributed matcher's output minus 1, and so on. For an explanation of the function of the distributed matcher, please refer to the preceding description.

[0273] For example, Where C represents the number of segments, B represents the number of bits in the first bit sequence, and N... thrThis indicates the first threshold, and L represents the number of CB-CRC bits contained in the C code blocks after segmentation. This indicates rounding up to the nearest integer.

[0274] Step 1202: The first communication device segments the first bit sequence according to the number of segments to obtain C code blocks.

[0275] For example, the first bit sequence is a bit sequence obtained by concatenating a transport block (TB) and a transport block cyclic redundancy check (TB-CRC) code.

[0276] Step 1203: The first communication device performs channel coding on C code blocks to obtain the encoded second bit sequence.

[0277] The second bit sequence refers to the concatenated bit sequence obtained by channel coding each of the C code blocks. For example, after segmenting the first bit sequence, C code blocks are obtained. Each of these C code blocks can be concatenated with a CB-CRC. Then, channel coding is performed on each of the C code blocks (or the C concatenated CB-CRC code blocks) to obtain C encoded bit sequences. Finally, these C encoded bit sequences are concatenated to obtain the second bit sequence.

[0278] Here, the channel coding can be, for example, LDPC channel coding.

[0279] Step 1204: The first communication device outputs the second bit sequence.

[0280] The output here refers to the encoder in the first communication device outputting the second bit sequence to other devices, such as a rate matcher, interleaver, or modem; or it can refer to the first communication device outputting the second bit sequence to other devices, such as a transceiver; or the output here can refer to transmission over the air interface.

[0281] Based on the above scheme, since the number of segments is determined based on the first threshold, the length of each code block after segmentation does not exceed the first threshold, or the length of each code block after cascading with a CRC does not exceed the first threshold. The first threshold is related to the maximum length of the output of the distributed matcher. Therefore, after inputting each segmented code block into the distributed matcher, the distributed matcher does not need to perform further segmentation, which can improve the speed of encoding and decoding and reduce the complexity of the encoder and decoder.

[0282] The following is a specific example of determining the number of segments C.

[0283] Where B represents the bit sequence following the P-bit TB-CRC code concatenated from a transport block consisting of A bits. The number of bits in the first bit sequence (i.e., B = A + P). C represents the number of code blocks after segmentation. K” equals the maximum length of the distributed matcher output. L represents the number of bits of the CB-CRC code concatenated in each segmented code block. This indicates rounding up to the nearest integer.

[0284] It can be seen that the length of the code block after each segmented code block is concatenated with an L-bit CB-CRC does not exceed the maximum length of the output of the distributed matcher. Therefore, when each segmented code block is input to the distributed matcher, the distributed matcher does not need to further segment each code block, thus improving the encoding speed and reducing the complexity of the encoder.

[0285] The following, with reference to Figure 13, provides a specific implementation of the embodiment of Figure 12. The encoding process in Figure 13 includes the following operations:

[0286] (a) A transport block (TB) consisting of A bits, using It means that, among them, This transport block is also called the payload bit sequence or payload sequence.

[0287] (b) TB-CRC add (attachment) module Perform CRC encoding, which is also... Concatenating P bits of TB-CRC code yields a bit sequence of length B = A + P. in, For example, P equals 16 or 24, etc.

[0288] (c) Code block segmentation and code block CRC attachment module for determining bit sequences. Is the length B greater than N? thr N thr This is the maximum output length of the distributed matcher. If B is greater than N... thr Then for The code blocks are segmented to obtain C segments of payload code blocks that do not contain CB-CRC codes. Then, CRC encoding is performed on each of these C segments, i.e., CB-CRC codes are concatenated to obtain C segments of code blocks with a length of K. in, And K is less than or equal to L represents the number of bits of the CB-CRC code concatenated in each segment's code block. If B is less than or equal to N thr Then the bit sequence of length B It is fed into the block code based shaping module.

[0289] The block code-based shaping module includes a log likelihood ratio generator (LLR generator), a block code decoder, a block code encoder, and a bit XOR (or bit masking).

[0290] A log-likelihood ratio generator is used to receive the input bit sequence (i.e., code blocks of length K each in C segments) from the code block segmentation and code block CRC addition module. Or a bit sequence of length B The LLR bit sequence is generated based on the input bit sequence and then output to the block code decoder.

[0291] The block code decoder is used to decode the LLR bit sequence to obtain the first output bit sequence, namely the auxiliary shaping (shaper bits or shaping redundancy bits) bit sequence, and then sends the auxiliary shaping bit sequence to the channel encoder and the block encoder.

[0292] A block encoder is used to generate a mask sequence based on an auxiliary shaping bit sequence and output the mask sequence to a bit XORer.

[0293] An exclusive OR (XOR) unit receives input bit sequences from the code block segmentation and code block CRC addition module and a mask sequence from the block encoder. It performs an XOR operation on the input bit sequence and the mask sequence to obtain a second output bit sequence, which is then fed into the channel encoder. The XOR operation means that if two bit values ​​are the same (e.g., two 0s or two 1s), the output result is 0; if the two bit values ​​are different, the output result is 1.

[0294] A channel encoder is used to perform channel coding (e.g., LDPC coding) based on the first and second received output bit sequences to obtain the encoded codewords. These codewords are then sent to a modulator for modulation to obtain modulated symbols, which are then mapped onto the channel for transmission.

[0295] Figure 14 is a flowchart illustrating a decoding method provided in an embodiment of this application. This method is an implementation method on the decoding side, and includes the following steps:

[0296] Step 1401: The second communication device acquires the first sequence to be decoded.

[0297] For example, the second communication device receives the first sequence to be decoded from the first communication device, or receives the information to be decoded from the first communication device and demodulates the information to be decoded to obtain the first sequence to be decoded.

[0298] Step 1402: The second communication device determines the number of segments (C) based on the first threshold.

[0299] The first threshold is related to the maximum length of the output of the distributed matcher.

[0300] Step 1403: The second communication device segments the first sequence to be decoded according to the number of segments to obtain C second sequences to be decoded.

[0301] The specific implementation methods of steps 1402 and 1403 are the same as steps 1201 and 1202 in the embodiment of Figure 12 above, and can be referred to the foregoing description.

[0302] Step 1404: The second communication device performs channel decoding on the C second sequences to be decoded to obtain the decoded bit sequences.

[0303] For example, channel decoding could be LDPC channel decoding.

[0304] The decoded bit sequence can be an information bit sequence.

[0305] Based on the above scheme, since the number of segments is determined based on the first threshold, the length of each code block after segmentation does not exceed the first threshold, or the length of each code block after cascading with a CRC does not exceed the first threshold. The first threshold is related to the maximum length of the output of the distributed matcher. Therefore, after inputting each segmented code block into the distributed matcher, the distributed matcher does not need to perform further segmentation, which can improve the speed of encoding and decoding and reduce the complexity of the encoder and decoder.

[0306] The above mainly describes the solution provided by the embodiments of this application from the perspective of the interaction between the first communication device and the second communication device. It is understood that, in order to achieve the above functions, the first communication device and the second communication device may include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0307] In this application embodiment, the first communication device and the second communication device can be divided into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0308] In the case of using integrated units, FIG15 shows a possible exemplary block diagram of the device involved in the embodiments of this application. As shown in FIG15, the device 1500 may include a processing unit 1502 and a communication unit 1503. The processing unit 1502 is used to control and manage the operation of the device 1500. The communication unit 1503 is used to support communication between the device 1500 and other devices. Optionally, the communication unit 1503 is also called a transceiver unit, and may include a receiving unit and / or a sending unit, respectively used to perform receiving and sending operations. The device 1500 may also include a storage unit 1501 for storing the program code and / or data of the device 1500.

[0309] The device 1500 can be the first communication device in the above embodiments. The processing unit 1502 can support the device 1500 in performing the operations of the first communication device in the above method embodiments. Alternatively, the processing unit 1502 mainly performs the internal operations of the first communication device in the method embodiments, and the communication unit 1503 can support communication between the device 1500 and other devices.

[0310] For example, in one embodiment, processing unit 1502 is used to determine a first segment number (C1) based on a first threshold and a first condition. The first segment number is M times the second segment number (C2), where M is an integer greater than 1. The second segment number is related to the first threshold, which is the maximum number of encoded information bits or the maximum length output by the distributed matcher. Based on the first segment number, the first bit sequence is segmented to obtain C1 code blocks. The C1 code blocks are channel-coded to obtain the encoded second bit sequence. Communication unit 1503 is used to output the second bit sequence.

[0311] For example, in another embodiment, the processing unit 1502 is used to determine the number of segments (C) according to a first threshold, which is related to the maximum length of the output of the distributed matcher; to segment the first bit sequence according to the number of segments to obtain C code blocks; to perform channel coding on the C code blocks to obtain the encoded second bit sequence; and the communication unit 1503 is used to output the second bit sequence.

[0312] The device 1500 can be the second communication device in the above embodiments. The processing unit 1502 can support the device 1500 in performing the operations of the second communication device in the above method embodiments. Alternatively, the processing unit 1502 mainly performs the internal operations of the second communication device in the method embodiments, and the communication unit 1503 can support communication between the device 1500 and other devices.

[0313] For example, in one embodiment, the communication unit 1503 is used to acquire a first sequence to be decoded; the processing unit 1502 is used to determine a first number of segments (C1) based on a first threshold and a first condition, wherein the first number of segments is M times the number of second segments (C2), where M is an integer greater than 1, and the number of second segments is related to the first threshold, which is the maximum number of encoded information bits, or the first threshold is related to the maximum length of the output of the distributed matcher; the first sequence to be decoded is segmented according to the first number of segments to obtain C1 second sequences to be decoded; and the C1 second sequences to be decoded are channel-decoded to obtain a decoded bit sequence.

[0314] For example, in another embodiment, the communication unit 1503 is used to acquire a first sequence to be decoded; the processing unit 1502 is used to determine the number of segments (C) according to a first threshold, the first threshold being related to the maximum length of the output of the distributed matcher; to segment the first sequence to be decoded according to the number of segments, to obtain C second sequences to be decoded; and to perform channel decoding on the C second sequences to be decoded to obtain a decoded bit sequence.

[0315] It should be understood that the division of units in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, all units in the device can be implemented entirely through software calls from processing elements; all units can be implemented entirely in hardware; or some units can be implemented through software calls from processing elements, and some units can be implemented in hardware. For example, each unit can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as a program in memory, called and executed by a processing element of the device. Moreover, these units can be fully or partially integrated together, or implemented independently. The processing element mentioned here can also be called a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, the operations of the above methods or the various units mentioned above can be implemented through integrated logic circuits in the processor element or through software calls from processing elements.

[0316] In one example, a unit in any of the above devices can be one or more integrated circuits configured to implement the methods described above, such as: one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. As another example, when a unit in the device can be implemented in the form of a processing element scheduler, the processing element can be a processor, such as a general-purpose central processing unit (CPU), or other processor capable of calling programs. Furthermore, these units can be integrated together and implemented as a System-on-a-Chip (SoC).

[0317] The receiving unit described above is an interface circuit of the device, used to receive signals from other devices. For example, when the device is implemented as a chip, the receiving unit is an interface circuit for the chip to receive signals from other chips or devices. The transmitting unit described above is an interface circuit of the device, used to transmit signals to other devices. For example, when the device is implemented as a chip, the transmitting unit is an interface circuit for the chip to transmit signals to other chips or devices.

[0318] Based on the same technical concept, this application also provides a communication device for implementing the functions of the first or second communication device described above. As shown in FIG16, the device may be a communication equipment or a component within a communication equipment (e.g., a processor, chip, or chip system). The device includes a processor 1601 and a communication interface 1602, and optionally, a memory 1603. The memory 1603 may be independent of the processor 1601 or integrated into the processor 1601; no specific limitation is made. It is understood that FIG16 only shows the main components of the communication device. In one possible implementation, the communication device may further include an input / output device (not shown in the figure).

[0319] The processor 1601 is used to execute the program code stored in the memory 1603, specifically to perform the actions of the aforementioned processing unit 1502, which will not be described in detail here. The communication interface 1602 is specifically used to perform the actions of the aforementioned communication unit 1503, which will not be described in detail here.

[0320] Processor 1601 can be a CPU, a digital processing unit, etc. Processor 1601 can be used to process communication protocols and communication data, control the entire communication device, execute software programs, and process software program data, such as, but not limited to, baseband-related processing. Communication interface 1602 can be used for transmitting and receiving signals, such as, but not limited to, radio frequency transceiver. The above-mentioned devices can be disposed on separate chips, or at least partially or entirely on the same chip. For example, processor 1601 can be further divided into an analog baseband processor and a digital baseband processor. The analog baseband processor can be integrated with the transceiver on the same chip, while the digital baseband processor can be disposed on a separate chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, a digital baseband processor can be integrated with multiple application processors (such as, but not limited to, graphics processors, multimedia processors, etc.) on the same chip. Such a chip can be called a system-on-a-chip (SoC). Whether to dispose of individual devices independently on different chips or integrate them on one or more chips often depends on the specific needs of the product design. The embodiments of this application do not limit the specific implementation of the above-mentioned devices.

[0321] The communication interface 1602 can be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip, etc. Optionally, the communication interface 1602 may include radio frequency (RF) circuitry and an antenna. The RF circuitry is mainly used for converting baseband signals to RF signals and processing RF signals. The antenna is mainly used for transmitting and receiving RF signals in the form of electromagnetic waves. Optionally, the communication interface 1602 can be an input / output interface or a chip pin.

[0322] Input / output devices, such as touchscreens, displays, and keyboards, are primarily used to receive user input data and output data to the user.

[0323] Memory 1603 is used to store programs executed by processor 1601. Memory 1603 can be non-volatile memory, such as a hard disk drive (HDD) or solid-state drive (SSD), or it can be volatile memory, such as random-access memory (RAM). Memory 1603 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited to these.

[0324] When the communication device is powered on, the processor 1601 can read the software program in the memory 1603, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 1601 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit processes the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 1601. The processor 1601 converts the baseband signal into data and processes the data.

[0325] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0326] This application embodiment does not limit the specific connection medium between the communication interface 1602, processor 1601, and memory 1603. In Figure 16, the memory 1603, processor 1601, and communication interface 1602 are connected via a bus 1604, which is represented by a thick line in Figure 16. The connection methods between other components are only illustrative and not intended to be limiting. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, only one thick line is used in Figure 16, but this does not indicate that there is only one bus or one type of bus.

[0327] Optionally, the communication device described above can be a standalone device or part of a larger device. For example, the communication device can be:

[0328] (1) An independent integrated circuit (IC), or chip, or chip system or subsystem;

[0329] (2) A collection of one or more ICs, optionally including a storage component for storing data and instructions;

[0330] (3) Application-specific integrated circuit (ASIC), such as modem;

[0331] (4) Modules that can be embedded in other devices;

[0332] (5) Receivers, smart terminals, wireless devices, handheld devices, mobile units, vehicle-mounted devices, cloud devices, artificial intelligence devices, etc.;

[0333] (6) Others, etc.

[0334] In this application embodiment, "multiple" can refer to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, "including at least one" means including one, two, or more. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A, B, and C. "And / or" describes the association relationship between related objects. Specifically, there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0335] Furthermore, the terms "system" and "network" in the embodiments of this application can be used interchangeably, as can "according to" and "based on". The ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are generally used to distinguish different objects and are not used to limit the order, sequence, priority, or importance of multiple objects. For example, the first communication device and the second communication device in the embodiments of this application are used to distinguish between two communication devices, and do not limit the priority or importance of these two communication devices.

[0336] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0337] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0338] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0339] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

Claims

1. An encoding method, characterized in that, include: Based on the first threshold and the first condition, the first segment number C1 is determined. The first segment number is M times the second segment number C2, where M is an integer greater than 1. The second segment number is related to the first threshold, which is the maximum number of encoded information bits, or the first threshold is related to the maximum length of the output of the distribution matcher. Based on the first segment number, the first bit sequence is segmented to obtain C1 code blocks; Channel coding is performed on the C1 code blocks to obtain the encoded second bit sequence; Output the second bit sequence.

2. A decoding method, characterized in that, include: Obtain the first sequence to be decoded; Based on the first threshold and the first condition, the first segment number C1 is determined. The first segment number is M times the second segment number C2, where M is an integer greater than 1. The second segment number is related to the first threshold, which is the maximum number of encoded information bits, or the first threshold is related to the maximum length of the output of the distribution matcher. Based on the first segmentation number, the first sequence to be decoded is segmented to obtain C1 second sequences to be decoded; Channel decoding is performed on the C1 second sequences to be decoded to obtain the decoded bit sequences.

3. The method as described in claim 1 or 2, characterized in that, Determining the first segment number based on the first threshold and the first condition includes: The second segment number is determined based on the first threshold; The first segment number is determined based on the first condition and the second segment number.

4. The method according to any one of claims 1 to 3, characterized in that, The first condition includes one or more of the following: The bitrate is greater than or equal to the bitrate threshold. The boost values ​​used in the code block encoding belong to a first set, which is a subset of the boost value set; or, In a high throughput scenario.

5. The method as described in claim 4, characterized in that, The bit rate threshold is equal to 22 / 23.

5.

6. The method as described in claim 4 or 5, characterized in that, The promotion value in the first set is a positive integer multiple of X, where X can be 9, 11, or 13.

7. The method according to any one of claims 4 to 6, characterized in that, The high throughput scenario is in effect when one or more of the following conditions are met: The index of the cache status report in the Media Access Control Unit (MAC CE) is greater than or equal to the second threshold value; The cache size value indicated by the index in the cache status report in MAC CE is greater than or equal to the third threshold value; The number of code block groups (CBGs) is greater than or equal to the fourth threshold value; The size of the transport block is greater than or equal to the fifth threshold value; The second segment number is greater than or equal to the sixth threshold value; The index of the modulation and coding scheme (MCS) is greater than or equal to the seventh threshold value; The modulation order is greater than or equal to the eighth threshold value; The spectral efficiency is greater than or equal to the ninth threshold. Enable probabilistic shaping; The operating frequency band is greater than or equal to the tenth threshold value; The number of streams in a Multiple-Input Multiple-Output MIMO is greater than or equal to the eleventh threshold. The required delay is less than or equal to the twelfth threshold value; The required block error rate is greater than or equal to the thirteenth threshold. The maximum number of iterations for the decoding algorithm is less than or equal to the fourteenth threshold. Enable Limited Cache Rate Matching (LBRM); The terminal's capabilities meet the preset conditions; In an enhanced mobile broadband (eMBB) scenario; or, The current work period is included in the preset work period.

8. The method according to any one of claims 1 to 7, characterized in that, The maximum number of encoded information bits is Y times 3840 or Y times 8448, where Y is an integer greater than 1.

9. The method according to any one of claims 1 to 8, characterized in that, The C1 code blocks correspond to P code lengths and Q code rates, where P is an integer greater than or equal to 1 and Q is an integer greater than or equal to 1.

10. The method according to any one of claims 1 to 9, characterized in that, The C1 code blocks include multiple sets of code blocks. Each set of code blocks contains M code blocks. The M code blocks in each set of code blocks correspond to the same cyclic redundancy check code. The number of sets of code blocks is equal to the number of the second segment.

11. The method as described in claim 10, characterized in that, The length of the C1 code blocks is less than the fifteenth threshold.

12. The method as described in claim 10, characterized in that, Each of the M code blocks is concatenated with a sub-code block cyclic redundancy check code.

13. The method as described in claim 12, characterized in that, The length of the C1 code blocks is greater than the fifteenth threshold.

14. An encoding method, characterized in that, include: The number of segments (C) is determined based on a first threshold, which is related to the maximum length of the output of the distribution matcher. Based on the number of segments, the first bit sequence is segmented to obtain C code blocks; Channel coding is performed on the C code blocks to obtain the encoded second bit sequence; Output the second bit sequence.

15. The method as described in claim 14, characterized in that, The first bit sequence is the bit sequence obtained by concatenating the transport block and the transport block cyclic redundancy check code.

16. The method as described in claim 14 or 15, characterized in that, Where C represents the number of segments, B represents the number of bits in the first bit sequence, and N thr L represents the first threshold, and L represents the number of bits of the cyclic redundancy check (CRC) code contained in the C code blocks. This indicates rounding up to the nearest integer.

17. A decoding method, characterized in that, include: Obtain the first sequence to be decoded; The number of segments (C) is determined based on a first threshold, which is related to the maximum length of the output of the distribution matcher. Based on the number of segments, the first sequence to be decoded is segmented to obtain C second sequences to be decoded. Channel decoding is performed on C second sequences to be decoded to obtain the decoded bit sequence.

18. A communication device, characterized in that, The device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and implement the method of any one of claims 1, 3 to 13, or the method of any one of claims 2 to 13, or the method of any one of claims 14 to 16, or the method of claim 17.

19. The apparatus as claimed in claim 18, characterized in that, The communication device further includes a memory for storing computer programs or instructions, which, when executed by the processor, implement the method of any one of claims 1, 3 to 13, or the method of any one of claims 2 to 13, or the method of any one of claims 14 to 16, or the method of claim 17.

20. A communication device, characterized in that, It includes modules for implementing the method of any one of claims 1, 3 to 13, or modules for implementing the method of any one of claims 2 to 13, or modules for implementing the method of any one of claims 14 to 16, or modules for implementing the method of claim 17.

21. A communication device, characterized in that, The device includes a processor coupled to a memory storing a computer program; the processor is configured to invoke part or all of the computer program in the memory to implement the method of any one of claims 1, 3 to 13, or the method of any one of claims 2 to 13, or the method of any one of claims 14 to 16, or the method of claim 17.

22. A computer program product, characterized in that, The computer program product includes instructions that, when executed, implement the method of any one of claims 1, 3 to 13, or the method of any one of claims 2 to 13, or the method of any one of claims 14 to 16, or the method of claim 17.

23. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed, implement the method of any one of claims 1, 3 to 13, or the method of any one of claims 2 to 13, or the method of any one of claims 14 to 16, or the method of claim 17.

24. A chip, characterized in that, The chip includes a processor, which is configured to implement the method of any one of claims 1, 3 to 13, or the method of any one of claims 2 to 13, or the method of any one of claims 14 to 16, or the method of claim 17.

25. A communication system, characterized in that, It includes a first communication device for implementing the method of any one of claims 1, 3 to 13, and a second communication device for implementing the method of any one of claims 2 to 13.

26. A communication system, characterized in that, It includes a first communication device for implementing the method of any one of claims 14 to 16, and a second communication device for implementing the method of claim 17.

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