Interrupt controller and electronic device

Abstract

The present application discloses an interrupt controller and an electronic device. The interrupt controller comprises an interrupt routing unit, and the interrupt routing unit comprises a routing module and an interrupt nesting module. The interrupt nesting module stores the priority of interrupt information being executed which is currently executed by a kernel. The routing module is configured to: determine valid interrupt information on the basis of at least one piece of received interrupt information to be reported; and when the priority of the valid interrupt information is higher than the priority of the interrupt information being executed, report the valid interrupt information to the kernel as new interrupt information being executed, and write the priority of the original interrupt information being executed into the interrupt nesting module as the priority of interrupt information to be executed for nested registration. After each execution of an interrupt task corresponding to the interrupt information being executed, the priority of the interrupt information being executed stored in the interrupt nesting module is updated to the highest priority in the priority ranking of the nested registration. The present application can improve the real-time performance and stability of a system in processing interrupts.

Description

Interrupt controllers and electronic devices

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411951030.0, filed on December 27, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This application relates to the field of processor technology, and more particularly to interrupt controllers and electronic devices. Background Technology

[0004] RISC-V (Reduced Instruction Set Computing-V), as an emerging open-source instruction set architecture, was first proposed in 2010. Its simple design, modular structure, ease of expansion, and the advantage of not requiring high licensing fees have quickly gained widespread attention and support. RISC-V not only avoids the legacy issues of traditional ISAs (Instruction Set Architectures), but also can adapt to different application areas through a limited combination of basic instruction sets and customized extensions, including but not limited to the Internet of Things, artificial intelligence, edge computing, and high-performance computing.

[0005] However, despite its many advantages, RISC-V still faces some challenges in practical applications, especially in interrupt handling. For any microprocessor, the interrupt mechanism is one of the key features for ensuring system responsiveness to real-time events and improving efficiency. In the RISC-V core, when a situation requiring host intervention arises, the system suspends the execution of the current program and switches to handle the new situation, before returning to the starting point to continue execution. This mechanism is crucial for maintaining system stability and reliability. Summary of the Invention

[0006] This application provides an interrupt controller, the interrupt routing unit including a routing module and an interrupt nesting module, the interrupt controller being applied to kernel interrupt handling. The routing module is configured to determine valid interrupt information based on at least one received interrupt information to be reported, wherein the valid interrupt information is the highest priority interrupt information among the at least one interrupt information to be reported. The interrupt nesting module stores the priorities of currently executing interrupt information in the kernel. The routing module is further configured to compare the priority of the valid interrupt information with the priority of the currently executing interrupt information; if it is determined that the priority of the valid interrupt information is higher than the priority of the currently executing interrupt information, the valid interrupt information is reported to the kernel as new currently executing interrupt information, and the priority of the original currently executing interrupt information is used as the priority of the interrupt information to be executed and written into the interrupt nesting module for priority-based nested storage. Each time the kernel finishes executing the interrupt task corresponding to the currently executing interrupt information, the priority of the currently executing interrupt information stored in the interrupt nesting module is updated to the highest priority in the priority order of the nested storage.

[0007] This application also provides an electronic device that includes an interrupt controller as described above. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0010] Figure 1 is a schematic diagram of the module structure provided in the first embodiment of the interrupt controller of this application;

[0011] Figure 2 is a schematic diagram of the module structure provided in the second embodiment of the interrupt controller of this application;

[0012] Figure 3 is a schematic diagram of the module structure provided in the third embodiment of the interrupt controller of this application;

[0013] Figure 4 is a schematic diagram of the module structure provided in the fourth embodiment of the interrupt controller of this application;

[0014] Figure 5 is a schematic diagram of another module structure provided in the fourth embodiment of the interrupt controller of this application;

[0015] Figure 6 is a schematic diagram of another module structure provided in the fourth embodiment of the interrupt controller of this application;

[0016] Figure 7 is a structural block diagram provided in an embodiment of this application;

[0017] Figure 8 is a schematic diagram of the state transition of an interrupt gating unit provided in an embodiment of this application;

[0018] Figure 9 is an operation logic diagram of an interrupt routing unit provided in an embodiment of this application;

[0019] Figure 10 is a schematic diagram of the update of the nested interrupt module provided in an embodiment of this application;

[0020] Figure 11 is an operational logic diagram of a serial-parallel combined comparator provided in an embodiment of this application;

[0021] Figure 12 is an operational logic diagram of a register group provided in an embodiment of this application.

[0022] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0024] It should be understood that the embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0025] As those skilled in the art will know, an interrupt controller is a hardware component in a computer system responsible for managing and scheduling all interrupt requests arriving at the processor. Its main responsibilities are receiving interrupt requests, ensuring that each interrupt is processed according to predetermined rules, and, when multiple interrupts occur simultaneously, selecting the first one to be processed based on a priority mechanism. Interrupt nesting refers to allowing a higher-priority interrupt to interrupt the currently being processed interrupt, switching to process the newly arrived higher-priority interrupt, and automatically returning to the point of interruption to continue processing the original interrupt after processing the new interrupt. When the interrupt controller supports interrupt nesting, this mechanism ensures that high-priority interrupts are not blocked for extended periods by lower-priority interrupts. This means that if a new, more important (i.e., higher-priority) interrupt occurs, it can be processed before the currently lower-priority interrupt is completed. Once the higher-priority interrupt is processed, the previously interrupted process will resume execution. This mechanism allows the system to respond more flexibly to different levels of emergencies, improving system response speed and efficiency, allowing for real-time processing of more urgent tasks while ensuring that all tasks ultimately receive appropriate attention.

[0026] Currently, the Priority Level Interrupt Controller (PLIC) in the RISC-V architecture is implemented in a relatively basic way, its main function being to select the highest priority interrupt to send to the core. While this approach is simple and direct, it can lead to high-priority interrupts being interrupted by newly arriving low-priority interrupts, thus affecting the system's real-time responsiveness and stability. To address this technical problem, related technologies have proposed methods for processing interrupts solely in chronological order and software-assisted methods for maintaining interrupt nesting.

[0027] However, processing interrupts only in chronological order means that interrupts cannot be processed in order of priority, which is clearly not the original intention of setting interrupt priorities.

[0028] Software-assisted interrupt nesting methods suffer from shortcomings in real-time performance and stability when handling a large number of interrupt requests. Regarding real-time performance, on the one hand, each time an interrupt is processed, the software needs to execute additional code to save the current context, update interrupt status information, check priorities, and decide whether to allow a new interrupt to interrupt the current process. These operations increase the number of instructions on each interrupt path, incurring additional instruction overhead and thus prolonging response time. On the other hand, in a multi-tasking environment, frequent interrupts lead to more context switching. Each switch requires saving and restoring register states and other related data structures, which not only consumes processor cycles but may also cause cache misses, further increasing latency. Regarding stability, on the one hand, in a concurrent environment, multiple interrupt sources simultaneously requesting services may lead to resource contention, resulting in priority inversion or task starvation. Especially for time-sensitive tasks, prolonged lack of service can severely impact performance and even cause system failures. On the other hand, the frequent allocation and release of data structures used to save interrupt contexts leads to memory fragmentation, impacting overall system performance over time. In addition, excessive memory allocation / deallocation operations can introduce uncertainty and affect the stable operation of the system.

[0029] In summary, the shortcomings of the RISC-V architecture in interrupt handling limit its application potential in high-performance computing, real-time systems, and other fields.

[0030] To address this, this application provides an interrupt controller, which includes an interrupt routing unit comprising a routing module and an interrupt nesting module. The interrupt controller is applied to kernel interrupt handling. The routing module is configured to determine valid interrupt information based on at least one received interrupt information to be reported, wherein the valid interrupt information is the highest priority interrupt information among the at least one interrupt information to be reported. The interrupt nesting module stores the priority of currently executing interrupt information in the kernel. The routing module is further configured to compare the priority of the valid interrupt information with the priority of the currently executing interrupt information. If the priority of the valid interrupt information is determined to be higher than the priority of the currently executing interrupt information, the valid interrupt information is reported to the kernel as new currently executing interrupt information, and the priority of the original currently executing interrupt information is used as the priority of the interrupt information to be executed and written to the interrupt nesting module for priority-based nested storage. Each time the kernel finishes executing the interrupt task corresponding to the currently executing interrupt information, the priority of the currently executing interrupt information stored in the interrupt nesting module is updated to the highest priority in the priority order of the nested storage.

[0031] This application implements interrupt nesting functionality on the RISC-V PLIC architecture. Through an interrupt nesting module integrated into the interrupt routing unit, combined with reasonable control implementation register shifting and buffering, this module stores the priorities of all unexecuted interrupts sent to the kernel and can also identify the priority of currently executing interrupts. By utilizing shift registers, interrupt nesting functionality is implemented in hardware with minimal logical overhead. This avoids situations where higher-priority interrupts in the kernel are interrupted by new, lower-priority interrupts sent by the interrupt controller. By implementing interrupt processing in hardware according to priority, software complexity and the number of instructions are reduced, increasing system efficiency. This reduces the software complexity of simply implementing interrupt nesting in software, decreases the number of instructions, and improves kernel execution efficiency. Consequently, it effectively enhances the interrupt handling capabilities based on the RISC-V architecture, improving the system's real-time performance and stability when handling a large number of interrupts.

[0032] It is worth mentioning that the embodiments of this application can adapt well to RISC-V cores supporting different numbers and priorities of interrupts, and can freely expand the supported nesting levels as long as the kernel supports it. Thus, based on the open-source architecture, this functionality is implemented in hardware with minimal logical overhead. By introducing hardware logic onto the existing RISC-V PLIC architecture, this embodiment implements interrupt nesting functionality with minimal overhead, ensuring that high-priority interrupts are not interrupted by newly arriving low-priority interrupts, thereby improving system response speed and processing efficiency. This embodiment not only retains the openness and flexibility of the RISC-V architecture but also enhances its robustness and efficiency in interrupt handling, providing stronger technical support for RISC-V-based electronic products.

[0033] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0034] Please refer to Figure 1, which is a schematic diagram of the module structure provided in the first embodiment of the interrupt controller of this application.

[0035] In this embodiment, the interrupt controller 100 includes an interrupt routing unit 1, which includes a routing module 11 and an interrupt nesting module 12. The interrupt controller 100 is applied to the interrupt handling of the kernel 200.

[0036] The routing module 11 is configured to determine the valid interrupt information based on at least one interrupt information to be reported received, wherein the valid interrupt information is the interrupt information with the highest priority among at least one interrupt information to be reported.

[0037] The interrupt nesting module 12 stores the priority of the currently executing interrupt information of kernel 200.

[0038] The routing module 11 is also configured to compare the priority of valid interrupt information with the priority of currently executing interrupt information; if it is determined that the priority of valid interrupt information is higher than the priority of currently executing interrupt information, the valid interrupt information is reported to the kernel 200 as new currently executing interrupt information, and the priority of the original currently executing interrupt information is used as the priority of the interrupt information to be executed and written to the interrupt nesting module 12 for priority-based nested register.

[0039] In particular, after each kernel 200 finishes executing the interrupt task corresponding to the current execution interrupt information, the priority of the current execution interrupt information stored in the interrupt nesting module 12 is updated to the highest priority in the priority sorting of the nested registers.

[0040] It should be noted that interrupt information refers to information related to a specific interrupted task. For example, interrupt information can be an interrupt source identifier (i.e., interrupt ID), and of course, it can also include priority level, timestamp, etc., but this embodiment does not make specific limitations.

[0041] In this embodiment, a pending interrupt refers to an interrupt task that has been triggered by an interrupt source but has not yet been submitted to the processor's kernel 200 for execution, and the pending interrupt information refers to the interrupt information of the pending interrupt. A valid interrupt refers to the highest priority interrupt task among at least one pending interrupt received, and the valid interrupt information refers to the interrupt information of the valid interrupt. A currently executing interrupt refers to an interrupt task that the processor's kernel 200 is currently executing, and the currently executing interrupt refers to the interrupt information of the currently executing interrupt. A pending interrupt refers to an interrupt task that is interrupted by the arrival of a higher-priority interrupt task, and the pending interrupt information refers to the interrupt information of the pending interrupt.

[0042] It should also be noted that, in this embodiment, the priority of interrupt information actually refers to the priority of the interrupt task corresponding to that interrupt information. For example, the priority of an interrupt information being executed actually refers to the priority of the interrupt task corresponding to the interrupt information being executed, that is, the priority of the interrupt being executed. Similarly, the priority of an interrupt information to be executed actually refers to the priority of the interrupt task corresponding to the interrupt information to be executed, that is, the priority of the interrupt to be executed. Furthermore, the interrupt information with the highest priority actually refers to the interrupt information of the interrupt task with the highest priority.

[0043] In this embodiment, in view of the aforementioned defects of the software-assisted interrupt nesting method when handling a large number of interrupt requests, this embodiment improves the interrupt controller 100 under the RISC-V architecture through hardware improvement, thereby realizing hardware interrupt nesting.

[0044] Specifically, in this embodiment, the interrupt controller 100 includes an interrupt routing unit 1, which is the core part of the interrupt controller 100 and consists of a hardware structure routing module 11 and a hardware structure interrupt nesting module 12.

[0045] In this embodiment, the interrupt nesting module 12 stores the priorities of the currently executing interrupts in the kernel 200. Furthermore, the interrupt nesting module 12 also stores the priorities of interrupts awaiting execution under the kernel 200 through a priority-ordered nested register. That is, the priorities of interrupts awaiting execution under the kernel 200 are arranged in priority order and then registered in the interrupt nesting module 12.

[0046] For example, in one feasible implementation, the interrupt task has 32 priority levels, each priority corresponding to a 5-bit binary data. The interrupt nesting module 12 can then be a 160-bit bidirectional shift register. The 160 bits of this bidirectional shift register are divided into 32 binary data segments of 5 bits each. Each binary data segment stores a 5-bit binary data, i.e., a priority. In this bidirectional shift register, the rightmost binary data segment is designated as the 1st binary data segment, and the leftmost binary data segment is designated as the 32nd binary data segment, arranged from right to left. The binary data segments that appear earlier in the sequence (i.e., further to the right) store a higher priority, and the 1st binary data segment stores the priority of the currently executing interrupt in kernel 200.

[0047] In this embodiment, whenever the priority of a valid interrupt is higher than the priority of a currently executing interrupt (i.e., higher than the priority stored in the first binary data segment), the priorities stored in each binary data segment of the bidirectional shift register are all shifted left by one binary data segment in sequence, thereby realizing nested registers based on priority order. Simultaneously, the priority of the valid interrupt is written into the first binary data segment as the new priority of the currently executing interrupt. Whenever the kernel 200 finishes executing the interrupt task corresponding to the currently executing interrupt information (i.e., the currently executing interrupt), the priorities stored in each binary data segment of the bidirectional shift register are all shifted right by one binary data segment in sequence. This updates the priority of the currently executing interrupt information stored in the interrupt nesting module 12, i.e., the priority stored in the first binary data segment, to the highest priority in the priority order of the nested register, i.e., the priority stored in the second binary data segment.

[0048] In addition to the methods described above, the interrupt nesting module 12 can also be a bidirectional shift register array. Using the same concept as described above, it dynamically adjusts the priorities of currently executing interrupts and interrupts awaiting execution. This allows this embodiment to complete complex interrupt management tasks in hardware with minimal logical overhead, dynamically adjusting the interrupt priority threshold (i.e., the priority of the currently executing interrupts being processed by the kernel 200, stored in the interrupt nesting module 12). When interrupt nesting occurs, the current interrupt priority state is saved, and the original priority is restored after processing higher-priority interrupts. Compared to software-assisted interrupt nesting maintenance methods, this embodiment's hardware-level interrupt nesting management and priority sorting ensure accurate processing of every interrupt event, even under high load or complex interrupt scenarios. It does not require additional software instructions to save the current interrupt priority state. Consequently, when a lower-priority interrupt regains execution rights, complex recovery operations are unnecessary. This simplifies the dynamic adjustment process of the interrupt priority threshold, avoids the code volume and logical overhead required for software-based dynamic adjustment of the interrupt priority threshold, reduces processor intervention, lowers the frequency of system calls, and improves interrupt response speed, thereby enhancing the system's real-time performance and stability.

[0049] In this embodiment, the routing module 11 is responsible for determining the highest priority interrupt task, i.e. the valid interrupt, among the at least one interrupt information to be reported, by comparing priorities. The valid interrupt information is then determined from the at least one interrupt information to be reported. The priority of the valid interrupt is then compared with the priority of the currently executing interrupt stored in the interrupt nesting module 12.

[0050] In this embodiment, if the priority of a valid interrupt is higher than the priority of the active interrupt currently being executed by the kernel 200, the routing module 11 is also responsible for reporting the valid interrupt information to the kernel 200 as a new active interrupt information, thereby interrupting the active interrupt currently being executed by the kernel 200 and causing the kernel 200 to treat the valid interrupt as a new active interrupt with priority.

[0051] It is easy to understand that after the routing module 11 reports the valid interrupt information to the kernel 200 as a new active interrupt information, and the kernel 200 prioritizes the valid interrupt as a new active interrupt, the priority of the active interrupt currently being executed by the kernel 200 stored in the interrupt nesting module 12 will also be updated synchronously to the priority of the valid interrupt, that is, the priority of the new active interrupt. This is so that when a new round of interrupts to be reported is received, the routing module 11 can compare the priority of the valid interrupts in the new round of interrupts to be reported with the priority of the new active interrupt, thereby preventing a high-priority interrupt from being interrupted by a newly arrived low-priority interrupt, and improving the real-time performance and stability of the system when handling a large number of interrupts.

[0052] Furthermore, in this embodiment, while reporting valid interrupt information to the kernel 200 as new active interrupt information, the routing module 11 also writes the priority of the original active interrupt as the priority of the interrupt to be executed into the interrupt nesting module 12 for priority-based nested storage. This ensures that when the kernel 200 finishes executing the new active interrupt and resumes executing the original active interrupt, the priority of the active interrupt currently being executed by the kernel 200 stored in the interrupt nesting module 12 is synchronously updated to the highest priority in the priority sorting of the nested storage, which is the priority of the original active interrupt. This allows the routing module 11 to compare the priority of the valid interrupt in the new round of interrupts to be reported with the priority of the original active interrupt when a new round of interrupts to be reported is received, thereby preventing newly arrived high-priority interrupts from being blocked by low-priority interrupts and improving the resource utilization of the system when processing a large number of interrupts.

[0053] It is worth mentioning that in this embodiment, the routing module 11 uses hardware such as the comparator 13 to compare the priorities of valid interrupts and determine valid interrupt information. Compared to software implementation, the hardware implementation of key functions (such as priority comparison and valid interrupt selection) in this embodiment has higher reliability and anti-interference capabilities. It eliminates the need for developers to write complex code to implement the priority relationships between different interrupts, reducing programming difficulty and the probability of errors. This reduces the risk of system crashes due to software errors or external attacks. Furthermore, hardware logic is generally more fixed and predictable, providing additional security for the system, especially in safety-critical applications such as automotive electronics and aerospace. In addition, compared to software-implemented priority comparison, the hardware comparator 13 has lower latency and faster processing speed, completing priority determination in almost zero waiting time, significantly improving system real-time performance and reducing processor involvement, thereby reducing overall system power consumption.

[0054] Through the hardware-implemented routing module 11 and interrupt nesting module 12, this embodiment not only achieves efficient interrupt management but also brings many added values, including but not limited to improving the system's real-time performance, stability, and security, optimizing resource utilization, simplifying the development process, and laying a solid foundation for future expansion and improvement. This design is particularly suitable for applications in fields that have high requirements for interrupt response speed, system stability, and energy efficiency.

[0055] This embodiment implements interrupt nesting functionality on the RISC-V PLIC architecture. Through an interrupt nesting module 12 integrated into the interrupt routing unit 1, combined with reasonable control implementation register shifting and buffering, the interrupt nesting module 12 stores all unexecuted interrupt priorities sent to the kernel 200. It can also identify the currently executing interrupt priority. Using shifting registers, the interrupt nesting function is implemented in hardware with minimal logical overhead, preventing higher-priority interrupts in the kernel 200 from being interrupted by lower-priority new interrupts sent by the interrupt controller 100. By implementing interrupt processing in hardware according to priority, software complexity and the number of instructions are reduced, increasing system efficiency. This reduces the software complexity of simply implementing interrupt nesting in software, lowers the number of instructions, and improves the execution efficiency of the kernel 200. Consequently, it effectively enhances the interrupt handling capability based on the RISC-V architecture, improving the system's real-time performance and stability when handling a large number of interrupts.

[0056] It is worth mentioning that the embodiments of this application can adapt well to RISC-V cores supporting different numbers and priorities of interrupts. With the support of kernel 200, the number of nesting levels can be freely expanded, thus implementing this function in hardware with less logical overhead on the basis of an open-source architecture. The embodiments of this application introduce hardware logic to implement interrupt nesting functionality with minimal overhead on the existing RISC-V PLIC architecture, ensuring that high-priority interrupts are not interrupted by newly arriving low-priority interrupts, thereby improving system response speed and processing efficiency. The embodiments of this application not only retain the openness and flexibility of the RISC-V architecture but also enhance its robustness and efficiency in interrupt handling, providing stronger technical support for RISC-V-based electronic products.

[0057] Based on the first embodiment described above, an interrupt controller according to a second embodiment of this application is proposed.

[0058] In the second embodiment of this application, the same or similar content as in the above embodiments can be referred to the above description, and will not be repeated hereafter.

[0059] Please refer to Figure 2, which is a schematic diagram of the module structure provided in the second embodiment of the interrupt controller of this application.

[0060] In this embodiment, the interrupt controller 100 also includes a register group 2. After the kernel 200 finishes executing the interrupt task corresponding to the current active interrupt information, it writes the currently executed active interrupt information into the register group 2.

[0061] Register group 2 is configured to generate the first signal after the kernel 200 writes the currently executed interrupt information to register group 2.

[0062] The routing module 11 is also configured to notify the kernel 200 to allow the execution of the interrupt task corresponding to the highest priority interrupt information when the first signal is detected generated by register group 2.

[0063] Among them, the routing module 11 updates the priority of the currently executing interrupt information stored in the interrupt nesting module 12 based on the highest priority interrupt information that is allowed to be executed.

[0064] It should be noted that, in this embodiment, the interrupt controller 100 also includes a register group 2 consisting of multiple registers. The second signal is used to trigger the routing module 11 to notify the kernel 200 to resume the execution of the interrupt that was interrupted (i.e., the interrupt task corresponding to the highest priority interrupt information, which is also the interrupt corresponding to the highest priority in the priority order of the nested registers).

[0065] In this embodiment, after the kernel 200 finishes executing the interrupt task corresponding to the current active interrupt information, that is, after the active interrupt, it writes the active interrupt information into register group 2, causing register group 2 to generate a first signal, thereby enabling the routing module 11 to notify the kernel 200 that it can execute the interrupt to be executed corresponding to the highest priority in the priority order of the nested registers. This allows the kernel 200 to automatically resume the execution of the interrupt that was previously interrupted after executing the higher priority interrupt, and to treat the interrupt to be executed as a new active interrupt.

[0066] In this embodiment, when the routing module 11 notifies the kernel 200 that the highest priority interrupt in the nested register priority order can be executed, it also synchronously updates the priority of the currently executing interrupt stored in the interrupt nesting module 12 to the highest priority in the nested register priority order, that is, the new priority of the currently executing interrupt. This realizes the dynamic adjustment of the interrupt priority threshold, so that when a new round of interrupts to be reported is received, the routing module 11 can compare the priority of the valid interrupts in the new round of interrupts to be reported with the priority of the new currently executing interrupt (that is, the dynamically adjusted interrupt priority threshold), so as to prevent the newly arrived high-priority interrupt from being blocked by low-priority interrupts and improve the resource utilization of the system when processing a large number of interrupts.

[0067] Furthermore, in one feasible implementation, if the priority of valid interrupt information is determined to be higher than the priority of currently executing interrupt information, the routing module 11 writes the valid interrupt information to register group 2.

[0068] Register group 2 is also configured to generate a second signal when kernel 200 reads valid interrupt information written to register group 2.

[0069] The routing module 11 is also configured to, upon detecting that a second signal is generated by register group 2, synchronously update the priority of the executing interrupt information stored in the interrupt nesting module 12, as well as the priority of the nested interrupt information to be executed, based on the valid interrupt information read by kernel 200.

[0070] It should be noted that, in this embodiment, the second signal is used to trigger the routing module 11 to read valid interrupt information in the kernel 200 and, when the interrupt task corresponding to the valid interrupt information is used as a new active interrupt, to synchronously update the priority of the active interrupt stored in the interrupt nesting module 12 and the priority of the nested interrupt to be executed.

[0071] In this embodiment, after comparing the priority of the valid interrupt with the priority of the currently executing interrupt stored in the interrupt nesting module 12, and determining that the priority of the valid interrupt is higher than the priority of the currently executing interrupt, the routing module 11 writes the valid interrupt information of the valid interrupt into register group 2 so that the kernel 200 can read the valid interrupt information. Then, it postpones the processing of the currently executing interrupt and prioritizes the processing of the valid interrupt, ensuring that a newly arrived higher priority interrupt can interrupt the currently executing lower priority interrupt. Simultaneously, after register group 2 detects that kernel 200 has read the valid interrupt information, it generates a second signal to enable routing module 11 to determine that the currently executing interrupt of kernel 200 has been interrupted and that the new executing interrupt is the valid interrupt. The original priority of the executing interrupt is then used as the priority of the interrupt to be executed, and written to interrupt nesting module 12 for priority-based nested register storage. The priority of the executing interrupt stored in interrupt nesting module 12 is then updated to the priority of the valid interrupt, i.e., the new priority of the executing interrupt. This achieves synchronous updates of the priorities of the executing interrupts stored in the interrupt nesting module and the priorities of the interrupts to be executed in the nested register, thereby completing the dynamic adjustment of the interrupt priority threshold and the maintenance of interrupt nesting. This ensures that higher-priority interrupts are not interrupted by newly arriving lower-priority interrupts, improving the real-time performance and stability of the system.

[0072] Based on the above embodiments, an interrupt controller according to a third embodiment of this application is proposed.

[0073] In the third embodiment of this application, the same or similar content as the above embodiments can be referred to the above description, and will not be repeated hereafter.

[0074] Please refer to Figure 3, which is a schematic diagram of the module structure provided in the third embodiment of the interrupt controller of this application.

[0075] In this embodiment, the interrupt routing unit 1 further includes multiple comparators 13 that combine serial and parallel connections.

[0076] The routing module 11 is also configured to, when multiple interrupt information to be reported is received at the same time, compare the priorities of the multiple interrupt information to be reported based on multiple comparators 13 that combine serial and parallel communication, determine the interrupt information with the highest priority among the interrupt information to be reported, and take the interrupt information with the highest priority among the interrupt information to be reported as the valid interrupt information.

[0077] Specifically, the priority comparison of multiple received interrupt information to be reported based on multiple comparators 13 in a serial-parallel combination means: the multiple interrupt information to be reported is divided into a first number of first comparison groups, each of which consists of two interrupt information to be reported; the first number of comparators 13 compare the first interrupt information with higher priority in each first comparison group; the multiple interrupt information to be reported is divided into a second number of second comparison groups, each of which consists of two interrupt information to be reported; the second number of comparators 13 compare the second interrupt information with higher priority in each second comparison group; and so on, until a target number of target interrupt information with higher priority is selected from the received interrupt information to be reported; and the interrupt information with the highest priority is determined from the target interrupt information based on a serial comparison method.

[0078] As those skilled in the art will know, comparator 13 is a circuit or logic unit used to compare two input signals and is widely used in analog and digital systems.

[0079] It should be noted that the target number refers to a number that is less than or equal to a preset number, which can be the number of serial comparators 13 among the multiple comparators 13 combined in serial and parallel.

[0080] In this embodiment, the interrupt routing unit 1 further includes multiple comparators 13 combined in series and parallel. When the routing module 11 receives multiple interrupt information to be reported simultaneously, it can use the multiple comparators 13 combined in series and parallel to first compare the priority of the multiple interrupt information to be reported in pairs using the parallel comparators 13 in multiple rounds until the target number of interrupt information with higher priority in their respective groups is selected from the received interrupt information to be reported as target interrupt information. Then, the target number of target interrupt information is compared in series using the serial comparators 13 until the interrupt information with the highest priority is selected from the target interrupt information as valid interrupt information.

[0081] It is easy to understand that this embodiment uses multiple comparators combined in series and parallel to implement the priority comparison of interrupt information to be reported in 13 stages. The comparison operations of each stage can be performed in parallel (i.e., the priority comparison of the first number of first comparison groups can be performed in parallel, the priority comparison of the second number of second comparison groups can be performed in parallel, etc.), thereby reducing the total comparison time and improving the real-time performance of the system when processing a large number of interrupts. The comparison operation of the last stage can be performed serially (i.e., the priority comparison of the target number of target interrupt information can be performed serially), thereby reducing the total comparator footprint. Thus, this embodiment achieves a better balance between priority comparison efficiency and comparator footprint.

[0082] This embodiment adopts a phased, layer-by-layer comparison approach, which makes the entire interrupt control structure clearer and more modular, facilitating maintenance and expansion. Compared to the complex logic of comparing all interrupt information at once, phased comparison simplifies the logic design of each stage and reduces the consumption of hardware resources.

[0083] This application implements the function on hardware with less logical overhead by building upon an open-source architecture. Furthermore, the parallel processing and layer-by-layer filtering design of this embodiment reduces unnecessary computation, ensures rapid response to interrupt requests even under high load, improves the system's real-time performance, and reduces power consumption, making it particularly suitable for low-power applications.

[0084] Based on the above embodiments, an interrupt controller according to a fourth embodiment of this application is proposed.

[0085] In the fourth embodiment of this application, the same or similar content as the above embodiments can be referred to the above description, and will not be repeated hereafter.

[0086] Please refer to Figure 4, which is a schematic diagram of the module structure provided in the fourth embodiment of the interrupt controller of this application.

[0087] In this embodiment, the interrupt controller 100 further includes an interrupt gating unit 3, which is configured to receive interrupt task information generated by external triggering and, based on the arbitration result of the interrupt task information, determine to send the interrupt task information as interrupt information to be reported to the routing module 11.

[0088] The routing module 11 is configured to receive at least one interrupt information to be reported from the interrupt gating unit 3.

[0089] It should be noted that the interrupted task information in this embodiment refers to interrupt information.

[0090] In this embodiment, the interrupt controller 100 further includes an interrupt gating unit 3, which is responsible for receiving interrupt task information generated by external triggers and determining whether to send the interrupt task information as interrupt information to the routing module 11 based on the arbitration result of the interrupt task information.

[0091] It is easy to understand that when the arbitration result indicates that the interrupt task information needs to be reported, the interrupt gating unit 3 determines to send the interrupt task information as the interrupt information to be reported to the routing module 11, while when the arbitration result indicates that the interrupt task information does not need to be reported, the interrupt gating unit 3 continues to receive new interrupt task information.

[0092] It should be noted that in this embodiment, each type of interrupt corresponds to an interrupt gating unit 3. After different types of interrupts are triggered, they are distributed to their respective interrupt gating units 3 to determine which interrupt task information needs to be sent to the routing module 11 as interrupt information to be reported. This ensures that only necessary interrupt information is passed to the routing module 11, reducing unnecessary processing delays and resource waste, preventing the routing module 11 from being overloaded by too many interrupt requests, avoiding confusion and conflicts, and thus improving the real-time performance and stability of the system when facing a large number of interrupt requests.

[0093] Furthermore, as shown in Figure 5, in one feasible implementation, the interrupt gating unit 3 is also equipped with a state machine 4, which controls the current interrupt state.

[0094] The routing module 11 is also configured to send the first information to the interrupt gating unit 3 corresponding to the valid interrupt information read by the kernel 200 when the second signal is detected generated by the register group 2. The first information is used to trigger the interrupt gating unit 3 to control the current interrupt state to the first state through the state machine 4. The first state makes the interrupt gating unit 3 shield itself from receiving new interrupt task information.

[0095] As those skilled in the art will know, a state machine 4 is a mathematical model used for modeling and controlling a finite set of states and their transitions.

[0096] In this embodiment, each interrupt gating unit 3 is configured with a state machine 4, and the current interrupt state of the interrupt gating unit 3 is controlled by the state machine 4.

[0097] In this embodiment, when the routing module 11 detects that the register group 2 generates a second signal, determines that the kernel 200 has read valid interrupt information, and prioritizes the interrupt task corresponding to the valid interrupt information as a new interrupt, it can send the first information used to trigger the interrupt gating unit 3 to control the current interrupt state to the first state through the state machine 4 to the interrupt gating unit 3 corresponding to the valid interrupt information (that is, to send the valid interrupt information as interrupt information to be reported to the interrupt gating unit 3 of the routing module 11). Thus, the state machine 4 modifies the current interrupt state of the interrupt gating unit 3 to the first state, so that the interrupt gating unit 3 is shielded from receiving new interrupt task information, so as to prevent the interrupt gating unit 3 from repeatedly sending the same interrupt information, causing interrupt nesting conflicts and resource waste, thereby reducing unnecessary interrupt processing, avoiding confusion and conflicts, and improving the real-time performance and stability of the system.

[0098] Furthermore, in one feasible implementation, the routing module 11 is also configured to send the second information to the interrupt gating unit 3 corresponding to the currently executing interrupt information completed by the kernel 200 when the first signal is detected generated by the register group 2. The second information is used to trigger the interrupt gating unit 3 to control the current interrupt state to the second state through the state machine 4. The second state enables the interrupt gating unit 3 to receive new interrupt task information.

[0099] In this embodiment, after the routing module 11 detects that the register group 2 generates the first signal and determines that the kernel 200 has completed the current active interrupt, it can send the second information used to trigger the interrupt gating unit 3 to control the current interrupt state to the second state through the state machine 4 to the interrupt gating unit 3 corresponding to the active interrupt information (that is, to send the active interrupt information as the interrupt information to be reported to the interrupt gating unit 3 of the routing module 11). Thus, the state machine 4 modifies the current interrupt state of the interrupt gating unit 3 to the second state, so that the interrupt gating unit 3 is allowed to receive new interrupt task information, ensuring that the interrupt of the interrupt type corresponding to the interrupt gating unit 3 can continue to be accepted and processed.

[0100] This embodiment introduces a state machine 4 to control the state of the interrupt gating unit 3. When the kernel 200 prioritizes a valid interrupt as a new active interrupt, the interrupt gating unit 3 corresponding to the valid interrupt is shielded from receiving new interrupt information. After the kernel 200 completes the execution of the new active interrupt, the shielding is removed, allowing the interrupt gating unit 3 to continue receiving new interrupt information. This ensures that critical interrupt tasks can be completed in a timely manner, and allows the reception of new interrupt requests immediately after completion, thereby improving the stability and real-time performance of the system.

[0101] It is worth mentioning that, in this embodiment, the interrupt gating unit 3 supports triggering methods for recognizing interrupt task information, including edge triggering and level triggering.

[0102] In this embodiment, edge triggering refers to triggering an interrupt when a signal state changes from one logic level to another. Specifically, it can be divided into rising edge triggering and falling edge triggering. Edge triggering can avoid repeated interruptions caused by maintaining the same level for a long time, and is particularly effective for responding to transient events.

[0103] In this embodiment, level triggering is based on the signal being maintained at a specific logic level (such as high or low level) to trigger an interrupt, which can be specifically divided into high-level triggering and low-level triggering. Compared to edge triggering, level triggering does not need to capture instantaneous changes, making it easier to implement. Moreover, in the case of unstable signals, level triggering can guarantee that at least one interrupt is handled correctly.

[0104] The interrupt gating unit 3 in this embodiment supports multiple triggering methods. The most suitable triggering mode can be selected according to the actual application requirements. For some application scenarios that require rapid response to instantaneous changes, edge triggering is used, while for those that want to ensure that all events that meet the conditions are captured, level triggering is used. This improves the system's flexibility and adaptability, helps to build a more stable and reliable interrupt handling mechanism, and improves the efficiency and reliability of the entire system.

[0105] Further, as shown in Figure 6, in one feasible implementation, the interrupt gating unit 3 is configured with an interrupt event counter 5. Each time the interrupt gating unit 3 receives interrupt task information triggered by the rising edge of the target, it increments the count value of the interrupt event counter 5 by one until the count value of the interrupt event counter 5 reaches a preset upper limit value. Each time the interrupt task information triggered by the rising edge of the target is sent to the routing module 11 as interrupt information to be reported, and the count value of the interrupt event counter 5 is not zero, the count value of the interrupt event counter 5 is decremented by one.

[0106] In this embodiment, each interrupt gating unit 3 is equipped with a corresponding interrupt event counter 5, which is used to statistically track the interrupt events of the interrupt gating unit 3, thereby managing and monitoring the interrupt handling process more precisely and improving the reliability and performance of the system.

[0107] It should be noted that in this embodiment, the target rising edge refers to the rising edge that triggers the generation of interrupt task information. The preset upper limit value is a preset value that can be flexibly adjusted according to actual needs.

[0108] In this embodiment, when the interrupt gating unit 3 is allowed to receive new interrupt task information, if the count value of the interrupt event counter 5 has not reached the preset upper limit, it can continue to receive new interrupt task information. Upon receiving interrupt task information triggered by the rising edge of the target, the count value is incremented by one. After the interrupt task information is sent to the routing module 11 as interrupt information to be reported, the count value is decremented by one, thereby ensuring that the system will not be overloaded due to too many unprocessed interrupt requests. Once the count value reaches the upper limit, new interrupt requests will be temporarily suspended until there are idle resources available to process them. This embodiment improves the stability and reliability of the system and avoids performance degradation or system crashes caused by interrupt accumulation.

[0109] It is worth mentioning that the arrival of interrupted task information is generally achieved in the form of an interrupt pulse. In this implementation, the count value can be updated at the end of each interrupt pulse, and then reset to zero and counted again.

[0110] To facilitate understanding of the technical concept or principle of the interrupt controller in the above embodiments of this application, a specific embodiment is provided:

[0111] This embodiment proposes a hardware-based interrupt controller for interrupt nesting based on the RISC-V architecture. The interrupt controller mainly consists of an interrupt gating unit, an interrupt routing unit, and a register set. Building upon the existing open-source PLIC architecture, this embodiment's interrupt controller uses a combination of serial and parallel processing to determine the highest priority among a large number of external interrupts, and then utilizes shift registers to implement interrupt nesting functionality in hardware with minimal logical overhead. This design reduces the software complexity of simply implementing interrupt nesting in software, reduces the number of instructions, increases the execution efficiency of the kernel, and is well-adaptable to RISC-V cores supporting different numbers and priorities of interrupts, allowing for flexible expansion of the supported nesting levels as the core supports it.

[0112] As shown in Figure 7, the interrupt controller in this embodiment is mainly implemented through the following four module units: interrupt synchronization unit 6, interrupt gating unit 3, interrupt routing unit 1, and register group 2.

[0113] Interrupt synchronization unit 6: It is set to interrupt synchronization and is used to synchronize external interrupts to the clock domain where the interrupt module is located.

[0114] Interrupt gating unit 3: It is set as an interrupt gating unit, determines the triggering mode of the input interrupt source, generates an interrupt ID (Identifier, number), that is, the interrupt number and the interrupt source identifier, which is also the interrupt information, and controls whether the interrupt is pending through a state machine.

[0115] Interrupt routing unit 1: It is set as an interrupt route, selects the interrupt with the highest priority and above the threshold to report to the target kernel 200, generates an irq / fiq (Interrupt Request / Fast Interrupt Request) interrupt flag, and locks the interrupt until the relevant signal is input, after which the lock is released and the interrupt reporting process is completed. The main logic of interrupt nesting is implemented here.

[0116] Register group 2: Used to store various registers, including but not limited to interrupt enable, interrupt priority threshold, interrupt priority, interrupt ID, etc., and can be read and written by the core through address mapping.

[0117] In this embodiment, each type of interrupt corresponds to an interrupt gating unit. For interrupts sent from the interrupt synchronization unit (i.e., interrupt tasks generated by external triggering), the interrupt gating unit determines the triggering mode by reading the settings in the register group. In other words, the interrupt gating unit supports identifying interrupt task information triggering modes including edge triggering and level triggering.

[0118] In this embodiment, for high-level triggered interrupts, when the interrupt gating unit is in the REPORT state (i.e., the second state), it directly generates an IP (interrupt pending) signal for the interrupt, determining that the interrupt needs to be reported, and thus inputs the interrupt ID (i.e., interrupt task information) into the interrupt routing unit. That is, the interrupt controller also includes an interrupt gating unit, which is configured to receive interrupt task information generated by external triggers and, based on the arbitration result of the interrupt task information, determine whether to send the interrupt task information as interrupt information to be reported to the routing module; the routing module is configured to receive at least one interrupt information to be reported sent by the interrupt gating unit.

[0119] In this embodiment, for rising edge-triggered interrupts, the interrupt gating unit internally implements an interrupt event counter, which is set with a configurable maximum count value (i.e., a preset upper limit). Whenever the rising edge triggering the interrupt (i.e., the target rising edge) arrives, and the interrupt event counter's count value has not reached the maximum count value, the interrupt event counter's count value is incremented by 1 (that is, each time an interrupt information to be reported triggered by the target rising edge is sent to the interrupt routing unit, the interrupt event counter's count value is incremented by one until the interrupt event counter's count value reaches the preset upper limit). Each time an interrupt is reported, and the interrupt event counter's count value is not 0, the interrupt event counter's count value is decremented by 1 (that is, each time an interrupt task information generated by the target rising edge is sent as interrupt information to the routing module, and the interrupt event counter's count value is not zero, the interrupt event counter's count value is decremented by one). The interrupt event counter's count value is updated each time the interrupt pulse ends. When the interrupt gating unit is in REPORT state and the counter value is greater than 0, it generates an IP signal and the interrupt gating unit also outputs the ID number of the current interrupt (i.e. the interrupt information to be reported).

[0120] As shown in Figure 8, when the interrupt gating unit is in the REPORT state, it generates an IP signal and a GRNT (Grant) signal upon receiving new interrupt information. If the interrupt gating unit has pending interrupts (i.e., valid interrupts with higher priority than the currently executing interrupt), the routing module reports the interrupt, and the core has read the interrupt information, then the interrupt gating unit's interrupt status enters the WAIT_FOR_COMPLETE state (i.e., the first state). After the core completes the execution of the interrupt, the interrupt gating unit's interrupt status returns to report via the complete signal, allowing it to handle new interrupt requests.

[0121] In this embodiment, each core in the central processing unit corresponds to an interrupt routing unit, and the interrupt nesting module proc_intr can be implemented using a bidirectional register array through a shift buffer.

[0122] As shown in Figure 9, in this embodiment, proc_intr[0] represents the priority stored in the first register in the bidirectional register array, which is the priority of the currently executing interrupt in the kernel. priority represents the priority of a valid interrupt. ip represents the interrupt request signal. ie (Interrupt Enable) represents the interrupt enable signal. lvl (Level) represents the interrupt priority. thre (Threshold) represents the interrupt priority threshold. claim (acceptance) and complete (completion) are flag bits. claim indicates that the interrupt request has been accepted, and complete indicates that the interrupt processing has been completed.

[0123] In this embodiment, after receiving the interrupt information to be reported sent by the interrupt gating unit, the routing module first checks whether the interrupt to be reported is a valid interrupt, that is, whether it satisfies ip&ie&lvl>thre (that is, if lvl>thre is determined when ip==1 and ie==1, it is a valid interrupt). If the interrupt to be reported is determined to be a valid interrupt, the priority of the valid interrupt is compared with the priority of the currently executing interrupt proc_intr[0] stored in the interrupt nesting module. Next, the steps of ip_qual are used to determine whether ip&ie&lvl>thre and priority>proc_intr[0] are satisfied at the same time. If satisfied, the priority level number priority id of the valid interrupt is determined, and the index pri_idx corresponding to the priority id in the interrupt nesting module is further determined. Then, according to pri_idx, the priority information in the interrupt nesting module proc_intr is updated through the up operation (update operation), and the interrupt number (i.e. interrupt source identifier, interrupt information) intr_id of the valid interrupt is output to the kernel core through the up operation, so that the valid interrupt is treated as a new active interrupt priority.

[0124] In this embodiment, the interrupt nesting module stores all unexecuted interrupt priorities (i.e., the priorities of interrupts yet to be executed) sent to the core, and can also identify the priority of the currently executing interrupt (i.e., the priority of the interrupt being executed). The register bit width of the dual register array is the interrupt priority bit width supported by the system, and the number of registers in the bidirectional register array is the number of interrupt priority levels supported by the system.

[0125] In one example, the system supports an interrupt priority bit width of 5 and an interrupt priority level of 32. The bidirectional register array is proc_intr[31:0][4:0], which consists of 32 registers with a bit width of 5.

[0126] As shown in Figure 10, when an interrupt A is sent to the core, and the core reads and is executing interrupt A (i.e., claiming A), the priority of interrupt A is written into the low-order register proc_intr[0][4:0] of the bidirectional register array. proc_intr[0][4:0] represents the priority of the interrupt being executed by the core, that is, the priority of the interrupt being executed. At this time, if the interrupt gating unit continues to pull the IP signal of the corresponding interrupt B high, the routing module will compare the priority of interrupt B with that of proc_intr[0][4:0]. Only interrupts with a priority higher than that of proc_intr[0][4:0] are truly valid interrupts and can continue to be sent to the core. When interrupt B (with a priority higher than A) is also read by the core, the priority of interrupt B will also be written into proc_intr[0][4:0] of the interrupt nesting module, while the priority in the original proc_intr[0] will be written into proc_intr[1][4:0]. That is, proc_intr[0][4:0] still represents the priority of the interrupt being executed by the core. If another interrupt is sent to the core before the current interrupt has finished executing, and so on, the data continues to be shifted to higher priority bits. Because the above situation is always caused by higher priority interrupts, the storage in the nested interrupt module will never overflow.

[0127] In this embodiment, after the core completes an interrupt, it discards the values ​​in proc_intr[0][4:0] and shifts the high-order bits of the data to the low-order bits in sequence, that is:

[0128] proc_intr[31:0][4:0]={5'b0,proc_intr[31:1][4:0]}

[0129] That is, the 5-bit priority data stored in proc_intr[0][4:0] is updated to the 5-bit priority data stored in proc_intr

[0001] [4:0]. In other words, after each kernel finishes executing the interrupt task corresponding to the interrupt information being executed, the priority of the interrupt information being executed stored in the interrupt nesting module is updated to the highest priority in the priority sorting of the nested registers.

[0130] The above logic implementation in this embodiment conforms to the logic of core execution interruption, because the core always restores to the state before the interrupt after executing the current interrupt. That is, when there is interrupt nesting, after the core executes the current active interrupt, it will restore to the state of executing the interrupt corresponding to proc_intr[1][4:0]. The shifted proc_intr[0][4:0] still represents the priority of the interrupt that the core is currently executing.

[0131] It is worth mentioning that if multiple interrupts to be reported are sent to the routing module by the interrupt gating unit at the same time, the routing module also needs to determine the priority of each interrupt to be reported. Because this may involve a large number of interrupt priority judgments (e.g., for a processor that supports 1024 interrupts and has an interrupt priority of 32, this involves 1024 comparisons of 5-bit data), taking into account timing and area, this embodiment introduces a combined serial-parallel method to select the highest priority.

[0132] As shown in Figure 11, in one example, the interrupt routing unit compares the priorities of all interrupts to be reported, divides the supported interrupts into groups of 32 / 64 (adjusted according to the number of interrupts supported by the scheme), and performs pairwise parallel priority comparisons in cycle 0 (for example, the interrupts to be reported corresponding to S0 and S1 are grouped together, and the interrupts to be reported corresponding to Sn-1 and Sn are grouped together). The values ​​obtained are then compared pairwise until the interrupt with the highest priority in a group is obtained (when the priorities are the same at the same time, the interrupt with the smaller interrupt number has a higher priority). Then, the final priorities of each group are stored in the register, i.e., cycle 1 is entered, and the priorities in the register are compared in turn to obtain the final value. In other words, the routing module is also set to compare the priorities of the multiple interrupts to be reported simultaneously based on multiple comparators combined in serial and parallel, and obtain the interrupt information with the highest priority among the interrupts to be reported, and take the interrupt information with the highest priority among the interrupts to be reported as the valid interrupt information.

[0133] In this example, the final value will be written to the interrupt nesting module, and then the route will pull up the corresponding bit of the interrupt in the CSR (Control and Status Register) register in the core. The corresponding interrupt ID (i.e., interrupt number, interrupt source identifier, interrupt information) will be written to the ID register in the register group, waiting for the core to read it.

[0134] As shown in Figure 12, in this embodiment, req_data represents the request data, used as the data input during write operations; req_addr represents the request address; req_type represents the request type; req_write represents the request type as a read request; rd is the read enable signal; wr is the write enable signal; mem_map is a memory mapping table used to map the request address req_addr to a specific register address in the register group; eq refers to mapping req_addr to a register address through mem_map; X_sel is a selection signal used to select a specific register in the register group; X_reg represents the specific register in the register group selected by X_sel; X_re_en is the read enable signal for X_reg; X_wr_en is the write enable signal for X_reg; id_rd_en is the read enable signal for the ID register; id_wr_en is the write enable signal for the ID register; resp_data is the response data, the output data during read operations; and mux (Multiplexer) is a multiplexer.

[0135] In this implementation, the requested address `req_addr` is first compared with the memory mapping table `mem_map`, and the corresponding register address `X_sel` is selected. If `req_type` is read mode, read enable signals `rd` and `X_re_en` are generated, and the value of the selected register `X_reg` is read through the `X_re_en` signal. Finally, valid 32-bit data `resp_data` is selected and output through `mux`. If `req_type` is write mode, write enable signals `wr` and `X_wr_en` are generated, and the requested data `req_data` is written to the selected register `X_reg`.

[0136] In this implementation, when a core reads the ID register via a read request, a claim signal (i.e., the second signal) is generated, indicating that the interrupt has been read by the core and is being executed. That is, the second signal is generated when the kernel reads valid interrupt information written to the register set. Conversely, when a core writes to the ID register via a write request, a complete signal (i.e., the first signal) is generated, indicating that the interrupt has been completed. That is, the first signal is generated after detecting that the kernel has written the currently executing interrupt information to the register set.

[0137] When a read / write request is completed, the register bank can logically generate claim and complete signals. When a core reads the ID register, it means that the interrupt has been read by the core and is being executed, so a claim signal for the corresponding core is generated. When a core writes to the ID register, it means that the interrupt corresponding to the ID has been executed and a complete signal for the corresponding interrupt of the corresponding core is generated. After processing, these signals are used for the state transition of the interrupt gating unit and the change control of the interrupt nesting module in the interrupt routing unit.

[0138] It should be noted that the above examples are only for the purpose of assisting in understanding this application and do not constitute a limitation on the interrupt controller of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0139] Furthermore, this application also provides an electronic device that includes the interrupt controller provided in the above embodiments.

[0140] The electronic device proposed in this embodiment belongs to the same technical concept as the interrupt controller proposed in the above embodiments. Technical details not described in detail in this embodiment can be found in any of the above embodiments, and this embodiment has the same beneficial effects as the above embodiments of the interrupt controller. The electronic device proposed in this embodiment can be, but is not limited to, a CPU processor, a SOC chip, a mobile phone, a computer, a server, etc.

[0141] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. An interrupt controller, the interrupt controller comprising an interrupt routing unit, the interrupt routing unit comprising a routing module and an interrupt nesting module, the interrupt controller being applied to interrupt handling in the kernel, wherein, The routing module is configured to determine the valid interrupt information based on at least one interrupt information to be reported received, wherein the valid interrupt information is the interrupt information with the highest priority among at least one interrupt information to be reported. The interrupt nesting module stores the priority of the interrupt information that the kernel is currently executing; The routing module is further configured to compare the priority of the valid interrupt information with the priority of the currently executing interrupt information; after determining that the priority of the valid interrupt information is higher than the priority of the currently executing interrupt information, the valid interrupt information is reported to the kernel as the new currently executing interrupt information, and the priority of the original currently executing interrupt information is used as the priority of the interrupt information to be executed and written to the interrupt nesting module for priority-based nested storage; and After the kernel finishes executing the interrupt task corresponding to the current execution interrupt information, the priority of the current execution interrupt information stored in the interrupt nesting module is updated to the highest priority in the priority sorting of the nested register.

2. The interrupt controller as described in claim 1, wherein, The interrupt controller also includes a register group. After the kernel finishes executing the interrupt task corresponding to the current active interrupt information, it writes the completed active interrupt information into the register group. The register group is configured to generate a first signal after detecting that the kernel has written the currently completed execution interrupt information to the register group; The routing module is further configured to, upon detecting that the register group generates the first signal, notify the kernel to allow execution of the interrupt task corresponding to the highest priority pending interrupt information; and The routing module updates the priority of the currently executing interrupt information stored in the interrupt nesting module based on the highest priority interrupt information that is allowed to be executed.

3. The interrupt controller as described in claim 2, wherein, If the priority of the valid interrupt information is determined to be higher than the priority of the currently executing interrupt information, the routing module writes the valid interrupt information into the register group; The register group is also configured to generate a second signal when the kernel reads valid interrupt information written to the register group; and The routing module is further configured to, upon detecting that the register group generates the second signal, synchronously update the priority of the executing interrupt information stored in the interrupt nesting module and the priority of the pending interrupt information stored in the nested register, based on the valid interrupt information read by the kernel.

4. The interrupt controller as described in any one of claims 1 to 3, wherein, The interrupt routing unit also includes multiple comparators combined in serial and parallel order; The routing module is further configured to, when receiving multiple interrupt information to be reported simultaneously, perform priority comparison on the multiple interrupt information to be reported based on the multiple comparators combining serial and parallel communication, compare and determine the interrupt information with the highest priority among the interrupt information to be reported, and take the interrupt information with the highest priority among the interrupt information to be reported as the valid interrupt information. The priority comparison of multiple received interrupt information to be reported, based on multiple comparators combining serial and parallel methods, refers to the following: the multiple interrupt information to be reported is divided into a first number of first comparison groups, each of which consists of two interrupt information to be reported. The first number of comparators are used to compare and identify the first interrupt information with higher priority in each of the first comparison groups. The multiple first interrupt information is then divided into a second number of second comparison groups, each of which consists of two interrupt information to be reported. The second number of comparators are used to compare and identify the second interrupt information with higher priority in each of the second comparison groups. This process is repeated until a target number of target interrupt information with higher priority is determined from the received interrupt information to be reported. Finally, based on a serial comparison method, the interrupt information with the highest priority is determined from the target interrupt information.

5. The interrupt controller as described in claim 3, wherein, The interrupt controller further includes an interrupt gating unit, which is configured to receive interrupt task information generated by external triggering, and based on the arbitration result of the interrupt task information, determine to send the interrupt task information as interrupt information to be reported to the routing module. The routing module is configured to receive at least one interrupt information to be reported from the interrupt gating unit.

6. The interrupt controller as described in claim 5, wherein, The interrupt gating unit is also equipped with a state machine, which controls the current interrupt state. The routing module is further configured to send first information to the interrupt gating unit corresponding to the valid interrupt information read by the kernel when the second signal is detected generated by the register group. The first information is used to trigger the interrupt gating unit to control the current interrupt state to the first state through the state machine. The first state causes the interrupt gating unit to block the reception of new interrupt task information.

7. The interrupt controller as described in claim 6, wherein, The routing module is further configured to send second information to the interrupt gating unit corresponding to the currently executing interrupt information of the kernel when the first signal is detected generated by the register group. The second information is used to trigger the interrupt gating unit to control the current interrupt state to the second state through the state machine. The second state enables the interrupt gating unit to receive new interrupt task information.

8. The interrupt controller as described in claim 5, wherein, The interrupt gating unit is equipped with an interrupt event counter. Each time the interrupt gating unit receives interrupt task information triggered by a rising edge of the target, it increments the count value of the interrupt event counter by one until the count value of the interrupt event counter reaches a preset upper limit value. Each time the interrupt task information triggered by the rising edge of the target is sent to the routing module as interrupt information to be reported, and the count value of the interrupt event counter is not zero, the count value of the interrupt event counter is decremented by one.

9. The interrupt controller as described in any one of claims 5 to 7, wherein, The interrupt gating unit supports triggering methods for recognizing the interrupt task information, including edge triggering and level triggering.

10. An electronic device comprising an interrupt controller as claimed in any one of claims 1 to 9.

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