Chip and preparation method therefor, package substrate and preparation method therefor, chip package structure, terminal device, and communication system

Abstract

Embodiments of the present application relate to the technical field of electronics, and provide a chip and a preparation method therefor, a package substrate and a preparation method therefor, a chip package structure, a terminal device, and a communication system, for use in improving signal transmission performance in the chip package structure. The chip comprises a first dielectric layer, a first capacitor plate, and a second capacitor plate, wherein the second capacitor plate, the first capacitor plate, and the first dielectric layer located between the second capacitor plate and the first capacitor plate form a coupling capacitor. The capacitor formed in the chip can mitigate the problem of unequal return ground voltages between the chip and other chips caused by common‑mode matching requirements. Therefore, when the chip and the other chips are co‑packaged, a signal return structure in the package substrate may be implemented as a full‑layer structure, and a signal line does not need to cross splits in the package substrate, thereby improving signal transmission performance.

Description

Chips and their fabrication methods, packaging substrates and their fabrication methods, chip packaging structures, terminal equipment and communication systems

[0001] This application claims priority to Chinese patent application filed on December 27, 2024, with application number 202411957603.0, entitled "Chip and its preparation method, packaging substrate and its preparation method, chip packaging structure, terminal equipment and communication system", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic technology, and in particular to a chip and its preparation method, a packaging substrate and its preparation method, a chip packaging structure, a terminal device and a communication system. Background Technology

[0003] As the operating frequency of high-speed signals in packages continues to increase and the signal rise time continues to shorten, signal integrity and power integrity issues become increasingly serious. Many signal integrity-related problems arise from improper design of the signal return path.

[0004] In some products, signal crossover occurs. Crossover may have little impact on low-speed signals, but in high-speed scenarios, an incomplete return plane can lead to impedance discontinuities in the signal, causing crosstalk loss and insertion loss, thus affecting signal transmission performance. Summary of the Invention

[0005] This application provides a chip and its fabrication method, a packaging substrate and its fabrication method, a chip packaging structure, a terminal device, and a communication system for improving the signal transmission performance in the chip packaging structure.

[0006] A first aspect of this application provides a chip, which can be any type of chip such as a network chip, wireless chip, radio frequency chip, or terminal chip. The chip can be, for example, a bare chip or a packaged chip.

[0007] The chip includes a first dielectric layer, a first pad layer, and a second capacitor plate. The first pad layer is disposed on one side of the first dielectric layer, for example, on the surface of the chip. The first pad layer includes a first pad and a second pad spaced apart. The first pad serves as, for example, a first capacitor plate, for coupling with a signal return structure in the package substrate. The second pad serves as, for example, for coupling with a signal line in the package substrate. The second capacitor plate is disposed on the surface of the first dielectric layer away from the first pad layer. The second capacitor plate is, for example, located on the top metal layer of the chip. The projection of the second capacitor plate onto the first dielectric layer overlaps with the projection of the first pad onto the first dielectric layer. The second capacitor plate, the first pad, and the first dielectric layer located between the second capacitor plate and the first pad form a coupling capacitor.

[0008] High-speed signals use a reference plane as their return path. If gaps or breaks appear in the reference plane, causing discontinuities, the signal return path lengthens, loop inductance increases, and insertion loss and crosstalk occur. The chip provided in this embodiment includes a first capacitor plate, a second capacitor plate, and a coupling capacitor formed by a first dielectric layer between the first and second capacitor plates. The return ground voltages on the two capacitor plates of the coupling capacitor can be unequal. Therefore, when the chip interconnects with other chips, the capacitor formed in the chip can improve the problem of unequal return ground voltages with other chips due to common-mode matching requirements. Thus, when the chip is packaged with other chips, the signal return structure in the package substrate can be a single-layer structure with only one return ground voltage plane, eliminating the need for multiple return ground voltage planes within the package substrate. Signal lines do not need to cross partitions within the package substrate, improving the continuity of signal line impedance and reducing signal reflections caused by impedance abrupt changes. Furthermore, it reduces signal crosstalk, magnetic field interference, and magnetic field coupling caused by energy leakage at partitions, reduces waveform oscillations caused by increased loop inductance at partitions, and improves signal transmission performance.

[0009] In one possible implementation, the projection of the second capacitor plate onto the first dielectric layer does not overlap with the second pad. If the second capacitor plate overlaps with the second pad, it will affect the impedance of the second pad and the signal line coupled to the second pad, causing signal reflection and degrading the performance of the signal line. By completely misaligning the second capacitor plate with the second pad, the performance impact caused by overlap can be avoided.

[0010] In one possible implementation, the thickness of the first dielectric layer is less than or equal to 10 μm. By limiting the thickness of the first dielectric layer to less than or equal to 10 μm, the impedance between the second capacitor plate and the first pad can be reduced, thereby reducing the series impedance encountered by the signal return current, providing a low-impedance path for the signal return current, and further improving the signal insertion loss benefit.

[0011] In one possible implementation, the second pad and the first pad are arranged adjacent to each other. The second pad is used for signal transmission, and the first pad serves as an electrode of a coupling capacitor. The first pad is positioned close to the signal line, which shortens the signal return path and further improves communication performance.

[0012] In one possible implementation, the side of the second capacitor plate near the second pad has a recess. The recess is used to avoid signal lines in the chip coupled to the second pad, so as to ensure the impedance continuity of the signal lines, avoid signal reflection, and improve signal performance.

[0013] In one possible implementation, the second capacitor plate is a mesh structure. The second capacitor plate can be directly fabricated using the structure of the top metal layer of a chip, as described in related technologies, with minimal process changes and ease of implementation.

[0014] In one possible implementation, at least a portion of the recessed profile is stepped. The second capacitor plate has a mesh structure, which avoids signal lines in the chip by extending the mesh more or less, making it easy to manufacture and implement. Therefore, the final recessed profile is at least partially stepped.

[0015] In one possible implementation, the first pad is a block structure. By setting the first pad to a block structure, it is easier to align and bond the first pad with the package substrate, thereby improving yield.

[0016] In one possible implementation, the chip further includes a third capacitor plate and a second dielectric layer, with the second dielectric layer disposed between the second and third capacitor plates. The projections of the third and second capacitor plates onto the second dielectric layer overlap. The third capacitor plate, the second capacitor plate, and the second dielectric layer located between them form a capacitor. The coupling capacitor in the chip is equivalent to including two capacitors in series to increase the capacitance value. For products where the capacitance requirement cannot be met by increasing the capacitor size, the capacitance requirement can be met by setting a series capacitor.

[0017] In one possible implementation, the chip includes an analog multiplexing / demultiplexing chip. Even if the return ground voltage of the analog multiplexing / demultiplexing chip is not the reference ground voltage, the analog multiplexing / demultiplexing chip can be packaged with any other chip by integrating a capacitor in the analog multiplexing / demultiplexing chip.

[0018] A second aspect of this application provides a packaging substrate, which includes a third dielectric layer, a second pad layer, a wiring layer, a first conductive pillar, and a second conductive pillar. The second pad layer is disposed on one side of the third dielectric layer, and for example, is located on the surface of the packaging substrate. The second pad layer includes a third pad and a fourth pad spaced apart. The wiring layer is disposed on the side of the third dielectric layer away from the second pad layer; the wiring layer includes a signal line and a signal return structure, the signal return structure including an opening, and the signal line disposed within the opening. The first conductive pillar and the second conductive pillar respectively penetrate the third dielectric layer. The two ends of the first conductive pillar are coupled to the signal return structure and the third pad, respectively, and the two ends of the second conductive pillar are coupled to one end of the signal line and the fourth pad, respectively.

[0019] In one possible implementation, the packaging substrate further includes a third conductive pillar and a fourth conductive pillar, and the second pad layer further includes a fifth pad and a sixth pad. The two ends of the third conductive pillar are coupled to the signal return structure and the fifth pad, respectively, and the two ends of the fourth conductive pillar are coupled to the other end of the signal line and the sixth pad, respectively. The third and fourth pads are used to couple with one chip, and the fifth and sixth pads are used to couple with another chip. The two chips transmit signals through the signal line, using the signal return structure as a return plane.

[0020] In one possible implementation, the signal return structure is a reference ground return structure. Since the signal return in the package substrate is a reference ground return, it is possible to package chips with various return ground voltages as reference ground voltages on the package substrate.

[0021] A third aspect of this application provides a chip packaging structure, which includes a first chip and a packaging substrate. The first chip includes the chip as described in any of the first aspects; the packaging substrate includes the packaging substrate as described in any of the second aspects. A first pad of the chip is bonded to a third pad of the packaging substrate to form a first bonding portion, and a second pad of the chip is bonded to a fourth pad of the packaging substrate to form a second bonding portion. The projection of a second capacitor plate on the bonding layer overlaps with the first bonding portion.

[0022] High-speed signals use a reference plane as their return path. If gaps or breaks appear in the reference plane, causing discontinuities, the signal return path lengthens, loop inductance increases, and insertion loss and crosstalk occur. However, in the chip package structure provided in this application, the first chip communicates with other chips via signal lines. The capacitance formed in the first chip can mitigate the problem of unequal return ground voltages between the first chip and other chips due to common-mode matching requirements. Therefore, the signal return structure in the package substrate can be a single-layer structure, eliminating the need for multiple return ground voltage planes within the package substrate. Signal lines do not need to cross partitions within the package substrate, improving the continuity of signal line impedance and reducing signal reflections caused by impedance abrupt changes. Furthermore, it reduces signal crosstalk, magnetic field interference, and magnetic field coupling caused by energy leakage at partitions, reduces waveform oscillations caused by increased loop inductance at partitions, and improves signal transmission performance.

[0023] In one possible implementation, the chip package structure further includes a second chip; the second chip is bonded to a fifth pad to form a third bonding portion, and to a sixth pad to form a fourth bonding portion. Both the first and second chips are coupled to the signal return structure, eliminating the need for a cross-segment return ground voltage plane within the package substrate, thus improving signal transmission performance.

[0024] In one possible implementation, the second chip includes an optical digital signal processing chip. In products where the analog multiplexing / demultiplexing chip and the optical digital signal processing chip are co-packaged, the signal return structure is a continuous, full-layer structure, which can improve signal transmission performance.

[0025] A fourth aspect of this application provides a chip packaging structure, comprising a packaging substrate, a bonding layer, and a first chip, wherein the first chip is bonded to the packaging substrate via the bonding layer. The packaging substrate includes a wiring layer, a fourth dielectric layer, a fifth conductive pillar, and a sixth conductive pillar, wherein the fourth dielectric layer is disposed between the wiring layer and the bonding layer. The wiring layer includes signal lines and a signal return structure, wherein the signal return structure includes an opening, and the signal line is disposed within the opening; the fifth conductive pillar penetrates the fourth dielectric layer and is coupled to the signal return structure, and the sixth conductive pillar penetrates the fourth dielectric layer and is coupled to the signal line. The bonding layer includes a fifth bonding portion and a sixth bonding portion spaced apart. The first chip is coupled to the fifth conductive pillar via the fifth bonding portion and to the sixth conductive pillar via the sixth bonding portion; the first chip includes a third conductive structure and a fifth dielectric layer, wherein the fifth dielectric layer is disposed between the third conductive structure and the bonding layer; the projection of the third conductive structure onto the bonding layer overlaps with the fifth bonding portion.

[0026] In one possible implementation, the chip package structure further includes a seventh conductive pillar and an eighth conductive pillar, and the bonding layer further includes a seventh bonding portion and an eighth bonding portion. The chip package structure also includes a second chip; the second chip is coupled to the seventh conductive pillar via the bonding portion, and the second chip is also coupled to the eighth conductive pillar via the eighth bonding portion. The seventh and eighth conductive pillars respectively penetrate the fourth dielectric layer. The seventh conductive pillar is coupled to the signal return structure, and the eighth conductive pillar penetrates the fourth dielectric layer and is coupled to the signal line. Since both the first and second chips are coupled to the signal return structure, there is no need to set a cross-segment return ground voltage plane within the package substrate, which can improve signal transmission performance.

[0027] In one possible implementation, the projection of the third conductive structure onto the bonding layer does not overlap with the sixth bonding portion. If the third conductive structure overlaps with the sixth bonding portion, it will affect the impedance of the sixth bonding portion and the signal line coupled to it, causing signal reflection and degrading the performance of the signal line. However, by completely misaligning the third conductive structure with the sixth bonding portion, the performance impact caused by overlap can be avoided.

[0028] In one possible implementation, the thickness of the fifth dielectric layer is less than or equal to 10 μm. By limiting the thickness of the fifth dielectric layer to less than or equal to 10 μm, the impedance between the third conductive structure and the fifth bonding portion can be reduced, thereby reducing the series impedance encountered by the signal return flow, providing a low-impedance path for the signal return flow, and further improving the signal insertion loss gain.

[0029] In one possible implementation, the fifth and sixth bonding portions are arranged adjacent to each other. The sixth bonding portion is used for signal transmission, and the fifth bonding portion serves as one electrode of the coupling capacitor. The fifth bonding portion is positioned close to the signal line, which shortens the signal return path and further improves communication performance.

[0030] In one possible implementation, the third conductive structure has a recess on its side near the sixth bonding portion. This recess serves to avoid signal lines coupled to the sixth bonding portion within the chip, thereby ensuring signal line impedance continuity, preventing signal reflection, and improving signal performance.

[0031] In one possible implementation, the third conductive structure is a mesh structure. This third conductive structure can be directly fabricated using the structure of the top metal layer of a chip, with minimal process changes and ease of implementation.

[0032] In one possible implementation, at least a portion of the recess's contour is stepped. The third conductive structure is a mesh structure, which avoids signal lines in the chip by extending the mesh more or less, making it easy to manufacture and implement. Therefore, the final recess will have at least a stepped contour.

[0033] In one possible implementation, the chip further includes a fourth conductive structure and a sixth dielectric layer, with the sixth dielectric layer disposed between the fourth and third conductive structures. The projections of the third conductive structure onto the sixth dielectric layer overlap. The third conductive structure, the fourth conductive structure, and the sixth dielectric layer between them form a capacitor. The coupling capacitor in the chip is equivalent to including two capacitors in series to increase the capacitance value. For products where increasing the capacitor size cannot meet the capacitance requirement, the capacitance requirement can be met by using a series capacitor.

[0034] In one possible implementation, the first chip includes an analog multiplexing / demultiplexing chip. Even if the return ground voltage of the analog multiplexing / demultiplexing chip is not the reference ground voltage, the analog multiplexing / demultiplexing chip can be packaged with any other chip by integrating a capacitor in the analog multiplexing / demultiplexing chip.

[0035] In one possible implementation, the second chip includes an optical digital signal processing chip. In products where the analog multiplexing / demultiplexing chip and the optical digital signal processing chip are co-packaged, the signal return structure is a continuous, full-layer structure, which can improve signal transmission performance.

[0036] A fifth aspect of the embodiments of this application provides a terminal device, the terminal device including: a circuit board and a chip packaging structure as described in any of the third or fourth aspects, the chip packaging structure being disposed on the circuit board.

[0037] The terminal device provided in this application includes a chip packaging structure according to any one of the third or fourth aspects, and its beneficial effects are the same as those of the chip packaging structure, which will not be repeated here.

[0038] In one possible implementation, the terminal device is a coherent optical module. In high-speed scenarios, the transmission performance of coherent optical modules is significantly affected by signal segmentation; the solution proposed in this application can improve the transmission performance of coherent optical modules.

[0039] A sixth aspect of the embodiments of this application provides a communication system, the communication system including two coherent optical modules and an optical fiber channel, the two coherent optical modules being connected through the optical fiber channel; the coherent optical modules include the coherent optical modules as described in the fifth aspect.

[0040] A seventh aspect of this application provides a method for fabricating a chip. The method includes forming a first pad layer, a first dielectric layer, and a second capacitor electrode. The first pad layer is located on a surface of the first dielectric layer. The first pad layer includes first pads and second pads spaced apart. The first pads serve as the first capacitor electrode. The second capacitor electrode is located on a surface of the first dielectric layer away from the first pad layer. The projection of the second capacitor electrode onto the first dielectric layer overlaps with the projection of the first pads onto the first dielectric layer. The beneficial effects of the chip fabricated by the method provided in the seventh aspect of this application are the same as those of the chip provided in the first aspect, and will not be repeated here.

[0041] In one possible implementation, the projection of the second capacitor plate onto the first dielectric layer does not overlap with the second pad.

[0042] In one possible implementation, the thickness of the first dielectric layer is less than or equal to 10 μm.

[0043] In one possible implementation, the second pad and the first pad are arranged adjacent to each other.

[0044] An eighth aspect of this application provides a method for fabricating a packaging substrate. The method includes forming a second pad layer, a third dielectric layer, a wiring layer, a first conductive pillar, and a second conductive pillar. The second pad layer is located on one side of the third dielectric layer. The second pad layer includes a third pad and a fourth pad spaced apart. The wiring layer is located on the side of the third dielectric layer away from the second pad layer. The wiring layer includes a signal line and a signal return structure. The signal return structure includes an opening, and the signal line is disposed within the opening. The first conductive pillar and the second conductive pillar respectively penetrate the third dielectric layer. The two ends of the first conductive pillar are coupled to the signal return structure and the third pad, respectively, and the two ends of the second conductive pillar are coupled to one end of the signal line and the fourth pad, respectively. The beneficial effects of the packaging substrate fabricated by the method provided in the eighth aspect of this application are the same as those of the packaging substrate provided in the second aspect, and will not be repeated here.

[0045] In one possible implementation, the signal return structure is a reference ground return structure. Attached Figure Description

[0046] Figure 1A is an architecture diagram of a communication system provided in an embodiment of this application;

[0047] Figure 1B is a schematic diagram of the structure of a coherent optical module provided in an embodiment of this application;

[0048] Figure 2A is a schematic diagram of a chip packaging structure;

[0049] Figure 2B is a topological schematic diagram of a chip packaging structure;

[0050] Figure 2C is a schematic diagram of another chip packaging structure;

[0051] Figure 2D is a topological schematic diagram of another chip packaging structure;

[0052] Figure 2E is a structural schematic diagram of a cross-segment product;

[0053] Figure 2F shows the energy leakage field diagram when the signal return plane is split.

[0054] Figure 3A is a schematic diagram of an improvement scheme for the cross-segmentation problem applied to a circuit board;

[0055] Figure 3B is a schematic diagram of another solution for improving the cross-segmentation problem applied to circuit boards;

[0056] Figure 4A is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0057] Figure 4B is a partial structural schematic diagram of a packaging substrate 80 provided in an embodiment of this application;

[0058] Figure 4C is a topological schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0059] Figure 4D is a comparison chart of crosstalk benefits of different products provided in an embodiment of this application;

[0060] Figure 5A is a schematic diagram of a signal return path provided in an embodiment of this application;

[0061] Figure 5B is an equivalent topology diagram of a signal return path provided in an embodiment of this application;

[0062] Figure 5C is a comparison chart of insertion loss benefits of different products provided in an embodiment of this application;

[0063] Figures 6A-6C are schematic diagrams of the structure of a first chip provided in an embodiment of this application;

[0064] Figure 7A is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0065] Figure 7B is a schematic diagram of a portion of the film layers of a chip packaging structure provided in an embodiment of this application;

[0066] Figure 8 is a schematic diagram showing the correspondence between a chip and a packaging substrate provided in an embodiment of this application;

[0067] Figure 9 is a partial structural schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0068] Figure 10 is an enlarged schematic diagram of a second capacitor plate provided in an embodiment of this application at point W in Figure 9;

[0069] Figure 11 is a schematic diagram of the structure of a first capacitor provided in an embodiment of this application.

[0070] Reference numerals: 1-Communication system; 10-Coherent optical module; 20-Fiber optic channel; 50-Chip packaging structure; 60-First chip; 61-First dielectric layer; 62-Second capacitor plate; 63-First pad layer; 631-First pad; 632-Second pad; 633-Fifth pad; 634-Sixth pad; 64-Second dielectric layer; 65-Third capacitor plate; 70-Second chip; 71-Seventh pad; 72-Eighth pad; 80-Packaging substrate; 81-Wiring layer; 811-Signal return structure; 812-Signal line; 82-Third dielectric layer; 83-First conductive pillar; 84-Second conductive pillar; 85-Third conductive pillar; 86-Fourth conductive pillar; 87-Second pad layer; 871-Third pad; 872-Fourth pad; 873-Fifth pad; 874-Sixth pad; 88-Accompanying conductive pillar; 90 - Bonding layer; 91 - First bonding portion; 92 - Second bonding portion; 93 - Third bonding portion; 94 - Fourth bonding portion; C - Capacitor; C1 - First capacitor; C2 - Second capacitor. Detailed Implementation

[0071] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0072] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0073] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0074] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0075] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0076] This application provides a terminal device. This terminal device can be, for example, an electronic device or a communication device. Communication devices include, for example, high-speed communication devices such as coherent optical modules. Electronic devices include, for example, consumer electronics, home electronics, in-vehicle electronics, or financial electronic devices. Consumer electronics include, for example, mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, servers, etc. Home electronics include, for example, smart locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), switches, etc. In-vehicle electronic devices include, for example, in-vehicle navigation systems, in-vehicle DVDs, etc. Financial electronic devices include, for example, ATMs, self-service electronic devices, etc.

[0077] This application does not impose any special limitations on the specific form of the above-described electronic device. For ease of explanation, the following embodiments all use a coherent optical module as an example of a terminal device. For example, a coherent optical module can be applied to the communication system provided in this application.

[0078] Figure 1A is an architecture diagram of a communication system provided in an embodiment of this application.

[0079] As shown in Figure 1A, this application embodiment provides a communication system 1, which includes two coherent optical modules 10 and an optical fiber channel 20. The two coherent optical modules 10 are connected through the optical fiber channel 20.

[0080] As a key component in fiber optic communication systems, the coherent optical module 10's core function is to convert electrical signals into optical signals. This solves the problems of signal attenuation and interference in traditional cable communication, ensuring efficient and long-distance signal transmission in fiber optic networks. Coherent light can be understood as light waves with the same frequency and a fixed phase relationship in optics.

[0081] The function of the coherent optical module 10 at the transmitting end is to convert the electrical signal into an optical signal, and then transmit the optical signal through the optical fiber channel 20 to the coherent optical module 10 at the receiving end. The function of the coherent optical module 10 at the receiving end is to convert the optical signal back into an optical signal and output it. Figure 1B is a schematic diagram of the structure of a coherent optical module provided in an embodiment of this application.

[0082] As shown in Figure 1B, for example, the coherent optical module 10 includes structures such as a circuit board assembly and interfaces. The circuit board assembly includes a printed circuit board (PCB) and various functional chips mounted on the PCB.

[0083] For example, the circuit board assembly includes a chip package structure 50 disposed on the circuit board and an unpackaged third chip. That is, the chip can be encapsulated on the PCB or the chip can be a separate chip disposed on the PCB. The chip package structure 50 includes, for example, a first chip and a second chip encapsulated on a packaging substrate. The coherent optical module 10 can be any product structure in the related art, and the circuit board assembly can also have various different architectures.

[0084] Optionally, the first chip includes an analog-multiplexer / de-multiplexer (A / D MUX) chip, the second chip includes an optical digital signal processing (oDSP) chip, and the chip package structure 50 is the digital signal processing component in the coherent optical module 10. The third chip may include, for example, an integrated tunable laser assembly (ITLA), a coherent driver modulator (CDM), and an integrated coherent receiver (ICR).

[0085] The coherent optical module 10 is used to achieve efficient, long-distance signal transmission with a relatively high signal rate. However, the incomplete return plane in the chip package structure 50 of the coherent optical module 10 causes impedance discontinuities in the signal, which significantly affects the transmission performance.

[0086] Figure 2A is a schematic diagram of one chip packaging structure, Figure 2B is a topological schematic diagram of one chip packaging structure, Figure 2C is a schematic diagram of another chip packaging structure, and Figure 2D is a topological schematic diagram of another chip packaging structure. Figure 2E is a structural schematic diagram of a cross-segment product.

[0087] In some technologies, structural adjustments have been made to the chip package structure 50 to mitigate the impact of incomplete return plane on transmission performance.

[0088] As shown in Figure 2A, the chip package structure 50 includes a package substrate, an oDSP chip, an A / D MUX chip, and a capacitor C. The oDSP chip and the A / D MUX chip are located on the same side of the package substrate, and the capacitor C is integrated inside the package substrate and coupled to the communication path between the oDSP chip and the A / D MUX chip.

[0089] As shown in Figure 2B, the power supply voltages of the oDSP chip and the A / DMUX chip are 1.2V and 4.8V, respectively. However, by setting an AC coupling capacitor on the communication path of the oDSP chip and the A / DMUX chip, common-mode matching of the signals of the oDSP chip and the A / DMUX chip can be achieved. At this time, the return ground voltage of both the oDSP chip and the A / DMUX chip is 0V. However, the integration cost of capacitor C is high, it occupies a large space, and it will introduce insertion loss.

[0090] Therefore, as shown in Figure 2C, it is desirable to remove the AC coupling capacitors on the signal path. As shown in Figure 2D, the power supply voltages of the oDSP chip and the A / DMUX chip are 1.2V and 1.8V, respectively. To meet the common-mode matching requirements, the return ground voltage of the oDSP chip is 0V, while the return ground voltage of the A / DMUX chip is -3V. As shown in Figure 2E, the 0V return ground plane can be bonded to the oDSP chip via a pad layer, and the -3V return ground plane can be bonded to the A / DMUX chip via a pad layer. In package design, the phenomenon where the return plane of a signal trace crosses from one plane to another is called signal cross-split.

[0091] For example, in Figure 2C, the reference plane of the signal trace spans from a 0V voltage plane to a -3V voltage plane. The 0V and -3V voltage planes serve as the return ground signals for the oDSP chip and the A / DMUX chip, respectively. Therefore, the division between the 0V and -3V voltage planes can be understood as the division of the reference ground plane.

[0092] Figure 2F shows the energy leakage field diagram when the signal return plane is split.

[0093] The impact of cross-segmentation on low-speed signals may be minimal, but in high-speed scenarios, since high-speed signals use the return plane as the return path, the following adverse effects will occur when the return plane is discontinuous: (1) The impedance of the traces will change abruptly at the segmentation point, resulting in impedance discontinuity of the traces. (2) The impedance change of the signal lines will cause reflection between signals. (3) As shown in Figure 2F, the energy leakage at the segmentation point indicates that there will be signal leakage at the segmentation point, which will cause crosstalk between signals. (4) Signal leakage will increase the radiation interference in space and is also easily affected by the space magnetic field. (5) Signal leakage will also increase the possibility of magnetic field coupling with other circuits on the package substrate. (6) After the return path is segmented, the return current will flow along the gap, increasing the loop area of ​​the return current and increasing the loop inductance, making the output waveform prone to oscillation. The above adverse effects will cause crosstalk loss and insertion loss of the chip package structure 50, affecting the signal transmission performance.

[0094] Figure 3A is a schematic diagram of an improvement scheme for the cross-segment problem applied to a circuit board. Figure 3B is a schematic diagram of another improvement scheme for the cross-segment problem applied to a circuit board.

[0095] As shown in Figure 3A, in some technologies, an AC coupling capacitor is placed at the signal crossover point on the circuit board. The presence of the capacitor provides a low-impedance path for the return current of the signal, suppresses energy leakage, and improves signal transmission performance.

[0096] However, placing capacitors on the circuit board takes up space, making it unsuitable for products with high integration requirements. Furthermore, the bandwidth of the capacitor must match the bandwidth of the signal line; a larger bandwidth increases the capacitor's cost. Moreover, capacitors need to be coupled to the circuit board via bonding, resulting in a larger equivalent series inductance (ESL) and higher impedance in the return path, limiting the improvement in insertion loss and crosstalk.

[0097] As shown in Figure 3B, in some technologies, bridging lines are set on the circuit board. By setting a bridging line on the same layer as the signal line, stable return current processing of the segmented signal can be achieved at the signal line layer. For example, a 0V bridging line can be used for return current at the position corresponding to the -3V negative power supply plane to improve insertion loss and crosstalk.

[0098] However, in this approach, the two ends of the bridge line cannot be connected to different voltage levels; they must be connected at equal voltage levels, which limits its applicability. Furthermore, in highly integrated scenarios, it is not possible to set separate bridge lines on both sides of each signal line, thus limiting the improvement in insertion loss and crosstalk.

[0099] As can be seen from the above description, there is currently no good solution in the field for the performance loss caused by the cross-segmentation of the reflow plane. Moreover, the improvement solutions mentioned above that are applied to circuit boards may not be applicable to packaging substrates, and even if they are applicable, the performance improvement effect is relatively limited.

[0100] This application provides a chip packaging structure 50 that can effectively reduce crosstalk loss and insertion loss caused by cross-segmentation of the return plane, thereby improving signal transmission performance. Of course, the chip packaging structure 50 provided in this application can also be applied to terminal devices such as electronic devices; the above is merely an illustrative example using a coherent optical module 10.

[0101] Figure 4A is a schematic diagram of a chip packaging structure provided in an embodiment of this application; Figure 4B is a partial structural schematic diagram of a packaging substrate 80 provided in an embodiment of this application; and Figure 4C is a topological schematic diagram of a chip packaging structure provided in an embodiment of this application.

[0102] This application provides a chip package structure 50, as shown in FIG4A. The chip package structure 50 includes a first chip 60 and a packaging substrate 80 provided in this application embodiment. For example, the chip package structure 50 further includes a second chip 70, and the first chip 60 and the second chip 70 can, for example, exchange signals through the packaging substrate 80. The chip package structure 50 may also include other chips, which are not shown in FIG4A.

[0103] The first chip 60 may be, for example, a network chip, a wireless chip, a radio frequency chip, or a terminal chip, and the second chip 70 may be, for example, a network chip, a wireless chip, a radio frequency chip, or a terminal chip. This application embodiment does not limit the specific structure of the first chip 60 and the second chip 70. For example, the first chip 60 and the second chip 70 are network chips. For instance, the first chip 60 includes an A / D MUX chip, and the second chip 70 includes an oDSP chip.

[0104] The chip package structure 50 also includes a bonding layer 90, through which the first chip 60 and the second chip 70 are bonded to the package substrate 80. For example, the bonding layer 90 includes a first bonding portion 91, a second bonding portion 92, a third bonding portion 93, and a fourth bonding portion 94. The first chip 60 is bonded to the package substrate 80 through the first bonding portion 91 and the second bonding portion 92, and the second chip 70 is bonded to the package substrate 80 through the third bonding portion 93 and the fourth bonding portion 94. Other bonding portions may also be included between the first chip 60 and the package substrate 80, and other bonding portions may also be included between the second chip 70 and the package substrate; this is merely an illustration.

[0105] The first chip 60 includes a first dielectric layer 61 and a second capacitor plate 62. The second capacitor plate 62 is disposed on the surface of the first dielectric layer 61 away from the bonding layer 90. The projection of the second capacitor plate 62 on the first dielectric layer 61 overlaps with the projection of the first bonding portion 91 on the first dielectric layer 61.

[0106] Overlap can be complete, such as being identical, or incomplete, such as having some overlap. The projection of the second capacitor plate 62 onto the first dielectric layer 61 overlaps with the projection of the first bonding portion 91 onto the first dielectric layer 61, the purpose of which is to form the first capacitor C1. Therefore, the degree of overlap between the projections of the second capacitor plate 62 and the first bonding portion 91 is related to their shapes and target capacitance values. The larger the capacitance value of the first capacitor C1, the smaller the parasitics, the larger the signal bandwidth, and the higher the signal transmission rate it can withstand.

[0107] The packaging substrate 80 includes a wiring layer, a third dielectric layer 82, and a first conductive post 83. The third dielectric layer 82 is disposed between the wiring layer and the bonding layer 90. The wiring layer includes a signal return structure 811. The first conductive post 83 penetrates the third dielectric layer 82 and is coupled to both the signal return structure 811 and the first bonding portion 91. Alternatively, the packaging substrate 80 may further include a third conductive post 85, which penetrates the third dielectric layer 82 and is coupled to both the signal return structure 811 and the third bonding portion 93.

[0108] The second capacitor plate 62, the first bonding portion 91, and the first dielectric layer 61 located between the second capacitor plate 62 and the first bonding portion 91 of the first chip 60 constitute a first capacitor C1. Regardless of the return ground voltage of the first chip 60, the return ground voltage of the first chip 60 can be coupled to the signal return structure 811 of the packaging substrate 80 through the AC coupling effect of the first capacitor C1. The second chip 70 is bonded to the third bonding portion 93, and the second chip 70 is coupled to the signal return structure 811 of the packaging substrate 80 through the third bonding portion 93.

[0109] Signal return refers to the process where, during signal transmission, the signal current flows from the driver end to the load end via a trace, and then returns from the load end to the driver end through the path of lowest impedance. This return signal on the path of lowest impedance is called the signal return path, and the structure used to transmit the return signal is called the signal return structure 811.

[0110] Taking Figure 4A as an example, the signal from the first chip 60 is transmitted to the second chip 70 via signal line 812, and then from the second chip 70 to the signal return structure 811 via the third conductive post 85. Finally, it returns to the first chip 60 via the first conductive post 83. The signal return structure 811, as the lowest impedance path for transmitting the returned signal, is located within the package substrate 80. From a physical structure perspective, the signal return structure 811 can be understood as the ground terminal in the circuit topology of the first chip 60 and the second chip 70.

[0111] As shown in Figure 4B, the signal return structure 811 in the packaging substrate 80 is a single-layer structure, shared by the first chip 60 and the second chip 70. For example, the wiring layer 81 includes the signal return structure 811 and signal lines 812. The signal return structure 811 includes an opening, and the signal lines 812 are disposed within the opening. The signal return structure 811 can be understood, for example, as a ground structure accompanying the signal lines 812, disposed on opposite sides of the signal lines 812, and in the same direction of extension as the signal lines 812.

[0112] The package substrate 80 may include a single signal line 812, or it may include multiple signal lines 812. For example, the package substrate 80 may include two signal lines 812, which form a pair of differential signal lines.

[0113] The opening on the signal return structure 811 can be a closed opening as shown in Figure 4B, for example, by removing part of the structure in the middle of the conductive layer to form an opening. The opening on the signal return structure 811 can also be an open opening. The notch of the opening on the signal return structure 811 is located at the end of the signal line 812; for example, the structure of the signal return structure 811 is U-shaped. The shape of the opening is not limited in this embodiment.

[0114] The packaging substrate 80 also includes a second conductive post 84 and a fourth conductive post 86, which penetrate the third dielectric layer 82. The two ends of the second conductive post 84 are coupled to one end of the signal line 812 and the second bonding portion 92, respectively. The two ends of the fourth conductive post 86 are coupled to the other end of the signal line 812 and the fourth bonding portion 94, respectively. The first chip 60 and the second chip 70 are interconnected and communicate via the signal line 812. The first capacitor C1 can improve the problem of unequal return-to-ground voltages of the first chip 60 and the second chip 70 due to common-mode matching requirements. Therefore, the signal return structure 811 in the packaging substrate 80 can be a single-layer structure, and the signal line 812 does not need to cross any partitions within the packaging substrate 80.

[0115] For example, as shown in Figure 4C, the first chip 60 includes an A / D MUX chip, and the second chip 70 includes an oDSP chip. When the packaging substrate 80 includes a signal return structure 811, the AC coupling effect of the first capacitor C1 can realize the signal return of the A / D MUX chip and the oDSP chip.

[0116] Figure 4D is a comparison chart of crosstalk benefits of different products provided in an embodiment of this application.

[0117] In Figure 4D, the horizontal axis represents frequency and the vertical axis represents amplitude. With the other structures of the chip package structure 50 remaining unchanged, simulation analysis of the chip package structure 50 obtained by adopting the package cross-segmentation scheme shown in Figure 2E, the package stitching capacitor scheme shown in Figure 3A to improve the cross-segmentation, and the cross-segmentation transfer scheme shown in Figure 4A of this application to improve the cross-segmentation shows that the crosstalk benefit of the chip package structure provided in this application is significantly improved.

[0118] High-speed signals use a reference plane as their return path. If gaps or breaks appear in the reference plane, causing discontinuities, the signal return path lengthens, loop inductance increases, and insertion loss and crosstalk occur. In the chip package structure 500 provided in this embodiment, the first chip 60 and the second chip 70 are interconnected via signal line 812. The first capacitor C1, acting as a coupling capacitor, can improve the problem of unequal return ground voltages between the first chip 60 and the second chip 70 due to common-mode matching requirements. Therefore, the signal return structure 811 in the package substrate 80 can be a single-layer structure, eliminating the need for multiple return ground voltage planes within the package substrate 80. The signal line 812 does not need to cross segments within the package substrate 80, improving the impedance continuity of the signal line 812 in the package and reducing signal reflections caused by impedance abrupt changes in the signal line 812. Furthermore, it reduces signal crosstalk, magnetic field interference, and magnetic field coupling caused by energy leakage at the segment, reduces waveform oscillations caused by increased loop inductance at the segment, and improves signal transmission performance.

[0119] In some embodiments, the thickness of the first dielectric layer 61 is less than or equal to 10 μm. For example, the thickness of the first dielectric layer 61 is 10 μm, 9 μm, 8 μm, 7 μm, 6 μm, 5 μm, 4 μm, 3 μm, 2 μm, 1 μm, or 0.5 μm.

[0120] Figure 5A is a schematic diagram of a signal return path provided in an embodiment of this application; Figure 5B is an equivalent topology diagram of a signal return path provided in an embodiment of this application; and Figure 5C is a comparison diagram of insertion loss benefits of different products provided in an embodiment of this application.

[0121] As shown in Figure 5A, according to transmission line theory, the signal return path can switch reference planes. After the signal is transmitted through signal line 812, the signal return path is through signal return structure 811 to the first bonding part 91, and then to the second capacitor plate 62. As shown in Figure 5B, the series impedance encountered by the signal return is Z = Z 812-91 +Z 91-62 Z 812-91 Z is the return impedance from signal line 812 to the first bonding section 91. 91-62 To reduce the return current impedance from the first bonding portion 91 to the second capacitor plate 62, Z can be reduced by limiting the thickness of the first dielectric layer 61 to less than or equal to 10 μm. 91- 62 This reduces the series impedance encountered by the signal return, provides a low-impedance path for the signal return, and further improves the signal insertion loss benefit.

[0122] For example, as shown in Figure 5C, the horizontal axis represents frequency and the vertical axis represents amplitude. With the other structures of the chip package structure 50 remaining unchanged, simulation analysis of the chip package structure 50 obtained by adopting the package cross-segment scheme shown in Figure 2E, the package stitching capacitor scheme shown in Figure 3A to improve the cross-segment, and the cross-segment transfer scheme shown in Figure 4A of this application to improve the cross-segment shows that the insertion loss benefit of the chip package structure provided by this application is significantly improved.

[0123] Figures 6A-6C are schematic diagrams of the structure of a first chip provided in an embodiment of this application.

[0124] In some embodiments, as shown in FIG6A, the first chip 60 includes a first dielectric layer 61, a second capacitor plate 62, and a first pad layer 63.

[0125] The first pad layer 63 is disposed on the surface of one side of the first dielectric layer 61. The first pad layer 63 includes a first pad 631 and a second pad 632 disposed at intervals. The first pad 631 and the second pad 632 are used for bonding with the package substrate 80. The first pad layer 63 can be understood, for example, as the surface layer of the first chip 60.

[0126] The first pad 631, for example, is used to bond with the package substrate 80 and then couple to the signal return structure 811 via the first conductive post 83. The second pad 632, for example, is used to bond with the package substrate 80 and then couple to the signal line 812 via the second conductive post 84. The first pad layer 63 may also include pads with other functions, which are not limited in this embodiment.

[0127] The second capacitor plate 62 is disposed on the surface of the first dielectric layer 61 away from the first pad layer 63. The second capacitor plate 62 can be understood, for example, as a structure in the top metal layer of the first chip 60. A dielectric layer is disposed between the second capacitor plate 62 and the first pad layer 63, and the projection of the second capacitor plate 62 on the first dielectric layer 61 overlaps with the projection of the first pad 631 on the first dielectric layer 61.

[0128] Overlap can be complete, such as being identical, or incomplete, such as having some overlap. The projection of the second capacitor plate 62 onto the first dielectric layer 61 overlaps with the projection of the first pad 631 onto the first dielectric layer 61, the purpose of which is to form the first capacitor C1. Therefore, the degree of overlap between the projections of the second capacitor plate 62 and the first pad 631 is related to their shapes and target capacitance values. The larger the capacitance value of the first capacitor C1, the larger the signal bandwidth and the higher the signal transmission rate it can withstand.

[0129] The first capacitor C1 formed in the chip package structure 50 is formed by the second capacitor plate 62 and the first pad 631, with the first pad 631 serving as the first capacitor plate. Therefore, based on the capacitance requirement, the overlap between the projection of the second capacitor plate 62 and the projection of the first pad 631 can be designed directly at the chip manufacturing stage. Subsequently, the first pad 631 can be directly bonded to the package substrate 80. There are no special requirements for the pad pattern of the package substrate 80, and factors such as bonding alignment deviations or dimensional deviations have minimal impact on the capacitance value of the first capacitor C1, resulting in good performance stability of the chip package structure 50.

[0130] In some embodiments, as shown in FIG6B, the first chip 60 further includes a third capacitor plate 65 and a second dielectric layer 64. The second dielectric layer 64 is disposed between the second capacitor plate 62 and the third capacitor plate 65, and the projection of the third capacitor plate 65 on the second dielectric layer 64 overlaps with the projection of the second capacitor plate 62 on the second dielectric layer 64.

[0131] The third capacitor plate 65, the second capacitor plate 62, and the second dielectric layer 64 located between the third capacitor plate 65 and the second capacitor plate 62 form the second capacitor C2. The coupling capacitor in the chip package structure 50 is equivalent to including the first capacitor C1 and the second capacitor C2 in series to increase the capacitance value of the coupling capacitor. For products where the capacitance requirement cannot be met by increasing the size of the first capacitor C1, the capacitance requirement can be met by setting the first capacitor C1 and the second capacitor C2 in series.

[0132] For example, as shown in Figure 6C, the first chip 60 also includes a transistor device layer and a wiring layer disposed on the side of the second capacitor plate 62 away from the first dielectric layer 61, so as to realize the corresponding function of the first chip 60.

[0133] The transistor device layer includes, for example, a transistor device structure formed using a front-end of line (FEOL) process. The wiring layer and the second capacitor plate 62 can be, for example, a redistribution layer structure formed using a back-end of line (BEOL) process. The redistribution layer is used to realize interconnections between transistor device structures and to realize interconnections between the first chip 60 and external devices through a pad layer. This application embodiment does not limit the internal interconnection method of the first chip 60. Except for the structure of the first capacitor C1, other structures can be internally interconnected using methods in related technologies that implement the corresponding functions of the first chip 60.

[0134] For example, the first chip 60 includes wiring disposed on the same layer as the second capacitor plate 62. The second pad 632 is coupled to the wiring through conductive pillars penetrating the first dielectric layer 61. The wiring is then coupled layer by layer to the transistors in the transistor device layer through the conductive pillars. The second capacitor plate 62 is coupled layer by layer to the transistors in the body transistor device layer through conductive pillars and wiring.

[0135] The second capacitor plate 62 serves as one electrode of the first capacitor, and its shape is related to the capacitance value of the first capacitor C1. The width of the second capacitor plate 62 and the linewidth of the wiring disposed on the same layer as the second capacitor plate 62 may be significantly different. This application also provides a method for fabricating a chip, the method comprising: forming the aforementioned second capacitor plate 62, a first dielectric layer 61, and a first pad layer 63.

[0136] For example, the first pad layer 63 is located on the surface of the first dielectric layer 61. The first pad layer 63 includes a first pad 631 and a second pad 632 spaced apart. The first pad 631 serves as a first capacitor plate. The second capacitor plate 62 is located on the surface of the first dielectric layer 61 away from the first pad layer 63. The projection of the second capacitor plate 62 on the first dielectric layer 61 overlaps with the projection of the first pad 631 on the first dielectric layer 61.

[0137] Figure 7A is a schematic diagram of a chip packaging structure provided in an embodiment of this application, and Figure 7B is a schematic diagram of a portion of the film layers of a chip packaging structure provided in an embodiment of this application.

[0138] In some embodiments, as shown in FIG7A, the packaging substrate 80 includes the wiring layer 81, the third dielectric layer 82, the first conductive pillar 83, the second conductive pillar 84, and the second pad layer 87.

[0139] The second pad layer 87 is disposed on one side of the third dielectric layer 82. The second pad 87 can be understood, for example, as the top layer of the package. The second pad layer 87 includes a third pad 871 and a fourth pad 872 spaced apart. The third pad 871 is used, for example, to bond to the first pad 631 of the first chip 60, and the fourth pad 872 is used, for example, to bond to the second pad 632 of the first chip 60. For example, the third pad 871 and the first pad 631 are bonded by solder balls, and the fourth pad 872 and the second pad 632 are bonded by solder balls. The second pad layer 87 may also include pads with other functions, which are not limited in this embodiment.

[0140] The first conductive post 83 and the second conductive post 84 respectively penetrate the third dielectric layer 82. The first conductive post 83 is coupled to the third pad 871, and the second conductive post 84 is coupled to the fourth pad 872.

[0141] The wiring layer 81 is disposed on the side of the third dielectric layer 82 away from the second pad layer 87. Multiple wiring layers may also be disposed at intervals on the side of the wiring layer 81 away from the third dielectric layer 82. The configuration schemes in related technologies are applicable to the embodiments of this application.

[0142] As shown in Figure 7B, the wiring layer 81 includes a signal line 812 and a signal return structure 811. The signal return structure 811 includes an opening, and the signal line 812 is disposed within the opening. The two ends of the first conductive post 83 are coupled to the signal return structure 811 and the third pad 871, respectively. The two ends of the second conductive post 84 are coupled to one end of the signal line 812 and the fourth pad 872, respectively.

[0143] For example, the second pad layer 87 also includes a fifth pad 873 and a sixth pad 874, wherein the fifth pad 873 is used, for example, to bond to a seventh pad of the second chip 70, and the sixth pad 874 is used, for example, to bond to an eighth pad of the second chip 70. For example, the fifth pad 873 and the seventh pad are bonded by solder balls, and the sixth pad 874 and the eighth pad are bonded by solder balls.

[0144] The packaging substrate 80 also includes a third conductive post 85 and a fourth conductive post 86, which penetrate the third dielectric layer 82.

[0145] The two ends of the third conductive post 85 are coupled to the signal return structure 811 and the fifth pad 873, respectively, and the two ends of the fourth conductive post 86 are coupled to the other end of the signal line 812 and the sixth pad 874, respectively.

[0146] In some embodiments, after the first chip 60 is bonded to the packaging substrate 80, the projection of the third pad 871 on the first dielectric layer 61 does not overlap with the second capacitor plate 62. The third pad 871 only serves to bond with the first pad 631 and is unrelated to the formation of capacitor C.

[0147] In other embodiments, after the first chip 60 is bonded to the packaging substrate 80, the projection of the third pad 871 on the first dielectric layer 61 overlaps with the second capacitor plate 62. The third pad 871 serves to bond with the first pad 631, and also serves to form a capacitor C opposite to the second capacitor plate 62. In this case, the first pad 631 may only serve to bond with the third pad 871, and the alignment relationship between the first pad 631 and the second capacitor plate 62 does not need to be limited.

[0148] This application embodiment also provides a method for preparing a packaging substrate, the method comprising: forming the above-mentioned second pad layer 87, third dielectric layer 82, wiring layer 81, first conductive pillar 83 and second conductive pillar 84.

[0149] For example, the second pad layer 87 is located on one side of the third dielectric layer 82, and the second pad layer 87 includes a third pad 871 and a fourth pad 872 spaced apart. The wiring layer 81 is located on the side of the third dielectric layer 82 away from the second pad layer 87, and the wiring layer 81 includes a signal line 812 and a signal return structure 811. The signal return structure 811 includes an opening, and the signal line 812 is disposed within the opening. A first conductive post 83 and a second conductive post 84 respectively penetrate the third dielectric layer 82. The two ends of the first conductive post 83 are coupled to the signal return structure 811 and the third pad 871, respectively, and the two ends of the second conductive post 84 are coupled to one end of the signal line 812 and the fourth pad 872, respectively.

[0150] Figure 8 is a schematic diagram of the correspondence between a chip and a packaging substrate provided in an embodiment of this application.

[0151] As shown in Figure 8, when the first chip 60 and the packaging substrate 80 provided in this embodiment of the application are bonded, the first pad 631 and the third pad 871 are bonded to form the first bonding portion 91 in the chip packaging structure 50, and the second pad 632 and the fourth pad 872 are bonded to form the second bonding portion 92 in the chip packaging structure 50. When the first chip 60 and the second chip 70 are packaged together, the seventh pad 71 and the fifth pad 873 of the second chip 70 are bonded to form the third bonding portion 93 in the chip packaging structure 50. The eighth pad 72 and the sixth pad 874 of the second chip 70 are bonded to form the fourth bonding portion 94 in the chip packaging structure 50.

[0152] In some embodiments, the signal return structure 811 is a reference ground return structure. The signal return structure 811 serves as a return layer of the package substrate 80, and may be, for example, a ground layer. By providing the reference ground return structure on the package substrate 80, interference of the signal return structure 811 to the signal line 812 can be reduced.

[0153] In some embodiments, the chip package structure further includes a plurality of accompanying conductive posts 88, which are disposed along the edge of the signal line 812 and can be understood as accompanying conductive posts 88 of the signal line 812. The accompanying conductive posts 88 penetrate the third dielectric layer 82 and are coupled to the signal return structure 811. For example, the accompanying conductive posts 88 are ground conductive posts.

[0154] In some embodiments, the second capacitor plate 62 is the circuit return ground of the first chip 60. The specific value of the return ground voltage of the second capacitor plate 62 is related to the circuit structure within the first chip 60, and this embodiment does not limit this.

[0155] The signal return structure 811 is the return plane of the chip package structure 50. The signal return structure 811 and the second capacitor plate 62 are tightly coupled in the stacking direction through the first capacitor C.

[0156] In some embodiments, the projection of the second capacitor plate 62 onto the first dielectric layer 61 does not overlap with the second pad 632. For example, the second capacitor plate 62 and the second pad 632 are completely misaligned.

[0157] If the second capacitor plate 62 overlaps with the second pad 632, it will affect the impedance of the second pad 632 and the second conductive post 84 coupled to the second pad 632, causing signal reflection and reducing the performance of the signal line 812. However, by completely misaligning the second capacitor plate 62 with the second pad 632, the performance impact caused by the overlap can be avoided.

[0158] Figure 9 is a partial structural schematic diagram of a chip packaging structure provided in an embodiment of this application.

[0159] In some embodiments, the second pad 632 and the first pad 631 are arranged adjacent to each other. Adjacent arrangement can be understood, for example, as having a gap between the second pad 632 and the first pad 631, with no other pads disposed within the gap.

[0160] As shown in Figure 9, the first bonding portion 91 formed by bonding the first pad and the third pad is disposed adjacent to the second bonding portion 92 formed by bonding the second pad and the fourth pad. The first conductive post 83 coupled to the first bonding portion 91 and the second conductive post 84 coupled to the second bonding portion 92 are disposed adjacent to each other.

[0161] The spacing between the first conductive post 83, which is closest to the second conductive post 84, and the second conductive post 84 meets the impedance requirements of the signal line 812. The first conductive post 83 adjacent to the second conductive post 84 is the first conductive post 83 closest to the second conductive post 84. Therefore, the first bonding portion 91, which is coupled to the first conductive post 83, is located close to the second conductive post 84. In other words, the first bonding portion 91 is located close to the signal line 812.

[0162] The first bonding part 91 serves as an electrode of the first capacitor C1. The first bonding part 91 is located close to the signal line 812, which makes the return path close to the signal line 812, thus shortening the signal return path and further improving the communication performance.

[0163] In some embodiments, as shown in FIG9, the second capacitor plate 62 has a recess on the side near the second pad (i.e., the second bonding portion 92).

[0164] The specific shape of the recess is not limited in this embodiment. The recess is used to avoid the signal line in the first chip 60 that is coupled to the second bonding portion 92, so as to ensure the impedance continuity of the signal line 812, avoid signal reflection, and improve signal performance.

[0165] Figure 10 is an enlarged schematic diagram of a second capacitor plate provided in an embodiment of this application at point W in Figure 9.

[0166] In some embodiments, as shown in FIG10, the second capacitor plate 62 has a mesh structure.

[0167] The specific structure of the second capacitor plate 62 is not limited in this application embodiment, and the structures used as the top metal layer of the chip in related technologies are applicable to this application embodiment.

[0168] Figure 11 is a schematic diagram of the structure of a first capacitor provided in an embodiment of this application.

[0169] In some embodiments, as shown in FIG11, at least a portion of the recessed contour is stepped.

[0170] The width of the steps in the staircase can be uniform or non-uniform; this embodiment does not limit this. The second capacitor plate 62 has a grid structure, which avoids the signal lines in the first chip 60 by extending the grid more or less. This process is simple and easy to implement. Therefore, at least part of the contour of the resulting recess is stepped.

[0171] In some embodiments, as shown in FIG11, the first pad 631 is a block structure.

[0172] The block structure can be a rectangular block, a circular block, or a block structure of any closed shape. By setting the first pad 631 as a block structure, the alignment and bonding of the first pad 631 and the third pad 871 can be facilitated, thereby improving the yield.

[0173] The first chip 60 provided in this application embodiment is prepared, for example, by the chip fabrication method provided in this application embodiment. The packaging substrate provided in this application embodiment is prepared, for example, by the packaged chip fabrication method provided in this application embodiment.

[0174] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized by The chip comprises: a first dielectric layer; a first pad layer arranged on a surface of one side of the first dielectric layer; the first pad layer comprises a first pad and a second pad arranged at intervals; the first pad serves as a first capacitor plate; a second capacitor plate arranged on a surface of the first dielectric layer away from the first pad layer; a projection of the second capacitor plate on the first dielectric layer overlaps with a projection of the first pad on the first dielectric layer.

2. The chip according to claim 1, characterized in that, The projection of the second capacitor plate on the first dielectric layer does not overlap with the second pad.

3. The chip according to claim 1 or 2, characterized in that, The thickness of the first dielectric layer is less than or equal to 10 um.

4. The chip according to any one of claims 1 to 3, characterized in that The second pad and the first pad are arranged adjacently.

5. The chip according to any one of claims 1 to 4, characterized in that The side edge of the second capacitor plate close to the second pad has a recess.

6. The chip according to any one of claims 1 to 5, characterized in that The second capacitor plate is of a grid structure.

7. The chip according to claim 5 or 6, characterized in that At least part of the contour of the recess is in a stepped shape.

8. The chip according to any one of claims 1 to 7, characterized in that The first pad is of a block structure.

9. The chip according to any one of claims 1 to 8, characterized in that The chip further comprises a third capacitor plate and a second dielectric layer arranged between the second capacitor plate and the third capacitor plate; a projection of the third capacitor plate on the second dielectric layer overlaps with a projection of the second capacitor plate on the second dielectric layer.

10. The chip according to any one of claims 1 to 9, characterized in that The chip comprises an analog multiplexing / demultiplexing chip.

11. A package substrate, characterized by, The package substrate comprises: a third dielectric layer; a second pad layer arranged on one side of the third dielectric layer; the second pad layer comprises a third pad and a fourth pad arranged at intervals; a wiring layer arranged on a surface of the third dielectric layer away from the second pad layer; the wiring layer comprises a signal line and a signal reflow structure; the signal reflow structure comprises an opening, and the signal line is arranged in the opening; a first conductive column and a second conductive column penetrating through the third dielectric layer respectively; two ends of the first conductive column are coupled with the signal reflow structure and the third pad respectively, and two ends of the second conductive column are coupled with one end of the signal line and the fourth pad respectively.

12. The package substrate of claim 11, wherein, The package substrate further comprises a third conductive column and a fourth conductive column; the second pad layer further comprises a fifth pad and a sixth pad; two ends of the third conductive column are coupled with the signal reflow structure and the fifth pad respectively, and two ends of the fourth conductive column are coupled with the other end of the signal line and the sixth pad respectively.

13. The package substrate of claim 11 or 12, wherein, The signal reflow structure is a reference ground reflow structure.

14. A chip package structure, comprising: The chip package structure comprises a first chip and a package substrate; The first chip comprises the chip according to any one of claims 1-10; and the package substrate comprises the package substrate according to any one of claims 11-13. The first pad of the chip and the third pad of the package substrate are bonded to form a first bonding part, and the second pad of the chip and the fourth pad of the package substrate are bonded to form a second bonding part; a projection of the second capacitor plate on the bonding layer overlaps with the first bonding part.

15. The chip package structure of claim 14, wherein, The chip package structure further comprises a second chip; the second chip is bonded with the fifth pad to form a third bonding part, and bonded with the sixth pad to form a fourth bonding part.

16. The chip package structure of claim 14 or 15, wherein, The second chip comprises an optical digital signal processing chip.

17. A chip package structure, comprising: The chip packaging structure comprises a packaging substrate, a bonding layer and a chip, the chip is bonded with the packaging substrate through the bonding layer; The packaging substrate comprises a wiring layer, a fourth dielectric layer, a fifth conductive column and a sixth conductive column, the fourth dielectric layer is arranged between the wiring layer and the bonding layer; the wiring layer comprises a signal line and a signal reflow structure, the signal reflow structure comprises an opening, and the signal line is arranged in the opening; The fifth conductive column is coupled with the signal reflow structure through the fourth dielectric layer, and the sixth conductive column is coupled with the signal line through the fourth dielectric layer; The bonding layer comprises a fifth bonding part and a sixth bonding part arranged at intervals; The chip is coupled with the fifth conductive column through the fifth bonding part and coupled with the sixth conductive column through the sixth bonding part; the chip comprises a third conductive structure and a fifth dielectric layer, the fifth dielectric layer is arranged between the third conductive structure and the bonding layer; and a projection of the third conductive structure on the bonding layer overlaps with the fifth bonding part.

18. A terminal device, comprising: The terminal device comprises: A circuit board; The chip packaging structure according to any one of claims 14-17 is arranged on the circuit board.

19. The terminal device of claim 18, wherein, The terminal device is a coherent optical module.

20. A communication system, characterized by The communication system comprises two coherent optical modules and an optical fiber channel, the two coherent optical modules are connected through the optical fiber channel; and the coherent optical module comprises the terminal device according to claim 19.

21. A method of fabricating a chip, characterized by, The preparation method comprises: forming a first pad layer, a first dielectric layer and a second capacitor plate; The first pad layer is located on a surface of the first dielectric layer; the first pad layer comprises a first pad and a second pad arranged at intervals; the first pad serves as a first capacitor plate; The second capacitor plate is located on a surface of the first dielectric layer away from the first pad layer; a projection of the second capacitor plate on the first dielectric layer overlaps with a projection of the first pad on the first dielectric layer.

22. The method of claim 21, wherein, The projection of the second capacitor plate on the first dielectric layer does not overlap with the second pad.

23. The method of manufacturing according to claim 21 or 22, wherein, The thickness of the first dielectric layer is less than or equal to 10 um.

24. The method of any one of claims 21-23, wherein, The second pad and the first pad are arranged adjacent to each other.

25. A method of fabricating a package substrate, comprising: The preparation method comprises: forming a second pad layer, a third dielectric layer, a wiring layer, a first conductive column and a second conductive column; The second pad layer is located on a side of the third dielectric layer; the second pad layer comprises a third pad and a fourth pad arranged at intervals; The wiring layer is located on a side of the third dielectric layer away from the second pad layer; the wiring layer comprises a signal line and a signal reflow structure, the signal re-flow structure comprises an opening, and the signal line is arranged in the opening; The first conductive column and the second conductive column respectively penetrate through the third dielectric layer; two ends of the first conductive column are respectively coupled with the signal reflow structure and the third pad, and two ends of the second conductive column are respectively coupled with one end of the signal line and the fourth pad.

26. The method of claim 25, wherein, The signal reflow structure is a reference ground reflow structure.

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