Photon detection circuitry, image sensor and electronic device

Abstract

The disclosure pertains to a photon detection circuitry that includes: a photon detection portion that is configured to set a path signal to a detection level when a photon is detected, wherein the detection level indicates the detected photon; and a latch portion that is configured to change its state to a detection state when the path signal changes to the detection level, wherein the detection state indicates the detected photon; wherein the latch portion is configured to inhibit a change of its state from the detection state to a reset state based on the path signal.

Description

[0001] Our ref.: 240288EPWOP 1

[0002] PHOTON DETECTION CIRCUITRY, IMAGE SENSOR AND ELECTRONIC DEVICE TECHNICAL FIELD

[0003] The present disclosure generally pertains to a photon detection circuitry, an image sensor and an electronic device.

[0004] TECHNICAL BACKGROUND

[0005] Photon detection circuits are generally known. For example, a photon detection circuit may include a single-photon avalanche diode (SPAD). When the SPAD detects a photon, the SPAD may propagate a signal that indicates the detected photon to a pixel frontend.

[0006] Although there exist techniques for photon detection circuitry, it is generally desirable to provide an improved photon detection circuitry, image sensor and electronic device.

[0007] SUMMARY

[0008] According to a first aspect, the disclosure provides a photon detection circuitry that includes: a photon detection portion that is configured to set a path signal to a detection level when a photon is detected, wherein the detection level indicates the detected photon; and a latch portion that is configured to change its state to a detection state when the path signal changes to the detection level, wherein the detection state indicates the detected photon; wherein the latch portion is configured to inhibit a change of its state from the detection state to a reset state based on the path signal.

[0009] According to a second aspect, the disclosure provides an image sensor that includes: a plurality of photon detection circuitries according to the first aspect; and a logic portion that is configured to generate an image signal based on the state of the latch portions of the plurality of photon detection circuitries.

[0010] According to a third aspect, the disclosure provides an electronic device that includes: the image sensor according to the second aspect; and a processing portion that is configured to perform processing according to the generated image signal.

[0011] Further aspects are set forth in the dependent claims, the drawings and the following description.Our ref.: 240288EPWOP 2

[0012] BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Embodiments are explained by way of example with respect to the accompanying drawings, in which:

[0014] Fig. 1 illustrates examples of a leakage problem;

[0015] Fig. 2 illustrates a photon detection circuitry according to an embodiment;

[0016] Fig. 3 illustrates a reset and SPAD recharge according to an embodiment;

[0017] Fig. 4 illustrates a detection of a photon according to an embodiment;

[0018] Fig. 5 illustrates a recharge prevention and readout according to an embodiment;

[0019] Fig. 6 illustrates a photon detection circuitry with an inverter-NAND-based latch according to an embodiment;

[0020] Fig. 7 illustrates a reset and SPAD recharge in a photon detection circuitry with an inverter-NAND-based latch according to an embodiment;

[0021] Fig. 8 illustrates a detection of a photon in a photon detection circuitry with an inverter-NAND-based latch according to an embodiment;

[0022] Fig. 9 illustrates a recharge prevention and readout in a photon detection circuitry with an inverter-NAND-based latch according to an embodiment;

[0023] Fig. 10 illustrates a photon detection circuitry with an inverter-tri state-inverter latch according to an embodiment;

[0024] Fig. 11 illustrates a reset and SPAD recharge in a photon detection circuitry with an inverter-tristate-inverter latch according to an embodiment;

[0025] Fig. 12 illustrates a detection of a photon in a photon detection circuitry with an inverter-tristate-inverter latch according to an embodiment;

[0026] Fig. 13 illustrates a recharge prevention and readout in a photon detection circuitry with an inverter-tristate-inverter latch according to an embodiment;

[0027] Fig. 14 illustrates a method for photon detection circuitry according to an embodiment;

[0028] Fig. 15 illustrates an image sensor according to an embodiment;

[0029] Fig. 16 illustrates an electronic device according to an embodiment; and

[0030] Fig. 17 illustrates an embodiment of a photon detection circuitry in which a photon detection portion is connected to a pixel front-end via an anode.Our ref.: 240288EPWOP 3

[0031] DETAILED DESCRIPTION OF EMBODIMENTS

[0032] Before a detailed description of the embodiments under reference of Fig. 2 is given, general explanations are made.

[0033] As mentioned in the outset, photon detection circuits are generally known. For example, a photon detection circuit may include a single-photon avalanche diode (SPAD). When the SPAD detects a photon, the SPAD may propagate a signal that indicates the detected photon to a pixel frontend.

[0034] For example, in clocked recharge pixels (which may include a SPAD to which a clocked recharge is applied) a light sensitive device (e.g., SPAD) may need to retain a detection signal that indicates a received photon until a Pixel Front-End (PFE) receives the detection signal to transfer an indication of the received photon to an elaboration and / or readout circuit.

[0035] Due to leakage, the SPAD may keep the detection signal in some instances only for a limited amount of time, and the detection signal may be potentially cancelled. If the pixel is exposed with a very low light condition and therefore long exposure time, the limitation due to the leakage may be unavoidable in some instances, and the data may be potentially lost.

[0036] Fig. 1 illustrates examples of a leakage problem. In some instances, the leakage problem causes a photon event loss and / or a false photon event.

[0037] In A of Fig. 1, an exemplary photon detection pixel 1 with a SPAD 2 is shown. An arrow 3 indicates a connection to a PFE that reads out a detection signal from the SPAD 2. A clamping transistor 4 is provided between the SPAD 2 and the PFE. When a level of an XCLAMP signal becomes low, the clamping transistor 4 becomes conductive and allows reading out the detection signal from the SPAD 2 and / or recharging the SPAD 2. A recharge transistor 5 is provided between a voltage source and the clamping transistor 4. When a level of an XRCG signal becomes low, the recharge transistor 5 becomes conductive and allows recharging the SPAD 2. In the example shown in Fig. 1, an anode of the SPAD 2 is connected to ground GND, the recharge transistor 5 is connected to a voltage source VDD whose electric potential is larger than GND, and the transistors 4 and 5 are of a p-type metal-oxide semiconductor (PMOS).

[0038] The SPAD node (a node between the SPAD 2 and the clamping transistor 4) and a VK node (a node between the clamping transistor 4 and the recharge transistor 5) are floating during operation and, therefore, can be affected by leakage of the surrounding circuitry.Our ref.: 240288EPWOP 4

[0039] Two main effects of leakage include a photon event loss, when the nodes are recharged, and a false photon event, when the nodes are discharged.

[0040] B of Fig. 1 shows a case in which a leakage effect causes a photon event loss.

[0041] At first, levels of the signals XRCG and XCLAMP become low such that the SPAD 2 is recharged through the recharge transistor 5 and the clamping transistor 4. After the recharging, a SPAD voltage (denoted as SPAD in Fig. 1; e.g., a voltage between a cathode and an anode of the SPAD 2) is large.

[0042] At ti, the SPAD 2 receives and detects a photon (denoted as Photon in Fig. 1) and the SPAD voltage drops. A low level of the SPAD voltage corresponds to a detection signal that indicates a photon event of detecting the photon.

[0043] Due to leakage towards VDD (e.g., a leakage of the recharge transistor 5 and / or the clamping transistor 4) the SPAD 2 is recharged towards VDD after the SPAD 2 has detected the photon, before a readout circuit has read out the photon event.

[0044] Therefore, when the XCLAMP signal becomes low between t2 and t3 such that the readout circuit can readout the detection signal from the SPAD 2, the level of the SPAD voltage has become so high that the readout circuit does not detect the photon event. Accordingly, a photon event loss has occurred.

[0045] C of Fig. 1 illustrates a case in which a device leakage effect causes a false photon event.

[0046] At first, the levels of the signals XRCG and XCLAMP become low such that the SPAD 2 is recharged, as described with respect to B of Fig. 1.

[0047] In C of Fig. 1, the SPAD 2 does not receive a photon at However, a device leakage (e.g., a leakage of the SPAD 2, or a leakage of any device that can cause leakage towards GND and that is connected to a cathode of the SPAD 2) occurs while the SPAD 2 is in a recharged state and is ready to detect a photon, such that the SPAD 2 is discharged (e.g., towards GND).

[0048] Therefore, when the XCLAMP signal becomes low between ts and te such that the readout circuit can readout the detection signal from the SPAD 2, the readout circuit may read a photon event even if no photon has been detected by the SPAD 2. Accordingly, a false photon event is detected.

[0049] In general image sensor implementations, an exposure time may be in the milli-seconds range. However, in some instances, depending on technology, a maximum exposure time before aOur ref.: 240288EPWOP 5

[0050] photon event loss and / or a false photon event occurs may correspond to or be smaller than a few tens of microseconds.

[0051] The leakage towards VDD and / or GND may occur based on an employed technology. Reasons of the leakage may include thermal noise, light leakage (e.g., reflections), and / or photoevents (e.g., creation of electron-hole pairs by a photon) within a semiconductor junction.

[0052] In some instances, increasing a recharge rate of recharging the SPAD 2 is power hungry and proportional to a recharge frequency. In some instances, using an active quenching mechanism is more area consuming and still requires more frequent recharges, increasing power consumption. In some instances, increasing a recharge rate also poses additional complexity to subsequent circuits that need to handle more data (e.g. counter depth). Further, other complex schemes might be used but these are not suitable for small pixels in some instances, so it has been recognized that a compact solution is needed.

[0053] To overcome to the leakage problem, a latch PFE for SPAD sensors is used in some embodiments. If a photon has been detected (e.g., during a shorter observation period), the latch may store the data and may keep it until the latch is reset. If no photon has been detected, the latch may be not triggered and may still be ready to acquire and store a photon event in a next exposure phase. This operation may be performed multiple times and may allow the PFE to be used to extend a maximum exposure time indefinitely.

[0054] Consequently, some embodiments of the disclosure pertain to a photon detection circuitry that includes:

[0055] a photon detection portion that is configured to set a path signal to a detection level when a photon is detected, wherein the detection level indicates the detected photon; and

[0056] a latch portion that is configured to change its state to a detection state when the path signal changes to the detection level, wherein the detection state indicates the detected photon;

[0057] wherein the latch portion is configured to inhibit a change of its state from the detection state to a reset state based on the path signal.

[0058] The photon detection circuitry may be formed as a semiconductor circuit. Portions of the photon detection circuitry (e.g., the photon detection portion, the latch portion, a switch, a recharge prevention portion, a feedback portion, a recharge portion, a clamping transistor, a reset transistor etc.) may be formed by circuit elements arranged on one or more semiconductor substrate(s). The photon detection circuitry may be formed by CMOS (complementary metal-oxide-semiconductor) technology.Our ref.: 240288EPWOP 6

[0059] The photon detection portion may be configured to detect single photons, or a small number of photons (e.g., two photons, five photons, ten photons etc.) that may arrive within a predetermined time interval. The photon detection portion may include a single-photon avalanche diode (SPAD). However, the disclosure is not limited to a SPAD, and the photon detection portion may include a jot, an avalanche photodiode (APD), a photomultiplier tube, or the like.

[0060] When the photon detection portion receives and detects a photon (or several photons), the photon detection portion may set a path signal (e.g., a voltage) at an output node of the photon detection portion to the detection level (e.g., a predetermined voltage level). The output node of the photon detection portion may be a node of the photon detection portion that is coupled to the latch portion.

[0061] The path signal may be controlled to change between the detection level and a reset level. The detection level and the reset level may be two predetermined voltage levels. The detection level may correspond to a case where the photon detection portion has detected a photon, and the reset level may correspond to a case where the photon detection portion has not detected a photon. For example, the detection level may correspond to a low voltage level, and the reset level may correspond to a high voltage level higher than the low voltage level, or vice versa.

[0062] For example, if the SPAD detects a photon, an avalanche current may propagate charges through the SPAD such that the path signal at the output node of the SPAD changes from the reset level to the detection level.

[0063] An input node of the latch portion may be coupled to the output node of the photon detection portion. The input node of the latch portion may be directly connected to the output node of the photon detection portion, or the input node of the latch portion may be indirectly connected to the output node of the photon detection portion through one or more transistors (e.g., through a switch for inhibiting a change of the state of the latch portion based on the path signal, and / or through a clamping transistor) and / or through other circuit elements (e.g., capacitance, resistor, etc.).

[0064] The latch portion may be configured to store a value. The value may be represented by the state of the latch portion. The latch portion may change between the reset state that may correspond to a case where the photon detection portion has not detected a photon and the detection state that may correspond to a case where the photon detection portion has detected a photon. The resetOur ref.: 240288EPWOP 7

[0065] state and the detection state may correspond to a voltage level at a node of (e.g., within) the latch portion (e.g., a low voltage level and a high voltage level higher than the low voltage level). The latch portion may change between the reset state and the detection state in accordance with a path signal (e.g., voltage level) at an input (e.g., the input node) of the latch portion. If the path signal at the input of the latch portion changes to the detection level, the latch portion may change its state to the detection state. If the path signal at the input of the latch portion changes to the reset level, the latch portion may change its state to the reset state.

[0066] The latch portion may provide a negated output signal and a non-negated output signal, wherein the negated output signal may correspond to a logically inverted value of the non-negated output signal. For example, if the non-negated output signal corresponds to a low voltage level, the negated output signal may correspond to a high voltage level higher than the low voltage level, and vice versa. However, the latch portion is not limited to provide a negated and a non-negated output signal. For example, the skilled person may appreciate that the disclosure also embraces a latch portion that provides a single output signal.

[0067] The inhibiting of a change of the state of the latch portion may include blocking a propagation of a path signal that corresponds to the reset level to the input node of the latch portion. Thus, a change of the state of the latch portion from the detection state to the reset state based on the path signal (e.g., if the path signal changes to the reset level) may be prevented.

[0068] For example, the latch portion may actively set its state according to the path signal at its input. For maintaining the detection state even in a case where a path signal at a node between the photon detection portion and the latch portion changes to the reset level (e.g., due to leakage (e.g., PMOS leakage) and / or due to recharging the SPAD), the latch portion may block the propagation of the path signal to the input of the latch portion. For example, the latch portion may decouple (e.g., electrically disconnect) its input node from the node between the photon detection portion and the latch portion.

[0069] Thus, due to the inhibiting of a change of the latch portion from the detection state to the reset state based on the path signal, the latch portion may keep the detection state for indicating the detected photon even if the path signal at the node between the photon detection portion and the latch portion changes to the reset level.

[0070] The photon detection circuitry may include a reset portion (e.g., a reset transistor) that may be configured to provide to the input of the latch portion a signal that corresponds to the reset level even when the latch portion is inhibiting a change of its state from the detection state to the resetOur ref.: 240288EPWOP 8

[0071] state based on the path signal. Thus, the latch portion may change its state from the detection state to the reset state based on the signal from the reset portion instead of based on the path signal, e.g., after the latch portion has been read out by a readout circuit.

[0072] The latch portion may store a single value that may indicate a single photon detection event in which the photon detection portion has detected a photon. The latch portion may inhibit the change of its state to the reset state based on the path signal until the detection state has been read out by a readout circuit. For example, after the detection state has been read out from the latch portion, the state of the latch portion may be changed to the reset state (e.g., through the reset portion / reset transistor). When the state of the latch portion has changed to the reset state, the latch portion may stop inhibiting the change if its state based on the path signal (e.g., the latch portion may cause an electric connection of its input node to a node between the photon detection portion and the latch portion), such that the latch portion may be ready for storing an indication of a photon detection event (e.g., changing its state to the detection state) based on the path signal.

[0073] The latch portion may also be configured as a counter (e.g., a plurality of toggle flipflops connected in series) such that the latch portion may indicate a number of photons that have been detected since a last readout of the latch portion. In such a case, the latch portion may inhibit a change of its state based on the path signal to prevent a counter overflow (e.g., if the counter has counted a maximum number of photon detection events that can be represented by the counter) until the counter has been readout and / or reset. In such a case, the latch portion may also inhibit a change of its state based on the path signal to prevent counting false photon detection events (e.g., due to SPAD device leakage) until the SPAD has been recharged.

[0074] In some embodiments, the photon detection circuitry further includes a switch that is configured to propagate, in accordance with the state of the latch portion, the path signal to the latch portion. The switch may be arranged before the input node of the latch portion, e.g., between the input node of the latch portion and the output node of the photon detection portion. If the photon detection circuitry includes a clamping transistor, the switch may be arranged between the clamping transistor and the input node of the latch portion.

[0075] The switch may be formed by a transistor, e.g., by an NMOS (N-type metal-oxide-semi conductor) or PMOS (p-channel metal-oxide-semiconductor) transistor.

[0076] The switch may be configured to propagate the path signal from the photon detection portion (and, potentially, from a clamping transistor) to the input of the latch portion in accordance withOur ref.: 240288EPWOP 9

[0077] the state of the latch portion. For example, the switch may propagate the path signal to the latch portion if the latch portion is in the reset state, and may not propagate the path signal to the latch portion if the latch portion is in the detection state.

[0078] By propagating or not propagating the path signal to the input of the latch portion, the switch may control whether the latch portion changes its state based on the path signal.

[0079] The switch may be provided in the latch portion or outside of the latch portion. One of a gate, a source and a drain of the switch may receive the path signal from the photon detection portion. Another one of the gate, source and drain of the switch may receive a signal that is based on an output of the latch portion (e.g., a non-inverted output of the latch portion, an inverted output of the latch portion, or a signal (e.g., an input of the latch portion) set by a feedback portion of the latch portion etc.), such that the switch may be controlled by the output of the latch portion. A source or drain of the switch that does neither receive the path signal nor the signal that is based on the output of the latch portion may may provide to an input of the latch portion a signal (e.g., voltage level) that corresponds to the path signal from the photon detection portion.

[0080] In some embodiments, the switch is configured to be controlled by an output of the latch portion that indicates the state of the latch portion.

[0081] The output (e.g., negated or non-negated output) of the latch portion may be connected to a gate of the switch such that the switch may become conductive when the latch portion provides an output that corresponds to the reset state, and that the switch may become non-conductive when the latch portion provides an output that corresponds to the detection state.

[0082] Thus, the latch portion may control the switch for inhibiting or not inhibiting a change of the state of the latch portion from the detection state to the reset state based on the path signal.

[0083] In some embodiments, the switch is configured to block the path signal when the state of the latch portion corresponds to the detection state.

[0084] By providing, to the gate of the switch, an output that corresponds to the detection state, the latch portion may cause the switch to block the path signal and, thus, the latch portion may inhibit a change of the state of the latch portion from the detection state to the reset state based on the path signal.

[0085] Thus, the latch portion may be decoupled from the path signal when the latch portion is in the detection state, such that the latch portion may store an indication of a photon detection eventOur ref.: 240288EPWOP 10

[0086] independent from a voltage level of a path signal at an output of the photon detection portion (e.g., in case of leakage and / or recharging the SPAD).

[0087] In some embodiments, the switch is configured to propagate the path signal to the latch portion when the state of the latch portion corresponds to the reset state.

[0088] By providing, to the gate of the switch, an output that corresponds to the reset state, the latch portion may cause the switch to propagate the path signal and, thus, the latch portion may be ready for receiving via the path signal from the photon detection portion an indication of a photon detection event.

[0089] Thus, the latch portion may be coupled to the path signal from the photon detection portion when the latch portion is in the reset state, such that the latch portion may receive, via the path signal, an indication of a photon detection event from the photon detection portion, and may change its state to the detection state for storing an indication of the photon detection event.

[0090] In some embodiments, the photon detection circuitry further includes a switch that is configured to propagate, in accordance with a control signal, the path signal to the latch portion.

[0091] The switch may include one or more transistors (e.g., NMOS and / or PMOS transistors) and may receive the control signal at its gate, source, drain and / or any voltage input. Thus, the control signal may decide whether the latch portion receives the path signal from the photon detection portion or keeps its current value (e.g., state). Thus, an isolation of the input of the latch portion from the path signal (e.g., from an output of the photon detection portion and / or of a clamping transistor) may be provided.

[0092] In some embodiments, the photon detection circuitry further includes a recharge prevention portion that is configured to inhibit a reset of the path signal in accordance with the state of the latch portion.

[0093] The recharge prevention portion may be formed by a transistor, e.g., a PMOS or NMOS transistor. The recharge prevention portion may be provided between the output node of the photon detection portion and a voltage source. A recharge portion may be provided between the recharge prevention portion and the voltage source or between the recharge prevention portion and the photon detection portion.

[0094] If the photon detection circuitry includes a clamping transistor, the recharge prevention portion may be provided between the voltage source and the clamping transistor. For example, aOur ref.: 240288EPWOP 11

[0095] terminal of the recharge prevention portion may be connected to a terminal of the clamping transistor and to a terminal of the switch.

[0096] The recharge prevention portion may decouple the photon detection portion from the voltage source (and, potentially, from the recharge portion) such that a recharge of the photon detection portion may be prevented, e.g., by blocking a charge propagation, when the recharge prevention portion inhibits a reset of the path signal.

[0097] The recharge prevention portion may inhibit a reset of the path signal and, therefore, a recharge of the photon detection portion (e.g., SPAD) according to the state of the latch portion. For example, the recharge prevention portion may inhibit or not inhibit the reset of the path signal based on the state of the latch portion.

[0098] In some embodiments, the inhibiting of the reset of the path signal includes blocking a reset of the path signal when the state of the latch portion corresponds to the detection state.

[0099] For example, the recharge prevention portion may block the reset of the path signal if the latch portion is in the detection state.

[0100] For example, the latch portion may not be able to receive a further indication of a photon detection event as long as the latch portion is in the detection state. Therefore, resetting the path signal (and recharging the photon detection portion) may be unnecessary while the latch portion is in the detection state. By inhibiting the reset of the path signal while the latch portion is in the detection state, unnecessary consumption of electric energy may be avoided and electric energy may be saved.

[0101] In some embodiments, the inhibiting of the reset of the path signal includes blocking an electric connection between a voltage source that is configured to provide the reset level and a node between the photon detection portion and the latch portion.

[0102] The blocking of the reset of the path signal may include blocking the electric connection between the voltage source and the node between the photon detection portion and the latch portion. Thus, the recharge prevention portion may electrically disconnect the photon detection portion from the voltage source and / or from a recharge portion.

[0103] In some embodiments, the recharge prevention portion is configured to be controlled by an output of the latch portion that indicates the state of the latch portion.

[0104] The output (e.g., negated or non-negated output) of the latch portion may be connected to a gate of the recharge prevention portion such that the recharge prevention portion may becomeOur ref.: 240288EPWOP 12

[0105] conductive when the latch portion provides an output that corresponds to the reset state, and that the recharge prevention portion may become non-conductive when the latch portion provides an output that corresponds to the detection state.

[0106] Thus, the latch portion may control the recharge prevention portion for inhibiting or not inhibiting a reset of the path signal and, thus, a recharge of the photon detection portion.

[0107] In some embodiments, the photon detection circuitry further includes a feedback portion that is configured to propagate a signal from an output of the latch portion to an input of the latch portion.

[0108] The feedback portion may be provided between the output (e.g., an output node) of the latch portion and the input (e.g., the input node) of the latch portion. The output of the feedback portion from which the feedback portion propagates the signal may correspond to a same voltage level as a path signal at the input of the latch portion. Thus, by propagating the signal from the output to the input of the latch portion, the feedback portion may cause the latch portion to maintain its current state.

[0109] The feedback portion may be provided between the input of the latch portion and the switch that is configured to propagate the path signal from the photon detection portion to the latch portion in accordance with the state of the latch portion. Therefore, when the latch portion inhibits a change of its state from the detection state to the reset state based on the path signal and the switch blocks the path signal, a floating voltage at the input of the latch portion may be prevented by the feedback portion such that the latch portion may maintain its state even if leakage occurs at the input of the latch portion.

[0110] In some embodiments, the feedback portion is configured to propagate the signal slower than a signal propagation through the latch portion.

[0111] The feedback portion may have a predetermined resistance that still allows the latch portion to change its state in response to a change of a path signal at the input of the latch portion before the feedback portion overwrites the changed path signal with the signal from the output of the latch portion. For example, the resistance of the feedback portion may allow the latch portion to change from the reset state to the detection state when the path signal from the photon detection state indicates a photon detection event. For example, the resistance of the feedback portion may allow the latch portion to change from the detection state to the reset state if a reset portion (e.g., reset transistor) provides to the input of the latch portion a signal that corresponds to the reset level.Our ref.: 240288EPWOP 13

[0112] However, the resistance of the feedback portion may be low enough to prevent a change of the path signal at the input of the latch portion due to leakage. Therefore, the feedback portion may allow the latch portion to maintain its state, e.g., the detection state, even if leakage occurs at the input of the latch portion.

[0113] In some embodiments, the feedback portion includes at least one transistor that is coupled between the output of the latch portion and the input of the latch portion, wherein the transistor is configured to receive a predetermined gate signal at which the transistor has a predetermined resistance.

[0114] The transistor of the feedback portion may be formed by an NMOS or PMOS transistor. The feedback portion may also include a plurality of transistors, e.g., an NMOS transistor and a PMOS transistor coupled in parallel to form a transmission gate such that the feedback portion may propagate both electrons and holes. The feedback portion may also include a plurality of NMOS transistors, PMOS transistors and / or transmission gates coupled in series. The plurality of transistors of the feedback portion may receive a same gate signal (e.g., a same voltage level) as the predetermined gate signal, or may receive different gate signals (e.g., different voltage levels, for example a first voltage level for NMOS transistors and a second voltage level for PMOS transistors) as the predetermined gate signal.

[0115] Thus, the resistance of the feedback portion may be controlled to compensate for leakage at the input of the latch portion while allowing a change of the path signal at the input of the latch portion caused by a photon detection event or by a reset operation of a reset portion.

[0116] In some embodiments, the photon detection circuitry further includes a recharge portion that is configured to reset the path signal to a reset level.

[0117] The recharge portion may be provided between the photon detection portion (e.g., SPAD) and a voltage source that is configured to provide the reset level. If photon detection circuitry includes the recharge prevention portion described above, the recharge portion may be provided between the voltage source and the recharge prevention portion or may be provided between the recharge prevention portion and the photon detection portion.

[0118] The resetting of the path signal to a reset level may include establishing a predetermined voltage gradient at the photon detection portion, e.g., establishing a reverse bias of the SPAD, such that the photon detection portion may be ready for detecting a photon.

[0119] The resetting of the path signal to the reset level may be performed after a photon detection event, when the photon detection portion has set the path signal to the detection level, becauseOur ref.: 240288EPWOP 14

[0120] the photon detection circuitry may not be able to detect a further photon as long as the path signal corresponds to the detection level. The resetting of the path signal may also be necessary for compensating for leakage (e.g., for PMOS leakage through the recharge portion and / or through the recharge prevention portion, and / or for (SPAD) device leakage through the photon detection portion) because the leakage may cause the path signal to approach the detection level, such that a false photon may be detected by the latch portion if the path signal is not reset by the recharge portion.

[0121] The recharge portion may be formed by a transistor, e.g., by an NMOS or PMOS transistor. The recharge portion may receive a gate signal and may become conductive when the gate signal corresponds to a first voltage level and may be come non-conductive when the gate signal corresponds to a second voltage level.

[0122] In some embodiments, the recharge portion is configured to reset the path signal in accordance with a clock signal.

[0123] The recharge portion may receive the clock signal as gate signal. The clock signal may change its voltage level such that the recharge portion may become conductive and reset the path signal to the reset level at predetermined points in time, e.g., at a predetermined recharge rate.

[0124] For example, the recharge rate may be chosen such that a change of the path signal to the detection level due to leakage may be prevented.

[0125] For example, the recharge rate may be chosen such that the path signal is reset (and the photon detection portion recharged) after a photon detection event has been read out from the latch portion such that a further photon may be detected.

[0126] The recharge rate may be equal to or higher than a readout rate at which a readout circuit reads out the latch portion. If the recharge rate is equal to the readout rate, the clock signal may cause the recharge portion to reset the path signal when the latch portion is read out (e.g., during or after the latch portion is read out and before the latch portion stops inhibiting a change of its state based on the path signal and controls the switch to propagate the path signal to the latch portion). However, due to the switch that blocks the path signal while the latch portion is in the detection state, the recharging may be performed independently of a readout and / or reset of the latch portion. The recharge rate may also be higher than the readout rate, for example, if the readout rate is so low that leakage might cause the path signal to approach the detection level within an exposure period such that a false photon might be detected if the path signal is not reset during the exposure period.Our ref.: 240288EPWOP 15

[0127] The clock signal may be generated and provided to multiple photon detection circuitries. Thus, for keeping a control circuit simple, the clock signal may be provided to the recharge portion irrespectively of whether the latch portion is in the detection state or in the reset state. Thus, the clock signal may cause the recharge portion to become conductive even in a case when the latch portion is in the detection state and cannot detect a further photon detection event. In such a case, the recharge prevention portion described above may inhibit the reset of the path signal such that an unnecessary consumption of electric energy for recharging the photon detection portion may be avoided and electric energy may be saved.

[0128] In some embodiments, the resetting of the path signal includes establishing an electric connection between a voltage source that is configured to provide the reset level and a node between the photon detection portion and the latch portion.

[0129] As mentioned, for resetting the path signal (and recharging the photon detection portion), the recharge portion may become conductive (e.g., in response to a corresponding gate signal) such that charges may flow between the voltage source and the node between the photon detection portion and the latch portion.

[0130] The node between the photon detection portion and the latch portion may be an output node of the photon detection portion or, if the photon detection circuitry includes a clamping transistor, may be a node between the clamping transistor and the input of the latch portion (e.g., between the clamping transistor and the switch for blocking the path signal from propagating to the latch portion).

[0131] In some embodiments, the latch portion includes:

[0132] a first inverter that is configured to invert an input of the latch portion; and

[0133] a second inverter that is configured to invert an output of the first inverter.

[0134] Thus, the latch portion may be configured as an inverter-based latch. An output of the second inverter may correspond to an input of the latch portion. Thus, the feedback portion may be coupled between the output of the second inverter and the input of the latch portion (e.g., of the first inverter).

[0135] The output of the first inverter may correspond to a first output of the latch portion, and the output of the second inverter may correspond to a second output of the latch portion. The second output may correspond to an inversion of the first output. Therefore, one of the first and second outputs may correspond to a non-negated output of the latch portion, and the other one of the first and second outputs may correspond to a negated output of the latch portion.Our ref.: 240288EPWOP 16

[0136] The first and second inverters may be similarly configured and may, for example, include an NMOS transistor and a PMOS transistor that may be coupled in series between ground and a voltage source that may provide a higher potential than ground, wherein a source of the NMOS transistor may be connected to ground and a source of the PMOS transistor may be connected to the voltage source. An input of the inverter may be provided to gates of the NMOS and PMOS transistors, and a node between the NMOS and PMOS transistors may correspond to an output of the inverter.

[0137] However, the disclosure is not limited to an inverter-based latch portion. The latch portion can also be implemented using different topologies, not only a weak-feedback inverter as described above. In some embodiments, the latch portion is implemented based on an SR-latch. In some embodiments, the latch portion is implemented based on a D-latch. In some embodiments, a weak-feedback inverter latch topology uses the lower number of transistors than another technology (e.g., SR latch and / or D-latch).

[0138] In some embodiments, the photon detection portion is configured to propagate, when a photon is detected, a signal that corresponds to the detection level from a fixed-voltage node to a node between the photon detection portion and the latch portion.

[0139] The fixed-voltage node may be coupled to an input of the photon detection portion and may provide a voltage level that causes the node between the photon detection portion and the latch portion to be set to the detection level when a photon is detected. For example, the fixed-voltage node may correspond to a voltage source and / or to ground.

[0140] By resetting the path signal via the recharge portion, thus recharging the photon detection portion, a voltage gradient across the photon detection portion may be established from the detection level at the input of the photon detection portion to the reset level at the output of the photon detection portion.

[0141] When the photon detection portion receives / detects a photon, the photon detection portion may cause charges to move through the photon detection portion such that a voltage level at the output of the photon detection portion may be set to the detection level and the voltage gradient across the photon detection portion may be reduced accordingly.

[0142] In some embodiments, the photon detection portion includes a single-photon avalanche diode (SPAD).Our ref.: 240288EPWOP 17

[0143] The SPAD may be coupled between ground and a voltage source that may provide a higher potential than ground. For example, an anode of the SPAD may be coupled to ground and a cathode of the SPAD may be coupled to the voltage source.

[0144] However, the technology is not limited to coupling the anode of the photon detection portion to ground. Instead, the photon detection portion may be coupled between any two voltage levels that allow a proper function of the photon detection portion (e.g., charging the SPAD, SPAD breakdown). For example, the anode of the SPAD may be coupled to a voltage level different than ground (e.g., a negative supply voltage), that may be sufficiently below a voltage level to which the cathode of the SPAD is coupled.

[0145] The latch portion (and, potentially, the switch for blocking the path signal from propagating to the latch portion) and, if provided, the recharge portion, the recharge prevention portion and the clamping transistor may be provided between the SPAD and the voltage source or may be provided between the SPAD and ground.

[0146] The voltage gradient from the detection level to the reset level, which may be established across the SPAD by resetting the path signal and recharging the SPAD, may correspond to a reverse bias of the SPAD, such that a photon incident to the SPAD may cause an avalanche current. The avalanche current in the SPAD may be passively quenched by the propagation of the detection level to the output of the SPAD, which may cause the voltage gradient to be reduced such that the avalanche current may cease.

[0147] Upon resetting the path signal, thus re-establishing the reset level at the output of the SPAD, the voltage gradient may be re-established and the SPAD may be ready for detecting a further photon.

[0148] Some embodiments pertain to an image sensor that includes:

[0149] a plurality of photon detection circuitries according to any one of the embodiments described above; and

[0150] a logic portion that is configured to generate an image signal based on the state of the latch portions of the plurality of photon detection circuitries.

[0151] The plurality of photon detection circuitries may be arranged in a one-dimensional or two-dimensional array. Each of the plurality of photon detection circuitries may correspond to a pixel.Our ref.: 240288EPWOP 18

[0152] The logic portion may include an analog circuit (e.g., electronic elements provided on a substrate and electrically connected) and / or a digital circuit (e.g., a programmed microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or the like).

[0153] The logic portion may include a readout circuit that reads out the latch portions of the plurality of photon detection circuitries. The logic portion may generate the image signal based on the states that have been read out from the respective latch portions.

[0154] For example, if a latch portion is in the reset state during readout, the logic portion may assign, to a corresponding pixel of an image frame represented by the image signal, a value that indicates that no photon has been detected (e.g., a dark color or black). If the latch portion is in the detection state during readout, the logic portion may assign to the corresponding pixel a value that indicates that a photon has been detected (e.g., a bright color or white). If the latch portion includes a counter that stores a number of detected photons, the logic portion may assign to the corresponding pixel a value that corresponds to the number of detected photons, such that shades of color may be represented by the pixel.

[0155] The readout circuit may read out the state(s) of the latch portion(s) at a predetermined readout rate. The readout circuit may read out the latch portions all photon detection circuitries in parallel (e.g., synchronously) or sequentially. For example, the readout circuit may read out columns of the array of photon detection circuitries in parallel, and may read out rows of a column sequentially (or vice versa). The readout circuit may also read out the latch portions asynchronously; e.g., a readout of a latch portion may be triggered when the latch portion changes from the reset state to the detection state, and the logic portion may generated an image signal that may indicate a pixel position at which a photon has been detected and, optionally, a timestamp that corresponds to the detected photon.

[0156] An image frame of the image signal may be based on a single readout operation of reading out the latch portions of all photon detection circuitries or on multiple (e.g., subsequent) readout operations. Thus, each pixel of the image frame may correspond to a single photon or to a plurality of photons detected by a photon detection circuitry. An image frame of the image signal may also be based on a single photon detection event from one photon detection circuitry or on several photon detection events (that may have occurred close in time) from one or more photon detection circuitries.Our ref.: 240288EPWOP 19

[0157] The image sensor may be provided on a single substrate. For example, the logic portion may be provided in a periphery of the array of photon detection circuitries. The image sensor may also be configured in a stacked manner, in which several substrates may be stacked. For example, the array of photon detection circuitries may be provided on a first substrate, and the logic portion may be provided on a second substrate. For example, the photon detection portions (e.g., SPADs) may be provided on a first substrate, further parts (e.g., the latch portions) of the photon detection circuitries may be provided on a second substrate, and the logic portion may be provided on a third substrate or on the second substrate or may be distributed across the second and the third substrate. The substrates may be electrically connected via solder bumps, via electrode pads, via through-silicon vias, via hybrid bonding and / or via copper-to-copper bonding.

[0158] The image sensor may be configured as a photon-counting image sensor that may, for example, provide a high dynamic range and may be based on global and / or rolling shutter. The image sensor may also be configured as a photon-counting-based event sensor and / or as a photon-counting-based depth sensor.

[0159] Some embodiments pertain to an electronic device that includes:

[0160] the image sensor according to any one of the embodiments described above; and a processing portion that is configured to perform processing according to the generated image signal.

[0161] The electronic device may further include an optical element (e.g. lens and / or mirror) that may focus incident light on the image sensor. The electronic device may also include an interface for receiving electric power (e.g., via a cable and / or via wireless power transmission) and / or may include a source of electric power (e.g., a battery, a capacitor, a photovoltaic element, a generator (e.g., driven by an internal combustion engine, any other thermal engine, a water turbine, a steam turbine, a water turbine, a wind turbine or the like), a fuel cell, a radioisotope battery or the like) for driving the electronic device.

[0162] The electronic device may be configured as a photographic camera, a movie camera, a surveillance camera, a smartphone, a tablet, smartglasses, a smartwatch, an autonomous vehicle, a human-driven vehicle or a driver assistance system thereof, a drone, a robot, an endoscope, a microscope, an optical distance measuring device, or the like.

[0163] The processing portion may include an information processing portion (e.g., a programmable microcontroller, an ASIC, an FPGA, a central processing unit (CPU) or the like), a storage (e.g.,Our ref.: 240288EPWOP 20

[0164] flash drive, hard-disk drive, solid-state drive etc.), a display (e.g., liquid-crystal display (LCD), organic light-emitting diode display (OLED), electronic paper, cathode-ray tube (CRT) or the like), a lamp (e.g., light-emitting diode (LED), incandescent light bulb, discharge tube or the like), a loudspeaker, an actuator (e.g., (electric) motor, valve, switch, or the like) or the like. The information processing portion may receive the image signal from the image sensor. The processing according to the image signal may include displaying an image frame represented by the image signal on the display and / or storing the image frame in the storage. Before displaying and / or storing the image frame, the information processing portion may manipulate the image frame, e.g., by scaling, cropping, compressing and / or color-correcting the image frame and / or by applying an artistic effect to the image frame.

[0165] The information processing portion may also perform image recognition on the image signal (e.g., on an image frame or on several subsequent image frames of the image signal), and may perform control according to a result of the image recognition.

[0166] For example, the information processing portion may detect a gesture performed by a user and may execute a command that corresponds to the gesture (e.g., opening an application, changing a sound playback volume, starting or pausing content (e.g., video or audio) playback, etc.).

[0167] For example, the information processing portion may identify a user (e.g., based on biometric features such as face, iris, fingerprint etc.) and may authorize a restricted operation (e.g., unlocking a lock screen of a user interface, granting access to a content, opening a door, starting a car engine, authorizing a payment, etc.).

[0168] For example, the information processing portion may decode a graphical representation of information (e.g., written or printed text, matrix code, QR code, Aztec Code, bar code, pictogram etc.) and may perform an operation according to the decoded information (e.g., display recognized text, read recognized text aloud, write a representation of the decoded information to the storage, access a recognized uniform resource identifier (URI) etc.).

[0169] For example, the information processing portion may detect a condition in an environment (e.g., brightness, distance of an object, movement of an object etc.) and may control a parameter for capturing an image of the environment (e.g., autofocus, aperture, exposure, signal gain etc.). For example, the information processing portion may detect a traffic condition (e.g., road, road user, obstacle, traffic sign, traffic lights etc.) and may perform control according to the traffic condition (e.g., reduce or increase speed of a vehicle, change a movement direction of the vehicle, alert a driver of the vehicle etc.).Our ref.: 240288EPWOP 21

[0170] The skilled person may find further applications of the photon detection circuitry, the image sensor and / or the electronic device according to the disclosure.

[0171] Some embodiments pertain to a method for the photon detection circuitry of any one of the embodiments described above, wherein the method includes:

[0172] receiving, at the latch portion, a path signal that corresponds to the detection level; changing the state of the latch portion to the detection state; and

[0173] inhibiting a change of the state of the latch portion from the detection state to the reset state based on the path signal.

[0174] In some embodiments, the method further includes blocking, by a switch, the path signal from propagating to the latch portion when the state of the latch portion corresponds to the detection state. In some embodiments, the method further includes blocking, by a recharge prevention portion, a reset of the path signal when the state of the latch portion corresponds to the detection state. In some embodiments, the method further includes propagating, by a feedback portion, a signal from an output of the latch portion to an input of the latch portion.

[0175] The method may be performed by the photon detection circuitry as described above. The method may have a corresponding feature for any feature described herein with respect to the photon detection circuitry.

[0176] In some embodiments, the present technology may have an advantage with respect to other existing solutions. In some embodiments, the photon detection circuitry according to the present technology guarantees a long integration time in clocked-recharge topology despite a leakage (e.g., PMOS leakage and / or (SPAD) device leakage). In some embodiments, the photon detection circuitry according to the present technology has a lower power consumption with respect to other implementations. In some embodiments, the photon detection circuitry according to the present technology occupies less area than other implementations.

[0177] Fig. 2 illustrates a photon detection circuitry 10 according to an embodiment. The photon detection circuitry 10 includes a photon detection portion 11 and a latch portion 12.

[0178] The photon detection portion 11 includes a SPAD 11. An anode of the SPAD 11 is connected to ground GND, which is an example of a fixed-voltage node and provides a fixed electric potential such that, at breakdown of the SPAD 11, a cathode of the SPAD 11 is set to a detection level (e.g., low level). When the SPAD 11 detects a photon (illustrated in Fig. 2 by wiggly arrows), an avalanche current flows through the SPAD 11, such that the SPAD 11 propagates a signal that corresponds to the detection level from GND to a node between the SPAD 11 and the latchOur ref.: 240288EPWOP 22

[0179] portion 12. Thus, the SPAD 11 is configured to set a path signal (e.g., a path signal at an output node (e.g., the cathode) of the SPAD 11) from a reset level to the detection level when a photon is detected in the SPAD 11. The detection level indicates the detected photon.

[0180] The latch portion 12 is configured to change its state from a reset state to a detection state when the path signal changes to the detection level. The detection state indicates the detected photon. When the SPAD 11 is recharged (i.e., a reverse bias (voltage gradient) is established across the SPAD 11), the path signal at a node between the SPAD 11 and the latch portion 12 corresponds to the reset level (e.g., a high level). When the SPAD 11 detects a photon, the detection level is propagated from the SPAD 11 to an input LA IN of the latch portion 12, such that the latch portion 12 changes its state based on the path signal.

[0181] When the latch portion 12 is in the detection state, it inhibits a change of its state from the detection state to the reset state based on the path signal.

[0182] The latch portion 12 includes a first inverter 12a and a second inverter 12b. The first inverter 12a inverts an input LA IN of the latch portion 12, and the second inverter 12b inverts an output of the first inverter 12a. The output of the first inverter 12a corresponds to a first output PFE OUT of the latch portion 12, and an output of the second inverter 12b corresponds to a second output LA OUT of the latch portion 12. Both the first output PFE OUT and the second output LA OUT indicate the state of the latch portion 12 and correspond to an inversion of each other. The first and second inverters 12a and 12b actively set their respective outputs based on their respective inputs. Therefore, for inhibiting a change of its state from the detection state to the reset state based on the path signal, the latch portion 12 inhibits a propagation of the path signal to the input LA IN of the latch portion 12.

[0183] The photon detection circuitry 10 includes a switch 13 that propagates, in accordance with the state of the latch portion 12, the path signal from the SPAD 12 to the input LA IN of the latch portion 12. The switch 13 is formed by an NMOS transistor whose gate is connected to the second output LA OUT of the latch portion 12, such that the switch 13 is controlled by the second output LA OUT of the latch portion 12.

[0184] When the state of the latch portion 12 corresponds to the detection state, the switch 13 blocks the path signal, such that the path signal is not propagated from the SPAD 11 to the latch portion 12. When the state of the latch portion 12 corresponds to the reset state, the switch 13 propagates the path signal from the SPAD 11 to the latch portion 12. Therefore, the switch 13 propagates the path signal in accordance with the state of the latch portion 12.Our ref.: 240288EPWOP 23

[0185] The photon detection circuitry 10 further includes a clamping transistor 14. The clamping transistor 14 is a PMOS transistor and receives a control signal XCLAMP at its gate. The clamping transistor 14 controls a propagation of the path signal (e.g., at the detection level) from the SPAD 11 to the switch 13 as well as a reset of the path signal to the reset level and, accordingly, a recharging of the SPAD 11.

[0186] The photon detection circuitry 10 further includes a feedback portion. The feedback portion is formed by a PMOS transistor 15a and an NMOS transistor 15b that are connected in parallel to form a high resistive path. The feedback portion propagates a signal from the second output LA OUT of the latch portion 12 to the input LA IN of the latch portion 12. Thus, when the switch 13 blocks the path signal, a floating state of the input LA IN of the latch portion 12 can be prevented.

[0187] The feedback portion propagates the signal slower than a signal propagation through the latch portion 12 such that the latch portion 12 can change its state when a photon is detected or when the latch portion 12 is intentionally reset.

[0188] As mentioned, the feedback portion includes the PMOS transistor 15a and the NMOS transistor 15b, which are coupled between the second output LA OUT of the latch portion 12 and the input LA IN of the latch portion 12. The transistors 15a and 15b receive a predetermined gate signal VM at which the transistors 15a and 15b have a predetermined resistance. VM corresponds to a middle voltage at which the resistance of the transistors 15a and 15b is high enough that an intentional change of the state of the latch portion 12 is possible, and is so low that a change of the state of the latch portion 12 due to leakage at the input LA IN can be prevented.

[0189] The photon detection circuitry 10 further includes a reset transistor 16. The reset transistor 16 is a PMOS transistor and receives a control signal XRST at its gate. When XRST has a low level, the reset transistor 16 propagates a voltage level that corresponds to the reset level from a voltage source VDDPLX, which provides an electric potential that is higher than GND, to the input LA IN of the latch portion 12, such that the state of the latch portion 12 is changed to the reset state, which indicates that no photon has been detected. For example, the reset transistor 16 resets the latch portion 12 to the reset state after the state of the latch portion 12 has been read out (e.g., at the first output PFE OUT).

[0190] The photon detection circuitry 10 further includes a recharge portion 17. The recharge portion 17 is a PMOS transistor and receives a control signal XRCG at its gate. When XRCG has a lowOur ref.: 240288EPWOP 24

[0191] level, the recharge portion 17 resets the path signal at the output of the SPAD 11 to the reset level such that the reverse bias of the SPAD 11 is established and the SPAD 11 is ready for detecting a photon. For example, a reset of the path signal can be performed when a new exposure period starts (e.g., when the latch portion 12 has been read out and is reset).

[0192] The resetting of the path signal includes establishing an electric connection between the voltage source VDDPLX, which is configured to provide the reset level, and a node between the SPAD 11 and the latch portion 12.

[0193] The recharge portion 17 resets the path signal in accordance with a clock signal. The control signal XRCG is set to the low level at a predetermined clock rate, such that a clocked recharging of the SPAD 11 can be realized.

[0194] When the latch portion 12 is in the detection state, the latch portion 12 cannot receive further detected photons. Therefore, an unnecessary consumption of electric energy may be avoided by preventing recharging the SPAD 11 via the recharge portion 17 while the latch portion 12 is in the detection state.

[0195] Therefore, the photon detection circuitry 10 further includes a recharge prevention portion 18. The recharge prevention portion 18 is a PMOS transistor that is provided between the recharge portion 17 and the clamping transistor 14.

[0196] The recharge prevention portion 18 inhibits a reset of the path signal via the recharge portion 17 in accordance with the state of the latch portion 12. The inhibiting of the reset of the path signal in accordance with the state of the latch portion 12 includes blocking, when the state of the latch portion 12 corresponds to the detection state, a reset of the path signal by blocking an electric connection between the voltage source VDDPLX, which is configured to provide the reset level, and the node between the SPAD 11 and the latch portion 12. When the recharge prevention portion 18 is inhibiting the reset of the path signal, the recharge portion 17 cannot reset the path signal because the charges from the voltage source VDDPLX are blocked by the recharge prevention portion 18 and do not reach the SPAD 11. However, when the latch portion 12 is in the reset state, the recharge prevention portion 18 does not inhibit the reset of the path signal but is conductive, such that the recharge portion 17 can reset the path signal.

[0197] A gate of the recharge prevention portion 18 is electrically connected to the first output PFE OUT of the latch portion 12. Thus, the recharge prevention portion 18 is controlled by the second output PFE OUT of the latch portion 12, which indicates the state of the latch portion 12.Our ref.: 240288EPWOP 25

[0198] Accordingly, the photon detection circuitry 10 provides a front-end that includes an inverterbased latch (e.g., the latch portion 12) with a weak connection (VM is a fixed voltage) between the input LA IN and a feedback that provided by a slow switch (i.e., the transistors 15a and 15b). This allows the NMOS transistor 13 at the latch input LA IN to act as a switch and not as a diode, while allowing a proper reset at the input LA IN with the reset PMOS transistor 16. The PMOS transistor 18, which is connected in series with the recharge transistor 17, acts as a recharge prevention portion by inhibiting a recharge of the SPAD 11 if the latch 12 stores a “0” (an example of the detection state that indicates that a light event has been detected). Until the next reset of the latch portion 12 via the reset transistor 16, the recharge prevention portion 18 is active and the latch 12 retains its value (i.e., detection state).

[0199] The voltage source VDDPLX may provide any suitable potential, e.g., 0.5 V, 1 V, 3 V, 5 V, 7.5 V, 12 V or the like (e.g., above GND), without limiting the disclosure to these values. The skilled person may find a suitable potential for VDDPLX.

[0200] A detailed functional behavior of the photon detection circuitry 10 of Fig. 2 is described below with respect to Fig. 3 to 5.

[0201] Fig. 3 illustrates a reset and SPAD 11 recharge according to an embodiment. A of Fig. 3 shows currents (indicated by bold arrows) that flow in the photon detection circuitry 10 when the path signal is reset and the SPAD 11 is recharged. B of Fig. 3 shows levels of control signals and path signals during the reset and SPAD 11 recharge.

[0202] At ti, XRST changes to a low level, such that the reset transistor 16 becomes conductive and propagates the reset level (e.g., corresponding to a high level) to the input LA IN of the latch portion 12. The first inverter 12a inverts its input and outputs, at t2, a low level. Thus, the first output PFE OUT of the latch portion 12 changes to the low level. The second inverter 12b inverts its input and outputs a high level, such that the second output LA OUT of the latch portion 12 changes to the high level (e.g., “0”). Consequently, the latch portion 12 changes to the reset state.

[0203] Also, at ti, XRCG and XCLAMP are set to a low level, such that the reset level (e.g., high level) is propagated from the voltage source VDDPLX through the recharge portion 17 and the recharge prevention portion 18 to the cathode of the SPAD 11. Consequently, the path signal at the cathode of the SPAD 11 is set to the reset level, the SPAD 11 is recharged and a voltage VSPAD across the SPAD 11 changes to a high level (e.g., a value corresponding to VDDPLX) at t2.Our ref.: 240288EPWOP 26

[0204] At t3, XRCG, XRST and XCLAMP are reset to the high level, such that the transistors 16, 17 and 18 become non-conductive.

[0205] Fig. 4 illustrates a detection of a photon according to an embodiment. A of Fig. 4 shows currents (indicated by bold arrows) that flow in the photon detection circuitry 10 when a photon is detected. B of Fig. 4 shows levels of control signals and path signals during an exposure period in which a photon is detected.

[0206] XRCG and XRST are at a high level, such that the transistors 16 and 17 are non-conductive, as indicated by the strikethrough sign.

[0207] The latch portion 12 is in the reset state, such that the first output PFE OUT is at a low level, and second output LA OUT is at a high level.

[0208] At t4, the SPAD 11 receives a photon and is triggered. The photon causes an avalanche current, such that the SPAD voltage VSPAD drops to the breakdown value, and the path signal at the output (cathode) of the SPAD 11 is set to the detection level (low level).

[0209] At ts, XCLAMP changes to the low level and the clamping transistor 14 becomes conductive. The path signal corresponding to the detection level (e.g., “0”) is propagated through the clamping transistor 14 and the switch 13 to the latch portion 12, such that the input LA IN of the latch portion 12 changes from the reset level (high level) to the detection level (low level). The first inverter 12a inverts the input LA IN, such that the first output PFE OUT changes to the high level, thus indicating that a photon has been detected. The second inverter 12b inverts its input, such that the second output LA OUT changes to the low level. The low level from LA OUT is propagated to the gate of the switch 13, such that the switch 13 becomes non-conductive (as indicated by the strikethrough sign), and a change of the state of the latch portion 12 from the detection state to the reset state based on the path signal is inhibited.

[0210] Further, the high level from the first output PFE OUT of the latch portion 12 is propagated to the gate of the recharge prevention portion 18, such that the recharge prevention portion 18 becomes non-conductive, and a reset of the path signal as well as a recharging of the SPAD 11 is inhibited.

[0211] Fig. 5 illustrates a recharge prevention and readout according to an embodiment. A of Fig. 5 shows currents (indicated by bold arrows) that flow in the photon detection circuitry 10 during a recharge prevention and readout. B of Fig. 5 shows levels of control signals and path signals during a recharge prevention and readout.Our ref.: 240288EPWOP 27

[0212] At t?, XRCG and XCLAMP change to a low level according to a clock for a clocked recharge of the SPAD 11. However, the latch portion 12 is in the detection state and cannot detect a further photon. Recharging the SPAD 11 would, therefore, consume electric energy unnecessarily. Therefore, recharge prevention portion 18 inhibits a recharge of the SPAD 11 while the latch portion 12 is in the detection state. The gate of the recharge prevention portion 18 receives a high level from the first output PFE OUT of the latch portion 12 that is in the detection state, such that the recharge prevention portion 18 is non-conductive, as indicated by the strikethrough sign. Charges propagated from VDDPLX through the recharge portion 17 are blocked by the recharge prevention portion 18, such that the SPAD 11 is not unnecessarily recharged and the SPAD voltage VSPAD remains low.

[0213] At ts, XRCG and XCLAMP change back to the high level.

[0214] Further, when the latch portion 12 is in the detection state, the gate of the switch 13 receives the low level from the second output LA OUT of the latch portion 12, such that the switch 13 is non-conductive (as indicated by the strikethrough sign) and blocks a path signal from propagating through the switch 13 to the latch portion 12. Thus, the recharge prevention portion 18 does not allow a recharge of the SPAD 11 until the latch portion 12 is reset by the reset transistor 16.

[0215] For avoiding a floating state of the input LA IN of the latch portion 12, the second output LA OUT of the latch portion 12 is fed back through the feedback portion provided by the transistors 15a and 15b to the input LA IN of the latch portion 12. Accordingly, the first output PFE OUT remains at a high level, and the input LA IN as well as the second output LA OUT remain at a low level until the latch portion 12 is reset by the reset transistor 16. As long as XRST remains at a high level, the reset transistor 16 is non-conductive, as indicated by the strikethrough sign.

[0216] Fig. 6 illustrates a photon detection circuitry 100 with an inverter-NAND-based latch according to an embodiment. The photon detection circuitry 100 includes a photon detection portion 101 and a latch portion 102 (indicated by a dashed line).

[0217] The photon detection portion 101 includes a SPAD 101 and is configured similar to the photon detection portion 11 of Fig. 2. As described with respect to Fig. 2, an anode of the SPAD 101 is connected to ground GND (an example of a fixed-voltage node that provides a first fixed electric potential for setting a cathode of the SPAD 101 to a detection level (e.g., low level) at SPAD breakdown).Our ref.: 240288EPWOP 28

[0218] When the SPAD 101 detects a photon (illustrated by wiggly arrows), an avalanche current flows through the SPAD 101, such that the SPAD 101 propagates a signal that corresponds to a detection level from GND to a VK node 103, which is a node between the SPAD 101 and the latch portion 102.

[0219] The photon detection circuitry 100 includes a clamping transistor 104 between the SPAD 101 and the VK node 103. The clamping transistor 104 is a PMOS transistor and receives a control signal XCLAMP at its gate. The clamping transistor 104 controls, in accordance with XCLAMP, a propagation of the path signal from the SPAD 101 at a drain of the clamping transistor 104 to the VK node 103 at a source of the clamping transistor 104 as well as a recharging of the SPAD 101.

[0220] The photon detection circuitry 100 further includes a first switch 105 and a second switch 106, which are configured as PMOS transistors. A source of the first switch 105 is connected to a voltage source VDDPLX, which provides an electric potential that is higher than GND. A drain of the first switch 105 is connected to a source of the second switch 106. A drain of the second switch 106 is connected to an input node LA IN of the latch portion 102. A gate of the first switch 105 is connected to the VK node 103. A gate of the second switch 106 receives a control signal XCLIP. Thus, the second switch 106 corresponds to a switch that is configured to propagate, in accordance with the control signal XCLIP, the path signal to the latch portion 102. The latch portion 102 includes an inverter-NAND (logical NOT-AND) gate 110. For example, the inverter-NAND gate 110 may be realized using transistors (e.g., NMOS transistors and / or PMOS transistors), as the skilled person may appreciate. A first input terminal of the inverter-NAND gate 110 is connected to the input LA_IN of the latch portion 102. A second input terminal of the inverter-NAND gate 110 receives a control signal XRST. Thus, an output PFE OUT of the inverter-NAND gate 110 (and of the latch portion 102) is set to a low level if both LA IN and XRST correspond to a high level, and to is set to a high level otherwise.

[0221] Accordingly, the latch portion 102 is configured as an inverter-NAND-based latch, and the latch portion 102 changes its state to a detection state when the path signal changes to the detection level, wherein the detection state indicates the detected photon.

[0222] The latch portion 102 further includes a feedback portion that is configured to propagate a signal from the output PFE OUT of the latch portion 102 to the input LA IN of the latch portion 102. The feedback portion includes a first feedback transistor 111, a second feedback transistor 112, a first reset transistor 113 and a second reset transistor 114.Our ref.: 240288EPWOP 29

[0223] The first feedback transistor 111 is a PMOS transistor. A source of the first feedback transistor Ill is connected to VDDPLX. A drain of the first feedback transistor 111 is connected to the input LA IN of the latch portion 102.

[0224] The second feedback transistor 112 is an NMOS transistor. A source of the second feedback transistor 112 is connected to ground GND. A drain of the second feedback transistor 112 is connected to sources of the first and second reset transistors 113 and 114. Drains of the first and second reset transistors 113 and 114 are connected to the input LA IN of the latch portion 102. Thus, the second feedback transistor 112 is connected to the input LA IN of the latch portion 102 via the first and second reset transistors 113 and 114.

[0225] The first and second reset transistors 113 and 114 are NMOS transistors. A gate of the first reset transistor 113 is connected to the VK node 103. A gate of the second reset transistor 114 receives the control signal XCLIP.

[0226] The first and second feedback transistors 111 and 112 receive the output PFE OUT of the latch portion 102 at their gates. Therefore, the feedback portion is configured to propagate a signal from the output PFE OUT of the latch portion 102 to the input LA IN of the latch portion 102. By providing the output PFE OUT of the latch portion 102 to the gates of the first and second feedback transistors 111 and 112, the latch portion 102 inhibits a change of its state from the detection state to a reset state based on the path signal (at the VK node 103).

[0227] The photon detection circuitry 100 further includes a recharge portion 120 and a recharge prevention portion 121, which are configured as PMOS transistors.

[0228] The recharge portion 120 receives a control signal XRCG at its gate. For example, XRCG is a clock signal, without limiting the disclosure thereto. A source of the recharge portion 120 is connected to VDDPLX. A drain of the recharge portion 120 is connected to a source of the recharge prevention portion 121. The recharge portion 120 resets, in accordance with XRCG and if the recharge prevention portion 121 is in a conducting state, the path signal at the VK node 103 (and at the cathode of the SPAD 101 if the clamping transistor 104 is in a conducting state) to a reset level. The reset level indicates that no photon has been detected. For resetting the path signal, the recharge portion 120 establishes an electric connection between VDDPLX and the VK node 103 (if the clamping transistor 104 is in a conducting state).

[0229] A gate of the recharge prevention portion 121 is connected to the input LA IN of the latch portion 102. A drain of the recharge prevention portion 121 is connected to the VK node 103. Thus, the recharge prevention portion 121 inhibits the reset of the path signal at the VK node 103Our ref.: 240288EPWOP 30

[0230] (and at the cathode of the SPAD 101) in accordance with the input LA IN (and, thus, with a state) of the latch portion 102. The inhibiting of the reset of the path signal includes blocking a reset of the path signal when a voltage at the gate of the recharge prevention portion 121 (and, thus, at LA IN) is at a low level. The inhibiting of the reset of the path signal further includes blocking an electric connection between LDDPLX and the VK node 103.

[0231] Accordingly, a front-end of the photon detection circuitry 100 includes an inverter-NAND-based latch (the latch portion 102) with the XCLIP signal, which decides either to receive a signal or to keep the values in the latch portion 102. This enables a proper isolation between the VK node 103 and the latch input LA IN for normal operations such as reset with recharging, signal receiving, and latching the data. The PMOS transistor 121 for the recharge prevention is included as well to inhibit the recharge if the latch portion 102 is in the detection state (e.g., stores a high value “H” that indicates that a light event has been detected). Until a next reset, the recharge prevention is active and the latch portion 102 retains the value.

[0232] A detailed functional behavior of the photon detection circuitry 100 is described below with respect to Fig. 7 to 9.

[0233] Fig. 7 illustrates a reset and SPAD 101 recharge in the photon detection circuitry 100 with the inverter-NAND-based latch 102 according to an embodiment. A of Fig. 7 shows currents (indicated by bold arrows) that flow in the photon detection circuitry 100 when the path signal is reset and the SPAD 101 is recharged. B of Fig. 7 shows levels of control signals and path signals during the reset and SPAD 101 recharge.

[0234] At tio, XCLAMP is set to a low level such that the recharge portion 120 can recharge the SPAD 101.

[0235] At tn, XRCG and XRST are set to a low level. XRST resets the latch portion 102 to the reset state such that PFE OUT is set to a high level and LA IN is set to a low level (e.g., “0”) via the transistors 114 and 112.

[0236] XRCG and XCLAMP cause the SPAD 101 to be recharged and the VK node 103 to be set to the reset level (e.g., VDD value).

[0237] At tn, XRCG and XRST are set to a high level. At ti3, XCLAMP is set to a high level.

[0238] During the processing of Fig. 7, XCLIP remains of a high level, and the transistors 106 and 111 remain in a non-conductive state.Our ref.: 240288EPWOP 31

[0239] For simplicity, Fig. 7 shows a case in which no photon is received during the reset and SPAD 101 recharge (as illustrated by the curve labelled with “Photon”).

[0240] Fig. 8 illustrates a detection of a photon in the photon detection circuitry 100 with the inverter-NAND-based latch 102 according to an embodiment. A of Fig. 8 shows currents (indicated by bold arrows) that flow in the photon detection circuitry 100 during triggering and latching due to a detected photon. B of Fig. 8 shows levels of control signals and path signals during the triggering and latching.

[0241] At tw, the SPAD 101 detects a photon, as indicated by the curve labelled with “Photon”. The SPAD 101 triggers and holds a VSPAD node (a cathode of the SPAD 101) at a low level (detection level).

[0242] At tis, XCLAMP is set to the low level such that the clamping transistor 104 propagates the path signal that corresponds to the detection level from the cathode of the SPAD 101 to the VK node 103. Thus, the VK node 103 is also set to the detection level (low level, “0”).

[0243] At tie, XCLIP is set to the low level for triggering the latch portion 102 with a high level (e.g., “1”). When the latch portion 102 is triggered, it disables the recharge prevention PMOS 121 by setting PFE OUT to the low level and LA IN to the high level. When PFE OUT is set to the low level, the first feedback transistor 111 causes the latch input LA IN to remain at the high level, as indicated by the dashed line.

[0244] Then, XCLIP is set to the high level and XCLAMP is set to the high level. During the processing of Fig. 8, XRCG and XRST remain at the high level, and the transistors 112, 113, 114 and 120 remain in a non-conductive state.

[0245] Fig. 9 illustrates a recharge prevention and readout in the photon detection circuitry 100 with the inverter-NAND-based latch 102 according to an embodiment. A of Fig. 9 shows currents (indicated by bold arrows) that flow in the photon detection circuitry 100 during recharge prevention and readout. B of Fig. 9 shows levels of control signals and path signals during recharge prevention and readout.

[0246] At tn, XCLAMP is set to the low level. Then, XCLIP is set to the low level and back to the high level. Then, XRCG is set to the low level and back to the high level.

[0247] At ti8, XCLAMP is set back to the high level.

[0248] During the processing of Fig. 9, the VK node 103 remains at the low level, XRST remains at the high level, LA IN remains at the high level, and PFE OUT remains at the low level. Thus, theOur ref.: 240288EPWOP 32

[0249] transistors 112, 113, 114 and 120 remain in a non-conducting state. Also, since LA IN remains at the high level, the recharge prevention portion 120 does not allow a recharge of the SPAD 101 until the latch portion 102 is reset. Further, Fig. 9 shows a case in which no photon is detected during the recharge prevention and readout.

[0250] Fig. 10 illustrates a photon detection circuitry 200 with an inverter-tristate-inverter latch 202 according to an embodiment. The photon detection circuitry 200 includes a photon detection portion 201 and a latch portion 202 (indicated by a dashed line).

[0251] The photon detection portion 201 includes a SPAD 201 and is configured similar to the photon detection portion 11 of Fig. 2 and the photon detection portion 101 of Fig. 6.

[0252] The photon detection circuitry 200 further includes a clamping transistor 204 that receives a control signal XCLAMP and that is connected between the SPAD 201 and a VK node 203. The clamping transistor 204 is configured similar to the clamping transistor 104 of Fig. 6.

[0253] The latch portion 202 is configured as an inverter-tristate-inverter latch and includes a first inverter 210 and a second inverter 211.

[0254] An input of the first inverter 210 is connected to the VK node 203. The first inverter 210 is configured as a tristate inverter. The first inverter 210 receives, as a first voltage, a control signal XCLIP and, as a second voltage, an output PFE OUT of the latch portion 202. In the embodiment of Fig. 10 to 13, the XCLIP input of the first inverter 210 is configured as an active low input. An output of the first inverter 210 corresponds to an input LA IN of the latch portion 202.

[0255] An input of the second inverter 211 is connected to the input LA IN of the latch portion 202. An output of the second inverter 211 corresponds to the output PFE OUT of the latch portion. The second inverter 211 receives a voltage VDDPLX (which corresponds to VDDPLX of Fig. 2 and 6) as voltage input.

[0256] Thus, the latch portion 202 changes its state to a detection state when the path signal changes to the detection level, wherein the detection state indicates the detected photon.

[0257] It is noted that the first and second inverters 210 and 211 may be realized using transistors (e.g., NMOS transistors and / or PMOS transistors), as the skilled person may appreciate.

[0258] The latch portion 202 includes a feedback portion, which includes the first inverter 210 and a feedback transistor 212. The feedback transistor 212 is a PMOS transistor and receives theOur ref.: 240288EPWOP 33

[0259] output PFE OUT of the latch portion 202 at its gate. A source of the feedback transistor 212 is connected to VDDPLX.

[0260] The latch portion 202 further includes a first reset transistor 213 and a second reset transistor 214, which receive a control signal RST at their gates. The first reset transistor 213 is a PMOS transistor. A source of the first reset transistor 213 is connected to a drain of the feedback transistor 212. A drain of the first reset transistor 213 is connected to the input LA IN of the latch portion 202 and to a drain of the second reset transistor 214. The second reset transistor 214 is an NMOS transistor. A source of the second reset transistor 214 is connected to ground GND. By providing the output PFE OUT of the latch portion 202 to the second voltage input of the first inverter 210 and to the gate of the feedback transistor 212, the latch portion 202 inhibits a change of its state from the detection state to a reset state based on the path signal (at the VK node 203).

[0261] Accordingly, the first inverter 210 corresponds to a switch that propagates, in accordance with the state of the latch portion 202, the path signal from the VK node 203 to the latch portion 202, is controlled by the output PFE OUT of the latch portion 202 that indicates the state of the latch portion 202, blocks the path signal from the VK node 203 when the state of the latch portion 202 corresponds to the detection state, and propagates the path signal from the VK node 203 to the latch portion 202 when the state of the latch portion 202 corresponds to the reset state. Further, the first inverter 210 corresponds to a switch that is configured to propagate, in accordance with the control signal XCLIP, the path signal to the latch portion 202.

[0262] The photon detection circuitry 200 further includes a recharge portion 220, which receives a control signal XRCG at its gate, and a recharge prevention portion 221, whose gate is connected to the input LA IN of the latch portion 202. The recharge portion 220 and the recharge prevention portion 221 are PMOS transistors and are configured similar to the recharge portion 120 and the recharge prevention portion 121 of Fig. 6, respectively.

[0263] Accordingly, a front-end of the photon detection circuitry 200 includes an inverter -tri stateinverter latch (the latch portion 202) with the XCLIP signal, which decides either to receive a signal or to keep the values in the latch portion 202. This enables the proper isolation between the VK node 203 and the latch input LA IN for normal operations such as reset with recharging, signal receiving, and latching the data. The PMOS transistor 221 for the recharge prevention is included as well to inhibit the recharge if the latch portion 202 is in the detection state (e.g.,Our ref.: 240288EPWOP 34

[0264] stores a high value “H” that indicates that a light event has been detected). Until a next reset, the recharge prevention is active and the latch portion 202 retains the value.

[0265] A detailed functional behavior of the photon detection circuitry 200 is described below with respect to Fig. 11 to 13.

[0266] Fig. 11 illustrates a reset and SPAD recharge in the photon detection circuitry 200 with the inverter-tristate-inverter latch 202 according to an embodiment. A of Fig. 11 shows currents (indicated by bold arrows) that flow in the photon detection circuitry 200 when the path signal is reset and the SPAD 201 is recharged. B of Fig. 11 shows levels of control signals and path signals during the reset and SPAD 201 recharge. The processing of Fig. 11 is similar to the processing of Fig. 7.

[0267] At t2o, XCLAMP is set to a low level such that the recharge portion 220 can recharge the SPAD 201.

[0268] At t2i, XRCG is set to a low level for recharging the SPAD 201. RST is set to a high level, such that the input LA_IN of the latch portion 202 is set to a low level (e.g., “0”) and latch portion 202 is reset to the reset state. Thus, PFE OUT is set to a high level. Further, the recharge prevention portion 221 becomes conductive and allows the SPAD 201 to be recharged.

[0269] XRCG and XCLAMP cause the SPAD 201 to be recharged and the VK node 203 to be set to the reset level (e.g., VDD value).

[0270] At t22, XRCG is set back to the high level and RST is set back to the low level. At t23, XCLAMP is set to the high level.

[0271] During the processing of Fig. 11, XCLIP remains at a high level. For simplicity, Fig. 11 shows a case in which no photon is received during the reset and SPAD 201 recharge (as illustrated by the curve labelled with “Photon”).

[0272] Fig. 12 illustrates a detection of a photon in the photon detection circuitry 200 with the inverter-tristate-inverter latch 202 according to an embodiment. A of Fig. 12 shows currents (indicated by bold arrows) that flow in the photon detection circuitry 200 during triggering and latching due to a detected photon. B of Fig. 12 shows levels of control signals and path signals during the triggering and latching. The processing of Fig. 12 is similar to the processing of Fig. 8.

[0273] At t24, the SPAD 201 detects a photon, as indicated by the curve labelled with “Photon”. The SPAD 201 triggers and holds a VSPAD node (a cathode of the SPAD 201) at a low level (detection level).Our ref.: 240288EPWOP 35

[0274] At t25, XCLAMP is set to the low level such that the clamping transistor 204 propagates the path signal that corresponds to the detection level from the cathode of the SPAD 201 to the VK node 203. Thus, the VK node 203 is also set to the detection level (low level, “0”).

[0275] At t26, XCLIP is set to the low level for triggering the latch portion 202 with a high level (e.g., “1”). When the latch portion 202 is triggered, it disables the recharge prevention PMOS 221 by setting PFE OUT to the low level and LA IN to the high level. When PFE OUT is set to the low level, the feedback transistor 212 causes the latch input LA IN to remain at the high level, as indicated by the dashed line.

[0276] Then, XCLIP is set to the high level and XCLAMP is set to the high level. During the processing of Fig. 12, XRCG remains at the high level, RST remains at the low level, and the transistors 214 and 220 remain in a non-conductive state.

[0277] Fig. 13 illustrates a recharge prevention and readout in the photon detection circuitry 200 with the inverter-tri state-inverter latch 202 according to an embodiment. A of Fig. 13 shows currents (indicated by bold arrows) that flow in the photon detection circuitry 200 during recharge prevention and readout. B of Fig. 13 shows levels of control signals and path signals during recharge prevention and readout. The processing of Fig. 13 is similar to the processing of Fig. 9. At t27, XCLAMP is set to the low level. Then, XCLIP is set to the low level and back to the high level. Then, XRCG is set to the low level and back to the high level.

[0278] At t28, XCLAMP is set back to the high level.

[0279] During the processing of Fig. 13, the VK node 203 remains at the low level, XRST remains at the low level, LA IN remains at the high level, and PFE OUT remains at the low level. Thus, the transistors 214 and 220 remain in a non-conducting state. Also, since LA IN remains at the high level, the recharge prevention portion 220 does not allow a recharge of the SPAD 201 until the latch portion 202 is reset. Further, Fig. 13 shows a case in which no photon is detected during the recharge prevention and readout.

[0280] Fig. 14 illustrates a method 20 for the photon detection circuitry 10 of Fig. 2, the photon detection circuitry 100 of Fig. 6 or the photon detection circuitry 200 of Fig. 10 according to an embodiment. The method 20 is performed by the photon detection circuitry 10, 100 or 200 when detecting a photon.

[0281] Before detecting a photon, the SPAD 11, 100 or 200 is (re)charged and the latch portion 12, 102 or 202 is set to the reset state (e.g., as illustrated in B of Fig. 3, in B of Fig. 7 and in B ofOur ref.: 240288EPWOP 36

[0282] Fig. 11). When detecting a photon, the SPAD 11, 101 or 201 breaks down and outputs a path signal that corresponds to the detection level (e.g., as illustrated at in B of Fig. 4).

[0283] At 21, the latch portion 12, 102 or 202 receives, from the SPAD 11, 101 or 201, a path signal that corresponds to the detection level (e.g., as illustrated at ts in B of Fig. 4, at tie in B of Fig. 8 and at t26 in B of Fig. 12) and, thus, indicates a photon detection event.

[0284] At 22, the state of the latch portion 12 changes to the detection state (e.g., as illustrated at ts in B of Fig. 4, at tie in B of Fig. 8 and at t26 in B of Fig. 12), thus indicating the photon detection event.

[0285] At 23, the latch portion 12, 102 or 202 inhibits a change of the state of the latch portion 12, 102 or 202 from the detection state to the reset state based on the path signal. In the photon detection circuit 10, the inhibiting includes providing the second output LA OUT to the gate of the switch 13, such that, at 24, the switch 13 blocks the path signal from the SPAD 11 from propagating to the latch portion 12 when the state of the latch portion 12 corresponds to the detection state. In the photon detection circuit 100, the inhibiting includes providing the output PFE OUT of the latch portion 102 to the first and second feedback transistors 111 and 112 such that the input LA IN of the latch portion 102 is kept at the high level. In the photon detection circuit 200, the inhibiting includes providing the output PFE OUT of the latch portion 202 to the feedback transistor 212 and to the second voltage input of the first inverter 210 such that the input LA IN of the latch portion 202 is kept at the high level.

[0286] At 25, the recharge prevention portion 18, 121 or 221 receives the first output PFE OUT of the latch portion 12, 102 o 202 and blocks a reset of the path signal when the state of the latch portion 12, 102 o 202 corresponds to the detection state.

[0287] At 26, the feedback portion (including the transistors 15a and 15b, the transistors 111, 112, 113 and 114, or the first inverter 210 and the transistor 212) propagates a signal from the second output LA OUT of the latch portion 12, 102 or 202 to the input LA IN of the latch portion 12, 102 or 202.

[0288] When the first output PFE OUT has been read out (e.g., by a logic portion of an image sensor, for example by the pixel logic circuit 34 of Fig. 15 or by the logic portion 44 of Fig. 16), the SPAD 11, 101 or 201 may be recharged and the latch portion 12, 102 or 202 may be set to the reset state, and the processing at 21 to 26 may be performed again, e.g., when the SPAD 11, 101 or 201 performs a further photon.Our ref.: 240288EPWOP 37

[0289] Fig. 15 illustrates an image sensor 30 according to an embodiment. The image sensor 30 includes a plurality of pixels 31 that are arranged in a two-dimensional array. Each pixel includes a SPAD 32 (an example of a photon detection portion, e.g., the SPAD 11 of Fig. 2, the SPAD 101 of Fig. 6, the SPAD 201 of Fig. 10, or the SPAD 51 of Fig. 17), a latch front-end 33 and a pixel logic circuit 34.

[0290] The latch front-end 33 includes a latch portion, a switch, a feedback portion, a reset transistor, a clamping transistor, a recharge portion and a recharge prevention portion. The SPAD 32 and the latch front-end 33 form a photon detection circuitry such as the photon detection circuitry 10 of Fig. 2, the photon detection circuitry 100 of Fig. 6, the photon detection circuitry 200 of Fig. 10 or the photon detection circuitry 50 of Fig. 17.

[0291] The pixel logic circuit 34 includes a readout circuit that reads out the state of the latch portion of the latch front-end 33 and, thus, reads out an indication of a photon detection event.

[0292] The pixel logic circuits 34 are part of a logic portion of the image sensor 30. The logic portion generates an image signal based on the state of the latch portions of the latch front-ends 33 of the plurality of pixels 31.

[0293] Fig. 16 illustrates an electronic device 40 according to an embodiment.

[0294] The electronic device 40 includes a lens 41, an image sensor 42 and a processing portion 45. The lens 41 is an example of an optical element and focuses incident light onto the image sensor 42. The image sensor 42 includes a plurality of photon detection circuitries 43, each of which is configured like the photon detection circuitry 10 of Fig. 2, like the photon detection circuitry 100 of Fig. 6, like the photon detection circuitry 200 of Fig. 10 or like the photon detection circuitry 50 of Fig. 17, and detects photons from the lens 41.

[0295] The image sensor 42 further includes a logic portion 44 that reads out the states of the latch portions of the plurality of photon detection circuitries 43 (e.g., with one or more readout circuit(s) of the logic portion 44) and generates an image signal based on the state of the latch portions of the plurality of photon detection circuitries 43.

[0296] The processing portion 45 receives the image signal from the logic portion 44 and performs processing according to the image signal.

[0297] The present technology may be used in any SPAD-based sensor as a circuit that is responsible for collecting information from the SPAD may store the information until it is transferred to aOur ref.: 240288EPWOP 38

[0298] readout circuit or to some signal conditioning circuit. It may have the role of recharging the SPAD to allow the sensor to be ready for receiving light information.

[0299] In some embodiments, the present technology allows subdividing a long exposure into multiple sub-exposures without losing a potential photon hit, preventing a recharge of a SPAD if an event has been received until the latch portion is reset, and / or storing a received event from the SPAD. In some embodiments, only one event may be detected between two reset phases (sub-exposure time).

[0300] It is noted that the photon detection circuitry 10 of Fig. 2, the photon detection circuitry 100 of Fig. 6, the photon detection circuitry 200 of Fig. 10 and the photon detection circuitry 50 of Fig. 17 are provided for exemplary purposes. The present technology may be carried out in various ways that depart from the embodiments of Fig. 2, 6, 10 and / or 17.

[0301] Although Fig. 2 to 13 and 17 show that the anode of the SPAD 11, 101, 201 or 51 is coupled to ground GND, the anode of the SPAD 11, 101, 201 or 51 may instead be coupled to a voltage level different than ground (e.g., a negative supply voltage) as long as a proper function (e.g., recharge, breakdown) of the SPAD 11, 101, 201 or 51 is possible. Likewise, the source of the second feedback transistor 112 of Fig. 6 to 9 and / or the source of the second reset transistor 214 of Fig. 10 to 13 may be coupled to a voltage level different than ground that may be sufficiently lower than the supply voltage VDDPLX.

[0302] Further, although Fig. 2 to 13 show that the pixel front-end (PFE) is coupled to the same voltage VDDPLX as the recharge portion 17, 120 and 220, respectively, the disclosure is not limited thereto. Instead, the PFE may have another supply domain (e.g., may be coupled to another supply voltage) than the recharge portion 17, 120 or 220, respectively. For example, the sources of the transistors 16, 105, 111 and / or 212 and / or the voltage input of the second inverter 211 may be connected to another voltage source than VDDPLX such that a supply voltage of the recharge portion 17, 120 or 220 may be different (e.g., higher or lower) than a supply voltage of the latch portion 12, 102 or 202, respectively. Accordingly, in some embodiments, a supply voltage of the recharge portion is different (e.g., higher or lower) than a supply voltage of the latch portion. The XCLAMP signal of Fig. 2 to 13 and 17 may be a toggling signal (e.g., in the case of Fig. 2, for making the clamping transistor 14 conductive only when the path signal is propagated from the SPAD 11 to the latch portion 12 and / or when the path signal reset) or may be a steady signal (e.g., a static signal that may be kept at a predetermined voltage level (e.g., “low”) during an operation of the photon detection circuitry 10, 100, 200 or 50 for allowing a current through theOur ref.: 240288EPWOP 39

[0303] clamping transistor 14, 104, 204 or 54), e.g., based on a circuit purpose. In some embodiments, the clamping transistor 14, 104, 204 or 54 is not provided.

[0304] The recharge portion 17, 120 or 220 and the recharge prevention portion 18, 121 or 221, respectively, may be exchanged.

[0305] The photon detection circuitry 10, 100, 200 or 50 may be provided on one substrate (e.g., wafer), or the SPAD 11, 101, 201 or 51 (or any other photon detection portion) may be included in another wafer than a logic wafer (on which the latch portion 12, 102, 202 or 52 may be provided), wherein the other wafer may be connected with the logic wafer.

[0306] Transistors of the photon detection circuitry 10, 100, 200 or 50 may be partially or totally provided in a SPAD layer (e.g., on a substrate / wafer on which the SPAD 11, 101, 201 or 51 may be provided) or in a logic layer (e.g., on a substrate / wafer on which a logic portion may be provided), or may be provided on another wafer (substrate) different from the SPAD layer and the logic layer.

[0307] The latch portion 12, 102, 202 or 52 may be implemented using different topologies than a weak-feedback inverter, for example, using an SR-latch and / or a D-latch. As mentioned, a weak-feedback inverter may require a lower number of transistors than other topologies.

[0308] In some embodiments, the latch portion provides two outputs, wherein a negated output may be taken from a second inverter output.

[0309] The SPAD 11 may be connected to the pixel front-end through its anode. For example, a cathode of the SPAD 11 may be connected to the voltage source VDDPLX. The switch 13, the clamping transistor 14, the recharge portion 17 and the recharge prevention portion 18 may then be provided between the anode of the SPAD 11 and ground GND. In such a case, a conductivity type of the transistors may be switched as compared to Fig. 2; e.g., the transistor 13 may then be a PMOS transistor, and the transistors 14, 16, 17 and 18 may then be NMOS transistors. Similar modifications may be applied to the embodiments of Fig. 6 and 10.

[0310] Fig. 17 illustrates an embodiment of a photon detection circuitry 50 in which a photon detection portion 51 is connected to a pixel front-end via an anode. A cathode of the photon detection portion 51 is connected to a voltage source (VDDPLX, which corresponds to VDDPLX of Fig. 2, 6 and 10). The photon detection portion 51 includes a SPAD 51.Our ref.: 240288EPWOP 40

[0311] The photon detection circuitry 50 includes a latch portion 52 and a VK node 53. The VK node 53 is connected to the anode of the SPAD 51 via a clamping transistor 54 and to an inverted data input D of the latch portion 52.

[0312] The latch portion 52 provides a first output PFE OUT and a second output. The second output is inverted and is connected to an input EN of the latch portion 52.

[0313] The VK node 53 is further connected to ground GND via a switch 55 (e.g., a transistor). The switch 55 is controlled by an output of a NAND gate 56. The NAND gate 56 receives as input a control signal RCG and the second output of the latch portion 52.

[0314] The photon detection circuitry 50 is controlled similar to the photon detection circuitry 10, 100 and 200 described above. In particular, the SPAD 51 set a path signal at its anode to a detection level when a photon is detected, wherein the detection level indicates the detected photon. When a control signal CLAMP is set to a high level, the clamping transistor 54 (an NMOS transistor) propagates the path signal from the anode of the SPAD 51 to the VK node 53.

[0315] When a path signal at the VK node 53 changes to the detection level, the latch portion 52 changes its state to a detection state. The detection state indicates the detected photon. The first output PFE OUT indicates the detected state to readout circuitry. The second output of the latch portion 52 is provided to the input EN of the latch portion 52 for inhibiting a change of the state of the latch portion 52 from the detection state to a reset state based on the path signal at the VK node 53 before the latch portion 52 is set to the reset state via a control signal RST. The second output of the latch portion 52 is further provided to the NAND gate 56 for inhibiting a reset of the path signal in accordance with the state of the latch potion 52.

[0316] Accordingly, the switch 55 and the NAND gate 56 correspond to a recharge portion and to a recharge prevention portion. Further, the connection between the second output of the latch portion 52 and the EN input of the latch portion 52 corresponds to a feedback portion.

[0317] The photon detection circuitry 50 may be controlled with a method similar to the method 20 of Fig. 14. The skilled person may find the necessary adaptations to the embodiment of Fig. 14 for controlling the photon detection circuitry 50.

[0318] It should be recognized that the embodiments describe methods with an exemplary ordering of method steps. The specific ordering of method steps is however given for illustrative purposes only and should not be construed as binding. For example, the ordering of 23, 25 and 26 in the embodiment of Fig. 14 may be exchanged. Other changes of the ordering of method steps may be apparent to the skilled person.Our ref.: 240288EPWOP 41

[0319] Please note that the division of the photon detection circuitry 10 into entities 11 to 18 is only made for illustration purposes and that the present disclosure is not limited to any specific division of functions in specific entities.

[0320] All units and entities described in this specification and claimed in the appended claims can, if not stated otherwise, be implemented as integrated circuit logic, for example on a chip, and functionality provided by such units and entities can, if not stated otherwise, be implemented by software.

[0321] In so far as the embodiments of the disclosure described above are implemented, at least in part, using software-controlled data processing apparatus, it will be appreciated that a computer program providing such software control and a transmission, storage or other medium by which such a computer program is provided are envisaged as aspects of the present disclosure.

[0322] Note that the present technology can also be configured as described below.

[0323] (1) A photon detection circuitry, comprising:

[0324] a photon detection portion configured to set a path signal to a detection level when a photon is detected, the detection level indicating the detected photon; and

[0325] a latch portion configured to change its state to a detection state when the path signal changes to the detection level, the detection state indicating the detected photon;

[0326] wherein the latch portion is configured to inhibit a change of its state from the detection state to a reset state based on the path signal.

[0327] (2) The photon detection circuitry of (1), further comprising:

[0328] a switch configured to propagate, in accordance with the state of the latch portion, the path signal to the latch portion.

[0329] (3) The photon detection circuitry of (2),

[0330] wherein the switch is configured to be controlled by an output of the latch portion that indicates the state of the latch portion.

[0331] (4) The photon detection circuitry of (2) or (3),

[0332] wherein the switch is configured to block the path signal when the state of the latch portion corresponds to the detection state.

[0333] (5) The photon detection circuitry of any one of (2) to (4),

[0334] wherein the switch is configured to propagate the path signal to the latch portion when the state of the latch portion corresponds to the reset state.Our ref.: 240288EPWOP 42

[0335] (6) The photon detection circuitry of any one of (1) to (5), further comprising:

[0336] a switch configured to propagate, in accordance with a control signal, the path signal to the latch portion.

[0337] (7) The photon detection circuitry of any one of (1) to (6), further comprising:

[0338] a recharge prevention portion configured to inhibit a reset of the path signal in accordance with the state of the latch portion.

[0339] (8) The photon detection circuitry of (7),

[0340] wherein the inhibiting of the reset of the path signal includes blocking a reset of the path signal when the state of the latch portion corresponds to the detection state.

[0341] (9) The photon detection circuitry of (7) or (8),

[0342] wherein the inhibiting of the reset of the path signal includes blocking an electric connection between a voltage source that is configured to provide the reset level and a node between the photon detection portion and the latch portion.

[0343] (10) The photon detection circuitry of any one of (7) to (9),

[0344] wherein the recharge prevention portion is configured to be controlled by an output of the latch portion that indicates the state of the latch portion.

[0345] (11) The photon detection circuitry of any one of (1) to (10), further comprising:

[0346] a feedback portion configured to propagate a signal from an output of the latch portion to an input of the latch portion.

[0347] (12) The photon detection circuitry of (11),

[0348] wherein the feedback portion is configured to propagate the signal slower than a signal propagation through the latch portion.

[0349] (13) The photon detection circuitry of (11) or (12),

[0350] wherein the feedback portion includes at least one transistor coupled between the output of the latch portion and the input of the latch portion, wherein the transistor is configured to receive a predetermined gate signal at which the transistor has a predetermined resistance.

[0351] (14) The photon detection circuitry of any one of (1) to (13), further comprising:

[0352] a recharge portion configured to reset the path signal to a reset level.

[0353] (15) The photon detection circuitry of (14),

[0354] wherein the recharge portion is configured to reset the path signal in accordance with a clock signal.Our ref.: 240288EPWOP 43

[0355] (16) The photon detection circuitry of (14) or (15),

[0356] wherein the resetting of the path signal includes establishing an electric connection between a voltage source that is configured to provide the reset level and a node between the photon detection portion and the latch portion.

[0357] (17) The photon detection circuitry of any one of (1) to (16), wherein the latch portion includes:

[0358] a first inverter configured to invert an input of the latch portion; and

[0359] a second inverter configured to invert an output of the first inverter.

[0360] (18) The photon detection circuitry of any one of (1) to (17),

[0361] wherein the photon detection portion is configured to propagate, when a photon is detected, a signal that corresponds to the detection level from a fixed-voltage node to a node between the photon detection portion and the latch portion.

[0362] (19) The photon detection circuitry of any one of (1) to (18),

[0363] wherein the photon detection portion includes a single-photon avalanche diode.

[0364] (20) An image sensor, comprising:

[0365] a plurality of photon detection circuitries according to any one of (1) to (19); and a logic portion configured to generate an image signal based on the state of the latch portions of the plurality of photon detection circuitries.

[0366] (21) An electronic device, comprising:

[0367] the image sensor according to (20); and

[0368] a processing portion configured to perform processing according to the generated image signal.

[0369] (22) A method for the photon detection circuitry of any one of (1) to (19), the method comprising:

[0370] receiving, at the latch portion, a path signal that corresponds to the detection level; changing the state of the latch portion to the detection state; and

[0371] inhibiting a change of the state of the latch portion from the detection state to the reset state based on the path signal.

[0372] (23) The method of (22), further comprising:

[0373] blocking, by a switch, the path signal from propagating to the latch portion when the state of the latch portion corresponds to the detection state.Our ref.: 240288EPWOP 44

[0374] (24) The method of (22) or (23), further comprising:

[0375] blocking, by a recharge prevention portion, a reset of the path signal when the state of the latch portion corresponds to the detection state.

[0376] (25) The method of any one of (22) to (24), further comprising:

[0377] propagating, by a feedback portion, a signal from an output of the latch portion to an input of the latch portion.

Claims

Our ref.: 240288EPWOP 1CLAIMS1. A photon detection circuitry, comprising:a photon detection portion configured to set a path signal to a detection level when a photon is detected, the detection level indicating the detected photon; anda latch portion configured to change its state to a detection state when the path signal changes to the detection level, the detection state indicating the detected photon;wherein the latch portion is configured to inhibit a change of its state from the detection state to a reset state based on the path signal.

2. The photon detection circuitry of claim 1, further comprising:a switch configured to propagate, in accordance with the state of the latch portion, the path signal to the latch portion.

3. The photon detection circuitry of claim 2,wherein the switch is configured to be controlled by an output of the latch portion that indicates the state of the latch portion.

4. The photon detection circuitry of claim 2,wherein the switch is configured to block the path signal when the state of the latch portion corresponds to the detection state.

5. The photon detection circuitry of claim 2,wherein the switch is configured to propagate the path signal to the latch portion when the state of the latch portion corresponds to the reset state.

6. The photon detection circuitry of claim 1, further comprising:a recharge prevention portion configured to inhibit a reset of the path signal in accordance with the state of the latch portion.

7. The photon detection circuitry of claim 6,wherein the inhibiting of the reset of the path signal includes blocking a reset of the path signal when the state of the latch portion corresponds to the detection state.

8. The photon detection circuitry of claim 6,wherein the inhibiting of the reset of the path signal includes blocking an electric connection between a voltage source that is configured to provide the reset level and a node between the photon detection portion and the latch portion.Our ref.: 240288EPWOP 29. The photon detection circuitry of claim 6,wherein the recharge prevention portion is configured to be controlled by an output of the latch portion that indicates the state of the latch portion.

10. The photon detection circuitry of claim 1, further comprising:a feedback portion configured to propagate a signal from an output of the latch portion to an input of the latch portion.

11. The photon detection circuitry of claim 10,wherein the feedback portion is configured to propagate the signal slower than a signal propagation through the latch portion.

12. The photon detection circuitry of claim 10,wherein the feedback portion includes at least one transistor coupled between the output of the latch portion and the input of the latch portion, wherein the transistor is configured to receive a predetermined gate signal at which the transistor has a predetermined resistance.

13. The photon detection circuitry of claim 1, further comprising:a recharge portion configured to reset the path signal to a reset level.

14. The photon detection circuitry of claim 13,wherein the recharge portion is configured to reset the path signal in accordance with a clock signal.

15. The photon detection circuitry of claim 13,wherein the resetting of the path signal includes establishing an electric connection between a voltage source that is configured to provide the reset level and a node between the photon detection portion and the latch portion.

16. The photon detection circuitry of claim 1, wherein the latch portion includes:a first inverter configured to invert an input of the latch portion; anda second inverter configured to invert an output of the first inverter.

17. The photon detection circuitry of claim 1,wherein the photon detection portion is configured to propagate, when a photon is detected, a signal that corresponds to the detection level from a fixed-voltage node to a node between the photon detection portion and the latch portion.

18. The photon detection circuitry of claim 1,wherein the photon detection portion includes a single-photon avalanche diode.Our ref.: 240288EPWOP 319. An image sensor, comprising:a plurality of photon detection circuitries, each including:a photon detection portion configured to set a path signal to a detection level when a photon is detected, the detection level indicating the detected photon, anda latch portion configured to change its state to a detection state when the path signal changes to the detection level, the detection state indicating the detected photon,wherein the latch portion is configured to inhibit a change of its state from the detection state to a reset state based on the path signal; anda logic portion configured to generate an image signal based on the state of the latch portions of the plurality of photon detection circuitries.

20. An electronic device, comprising:an image sensor, including:a plurality of photon detection circuitries, each including:a photon detection portion configured to set a path signal to a detection level when a photon is detected, the detection level indicating the detected photon, anda latch portion configured to change its state to a detection state when the path signal changes to the detection level, the detection state indicating the detected photon, wherein the latch portion is configured to inhibit a change of its state from the detection state to a reset state based on the path signal; anda logic portion configured to generate an image signal based on the state of the latch portions of the plurality of photon detection circuitries; anda processing portion configured to perform processing according to the generated image signal.

Images