Field effect device and method of manufacturing
The field effect transistor design with a 2D material active layer oriented transversally to the substrate addresses channel length limitations, enhancing integration and performance by minimizing process complexity and contact resistance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- IDEADED SL
- Filing Date
- 2025-12-23
- Publication Date
- 2026-07-02
Smart Images
Figure EP2025088947_02072026_PF_FP_ABST
Abstract
Description
IDEADED S.L. DECEMBER 23, 2025 P011WO P5610PC00FIELD EFFECT DEVICE AND METHOD OF MANUFACTURING
[0001] The present application claims the benefit of European patent application n° EP24383459.5 filed on December 24th, 2024. The present disclosure relates to field effect devices such as field effect transistors, and to methods of manufacturing the same.BACKGROUND
[0002] A field effect transistor (FET) comprises three main terminals: source, drain and gate. A fourth terminal is associated with the body or substrate but is commonly connected to the source, so that the FET is controlled as a three-terminal device. Current can flow from the source to the drain via a channel created in an active (e.g., semiconducting) material, the conductivity of which is controlled by the voltage applied to the gate.
[0003] Both source and drain are commonly arranged on a two-dimensional plane and formed on a surface of a substrate, thus providing a so-called planar transistor. The length of the channel is defined by the distance between the source and the drain. In order to modulate the conductivity of the channel, voltage is applied to a gate electrode, which is arranged in an area between the source and the drain, and which is separated from the active material forming the channel by means of a gate dielectric. Upon application of the voltage, current flows in the direction with no confinement between the source and the drain, i.e. parallel to the plane containing the channel.
[0004] The length of the channel influences the performance of the transistor in relation to different indicators such as speed or power. In particular, the switching speed of planar transistors can be increased by shrinking the channel, i.e. reducing the length of the channel. Nevertheless, the shrinking of conventional planar transistors has reached its physical limits. Indeed, short-channel effects, such as leakage current, and drain-induced barrier lowering or velocity saturation, can occur as the channel length becomes of the same order of magnitude as the depletion-layer widths of the source and drain junctions. As a result, the ability of the gate to properly control the flow of current in the channel is reduced.
[0005] Gate device architectures, such as FinFETs or Gate-AII-Around FETs allow channel length reduction to few nanometers. Nevertheless, the manufacturing processes involved are complex and require sophisticated techniques such as extreme ultraviolet lithography.Furthermore, these gate device architectures impose limits on the downscaling due to the mechanical and structural properties of the resulting structures.
[0006] In summary, the continued need for increased integration of field effect devices has resulted in a large number of transistor geometries and architectures using a range of different materials. There is still a need for a transistor design that preserves, or even improves, the performance of FET transistors while enabling even larger integration, leading to channel scaling towards the sub-nanometer scale. There is also a need for a corresponding manufacturing process.SUMMARY
[0007] In an aspect of the present disclosure, a field effect transistor (FET) is provided. The FET comprises a substrate and a first electrode arranged on the substrate and configured as either a source or a drain of the transistor. The FET further comprises a second electrode arranged on the substrate, configured as the other of the source and the drain of the transistor. An active layer is sandwiched between the first electrode and the second electrode, the active layer defining a channel of the transistor. The FET comprises a gate having a gate conductor portion and a gate insulating layer, the gate insulating layer being arranged between the gate conductor and the active layer. The active layer comprises a 2D material arranged with its plane substantially perpendicular or slanted to the substrate
[0008] According to this aspect, a FET with current flowing from the source to the drain through the active layer is provided. The direction of the current flow is substantially parallel to the substrate and predominantly perpendicular to the plane defined by the active layer. The channel length is determined by the width of the active layer. In other words, in the case of 2D materials, the current flows significantly transversally to the plane of the active layer made of a 2D material, i.e. current flows through the active layer rather than along the active layer. In particular, the current flow is substantially transversal to the plane defined by the 2D material in cases wherein the active layer is arranged with its plane substantially perpendicular to the substrate.
[0009] Transversal transport may thus be regarded as transport along a direction in which the respective material exhibits quantum confinement. The FET according to this aspect can increase integration of the number of transistors in a given area of a substrate while reducing the channel length.
[0010] In accordance with this aspect, the gate insulating layer is arranged between the gate conductor portion and the active layer so as to prevent direct contact between the gate conductor and the active layer i.e., the gate insulating layer forms a barrier between the gateconductor and the active layer. The gate insulating layer however does not prevent the active layer from experiencing the field effect.
[0011] Throughout the present disclosure, the term active material refers to a material whose conductivity can be actively modulated by, e.g. applying a voltage, so that a conducting channel can be created. In particular, said active material may comprise a semiconductor material. Accordingly, an active layer refers to a layer comprising such an active material.
[0012] Throughout the present disclosure the terms “sandwiching” and a “sandwich” structure may be used to refer to an arrangement in which the active layer is arranged between and directly adjacent to the two electrodes. Thus, throughout this disclosure, a sandwich arrangement is understood as meaning that the active layer extends over the overlapping region so as to prevent any direct contact between the electrodes.
[0013] Throughout the present disclosure, the arrangement of the first electrode and the second electrode on the substrate is not to be interpreted as limited to a direct arrangement. In particular, it is known that some surface treatments, in some cases involving the deposition of, e.g., protective layers, may be practiced on the substrate. Consequently, the arrangement of the electrodes on the substrate does not exclude embodiments in which a surface coating or the like is provided on the substrate.
[0014] In a further aspect of the disclosure, a method of manufacturing a field effect transistor is provided. The method comprises: providing a first electrode on a substrate; providing a second electrode on the substrate; and providing an active layer in between the first electrode and the second electrode, thus creating a sandwich structure. When providing the active layer, the active layer defines a plane that is substantially perpendicular or slanted to the substrate. The method further comprises forming a gate insulating layer on the active layer and forming a gate conductor on the gate insulating layer. The method further comprises forming electrical contacts for the first electrode, the second electrode and the gate.
[0015] It is understood that the method according to this further aspect of the disclosure is not limited to a precise sequence when providing the first electrode, second electrode, and active layer. Hence, in some examples, the method may comprise forming the first electrode on the substrate and, subsequently, forming the active layer. Then, the second electrode may be formed. Instead, in other alternatives, the first and second electrode may be first formed on the substrate and, subsequently, the active layer may be arranged in a space defined in between said first and second electrode.
[0016] According to examples of this further aspect of the disclosure, a method of manufacturing a FET with minimal or reduced process steps is provided. The method examplesallow channel downscaling and / or larger contact length between channel and source / drain electrodes, which reduces contact resistance and improved performance.BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Non-limiting examples of the present disclosure will be described in the following, with reference to the drawings, in which:Figures 1A - 1B schematically illustrates a side view of a field effect transistor according to an example of the disclosure;Figure 2 shows a flowchart illustrating a method for manufacturing a transistor according to an example of the disclosure; andFigure 3 shows a flowchart illustrating a further method for manufacturing a transistor according to another example of the disclosure.DETAILED DESCRIPTION OF EXAMPLES
[0018] Reference now will be made in detail to embodiments, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation only, not as a limitation. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure. For instance, features illustrated or described as part of one embodiment can be used with another embodiment to yield a still further embodiment. It is intended that the present disclosure covers such modifications and variations as come within the scope of the appended claims and their equivalents. Furthermore, drawings are intended to illustrate the different embodiments and manufacturing process. For the sake of clarity, dimensions of the different elements are not at scale to facilitate identification of the different components.
[0019] Figure 1A is a side view of an example of a field effect transistor 100 according to the disclosure. The field effect transistor 100 comprises a substrate 102, a first electrode 104 arranged on the substrate 102, and a second electrode 106 arranged on the substrate 102. The substrate 102 may be a silicon (Si) wafer but other substrates known in the art may also be employed, such as silicon germanium (SiGe) or a lll-V semiconductor wafer. Furthermore, the substrate 102 may comprise a surface coating or treatment.
[0020] Referring back to the electrodes, the first electrode 104 acts as either the source or the drain of the transistor 100 whereas the second electrode 106 acts as the other of the source and the drain of the transistor 100. Different conducting materials may be used for the first electrode 104 and the second electrode 106, including: metals, e.g., palladium (Pd), rhodium(Rh), molybdenum (Mo), scandium (Sc), gold (Au), platinum (Pt), tungsten (W), titanium (Ti); nitrides, e.g., titanium nitride (TiN); oxides, e.g., transparent conductive oxides (TCOs); 2D materials, e.g. graphene; or 1D materials, e.g., metallic carbon nanotubes. For example, this allows for a way of using different conductors for work function engineering for tuning electrical resistance at the contacts with an active layer 108. Therefore, the first electrode 104 and / or the second electrode 106 may comprise either a metal, or a semi-metal, or a 1D conductor, or a 2D conductor, or a doped semiconductor.
[0021] Between the first electrode 104 and the second electrode 106, it is arranged the active layer 108. In the example of figure 1A, the active layer 108 is also arranged on the substrate 102. Therefore, as shown in figure 1A, the active layer 108 is sandwiched between the first electrode 104 and the second electrode 106. The active layer 108 acts as the channel of the field effect transistor 100, whose channel length is then dependent on the width of the active layer 108.
[0022] Particularly, the active layer 108 comprises a two-dimensional (2D) material. Throughout the present disclosure, 2D materials may be regarded as crystalline materials consisting of single- or few-layer atoms. In 2D materials, two dimensions are outside the nanoscale.
[0023] The active layer 108 is made of 2D materials which include, e.g., graphene, nanofilms, nanolayers, nano-coatings, and transition metal dichalcogenide materials. In some examples, transition metal dichalcogenide materials may comprise a MX2 material wherein the M is a transition-metal and the X is a chalcogen. In some examples, the MX2 material may be selected from at least one of the following: M0S2, WeS2 or WS2.
[0024] In some examples, the active layer 108 may comprise a stack of 2D material sheets of any aforementioned material.
[0025] In some examples, the active layer 108 may comprise a plurality of sub-layers. In some of these examples, at least one sub-layer of the at least two sub-layers forming the active layer 108 may comprise a different active material.
[0026] In 2D materials, motion is not confined in the two directions defining the plane of the active layer 108 made of the 2D material. However, motion in the perpendicular direction of the plane defined by the active layer 108, as the one resulting from the present disclosure, exhibits quantum confinement so that it corresponds to transversal transport. Accordingly, the length of the channel in the present disclosure is characterized by the width of the active layer 108 between the first electrode 104 and the second electrode 106.
[0027] Figure 1B is a side view of an example of a field effect transistor 100 according to the disclosure. Figure 1B represents the field effect transistor 100 represented in figure 1A. Figure 1B illustrates that a plane AA’ 114 defined by the active layer 108 is perpendicular or slanted to the substrate 102. Particularly, the plane AA’ 114 is perpendicular or slanted to a plane BB’ 116 defined by the substrate 102.
[0028] In some examples, the plane AA’ 114 defined by the active layer 108 may be angled between 45 degrees and 135 degrees with respect to the plane BB’ 116 defined by the substrate 102. Particularly, the plane AA’ 114 defined by the active layer 108 may be angled between 80 degrees and 120 degrees with respect to the plane BB’ 116 defined by the substrate 102.
[0029] In any case, transport occurs significantly in the direction with confinement of the active layer 108, i.e. transport occurs at least partially in the out-of-plane direction with respect to the plane of the active layer. Specifically, transport occurs substantially in the direction with confinement of the active layer 108, i.e., in the direction transversal to the plane defined by the 2D material, in cases wherein the active layer 108 is substantially perpendicular to the substrate. On the other hand, when the active layer 108 is not perpendicular but slanted, transport still occurs with a significant component in the out-of-plane or transversal direction with respect to the plane defined by the 2D material. Consequently, in the example depicted in Figure 1B, the motion is in the perpendicular direction with respect to the plane AA’ 114 defined by the active layer 108. As a result, the transport in this field effect transistor 100 is transversal.
[0030] Referring back to figure 1A, a gate insulating layer 110 is arranged in contact with the active layer 108. The gate insulating layer 110 may be made of a material with a high dielectric constant. Thus, silicon dioxide SiC>2, silicon oxynitride SiOxNyA, or high-K materials (e.g. hafnium oxide HfC>2, aluminum oxide AI2O3, hafnium silicon oxynitride HfSiON, zirconia ZrC>2, lanthanum oxide La2Os, tantalum oxide Ta2Os, titanium dioxide TiC>2, barium titanate BaTiCh) may be used.
[0031] A gate conductor portion 112 is arranged on the gate insulating layer 110. Therefore, the gate insulating layer 110 is arranged between the gate conductor portion 112 and the active layer 108. Similarly to the first electrode 104 and / or the second electrode 106, the gate conductor portion 112 may comprise either a metal, or a semi-metal, or a 1D conductor, or a 2D conductor, or a doped semiconductor. The gate conductor portion 112 is deposited (i.e., formed or grown) on top of the gate insulating layer 110 so that direct contact between the gate conductor portion 112 and any of the electrodes, 102 and 104, or the active layer 108 is prevented. The application of a certain voltage to the gate conductor portion 112 determinesthe current flow between the first electrode 104 and the second electrode 106 via the active layer 108.
[0032] As shown in figure 1A, the gate insulating layer 110 and the gate conductor portion 112 forms a gate of the field effect transistor 100. In some examples, the gate may be at least partially arranged on the first electrode 104 and the active layer 108. In some other examples, the gate may be arranged on the first electrode 104, the second electrode 106, and the active layer 108.
[0033] Not shown in figure 1A or figure 1 B, three contacts defining the three terminals of the transistor may be provided. In particular, a first source / drain contact may be used to contact the first electrode 104, a second source / drain contact may be used for the second electrode 106, and a third contact may be used for the gate conductor portion 112. Similarly to the electrodes, different materials may also be used for the contacts. These materials comprise metals, e.g., palladium (Pd), rhodium (Rh), molybdenum (Mo), scandium (Sc), gold (Au), platinum (Pt), tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni); nitrides, e.g., titanium nitride (TiN), tantalum nitride (TaN); binary alloys; 1D materials, e.g., metallic carbon nanotubes; or conductive 2D materials, e.g. graphene.
[0034] By disposing two field effect transistors 100 according to the description referring to figure 1A and 1B, a semiconducting structure may be obtained. For example, the second field effect transistor may be disposed either on top or on a side of the first field effect transistor. In some examples, the first field effect transistor may be either a P-type or N-type transistor and the second field effect transistor may be the other of a P-type and N-type transistor. By arranging the two field effect transistors, further size reduction may be obtained for complementary configurations.
[0035] Figure 2 shows a flowchart illustrating a method for manufacturing a field effect transistor 100 according to an example of the disclosure.
[0036] The method 200 comprises forming a first electrode on a substrate in block 202. The substrate may be a silicon (Si) wafer but other substrates may also be employed, such as silicon germanium (SiGe) or a lll-V semiconductor wafer. Furthermore, the substrate may comprise a dielectric layer such as a thermally grown oxide. Alternatively, a dielectric layer may be deposited with standard deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.
[0037] As already mentioned with reference to figure 1A or figure 1B, different materials may be used for the first electrode. The selection of one material or another may also impact on the technique used for its formation. Lithography along with lift-off and / or etching basedprocesses as well as additive methods can be used for desired pattern shaping. In some examples, the substrate may first be patterned by means of a photolithography and dry etching step. Subsequently, the material for the first electrode may be deposited (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.). Afterwards, a chemical mechanical planarization (CMP) process may be used to obtain a smooth surface and remove necessary amount of material.
[0038] Block 204 comprises providing a second electrode on the substrate. Similar materials and techniques as those already mentioned with respect to the first electrode and mentioned with reference to figure 1A or figure 1B, may be used for the second electrode.
[0039] The method 200 shown in Figure 2 also comprises providing an active layer in block 206. The active layer is provided between the first electrode and the second electrode. At this stage of the manufacturing process, a sandwich structure is formed with the first electrode at a first side, the second electrode at an opposing side facing the first side, and the active layer in between the first electrode and the second electrode. The active layer comprises a 2D material and it defines a plane that is substantially perpendicular or slanted to the substrate. Particularly, the active layer may comprise a transition metal dichalcogenide material. More specifically, the transition metal dichalcogenide material may comprise a MX2material wherein the M is a transition-metal and the X is a chalcogen. In these examples, the MX2material may be selected from at least one of the following: MoS2, WeS2or WS2.
[0040] The selection of the most appropriate material depends on whether the transistor is intended to have P-type or N-type character. In that sense, different processes such as doping, annealing or other kind of known manipulations may be used to alter the active layer so as to vary its character. Said 2D materials may be grown via, e.g., chemical vapor deposition (CVD) or atomic layer deposition (ALD), transferred, spin coating deposited, chemical deposition by dip coating etc. The 2D materials are arranged with their plane substantially perpendicular or slanted to the substrate, such that current flows, at least partially, along the width of the active layer made of the 2D materials, i.e., transversally to the plane of the active layer.
[0041] In some examples, forming or depositing the active layer may comprise forming or depositing a plurality of sub-layers so as to achieve the desired transistor properties. In some of these examples, depositing a plurality of sub-layers may comprise depositing at least two sub-layers where at least one sub-layer of the at least two sub-layers comprises a different active material. Furthermore, the combination of active materials may vary for other examples and, for instance, active layers may comprise sub-layers with different types of semiconductors but with similar geometry such as a stack of 2D material sub-layers comprising a combination of, e.g., MOS2and WS2sub-layers.
[0042] Block 208 comprises providing a gate insulating layer on the active layer. The gate insulating layer may comprise different materials such as, but not limited to, silicon oxide, aluminum oxide AI2O3, titanium dioxide TiC>2, tantalum oxide Ta2Os, yttrium oxide, silicon oxynitride SiOxNyA, silicon nitride, boron nitride, zirconium silicon oxide, hafnium silicon oxide, zirconium oxide, lanthanum oxide La20s, or high-K materials (e.g. HfC>2, HfSiC>4 or CUSiZr). Depending on the selected material, the gate insulating layer may be formed with standard techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, or atomic layer deposition (ALD) as known by those skilled in the art.
[0043] In some examples, the method 200 may further comprise removing material from those areas extending beyond the borders of a gate region, i.e. , footprint of the to-be-formed gate of the field effect transistor. For that purpose, an etching, and a chemical mechanical planarization (CMP) process may be used.
[0044] Block 210 comprises forming a gate conductor on the gate insulating layer such that the gate insulating layer is arranged between the gate conductor and the active layer. Similarly to the first electrode and / or the second electrode, the gate conductor may comprise either a metal, or a semi-metal, or a 1D conductor, or a 2D conductor, or a doped semiconductor. The material for the gate conductor may be deposited, e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). After forming or depositing the gate conductor, a chemical mechanical planarization (CMP) process may be used to obtain a smooth surface and remove necessary amount of material.
[0045] Block 212 comprises forming electrical contacts for the first electrode, the second electrode, and the gate conductor. Contact material may be deposited to create a first electrode contact, a second electrode contact and a gate conductor contact. In this case, although not shown in the flowchart of figure 2, the contact material may be deposited over the whole surface and then selectively removed from the areas not aligned with the electrodes and with the gate by means of a chemical mechanical planarization (CMP) process. Multiple contact material stacks may be used, such as barrier layer (TiN, Ti) by PVD or ALD and subsequent material (such as but not limited to Al; Cu; W by ALD, PVD or CVD; 2D or 1D by CVD; or coating like deposition). Other conductors such as ruthenium oxide, tantalum nitride may be also employed.
[0046] Although Figure 2 represents a certain number of blocks, the method 200 is not limited to a precise sequence. In particular, it is not limited to a precise sequence while providing the first electrode, second electrode, and the active layer.
[0047] In that sense, Figure 3 shows a variant in which the active layer is deposited on the first electrode, and the second electrode is subsequently deposited on the active layer. Specifically, the method 300 according to this variant comprises, in block 302, forming a first electrode on a substrate. For this first block, similar considerations to those indicated above for block 202 of method 200 (see Figure 2) may apply.
[0048] Then, the method 300 according to this variant comprises, in block 304, forming an active layer. The active layer comprises a 2D material and it defines a plane that is substantially perpendicular or slanted to the substrate. The same considerations, e.g. in terms of the materials used, as those already described with reference to block 206 of method 200 may apply.
[0049] Block 306 then comprises forming or depositing a second electrode on the active layer. Similar materials and techniques as those already mentioned with respect to the first electrode, may be used for the second electrode. At this stage of the manufacturing process, a sandwich structure is created with the first electrode at a first vertical side, the second electrode at an opposing side facing the first vertical side, and the active layer in between the first electrode and the second electrode.
[0050] In some examples, after forming the second electrode on the active layer, the method 300 may comprise e.g., photolithography and / or dry etching to define an area of the field effect transistor. Etch masks may be used to facilitate etching as known by those skilled in the art. In particular, the dimensions of the active layer and of the electrodes may be selected. Consequently, shape and dimensions of an overlapping region of the sandwich structure may be selected, i.e., a region where the second electrode overlaps the first electrode. This overlapping region defines an outer overlapping perimeter.
[0051] Block 308 comprises forming or depositing a gate insulating layer on the active layer. Block 308 may be equivalent to previously described block 208 so not further details will be provided here.
[0052] In some examples, the method 300 may further comprise removing material from those areas extending beyond the borders of a gate region, i.e., footprint of the to-be-formed gate of the field effect transistor. For that purpose, an etching, and a chemical mechanical planarization (CMP) process may be used.
[0053] In a similar manner as block 210 of method 200, block 310 of method 300 comprises forming a gate conductor on the gate insulating layer such that the gate insulating layer is arranged between the gate conductor and the active layer.
[0054] Subsequently, block 312 comprises forming electrical contacts for the first electrode, the second electrode, and the gate conductor. Similar considerations to those already described with reference to block 212 of method 200 may be equally applicable to block 312 of this method 300.
[0055] FETs in examples of the present disclosure exhibit a current flow, which is particularly advantageous for stacking in complementary circuits comprising at least one P-type transistor and one N-type transistor. By arranging the two transistors side by side, further size reduction becomes feasible for complementary configurations. Nevertheless, it is understood that further examples may be envisaged where a P-type FET and an N-type FET may also be arranged in a vertical arrangement, i.e. with a first FET arranged on top of a second FET.
[0056] For the sake of clarification, and even if most examples comprising 2D materials have been described, examples comprising 2D materials are not to be understood as limited to specific 2D materials and it should be clear that different materials such as graphene, M0S2 or WS2 may be used in different variants.
[0057] Particularly, the method 200 may further comprise: providing a step edge, e.g., 300 nm etched from the substrate, and providing a HfC>2 coating on a side wall of the provided step edge, which allows formation or deposition of the active layer.
[0058] The HfC>2 coating may be obtained via atomic layer deposition (ALD) and anisotropic dry etching. HfC>2 coating may support the deposition of the 2D material (e.g., M0S2 and WS2) forming the active layer.
[0059] In this example, subsequent to the deposition of the active layer, the deposition of the first electrode, and the deposition of the second electrode, wet etching may be used to remove the step edge. As a result, a sandwich structure comprising the electrodes and the active layer may be obtained.
[0060] For reasons of completeness, various aspects of the present disclosure are set out in the following numbered clauses:Clause 1. A field effect transistor, comprising:a substrate;a first electrode on the substrate and configured as either a source or a drain of the transistor;a second electrode on the substrate and configured as the other of the source and the drain of the transistor,an active layer sandwiched between the first electrode and the second electrode, the active layer defining a channel of the transistor; anda gate having a gate conductor portion and a gate insulating layer, the gate insulating layer being arranged between the gate conductor portion and the active layer,wherein the active layer comprises a 2D material arranged with its plane substantially perpendicular or slanted to the substrate.Clause 2. The field effect transistor according to claim 1 , wherein the plane defined by the active layer is angled between 45 degrees and 135 degrees with respect to a plane defined by the substrate, specifically the plane defined by the active layer is angled between 80 degrees and 120 degrees with respect to a plane defined by the substrate.Clause 3. The field effect transistor according to clause 1 or clause 2, wherein the gate is at least partially arranged on the first electrode and the active layer.Clause 4. The field effect transistor according to any of clauses 1 to 3, wherein the gate is at least partially arranged on the second electrode and the active layer.Clause 5. The field effect transistor according to any of clauses 1 to 4, wherein the active layer comprises a transition metal dichalcogenide material, and specifically the transition metal dichalcogenide material comprises a MX2material wherein the M is a transition-metal and the X is a chalcogen.Clause 6. The field effect transistor according to clause 5, wherein the active layer comprises a MX2material, and wherein the MX2material is selected from at least one of the following: MoS2, WeS2or WS2.Clause 7. The field effect transistor according to any of clauses 1 to 6 wherein the active layer comprises a stack of 2D material sheets.Clause 8. The field effect transistor according to any of clauses 1 to 7, wherein the active layer comprises a plurality of sub-layers.Clause 9. The field effect transistor according to clause 8, wherein at least one sub-layer of the at least two sub-layers comprises a different active material.Clause 10. The field effect transistor according to any of clauses 1 to 9, wherein the first electrode and / or the second electrode comprises either a metal, or a semi-metal, or a 1D conductor, or a 2D conductor, or a doped semiconductor.Clause 11. The field effect transistor according to any of clauses 1 to 10, wherein the gate conductor portion comprises at least one of a metal, or a semi-metal, or a 1D conductor, or a 2D transition metal dichalcogenide, or a doped semiconductor.Clause 12. A semiconducting structure comprising a first field effect transistor according to any of clauses 1 to 11 and a second field effect transistor according to any of clauses 1 to 11, the second field effect transistor being disposed on top of the first field effect transistor.Clause 13. A semiconducting structure comprising a first field effect transistor according to any of clauses 1 to 11 and a second field effect transistor according to any of clauses 1 to 11, the second field effect transistor being disposed on a side of the first field effect transistor. Clause 14. The semiconducting structure according to clause 12 or clause 13, wherein the first field effect transistor is either a P-type or N-type transistor and the second field effect transistor is the other of a P-type and N-type transistor.Clause 15. A method of manufacturing a field effect transistor, specifically a field effect transistor according to any of clauses 1 to 14, the method comprising:forming or depositing a first electrode on a substrate;forming or depositing a second electrode on the substrate;forming or depositing an active layer between the first electrode and the second electrode, the active layer defining a plane that is substantially perpendicular or slanted to the substrate;forming or depositing a gate insulating layer on the active layer;forming or depositing a gate conductor on the gate insulating layer, the gate insulating layer being arranged between the gate conductor and the active layer; and forming electrical contacts for the first electrode, the second electrode and the gate conductor.Clause 16. The method of manufacturing a field effect transistor according to clause 15, wherein depositing an active layer comprises depositing a 2D material.Clause 17. The method of manufacturing a field effect transistor according to clause 15 or 16, wherein the active layer comprises a transition metal dichalcogenide material, and specifically the transition metal dichalcogenide material comprises a MX2material wherein the M is a transition-metal and the X is a chalcogen.Clause 18. The method of manufacturing a field effect transistor according to clause 17, wherein the active layer comprises a MX2material, and wherein the MX2material is selected from at least one of the following: MoS2, WeS2or WS2.Clause 19. A method of manufacturing a field effect transistor according to any of clauses 15 to 18, wherein depositing an active layer comprises depositing a plurality of sub-layers. Clause 20. A method of manufacturing a field effect transistor according to clause 19, wherein depositing a plurality of sub-layers comprises depositing at least two sub-layers and wherein at least one sub-layer of the at least two sub-layers comprises a different active material.Clause 21. A method of manufacturing a semiconducting structure comprising manufacturing of a first field effect transistor according to the method of any of clauses 15 to 20 and manufacturing a second field effect transistor either on top or on a side of the first field effect transistor.
[0061] This written description uses examples to disclose the teaching, including the preferred embodiments, and also to enable any person skilled in the art to practice the teaching, including making and using any devices or systems and performing any incorporated methods. The patentable scope is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims. Aspects from the various embodiments described, as well as other known equivalents for each such aspects, can be mixed and matched by one of ordinary skill in the art to construct additional embodiments and techniques in accordance with principles of this application. If reference signs related to drawings are placed in parentheses in a claim, they are solely for attempting to increase the intelligibility of the claim, and shall not be construed as limiting the scope of the claim.
Claims
CLAIMS1. A field effect transistor, comprising:a substrate;a first electrode on the substrate and configured as either a source or a drain of the transistor;a second electrode on the substrate and configured as the other of the source and the drain of the transistor;an active layer sandwiched between the first electrode and the second electrode; the active layer defining a channel of the transistor; anda gate having a gate conductor portion and a gate insulating layer, the gate insulating layer being arranged between the gate conductor portion and the active layer;wherein the active layer comprises a 2D material arranged with its plane substantially perpendicular or slanted to the substrate.
2. The field effect transistor according to claim 1 , wherein the plane defined by the active layer is angled between 45 degrees and 135 degrees with respect to a plane defined by the substrate, specifically between 80 degrees and 120 degrees with respect to a plane defined by the substrate.
3. The field effect transistor according to claim 1 or claim 2, wherein the gate is at least partially arranged on the first electrode and the active layer.
4. The field effect transistor according to any of claims 1 to 3, wherein the gate is arranged on the first electrode, the second electrode, and the active layer.
5. The field effect transistor according to any of claims 1 to 4, wherein the active layer comprises a transition metal dichalcogenide material, and specifically the transition metal dichalcogenide material comprises a MX2 material wherein the M is a transition-metal and the X is a chalcogen.
6. The field effect transistor according to claim 5, wherein the active layer comprises a MX2 material, and wherein the MX2 material is selected from at least one of the following: M0S2, WeS2or WS2.
7. The field effect transistor according to any of claims 1 to 6 wherein the active layercomprises a stack of 2D material sheets.
8. The field effect transistor according to any of claims 1 to 7, wherein the active layer comprises a plurality of sub-layers.
9. The field effect transistor of claim 8, wherein the active layer comprises at least two sub-layers and wherein at least one sub-layer of the at least two sub-layers comprises a different active material.
10. The field effect transistor according to any of claims 1 to 9, wherein at least one of the first electrode, the second electrode, or the gate conductor portion comprises either a metal, or a semi-metal, or a 1 D conductor, or a 2D conductor, or a doped semiconductor.
11. A semiconducting structure comprising a first field effect transistor according to any of claims 1 to 10 and a second field effect transistor according to any of claims 1 to 10, the second field effect transistor being disposed either on top or on a side of the first field effect transistor.
12. The semiconducting structure of claim 11, wherein the first field effect transistor is either a P-type or N-type transistor and the second field effect transistor is the other of a P-type and N-type transistor.
13. A method of manufacturing a field effect transistor according to any of claims 1 to 12, the method comprising:providing a first electrode on a substrate;providing a second electrode on the substrate;providing an active layer between the first electrode and the second electrode, thus forming a sandwich structure, the active layer comprising a 2D material and the active layer defining a plane that is substantially perpendicular or slanted to the substrate; providing a gate insulating layer on the active layer;providing a gate conductor on the gate insulating layer, the gate insulating layer being arranged between the gate conductor and the active layer; andproviding electrical contacts for the first electrode, the second electrode and the gate conductor.
14. The method of manufacturing a field effect transistor according to claim 13, wherein the 2D material comprises a transition metal dichalcogenide material, and specifically the transition17metal dichalcogenide material comprises a MX2 material wherein the M is a transition-metal and the X is a chalcogen.
15. The method of manufacturing a field effect transistor according to claim 13 or claim 14, wherein the active layer comprises at least two sub-layers, and wherein at least one sub-layer of the at least two sub-layers comprises a different active material.