Semiconductor device

Abstract

Provided is a novel semiconductor device. This semiconductor device has: a first processing region configured to perform a multiply-accumulate operation using digital data; and a second processing region configured to perform a multiply-accumulate operation using analog data, the second processing region having a function of converting input digital data into analog data and a function of converting, into digital data, a result of the multiply-accumulate operation performed using the analog data. Arithmetic processing for which operation speed or operation accuracy is prioritized is performed in the first processing region, and other arithmetic processing is performed in the second processing region.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to objects, methods of operation, or methods of manufacturing. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, energy storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, computing devices (including processors), electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for testing them.

[0003] In recent years, the use of artificial intelligence (AI) has been explored for a variety of applications. Examples of AI types include discriminative AI such as image recognition and speech recognition, executive AI such as machine control and autonomous driving, and generative AI such as text generation and image generation, which are used according to their applications. For example, in applications such as image recognition, an artificial neural network model is used to repeatedly multiply image data by weight coefficients called filters (also known as connection strengths) and add them up (sum-accumulate operation), thereby detecting the features of the image data.

[0004] The multiply-accumulate operation is a frequently used arithmetic operation in digital circuits. Performing the multiply-accumulate operation using digital circuits enables highly accurate and high-speed arithmetic processing. On the other hand, it requires a huge amount of processing, which tends to increase power consumption. To suppress the increase in power consumption, various methods have been proposed that convert digital data to analog data and perform the arithmetic operation using analog circuits. Patent document 1 discloses an arithmetic circuit that can simultaneously perform nonlinear conversion operations and weighting operations.

[0005] In recent years, transistors incorporating oxide semiconductors in the channel formation region have attracted attention. For example, In ２ O ３ Its use in thin-film transistors has been reported (Non-Patent Document 1). Transistors with oxide semiconductors in the channel formation region have the characteristic of very low off-current and are expected to be applied to semiconductor devices such as memory devices, display devices, and arithmetic units.

[0006] Japanese Patent Publication No. 2004-110421

[0007] Dhananjay and C. W. Chu, “Realization of In2O3 thin film transistors through reactive evaporation process.” Appl. Phys. Lett. 91, 132111 (2007). Takashi Koida, “High-mobility transparent conductive film,” National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0008] Using analog circuits allows for more power-efficient computation than digital circuits. On the other hand, it is said that achieving high accuracy and high speed in analog circuits is more difficult compared to digital circuits. For example, in digital circuits, simple inference tends to consume a lot of power and have low computational efficiency. Also, in analog circuits, when performing AI calculations that require high accuracy, processing time tends to be long and the accuracy rate tends to be low.

[0009] One aspect of the present invention aims to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention aims to provide a semiconductor device with high computation speed. Alternatively, one aspect of the present invention aims to provide a semiconductor device that achieves high-precision computation. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device.

[0010] Note that the problems of one aspect of the present invention are not limited to the above problems. The above problems do not prevent the existence of other problems. Note that other problems are those not mentioned in this item as described below. Problems not mentioned in this item can be derived from the descriptions in the specification, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one aspect of the present invention solves at least one of the above problems and other problems, and does not need to solve all of the above problems and other problems.

[0011] One aspect of the present invention is a semiconductor device capable of selecting an analog circuit and a digital circuit used for arithmetic processing according to the scale of AI arithmetic. A configuration example of the semiconductor device will be described below.

[0012] (1) One aspect of the present invention is a semiconductor device having a first processing region and a second processing region. The first processing region has a function of performing a first arithmetic processing using first digital data. The second processing region has a first function of generating first analog data from second digital data, a second function of generating second analog data from third digital data, a function of generating third analog data by second arithmetic processing using the first analog data and the second analog data, and a third function of generating fourth digital data from the third analog data. Note that each of the first arithmetic processing and the second arithmetic processing includes a sum-of-products arithmetic processing and a function arithmetic processing.

[0013] (2) Alternatively, one aspect of the present invention may be configured to have an arithmetic processing control unit. In particular, it is preferable that the arithmetic processing control unit has a function of selecting one of the first arithmetic processing performed in the first processing region and the second arithmetic processing performed in the second processing region according to the content of the arithmetic to be processed.

[0014] (3) In one aspect of the present invention, the configuration in (2) above may include a storage unit. In particular, the storage unit preferably has a plurality of storage cells that hold first digital data, second digital data, third digital data, and fourth digital data. Furthermore, the second processing area preferably includes a digital-to-analog conversion unit, a multiply-accumulate unit, an arithmetic unit, and an analog-to-digital conversion unit. Furthermore, the multiply-accumulate unit preferably has a plurality of arithmetic cells that hold first analog data.

[0015] The digital-to-analog conversion unit preferably has a first function and a second function. Furthermore, the sum-of-accumulate unit preferably has a function that performs sum-of-accumulate calculations using the first analog data and the second analog data with a plurality of calculation cells. Furthermore, the calculation unit preferably has a function that performs function calculations using the results of the sum-of-accumulate calculations performed by the sum-of-accumulate unit. Furthermore, the analog-to-digital conversion unit preferably has a third function.

[0016] (4) Alternatively, in one aspect of the present invention, in (3) above, the plurality of calculation cells of the sum-accumulate unit may be provided in the storage unit. In particular, it is preferable that each of the plurality of calculation cells and the plurality of storage cells has one selected from an inverter loop, a transistor with a floating layer, a capacitive element, a resistive switching element, a magnetic tunnel junction element, a ferroelectric capacitor, and a phase-change memory as a circuit or circuit element for holding data.

[0017] (5) Alternatively, in one aspect of the present invention, in (3) above, each of the plurality of arithmetic cells has one selected from an inverter loop, a transistor with a floating layer, a capacitive element, a resistive switching element, a magnetic tunnel junction element, and a phase change memory as a circuit or circuit element for holding data, and each of the plurality of storage cells has one selected from an inverter loop, a transistor with a floating layer, a capacitive element, a resistive switching element, a magnetic tunnel junction element, and a phase change memory as a circuit or circuit element for holding data.

[0018] (6) Alternatively, in one aspect of the present invention, in (4) or (5) above, the plurality of arithmetic cells may be configured to have transistors. In particular, the transistors preferably have an oxide semiconductor in the channel formation region, and the oxide semiconductor preferably contains indium.

[0019] In the configuration described in (1) above, AI calculations are performed by digital circuits in the first processing area, and AI calculations are performed by analog circuits in the second processing area. In one aspect of the present invention, by using the configuration described in (1) above, it is possible to select between digital circuits and analog circuits as the circuits used for calculation processing, depending on the scale of the AI ​​calculations.

[0020] Furthermore, as described in (4) above, by providing a multiply-accumulate unit in the memory unit, the circuit area of ​​the semiconductor device can be reduced. This makes it possible to miniaturize electronic devices equipped with semiconductor devices.

[0021] According to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a high processing speed can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that achieves high-precision processing can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0022] Furthermore, the effects of one aspect of the present invention are not limited to the effects described above. The effects described above do not preclude the existence of other effects. Other effects are those described below, which are not mentioned in this section. Effects not mentioned in this section can be derived by those skilled in the art from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Furthermore, one aspect of the present invention has at least one of the effects described above and other effects. Accordingly, one aspect of the present invention may, in some cases, not have the effects listed above.

[0023] Figures 1A and 1B are block diagrams showing example configurations of semiconductor devices. Figure 2 is a block diagram showing example configurations of semiconductor devices. Figure 3 is a timing chart showing an example of operation of a semiconductor device. Figure 4 is a block diagram showing example configurations of semiconductor devices. Figure 5 is a block diagram showing example configurations of circuits included in a semiconductor device. Figure 6 is a block diagram showing example configurations of semiconductor devices. Figure 7 is a block diagram showing example configurations of semiconductor devices. Figure 8 is a circuit diagram showing an example configuration of a processing area provided in a semiconductor device. Figure 9 is a circuit diagram showing an example configuration of a processing area provided in a semiconductor device. Figure 10 is a block diagram showing an example configuration of a processing area provided in a semiconductor device. Figures 11A, 11B, 11C, 11D, 11E, and 11F are circuit diagrams showing example configurations of arithmetic cells included in a processing area. Figure 12 is a block diagram illustrating an example configuration of a processing area provided in a semiconductor device. Figures 13A and 13B are block diagrams illustrating example configurations of circuits included in a processing area. Figures 14A and 14B are block diagrams illustrating example configurations of circuits included in a processing area. Figure 15A is a block diagram illustrating an example of a memory circuit configuration, and Figures 15B and 15C are circuit diagrams illustrating an example of a memory cell configuration. Figures 16A, 16B, 16C, 16D, 16E, and 16F are circuit diagrams illustrating an example of a memory cell configuration. Figure 17 is a schematic cross-sectional view showing an example of a processing region configuration. Figure 18 is a schematic cross-sectional view showing an example of a transistor configuration included in the processing region. Figures 19A and 19B are schematic cross-sectional views showing an example of a transistor configuration included in the processing region. Figure 20A is a schematic plan view showing an example of a transistor configuration included in the processing region, and Figures 20B and 20C are schematic cross-sectional views showing an example of a transistor configuration included in the processing region. Figure 21 is a schematic perspective view showing an example of a transistor configuration included in the processing region. Figures 22A and 22B illustrate the carrier concentration dependence of Hall mobility. Figure 22C is a cross-sectional view illustrating an indium oxide film. Figures 23A, 23B, 23C, and 23D show examples of electronic components. Figure 24 shows an example of an information processing system. Figure 25 shows an example of space equipment.

[0024] (Notes relating to this specification) In this specification, a semiconductor device is a device that utilizes semiconductor properties, and refers to a circuit containing semiconductor elements (e.g., transistors, diodes, and photodiodes), or a device having such a circuit. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor properties. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component in which a chip is housed in a package. Furthermore, for example, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may be semiconductor devices themselves or may have semiconductor devices.

[0025] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0026] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0027] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0028] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0029] Even if independent components are shown connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a "wire" also functions as an "electrode," a single conductive film possesses the functions of both a "wire" and an "electrode." Similarly, if part of a "wire" also functions as a "terminal," a single conductive film possesses the functions of both a "wire" and a "terminal." Therefore, it can be said that two or more components selected from "electrodes," "wires," and "terminals" are formed as a single unit. Furthermore, the terms "electrode," "wire," or "terminal" may be replaced with the term "region" depending on the context. Consequently, in this specification, connection includes cases where a single conductive film possesses the functions of multiple components.

[0030] The switches described herein are described as having the function of being in an ON or OFF state and controlling whether or not to allow current to flow, or having the function of selecting and switching the path through which current flows.

[0031] Furthermore, in this specification, "conductive state" means a state in which current can flow between two input / output terminals, and "non-conductive state" means a state in which the two input / output terminals can be considered electrically disconnected. Also, in this specification, the ON state of a switch falls under the category of "conductive state," and the OFF state of a switch falls under the category of "non-conductive state." For this reason, in this specification, "conductive state" and "ON state" are interchangeable with each other, and "non-conductive state" and "OFF state" are interchangeable with each other.

[0032] Furthermore, in this specification, the terms "conductive" or "conductive state" used when conductive layers are in direct contact with each other refer, for example, to a state in which an electric current can flow between the conductive layers.

[0033] Furthermore, a switch may have two or more terminals for conducting current, in addition to its control terminals. Examples include electrical switches and mechanical switches. In other words, a switch is not limited to a specific type, as long as it has the function of controlling current.

[0034] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. An example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and the movement of these electrodes controls the on and off states.

[0035] In this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the switching between the conductive and non-conductive states of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel or p-channel) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain may be interchangeable. In this specification, when describing the connection relationships of a transistor, the notations "one of the source and drain" and "the other of the source and drain" are used. In this specification, one of the source and drain may be referred to as the "first electrode of the transistor" or "first terminal of the transistor," and the other of the source and drain may be referred to as the "second electrode of the transistor" or "second terminal of the transistor." Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this specification, one of the gate or back gate of a transistor may be referred to as the first gate, and the other of the gate or back gate of a transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Also, if a transistor has three or more gates, each gate may be referred to as the first gate, second gate, third gate, and so on.

[0036] For example, one example of a transistor described herein may include a multi-gate transistor with two or more gate electrodes. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure where multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-current and improve the transistor's breakdown voltage (improve reliability). Alternatively, the multi-gate structure allows for the acquisition of an Id-Vds characteristic where, when operating in the saturation region of the Id (source-drain current)-Vds (drain-source voltage) characteristic, the current between the drain and source does not change much even when the voltage between the drain and source changes, resulting in a flat slope. By utilizing the Id-Vds characteristic in this region, an ideal current source circuit or an active load with a very high resistance can be realized. As a result, a differential circuit or current mirror circuit with good characteristics can be realized.

[0037] Generally, the threshold voltage of a transistor is the voltage located between the subthreshold region (weak inversion region) and the strong inversion region, and can also be described as the voltage at which the switching between the subthreshold region and the strong inversion region occurs. One example of a method for measuring the threshold voltage is to use the Id (source-drain current) - Vgs (gate-source voltage) characteristic as a basis for measuring the Id １／２ - Plot the Vgs characteristics and Id １／２ -Id on the tangent line where the slope of the Vgs characteristic is maximum １／２ One method is to use the Vgs value where = 0 as the threshold voltage. Another example is an Id-Vgs characteristic with a drain potential of 1.2V, where Id = 1.0 × 10 −１２ One method is to use Vgs, which is A, as the threshold voltage.

[0038] Furthermore, in this specification, operation in the subthreshold region of a transistor includes cases where the gate-source voltage of the transistor is lower than the threshold voltage, and more preferably, cases where the drain current of the transistor increases exponentially with respect to the gate-source voltage. In this case, the gate potential, source potential, and drain potential supplied to the transistor are also included in cases where they are appropriately supplied as potentials within the range in which the transistor operates in the subthreshold region.

[0039] Furthermore, in this specification, the subthreshold region refers to the region in the graph showing the Id-Vgs characteristic of a transistor where Vgs is lower than the threshold voltage. Alternatively, the subthreshold region refers to the region where current flows due to carrier diffusion, deviating from the gradient dual-channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to the region where Id increases exponentially with increasing Vgs. Alternatively, the subthreshold region includes regions that can be considered as the regions described in each of the above explanations.

[0040] Furthermore, in this specification, the source-drain current when a transistor operates in the subthreshold region is referred to as the subthreshold current. The subthreshold current increases exponentially with respect to the gate-source voltage, regardless of the drain potential.

[0041] Furthermore, generally speaking, the off-current in a transistor sometimes refers to the source-drain current that flows when the gate-source voltage Vgs is lower than the threshold voltage. For this reason, the off-current may include the subthreshold current. In this specification, since we are dealing with circuits driven by the subthreshold current, unless otherwise specified, the off-current will be described as a current smaller than the subthreshold current.

[0042] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Nor do they limit the order of components, such as process order or layering order. In addition, even if a term in this specification does not have an ordinal number, an ordinal number may be added in the claims to avoid confusion of components. Also, even if a term in this specification has an ordinal number, a different ordinal number may be added in the claims. Furthermore, even if a term in this specification has an ordinal number, the ordinal number may be omitted in the claims. For example, a component that is designated with the ordinal number "first" in one embodiment of this specification may be designated with a different ordinal number such as "second," "third," etc., in another embodiment or in the claims. Also, for example, a component that is designated with the ordinal number "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0043] Furthermore, flowcharts may be used in this specification to explain the operation of semiconductor devices. In this specification, the processes shown in the flowcharts are classified by operation and shown as independent steps. However, in actual operations, it is difficult to separate the processes shown in the flowcharts by operation, and a single step may involve multiple steps, or a single step may involve multiple steps. Therefore, the processes shown in the flowcharts are not limited to the steps described in the specification and can be appropriately rearranged depending on the situation. Specifically, the order of steps can be changed, steps can be added, and steps can be deleted depending on the situation.

[0044] Embodiments described herein are explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Therefore, the present invention is not to be construed as being limited to the contents described in the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in drawings such as perspective views, descriptions of other components may be omitted in order to clearly show the components that are to be described.

[0045] In this specification, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". In addition, in drawings, etc., when an identifying numeral such as "_1", "[n]", or "[m,n]" is accompanied by a reference numeral, the identifying numeral may be omitted in this specification if it is not necessary to distinguish them.

[0046] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0047] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention.

[0048] <Example of Semiconductor Device Configuration> Figure 1A is a block diagram showing an example of the configuration of a processor, which is a semiconductor device according to one aspect of the present invention. The processor NP1 shown in Figure 1A includes, as an example, a digital processing area DNP, an analog processing area ANP, and an arithmetic processing control unit CTU. Figure 1A also shows an example in which the processor NP1 is provided with four digital processing areas DNP, one analog processing area ANP, and one arithmetic processing control unit CTU.

[0049] Processor NP1 can distribute the processing of artificial neural network calculations (also known as AI calculations) to either the digital processing area (DNP) or the analog processing area (ANP), depending on the scale and nature of the calculations. In other words, processor NP1 can handle a wide range of AI calculations.

[0050] The arithmetic processing control unit (CTU) has a function, for example, to determine whether the AI ​​calculation performed by the processor NP1 is performed digitally or analogously. Specifically, the CTU determines, based on the instruction input to the processor NP1 and the content of the AI ​​calculation, whether to perform the AI ​​calculation with high precision calculation or with high-speed calculation, and then decides whether to perform the AI ​​calculation in the digital processing area (DNP) or the analog processing area (ANP).

[0051] The digital processing area (DNP) includes, for example, digital arithmetic circuits (also called digital circuits). Specifically, the digital processing area (DNP) includes adders, multipliers, and other circuits that combine logic gates such as NOR and NAND gates.

[0052] As shown in Figure 1A, by providing multiple digital processing areas (DNPs) in the processor NP1, the calculations in the same artificial neural network can be divided, and each of the divided calculations can be processed by multiple digital processing areas (DNPs). Furthermore, different AI calculations can be performed simultaneously in parallel. Note that the multiple digital processing areas (DNPs) may have the same configuration or different configurations.

[0053] Digital arithmetic circuits offer high calculation accuracy and high-speed computation. Therefore, digital arithmetic circuits are well-suited for AI computations that require fast response times. Examples of AI computations requiring fast response times include autonomous driving technology and image recognition used in surveillance cameras.

[0054] The analog processing area (ANP) includes, for example, analog arithmetic circuits (also called analog circuits). Compared to digital arithmetic circuits, analog arithmetic circuits can have a smaller circuit configuration. Therefore, analog arithmetic circuits can perform calculations with low power consumption (high computational efficiency). Furthermore, analog arithmetic circuits are suitable for AI calculations that perform simple inference. Examples of simple inference include authentication systems using fingerprints, irises, and veins, and handwritten character recognition.

[0055] It should be noted that the semiconductor device according to one aspect of the present invention is not limited to the configuration shown in Figure 1A. The semiconductor device according to one aspect of the present invention may have, for example, multiple analog processing regions (ANPs) instead of just one, as shown in the processor NP2 in Figure 1B. By providing multiple analog processing regions (ANPs), the calculations in the same artificial neural network can be divided, and each of the divided calculations can be processed by the multiple analog processing regions (ANPs). Furthermore, calculations for different artificial neural network models can be performed simultaneously and in parallel. The multiple analog processing regions (ANPs) may have the same configuration or different configurations.

[0056] Furthermore, in one embodiment of the present invention, the semiconductor device may be configured to allow so-called recursive input, where the results of calculations are reused in the analog processing area ANP or digital processing area DNP shown in Figure 1A. This enables the processor NP1 in Figure 1A to perform calculations such as those of a reservoir computing system, typified by an echo state network.

[0057] Furthermore, a semiconductor device according to one aspect of the present invention may have the configuration of the processor CP1 shown in Figure 2. The processor CP1 has a semiconductor device configuration in which an analog processing area ANP is provided to the CPU (Central Processing Unit), and includes an arithmetic processing control unit CTU, an adder AD, a shift register SR, a floating-point arithmetic unit FTC, and the analog processing area ANP. In Figure 2, the adder AD, the shift register SR, and the floating-point arithmetic unit FTC are combined into a digital processing area DNP. Even with the configuration of the processor CP1, it is possible to select whether AI calculations are performed digitally or analogously.

[0058] <<Example of Semiconductor Device Operation>> An example of operation of processor NP1, processor NP2, or processor CP1, which are semiconductor devices according to one aspect of the present invention, will be explained with reference to the drawings. Figure 3 is a flowchart illustrating an example of operation when a multiply-accumulate operation is performed in each processing area of ​​processor NP1, processor NP2, or processor CP1. In Figure 3, the flowchart is divided into three lanes to make it easier to understand where each process shown in the flowchart is performed in the arithmetic processing control unit (CTU), the digital processing area (DNP), or the analog processing area (ANP). Also, "START" in Figure 3 indicates the start of operation, and "END" indicates the end of operation.

[0059] When performing a multiply-accumulate operation, the arithmetic processing control unit (CTU) decides whether to perform the operation in the digital processing area (DNP) or the analog processing area (ANP). Specifically, it makes a decision (step S01) on whether to perform high-precision arithmetic processing with high calculation accuracy, and a decision (step S02) on whether to perform high-speed arithmetic processing with high calculation speed.

[0060] If it is necessary to perform either high-precision arithmetic processing or high-speed arithmetic processing or both, it is determined that the multiply-accumulate operation should be performed in the digital processing area DNP (determined as "Yes" in step S01 or step S02), and the process proceeds to step S03. If it is not necessary to perform either high-precision arithmetic processing or high-speed arithmetic processing, it is determined that the multiply-accumulate operation should be performed in the analog processing area ANP, which consumes less power (determined as "No" in both step S01 and step S02), and the process proceeds to step S04.

[0061] Next, we will describe an example of operation when the arithmetic processing control unit (CTU) determines to perform a multiply-accumulate operation in the digital processing area (DNP). In step S03, the arithmetic processing control unit (CTU) determines whether to use existing first data held in the digital processing area (DNP) or new first data as the first data to be used as a multiplier during the multiply-accumulate operation. If existing first data is to be used, the process proceeds to step S12 (in Figure 3, step S03 is indicated as "No").

[0062] When new first data is to be used (indicated as "Yes" in step S03 in Figure 3), the existing first data held in the digital processing area DNP is overwritten. Specifically, the digital processing area DNP reads the new first data and holds the read first data (step S11). Then, the process proceeds to step S12. The source of the first data can be a storage unit (not shown) provided in processor NP1, processor NP2, or processor CP1, or an external storage device of processor NP1, processor NP2, or processor CP1. The storage unit provided in processor NP1, processor NP2, or processor CP1 can be the storage unit SPD described later.

[0063] Next, the digital processing area DNP reads the second data to be used as the multiplicand during the sum-of-products operation (step S12), and performs the sum-of-products operation using the first and second data (step S13). In step S13, the activation function of the artificial neural network may also be calculated using the result of the sum-of-products operation. After the sum-of-products operation or the activation function calculation is completed, the result is output (step S14).

[0064] Next, we will describe an example of operation when the arithmetic processing control unit CTU determines to perform a multiply-accumulate operation in the analog processing area ANP (when "No" is selected in both step S01 and step S02). In step S04, the arithmetic processing control unit CTU determines whether to use existing first data held in the analog processing area ANP as the first data to be used as a multiplier during the multiply-accumulate operation, or to use new first data. If existing first data is to be used, the process proceeds to step S23 (in Figure 3, "No" is indicated in step S04).

[0065] When new first data is to be used (indicated as "Yes" in step S04 of Figure 3), the existing first data held in the analog processing area ANP is overwritten. Specifically, the analog processing area ANP reads the new first data (step S21). The source of the first data can be a storage unit (not shown) provided in processor NP1, processor NP2, or processor CP1, or an external storage device of processor NP1, processor NP2, or processor CP1. The storage unit provided in processor NP1, processor NP2, or processor CP1 can be the storage unit SPD described later.

[0066] Next, since the first data read is a digital value, the first data is converted to an analog value and stored (step S22). After that, the process proceeds to step S23.

[0067] Next, the analog processing area ANP reads the second data (step S23). Since the read second data is a digital value, it is converted to an analog value (step S24).

[0068] Subsequently, the analog processing area ANP performs a sum-of-accumulate operation using the first data, which is an analog value, and the second data, which is an analog value (step S25). In step S25, the activation function of the artificial neural network may also be calculated using the result of the sum-of-accumulate operation. As a result of performing the sum-of-accumulate operation or the activation function calculation in the analog processing area ANP, the data obtained is an analog value, so this data is converted to a digital value (step S26). Subsequently, this digital value is output (step S27). After step S27, the operation of processor NP1, processor NP2, or processor CP1 is completed.

[0069] In this way, by using the digital processing area (DNP) and the analog processing area (ANP) according to the purpose of the computation, the power consumption of processor NP1, processor NP2, or processor CP1 can be reduced. Furthermore, the computations performed by processor NP1, processor NP2, or processor CP1 can be carried out more efficiently.

[0070] <Specific Configuration Examples of Processor NP1 or Processor NP2> Figure 4 shows specific configuration examples of Processor NP1 in Figure 1A or Processor NP2 in Figure 1B. The Processor NPA shown in Figure 4 is a block diagram showing a configuration example of Processor NP1 in Figure 1A or Processor NP2 in Figure 1B, and comprises various components.

[0071] The processor NPA in Figure 4, as an example, includes an interface IF, a DA conversion unit (digital-to-analog conversion unit) DAC, an arithmetic unit FA, an AD conversion unit (analog-to-digital conversion unit) ADC, a memory unit SPD, and multiple digital processing areas DNP. The memory unit SPD is equipped with an iMC (in Memory Computing) or CiM (Computing in Memory, or Computation in Memory) arithmetic circuit, and the area containing this arithmetic circuit is designated as the sum-of-accumulate unit CA.

[0072] In particular, in the processor NPA shown in Figure 4, the analog processing area ANP includes, for example, a DAC (digital-to-analog converter), a FA (arithmetic unit), an ADC (analog-to-digital converter), and a CA (multiply-accumulate unit), which is a part of the SPD (storage unit). Figure 4 also shows diagonal hatching to indicate the blocks of each component included in the analog processing area ANP. Furthermore, the order of processing performed by each component in the analog processing area ANP is shown in the block diagram of Figure 5. Figure 5 also shows the interface IF (interface) to explain the connection to the analog processing area ANP.

[0073] The interface (IF) is a connection part for communication between the processor NPA and external electronic devices. Through the interface (IF), the processor NPA can acquire digital data (input values, weight coefficients, etc.) used for calculations in the artificial neural network from electronic devices, and can also transmit the output values ​​obtained by the calculations of the artificial neural network as digital data to the electronic devices.

[0074] The DA conversion unit DAC has the function of acquiring digital data used for calculations in the artificial neural network from the interface IF and converting said digital data into analog data. By converting the digital data into analog data, the sum-of-accumulate unit CA can perform sum-of-accumulate calculations. The digital data can be the first data and second data as explained in the flowchart of Figure 3. In particular, the first data can be the weight coefficients in the artificial neural network, and the second data can be the input values ​​input to the neurons of the artificial neural network.

[0075] As described above, the multiply-accumulate unit CA has a CiM-type arithmetic circuit. A CiM-type arithmetic circuit is a circuit that has the function of holding the values ​​necessary for the calculation in addition to the function of performing the calculation. Conventional arithmetic circuits were configured to read the necessary values ​​from a memory device each time an calculation was performed, but with a CiM-type arithmetic circuit, once the necessary values ​​are held, those values ​​can always be used in calculations until they are overwritten with different values. Therefore, the amount of data communication between the processor NPA and its external memory device can be greatly reduced, thus reducing power consumption.

[0076] Furthermore, in the processor NPA shown in Figure 4, the multiply-accumulate unit CA can be provided in the storage unit SPD by providing the storage circuit in the storage unit SPD with the functionality of an arithmetic circuit. In addition, by using a part of the storage unit SPD as the multiply-accumulate unit CA, the circuit area of ​​the processor NPA can be reduced.

[0077] The multiply-accumulate unit CA has the function of performing a multiply-accumulate operation between the input value converted to analog data and a weight coefficient. Specifically, first, each of the multiple calculation cells included in the multiply-accumulate unit CA holds the weight coefficient, and then, when the input value is provided to each calculation cell, each calculation cell outputs a current corresponding to the multiplication of the weight coefficient and the input value. Furthermore, by adding up the currents output from each calculation cell, the summed current can be treated as the result of the multiply-accumulate operation between the input value and the weight coefficient. The summed current is then provided to the calculation unit FA.

[0078] The arithmetic unit FA has the function of calculating activation functions in an artificial neural network. Examples of such activation functions include the sigmoid function, tanh function, softmax function, ReLU function, or threshold function. The arithmetic unit FA obtains the current, which is the result of the sum-of-products operation, from the sum-of-products operation unit CA, and then performs the calculation of the activation function to which this result is substituted as a variable. The result of the activation function calculation is then transmitted as analog data to the AD conversion unit ADC.

[0079] The AD converter (ADC) has the function of converting analog data, which is the result of the activation function calculation transmitted from the arithmetic unit (FA), into digital data. By converting this analog data into digital data, the result of the activation function calculation can be handled in the digital processing area (DNP), interface (IF), etc., which are located outside the analog processing area (ANP).

[0080] Furthermore, the AD conversion unit ADC may have a function to transmit the digital data to the interface IF and the digital processing area DNP. Alternatively, the AD conversion unit ADC may transmit the digital data to a storage circuit in the area outside the sum-of-accumulate unit CA of the storage unit SPD, causing the storage circuit to hold the digital data.

[0081] As described above, the storage unit SPD in Figure 4 has the function of holding digital data which is the result of calculations performed in the analog processing area ANP. The storage unit SPD may also acquire digital data (first data or second data) transmitted to the interface IF from outside the processor NPA and hold said digital data in the storage circuit included in the storage unit SPD.

[0082] For example, SRAM (Static Random Access Memory) can be used as the storage unit SPD. In addition to SRAM, other types of memory include NOSRAM (Registered Trademark) (Nonvolatile Oxide Semiconductor Random Access Memory), DOSRAM (Registered Trademark) (Dynamic Oxide Semiconductor Random Access Memory), DRAM (Dynamic Random Access Memory), flash memory, ReRAM (Resistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), MRAM (Machinetoresistive Random Access Memory), and PRAM (Phase A Change Random Access Memory (SPD) can be used. In other words, a memory cell included in the memory unit SPD can be said to have one selected from an inverter loop, a transistor with a floating layer (also called a floating gate), a capacitive element, a resistive switching element, a magnetic tunnel junction (MTJ) element, or a phase-change memory (PCM) as a circuit or circuit element for holding data.

[0083] Furthermore, since the memory unit SPD includes the multiply-accumulate unit CA, it can be said that the memory unit SPD also includes the arithmetic circuit provided in the multiply-accumulate unit CA. In addition, since the arithmetic circuit has the function of holding the values ​​necessary for calculation, the arithmetic circuit may include one selected from an inverter loop, a transistor with a floating layer, a capacitive element, a resistive switching element, an MTJ element, and a phase-change memory as a circuit or circuit element for holding data.

[0084] In the processor NPA shown in Figure 4, each of the multiple digital processing areas DNP includes, for example, a multiply-accumulate unit MUCA, an arithmetic unit FC, a conversion unit CV, and a load-store unit LSU.

[0085] In particular, the MUCA multiply-accumulate unit has the function of acquiring digital data (input values, weight coefficients, etc.) used for calculations in the artificial neural network from the interface IF or the memory unit SPD, and performing a multiply-accumulate operation between the input values ​​and weight coefficients. The MUCA multiply-accumulate unit also has the function of outputting the result of the multiply-accumulate operation as digital data.

[0086] The arithmetic unit FC, for example, acquires digital data, which is the result of a sum-of-products operation performed by the sum-of-products operation unit MUCA, and performs calculations on the activation function to which this result is assigned as a variable. The activation function can be the same as the activation function handled by the arithmetic unit FA. However, the arithmetic unit FC differs from the arithmetic unit FA in that it performs function calculations in a digital manner.

[0087] The conversion unit CV, for example, has the function of changing the potential level of the digital data input to the digital processing area DNP so that it can be handled by each circuit in the digital processing area DNP. The conversion unit CV may also have the AD conversion unit and DA conversion unit described above.

[0088] The load-store unit (LSU) has, for example, the function of storing instructions for each circuit included in the digital processing area (DNP), and the function of reading the instructions in order and executing them in that order.

[0089] It should be noted that the semiconductor device according to one aspect of the present invention is not limited to the configuration of the processor NPA shown in Figure 4. The semiconductor device according to one aspect of the present invention may be, for example, the processor NPB shown in Figure 6. The processor NPB is a modified example of the processor NPA and differs from the processor NPA in that it does not have a DA conversion unit DAC, an arithmetic unit FA, and an AD conversion unit ADC.

[0090] Furthermore, the processor NPB in Figure 6 has a configuration in which the multiply-accumulate unit CA included in the memory unit SPD, the arithmetic unit FC included in the digital processing area DNP, and the conversion unit CV are all included in the analog processing area ANP. In other words, the arithmetic unit FC and the conversion unit CV included in the digital processing area DNP are shared by the analog processing area ANP. In this case, the conversion unit CV is assumed to have the AD conversion unit and DA conversion unit described above.

[0091] In the NPB processor shown in Figure 6, as an example, when performing calculations in the multiply-accumulate unit CA, the conversion unit CV is used to convert the input values ​​and weight coefficients into analog data. After inputting this analog data into the multiply-accumulate unit CA and performing calculations, the conversion unit CV is used to convert the result of the calculations into digital data. Subsequently, the calculation unit FC performs calculations on the activation function to which this digital data has been substituted as a variable, thereby obtaining the output of the artificial neural network.

[0092] Compared to the processor NPA in Figure 4, the NPB processor in Figure 6 does not have a DAC (digital-to-analog converter), a FA (arithmetic unit), or an ADC (analog-to-digital converter), thus reducing the circuit area.

[0093] Furthermore, a semiconductor device according to one aspect of the present invention may be, for example, the processor NPC shown in Figure 7. The processor NPC is a modified example of the processor NPA, and differs from the processor NPA in that the multiply-accumulate operation unit CA is provided outside the storage unit SPD, rather than inside the storage unit SPD.

[0094] As shown in Figure 7, by placing the multiply-accumulate unit CA and the memory unit SPD in different regions, the memory circuit portion of the calculation circuit in the multiply-accumulate unit CA can have a different configuration from the memory circuit in the memory unit SPD. For example, SRAM can be used in the memory unit SPD, while NOSRAM (registered trademark), DOSRAM (registered trademark), DRAM, ReRAM, FeRAM, MRAM, PRAM, etc. can be used in the memory circuit portion of the multiply-accumulate unit CA. For example, NOSRAM, ReRAM, FeRAM, MRAM, PRAM, etc. consume less power than SRAM, so it is preferable to use these memory circuits in the analog processing area ANP that performs simple inference.

[0095] <<Example 1 of Analog Processing Area ANP Configuration>> Next, a specific example of the configuration of the analog processing area ANP described above will be explained. Figure 8 is a circuit diagram showing an example of the configuration of the analog processing area ANP shown in Figures 1A to 7. The analog processing area ANP 1 shown in Figure 8 has the DA conversion unit DAC, the multiply-accumulate operation unit CA, the operation unit FA, the AD conversion unit ADC, and a drive circuit WSD. Also, in Figure 8, the DA conversion unit DAC has a configuration that includes a drive circuit WCS and a drive circuit XCS.

[0096] [Add-and-Accumulate Unit CA] The add-and-accumulate unit CA includes, as an example, calculation cells IM[1,1] to IM[m,n] (where m and n are integers of 1 or more) and drive cells IMD_1 to IMD_m. The drive cells IMD_1 to IMD_m and calculation cells IM[1,1] to IM[m,n] are arranged in a matrix within the add-and-accumulate unit CA. Specifically, the drive cells IMD_1 to IMD_m are arranged sequentially in the column direction, and the calculation cells IM[1,1] to IM[m,n] are arranged in an m x n matrix.

[0097] In this embodiment, for the sake of simplicity, the configurations of each of the calculation cells IM[1,1] to IM[m,n] are assumed to be the same, and the common elements are sometimes referred to simply as calculation cell IM, omitting the address notation. Similarly, the configurations of each of the drive cells IMD_1 to IMD_m are assumed to be the same, and the common elements are sometimes referred to simply as drive cell IMD, omitting the address notation.

[0098] In the analog processing area ANP1 shown in Figure 8, the multiply-accumulate unit CA has the function of performing a multiply-accumulate operation on, for example, the first data written to each of the multiple calculation cells IM and the second data transmitted from the drive circuit XCS to each of the multiple calculation cells. The first and second data handled in the analog processing area ANP1 shown in Figure 8 are positive values ​​or "0".

[0099] Furthermore, as described above, the first data can be a multiplier or a weight coefficient in an artificial neural network. The second data can be a multiplicand or an input value to a neuron in an artificial neural network. Also, in this specification, due to the commutative property of multiplication, the multiplier and multiplicand may be interchanged in the explanation.

[0100] The calculation cell IM included in the sum-of-products unit CA has, for example, the function of holding the first data and the function of calculating (first data × second data) / (reference value). The reference value will be explained later. In particular, because the calculation cell MC holds the first data once, it can always be treated as the multiplier until the first data is overwritten with a different value. For this reason, the operation method of the sum-of-products unit CA is sometimes called the CiM method.

[0101] Furthermore, the drive cell IMD has a function to maintain a potential corresponding to a reference value in order to perform calculations in the calculation cell IM. The potential corresponding to the reference value is the potential of wiring XCL when the first data is written to the calculation cell IM, and by changing this potential to a potential corresponding to the second data, the calculation (first data × second data) / (reference value) is performed in the calculation cell IM. In particular, by setting the reference value to 1, the calculation cell IM can perform multiplication of the first data and the second data.

[0102] The calculation cell IM, for example, includes transistor F1, transistor F2, transistor F5, and a capacitive element C5. The drive cell IMD, for example, includes transistor F1, transistor F2D, transistor F5D, and a capacitive element C5D.

[0103] It is preferable that the structure of transistor F1 contained in each of the multiple calculation cells IM contained in the multiply-accumulate unit CA (e.g., channel length, channel width, shape, etc.) is the same as that of transistors F2 and F5 contained in each of the multiple calculation cells IM contained in the multiply-accumulate unit CA. This makes it possible to match the electrical characteristics of each calculation cell IM. Furthermore, it is preferable that the structure of transistor F1D contained in each of the multiple drive cells IMD contained in the multiply-accumulate unit CA is the same as that of transistors F2D and F5D contained in each of the multiple drive cells IMD contained in the multiply-accumulate unit CA. This makes it possible to match the electrical characteristics of each drive cell IMD.

[0104] Transistors F1 and F1D each function as switching transistors, for example. Furthermore, transistor F1 may be referred to as the writing transistor in the calculation cell IM, and transistor F1D may be referred to as the writing transistor in the drive cell IMD.

[0105] Unless otherwise specified, the operation of transistors F2 and F2D includes cases where they operate in the subthreshold region (i.e., in transistor F2 or transistor F2D, the gate-source voltage is lower than the threshold voltage, more preferably the drain current increases exponentially with respect to the gate-source voltage). In other words, the operation of each transistor described above includes cases where the gate, source, and drain of the transistor are appropriately biased with voltages within the range of operation in the subthreshold region. For this reason, transistors F2 and F2D also include cases where an off-current flows between the source and drain.

[0106] Furthermore, transistors F5 and F5D function as clamp transistors, for example. For this reason, it is preferable to provide a fixed potential to the gates of transistors F5 and F5D. As will be described in more detail later, by providing transistor F5, DIBL (drain-induced barrier drop) in transistor F2 can be prevented. Similarly, by providing transistor F5D, DIBL in transistor F2D can be prevented. On the other hand, if DIBL in transistor F2 can be ignored, the arithmetic cell IM may be configured without transistor F5. Similarly, if DIBL in transistor F2D can be ignored, the drive cell IMD may be configured without transistor F5D.

[0107] Furthermore, transistors containing an oxide semiconductor in the channel formation region (also called OS transistors) can be used in the multiply-accumulate unit CA shown in Figure 8. In particular, by using OS transistors for transistors F1 and F1D, the leakage current of these transistors can be suppressed, thereby reducing the power consumption of the calculation cell IM. Specifically, for example, when transistor F1 is in a non-conductive state, the leakage current from the holding nodes (e.g., the first terminal of transistor F1, the first terminal of the capacitive element C5, and the gate of transistor F2) to the wiring WCL can be made very small, thus reducing the refresh operation of the potential of the holding nodes. In addition, by reducing the refresh operation, the power consumption of the calculation cell IM can be reduced. In particular, by using transistors containing indium oxide in the channel formation region (also called IO transistors), which are a type of OS transistor, for transistors F2 and F2D, the on-current of these transistors can be increased. In other words, the ratio of the off-current to the off-current of transistors F2 and F2D can be increased. Specifically, the I / O transistor has an on-current ratio of 1.0 × 10⁻¹⁰ to off-current. １７ The above characteristics are highly desirable. Therefore, by applying I / O transistors to the transistors in the calculation cell IM and the drive cell IMD, malfunctions due to current leakage can be prevented, and the drive speed can be increased by the on-current. Indium oxide will be described in detail in Embodiment 3.

[0108] In addition, the transistors included in the multiply-accumulate unit CA in Figure 8 can be transistors containing silicon in the channel formation region (also called Si transistors), other than OS transistors. Examples of silicon include single-crystal silicon, amorphous silicon, microcrystalline silicon, or polycrystalline silicon (including low-temperature polycrystalline silicon (LTPS)).

[0109] In the calculation cell IM of Figure 8, the first terminal of transistor F1 is connected to the gate of transistor F2 and the first terminal of capacitive element C5. The first terminal of transistor F2 is connected to the first terminal of transistor F5, and the second terminal of transistor F2 is connected to wiring VE0. The second terminal of transistor F5 is connected to the second terminal of transistor F1, and the gate of transistor F5 is connected to wiring VE1.

[0110] In the drive cell IMD shown in Figure 8, the first terminal of transistor F1D is connected to the gate of transistor F2D and the first terminal of capacitive element C5D. The first terminal of transistor F2D is connected to the first terminal of transistor F5D, and the second terminal of transistor F2D is connected to wiring VE0. The second terminal of transistor F5D is connected to the second terminal of transistor F1D, and the gate of transistor F5D is connected to wiring VE1.

[0111] Wiring VE0 functions as a wire for supplying current between the first and second terminals of transistor F2 in the calculation cell IM. Wiring VE0 also functions as a wire for supplying current between the first and second terminals of transistor F2D in the drive cell IMD. For example, wiring VE0 functions as a wire for supplying a fixed potential. This fixed potential can be a low-level potential or ground potential.

[0112] Wiring VE1 functions as wiring for applying potential to the gate of transistor F5 of the calculation cell IM and the gate of transistor F5D of the drive cell IMD. Preferably, the potential is within the range in which transistors F5 and F5D function as clamp transistors.

[0113] In the calculation cell IM[i,j] (not shown) located in the i-th row and j-th column of the sum-of-accumulate unit CA in Figure 8, the second terminals of transistor F1 and transistor F5 are connected to wiring WCL_j, and the gate of transistor F1 is connected to wiring WSL_i. In addition, the second terminal of the capacitive element C5 is connected to wiring XCL_i.

[0114] Furthermore, in the drive cell IMD_i (not shown) located in row i of the multiply-accumulate unit CA in Figure 8, the second terminal of transistor F1 and the second terminal of transistor F5D are connected to wiring XCL_i, and the gate of transistor F1 is connected to wiring WSL_i. Also, the second terminal of the capacitive element C5D is connected to wiring XCL_i.

[0115] [Drive Circuit WSD] The drive circuit WSD, as an example, has the function of selecting the row of the sum-of-accumulate unit CA where the calculation cell IM to be written is located when writing the first data. Also, when writing the first data, the drive cell IMD in the same row is selected, and the reference value is written to the drive cell IMD.

[0116] Specifically, for example, in Figure 8, the drive circuit WSD supplies a high-level potential to wiring WSL_1 and a low-level potential to wiring WSL_2 (not shown) through WSL_m, thereby turning on the gated transistors F1 and F1D connected to wiring WSL_1, and turning off the gated transistors F1 and F1D connected to wiring WSL_2 through WSL_m. In other words, the write switches of the calculation cell IM and the drive cell IMD located in the first row of the multiply-accumulate unit CA can be turned on.

[0117] [Drive Circuit WCS] The drive circuit WCS, as an example, acquires first data, which is digital data, from outside the analog processing area ANP1 via wiring IWL_1 to IWL_n, converts the first data into analog data (current), and further supplies the first data converted into analog data to the calculation cell IM of the multiply-accumulate unit CA. For example, when the drive circuit WCS writes first data to the calculation cell IM[i,1] included in the multiply-accumulate unit CA, the aforementioned drive circuit WSD selects the calculation cell IM[i,1] to IM[i,n] of the i-th row of the multiply-accumulate unit CA, and then the drive circuit WCS supplies the first data to the calculation cell IMS[i,1] of the multiply-accumulate unit CA via wiring WCL_1.

[0118] Furthermore, the area outside the analog processing area ANP1 includes, for example, areas of the memory unit SPD other than the multiply-accumulate unit CA, interface IF, and other circuits included in processor NP1 or processor NP2.

[0119] The drive circuit WCS includes, for example, circuit SWCA and circuits WCSa_1 to WCSa_n.

[0120] Circuit SWCA has the function of controlling the switching between a conductive state and a non-conductive state between wiring WCL_j (not shown) and circuit WCSa_j (not shown). For this reason, circuit SWCA includes switches SA_1 to SA_n as an example.

[0121] The first terminal of switch SA_j (not shown) is connected to wiring WCL_j, the second terminal of switch SA_j is connected to circuit WCSa_j, and the control terminal of switch SA_j is connected to wiring SWLA.

[0122] Switch SA_j can be an electrical switch, such as an analog switch or a transistor. In particular, it is preferable to use an OS transistor, which has a small off-current, as the electrical switch for switch SA_j. Furthermore, by using an IO transistor, which is a type of OS transistor, for switch SA_j, the on-current of switch SA_j can be increased. When an electrical switch is used for switch SA_j, it can be an OS transistor or, for example, an Si transistor. Alternatively, a mechanical switch may be used for switch SA_j.

[0123] Wiring SWLA functions, for example, as wiring for switching between the ON and OFF states of switch SA_j. Therefore, wiring SWLA is supplied with, for example, a high-level potential or a low-level potential.

[0124] In the drive circuit WCS, switch SA_j is turned ON when the first data is written to the calculation cell IM of the sum-of-accumulate unit CA. Conversely, when the sum-of-accumulate unit CA performs a sum-of-accumulate operation between the first data and the second data, switch SA_j is turned OFF.

[0125] Furthermore, circuit WCSa_j is connected to wiring IWL_j. Wiring IWL_j functions as wiring for transmitting the first data, which is digital data, from an external source to circuit WCSa_j.

[0126] Circuit WCSa_j, for example, has the function of acquiring first data from wiring IWL_j (not shown) and supplying a signal corresponding to the first data to wiring WCL_j. Specifically, when switch SA_j is ON, circuit WCSa_j supplies first data to be stored in one of the calculation cells IM[1,j] to IM[m,j] located in the j-th column of the sum-of-accumulate unit CA. In the case of the sum-of-accumulate unit CA shown in Figure 8, it is preferable that the signal is analog data (current). In other words, a digital-to-analog conversion circuit that converts digital potential to analog current can be applied to circuit WCSa_j. Furthermore, it is preferable to use a current-type ladder-type digital-to-analog conversion circuit as the digital-to-analog conversion circuit.

[0127] [Drive Circuit XCS] The drive circuit XCS, as an example, acquires second data, which is digital data, from outside the analog processing area ANP1 via wiring IXL_1 to IXL_m, converts the second data into analog data (current), and further supplies the second data to the drive cell IMD and calculation cell IM of the multiply-accumulate unit CA. For example, when the drive circuit XCS supplies the second data to the i-th row calculation cell IM[i,1] to calculation cell IM[i,n] included in the multiply-accumulate unit CA, the drive circuit XCS supplies the second data to the i-th row calculation cell of the multiply-accumulate unit CA via wiring XCL_i.

[0128] The drive circuit XCS includes, for example, circuits XCSa_1 to XCSa_m. Circuit XCSa_i is connected to wiring IXL_i.

[0129] Wiring IXL_i functions as wiring for transmitting second data, which is digital data, from an external source to circuit XCSa_i.

[0130] Furthermore, circuit XCSa_i may, for example, have the function of acquiring a reference value (described later) from wiring IXL_i and supplying a signal corresponding to that reference value to wiring XCL_i. Alternatively, circuit XCSa_i may, for example, acquire second data from wiring IXL_i and supply a signal corresponding to that second data. In the case of the sum-of-accumulate unit CA in Figure 8, it is preferable that the above-mentioned signals be analog data (current). In other words, a digital-to-analog conversion circuit that converts digital potential to analog current can be applied to circuit XCSa_i, similar to circuit WCSa_j.

[0131] [Calculation Unit FA] As described above, the calculation unit FA has the function of calculating activation functions. For this reason, the calculation unit FA has, as an example, circuits ITSa_1 to ITSa_n that perform calculations on a system of functions (for example, a system of nonlinear functions). The calculation unit FA also has circuit SWCB. Circuit ITSa_j (not shown) is configured to calculate an activation function according to the amount of current by acquiring the current flowing through wiring WCL_j (not shown).

[0132] The SWCB circuit, for example, has the function of controlling the switching between a conductive state and a non-conductive state between the wiring WCL_j and the circuit ITSa_j. Therefore, the SWCB circuit may include switches SB_1 to SB_n as an example.

[0133] The first terminal of switch SB_j (not shown) is connected to wiring WCL_j, the second terminal of switch SB_j is connected to circuit ITSa_j, and the control terminal of switch SB_j is connected to wiring SWLB.

[0134] Switch SB_j can be any switch applicable to switches SA_1 through SA_n. Therefore, for switch SB_j, you can refer to the description of switches SA_1 through SA_n.

[0135] The SWLB wiring, for example, functions as wiring for switching between the ON and OFF states of switch SB_j. Therefore, the SWLB wiring is supplied with, for example, a high-level potential or a low-level potential.

[0136] In the calculation unit FA, when the first data is written to the calculation cell IM of the sum-of-products calculation unit CA, switch SB_j is in the off state. Conversely, when the sum-of-products calculation is performed on the first data and the second data in the sum-of-products calculation unit CA, switch SB_j is in the on state. As a result, the calculation unit FA can transmit the calculation result of the activation function corresponding to the result of the sum-of-products calculation of the first data and the second data to the AD conversion unit ADC.

[0137] [AD Conversion Unit ADC] As described above, the AD conversion unit ADC has the function of converting analog data, which is the result of the activation function calculation transmitted from the arithmetic unit FA, into digital data. For this reason, it is preferable that the AD conversion unit ADC has an analog-to-digital conversion circuit.

[0138] The AD converter (ADC) includes, for example, circuits ADa_1 to ADa_n. Circuit ADa_j (not shown) is preferably an analog-to-digital conversion circuit for converting analog data, which is the result of the activation function calculation, into digital data.

[0139] The input terminal of circuit ADa_j is connected to circuit ITSa_j, and the output terminal of circuit ADa_j is connected to wiring OL_j.

[0140] The wiring OL_j (not shown) functions as wiring for outputting the result of calculations performed in the analog processing area ANP1 as digital data to the storage unit SPD or to an external source.

[0141] <<Example 2 of Analog Processing Area ANP Configuration>> Figure 9 is a circuit diagram showing an example of the configuration of the analog processing area ANP shown in Figures 1A to 7, which is different from Figure 8. The analog processing area ANP2 in Figure 9 includes, as an example, a multiply-accumulate unit CA, a drive circuit WBS, a drive circuit WCS, an arithmetic unit FA, and an AD conversion unit ADC. In Figure 9, the DA conversion unit DAC has a configuration that includes a drive circuit XCS.

[0142] The sum-of-products unit CA is assumed to have multiple calculation cells IMS arranged in a matrix of m rows and n columns (where m and n are integers of 1 or greater). In particular, in the sum-of-products unit CA shown in Figure 9, the calculation cell IMS located in the i-th row and j-th column is denoted as calculation cell IMS[i,j]. Specifically, the sum-of-products unit CA in Figure 9 shows calculation cells MC[1,j] and MC[m,j] as examples.

[0143] The analog processing area ANP2 shown in Figure 9 has the function of performing a sum-of-products operation on multiple first data and multiple second data, and the function of performing an activation function operation on which the result of the sum-of-products operation is assigned as a variable. In particular, the sum-of-products unit CA in Figure 9 operates in the same CiM manner as the sum-of-products unit CA in Figure 8.

[0144] The first data that can be handled in the analog processing area ANP2 in Figure 9 is, for example, a binary digital data of "1" or "0". The second data that can be handled in the analog processing area ANP2 in Figure 9 is an analog potential of a positive value or "0".

[0145] In the sum-of-accumulate unit CA, the wirings WBL_1 to WBL_n, WBLb_1 to WBLb_n, and RBL_1 to RBL_n each extend in the column direction, and the wirings XCL_1 to XCL_m and WSL_1 to WSL_m each extend in the row direction.

[0146] The drive circuit WBS is connected to wiring WBL_1 to WBL_n and wiring WBLb_1 to WBLb_n, respectively. The calculation unit FA is connected to wiring RBL_1 to RBL_n, respectively. The drive circuit XCS is connected to wiring XCL_1 to XCL_m, respectively. The drive circuit WSD is connected to wiring WSL_1 to WSL_m, respectively. The calculation cell IMS[i,j] is connected to wiring WBL_j, wiring WBLb_j, wiring XCL_i, wiring WSL_i, and wiring RBL_j.

[0147] The drive circuit WSD, for example, has the function of selecting the row of the multiply-accumulate unit CA where the calculation cell IM to be written is located when writing the first data. In other words, the drive circuit WSD, for example, has the function of sending a selection signal to the wiring WSL connected to the calculation cell IMS when writing the first data to that calculation cell IMS. Also, the drive circuit WSD, for example, has the function of sending a non-selection signal to the wiring WSL connected to the calculation cell IMS when not writing the first data to that calculation cell IMS.

[0148] The drive circuit WBS has the function of acquiring first data, which is digital data, from outside the analog processing area ANP2 (for example, circuits included in processor NP1 or processor NP2, such as areas other than the multiply-accumulate unit CA of the memory unit SPD, interface IF, etc., similar to the area outside the analog processing area ANP1, via wiring IWL_j), converting the first data into complementary data, and then transmitting the complementary data to the calculation cell IMS included in the multiply-accumulate unit CA using wiring WBL_j and wiring WBLb_j. For example, when the drive circuit WBS writes the first data to the calculation cell IMS[i,j] in the jth column of the sum-of-accumulate unit CA, the aforementioned drive circuit WSD selects the calculation cell IMS[i,1] to calculation cell IMS[i,n] in the ith row of the sum-of-accumulate unit CA, and then the drive circuit WBS supplies the first data to the calculation cell IMS[i,j] of the sum-of-accumulate unit CA via the wiring WBL_j and the wiring WBLb_j.

[0149] For example, when the first data transmitted from wiring IWL_j is "1", the drive circuit WBS treats the first data as complementary data, assigning a high-level potential to wiring WBL_j and a low-level potential to wiring WBLb_j. Also, for example, when the first data transmitted from wiring IWL_j is "0", the drive circuit WBS treats the first data as complementary data, assigning a low-level potential to wiring WBL_j and a high-level potential to wiring WBLb_j.

[0150] Thus, wiring WBL and wiring WBLb function, for example, as wiring for transmitting first data from the drive circuit WBS to the calculation cell IMS. Wiring WBL and wiring WBLb are sometimes referred to as a data line pair that transmits data complementaryly.

[0151] For example, the drive circuit XCS acquires second data, which is digital data, from outside the analog processing area ANP2 via wiring IXL_1 to IXL_m, converts the second data into an analog potential, and further supplies the analog potential to the calculation cell IMS of the multiply-accumulate unit CA. For example, when the drive circuit XCS supplies second data to the i-th row calculation cell IMS[i,1] to calculation cell IMS[i,n] included in the multiply-accumulate unit CA, the drive circuit XCS supplies the analog potential to the i-th row calculation cell of the multiply-accumulate unit CA via wiring XCL_i.

[0152] Therefore, the wiring XCL functions, for example, as wiring for transmitting second data from the drive circuit XCS to the calculation cell IMS.

[0153] The calculation unit FA in Figure 9, similar to the calculation unit FA in Figure 8, has the function of obtaining the sum of the results of the multiplication of the first data and the second data performed in each of the multiple calculation cells IMS arranged in one row of the sum-of-products calculation unit CA, from the signals transmitted to the wiring RBL from each of the multiple calculation cells IMS. Furthermore, the calculation unit FA in Figure 9, similar to the calculation unit FA in Figure 8, may, as an example, have the function of performing activation function calculations with the result of the sum-of-products calculation as a variable.

[0154] Furthermore, Figure 9 shows an example where the calculation unit FA includes a switch SWR and a circuit ITSa_j. The first terminal of switch SWR is connected to wiring RBL_j, and the second terminal of switch SWR is connected to wiring VEG. In addition, the input terminal of circuit ITSa_j is connected to wiring RBL_j.

[0155] Circuit ITSa_j, like the circuit ITSa_j in Figure 8, has the function of performing calculations on a system of functions (for example, a system of nonlinear functions). Note that while the circuit ITSa_j in Figure 8 is configured to perform calculations on a system of functions when current is input, the circuit ITSa_j shown in Figure 9 is configured to perform calculations on a system of functions when electric potential is input.

[0156] Furthermore, the VEG wiring also functions as wiring that provides a fixed potential, for example. This fixed potential can be a low-level potential, a ground potential, or the like. For convenience, in the following explanation, the fixed potential provided by the VEG wiring will be described as the ground potential.

[0157] Switch SWR functions as a switch that controls whether or not a fixed potential from wiring VEG is applied to wiring RBL_j. In this case, turning switch SWR ON is sometimes referred to as initializing the potential of wiring RBL_j.

[0158] As described above, the ADC in Figure 9 has the function of converting analog data, which is the result of the activation function calculation transmitted from the FA unit, into digital data. Therefore, it is preferable that the ADC has an analog-to-digital conversion circuit.

[0159] The input terminal of the ADC in the AD conversion unit is connected to circuit ITSa_j, and the output terminal of the ADC in the AD conversion unit is connected to wiring OL_j.

[0160] The wiring OL_j functions as wiring for outputting the results of calculations performed in the analog processing area ANP2 as digital data to the storage unit SPD or to an external source.

[0161] The calculation cell IMS located in the sum-of-accumulate unit CA includes, as an example, a transistor F3, a transistor F3b, an inverter IVa, an inverter IVb, a switch SWS, a switch SWSb, and a capacitive element C4.

[0162] For transistors F3 and F3b, for example, transistors applicable to transistors F1, F2, or F5 described above can be used. Also, for switches SWS and SWSb, for example, switches applicable to switches SA_1 to SA_n described above can be used.

[0163] Furthermore, in this case, for both switch SWS and switch SWSb, when a high-level potential is applied to the control terminal, the switch will be in the ON state, and when a low-level potential is applied to the control terminal, the switch will be in the OFF state.

[0164] In the calculation cell IMS[i,j], the first terminal of transistor F3 is connected to the input terminal of inverter IVa, the output terminal of inverter IVb, and the control terminal of switch SWS. The second terminal of transistor F3 is connected to wiring WBL_j. The first terminal of transistor F3b is connected to the output terminal of inverter IVa, the input terminal of inverter IVb, and the control terminal of switch SWSb. The second terminal of transistor F3b is connected to wiring WBLb_j. The gates of transistors F3 and F3b are connected to wiring WSL_i.

[0165] The first terminal of switch SWS is connected to the first terminal of switch SWSb and the first terminal of capacitive element C4. The second terminal of switch SWS is connected to wiring XCL_i. The second terminal of switch SWSb is connected to wiring VEG. The second terminal of capacitive element C4 is connected to wiring RBL_j.

[0166] Next, we will explain the operation of the sum-of-products operation between the first data and the second data in calculation cell IMS[1,j] to calculation cell IMS[m,j].

[0167] In the analog processing area ANP2, the initialization operation involves turning on switches SWSb and SWR to set the voltage between the first and second terminals of the capacitive element C4 in each of the calculation cells IMS[1,j] to IMS[m,j] to 0V. Then, the switch SWR is turned off to set the wiring RBL_j to a floating state.

[0168] Next, the first data is written to each of the calculation cells IMS[1,j] through IMS[m,j]. For example, when "1" is written as the first data to calculation cell IMS[i,j], a high-level potential is applied from wiring WBL_j to the control terminal of switch SWS via transistor F3, and a low-level potential is applied from wiring WBLb_j to the control terminal of switch SWSb via transistor F3b. As a result, switch SWS turns ON and switch SWSb turns OFF. Also, as an example, when "0" is written as the first data to calculation cell IMS[i,j], a low-level potential is applied from wiring WBL_j to the control terminal of switch SWS via transistor F3, and a high-level potential is applied from wiring WBLb_j to the control terminal of switch SWSb via transistor F3b. As a result, switch SWS turns OFF and switch SWSb turns ON.

[0169] When "1" is written as the first data in the calculation cell IMS[i,j], an analog potential corresponding to a positive value or "0" is supplied to the first terminal of the capacitive element C4 via the wiring XCL_i from the circuit XCSa_i of the drive circuit XCS as the second data. In particular, the analog potential corresponding to "0" as the second data is set to the ground potential. Also, when "0" is written as the first data in the calculation cell IMS[i,j], the ground potential from the wiring VEG is supplied to the first terminal of the capacitive element C4.

[0170] When an analog potential corresponding to a positive value is provided as the second data from circuit XCSa_i of the drive circuit XCS to the calculation cell IMS[i,j] which has "1" written as the first data, the potential of wiring RBL_j also changes according to the analog potential due to the capacitive coupling of capacitive element C4, since wiring RBL_j is in a floating state. On the other hand, when an analog potential corresponding to "0" (ground potential) is provided as the second data from circuit XCSa_i of the drive circuit XCS, the potential of wiring RBL_j does not change.

[0171] Furthermore, when "0" is written as the first data in the calculation cell IMS[i,j], the switch SWS is in the off state, so the second data from the drive circuit XCSa_i is not input to the calculation cell IMS[i,j]. In this case as well, the potential of the wiring RBL_j does not change.

[0172] As described above, the potential change of wiring RBL_j due to capacitive coupling via the capacitive element C4 can occur in each of the calculation cells IMS[1,j] to IMS[m,j]. Therefore, the potential of wiring RBL_j is determined according to the multiplication of the first data and the second data in each of the calculation cells IMS[1,j] to IMS[m,j], and the sum of the results of that multiplication. In other words, the potential of wiring RBL_j is the potential corresponding to the result of the sum-of-products operation of multiple first data and multiple second data.

[0173] Furthermore, the potential of wiring RBL_j, corresponding to the result of the sum-of-products operation between multiple first data points and multiple second data points, is supplied to the input terminal of circuit ITSa_j. As a result, circuit ITSa_j performs an activation function operation in which the result of the sum-of-products operation between the first data points and the second data points is substituted as a variable. The result of this operation is then supplied to the ADC (Analog-to-Digital Converter), where it is converted from analog data to digital data and output to wiring OL_j.

[0174] As described above, by operating the analog processing area ANP2 shown in Figure 9, the calculations of the artificial neural network can be performed in an analog manner.

[0175] <<Example 3 of Analog Processing Area ANP Configuration>> Figure 10 is a block diagram showing an example of the configuration of the analog processing area ANP shown in Figures 1A to 7, which differs from Figures 8 and 9. The analog processing area ANP 3 in Figure 10 includes, as an example, a multiply-accumulate unit CA, a drive circuit WCD, a drive circuit XWSD, an arithmetic unit FA, and an AD conversion unit ADC. In addition, the multiply-accumulate unit CA has multiple arithmetic cells MC arranged in a matrix of m rows and n columns (m and n are integers of 1 or more).

[0176] In particular, in the sum-of-products calculation unit CA of Figure 10, the calculation cell MC located in the i-th row and j-th column is represented as calculation cell MC[i,j], similar to the sum-of-products calculation unit CA of Figure 8. Specifically, the sum-of-products calculation unit CA of Figure 10 shows a selection of calculation cells MC[1,1], MC[m,1], MC[1,n], and MC[m,n].

[0177] The analog processing area ANP3 shown in Figure 10 has the function of performing a sum-of-products operation on multiple first data and multiple second data, and the function of performing operations on a function system to which the result of the sum-of-products operation has been assigned as a variable. In particular, the sum-of-products unit CA in Figure 10 operates in the CiM method, similar to the sum-of-products unit CA in Figure 8 or Figure 9.

[0178] In the sum-of-accumulate unit CA, each of the wirings WBL_1 to WBL_n extends in the column direction, and each of the wirings WXL_1 to WXL_m extends in the row direction.

[0179] The drive circuit WCD is connected to each of the wirings WBL_1 through WBL_n. The calculation unit FA is also connected to each of the wirings WBL_1 through WBL_n. The drive circuit XWSD is connected to each of the wirings WXL_1 through WXL_m. The calculation cell MC[i,j] is connected to wiring WXL_i and wiring WBL_j.

[0180] Wiring WBL, for example, functions as wiring for transmitting first data from the drive circuit WCD to the calculation cell MC. Wiring WBL also functions as wiring for transmitting the result of the multiplication of the first data and the second data performed by the calculation cell MC to the calculation unit FA.

[0181] Wiring WXL functions, for example, as a selection signal line for sending a selection signal to the calculation cell MC when writing the first data to that calculation cell MC. It also functions as a selection signal line for sending a non-selection signal to the calculation cell MC when the first data is not written to that calculation cell MC. Furthermore, wiring WXL also functions, for example, as wiring for sending the second data from the drive circuit XWSD to the calculation cell MC.

[0182] The drive circuit WCD, for example, has the function of acquiring multiple first data points from outside the analog processing area ANP3 and transmitting signals corresponding to the first data points to multiple calculation cells MC of the sum-of-accumulate unit CA via the wiring WBL. In other words, the drive circuit WCD functions as a writing circuit for the calculation cells MC.

[0183] As an example, the drive circuit XWSD has the function of sequentially transmitting a selection signal to each of the multiple calculation cells MC of the multiply-accumulate unit CA via wiring WXL when writing the first data. Also, as an example, the drive circuit XWSD has the function of acquiring multiple second data from outside the analog processing area ANP3 when multiplying the first data and the second data, and transmitting the second data all at once to each of the multiple calculation cells MC of the multiply-accumulate unit CA via wiring WXL.

[0184] The calculation unit FA in Figure 10, similar to the calculation unit FA in Figure 8, has the function of obtaining the sum of the results of multiplication of the first data and the second data performed in each of the multiple calculation cells MC arranged in a single row of the multiply-accumulate calculation unit CA, from the signals transmitted to the wiring WBL from each of the multiple calculation cells MC. Furthermore, the calculation unit FA in Figure 10, similar to the calculation unit FA in Figure 8, may, as an example, have the function of performing calculations on an activation function to which the result of the multiply-accumulate calculation has been assigned as a variable.

[0185] Next, we will explain an example of the configuration of the calculation cell MC.

[0186] The arithmetic cell MC1 shown in Figure 11A is an example of a circuit that can be applied to the arithmetic cell MC shown in Figure 10, and is a circuit that uses memory elements used in DRAM. For example, the arithmetic cell MC1 has the function of holding a first data as a binary value of "0" or "1", and the function of multiplying the first data by a second data as a binary value of "0" or "1".

[0187] The calculation cell MC1 includes, for example, a transistor WTr and a capacitive element C11.

[0188] Transistor WTr functions as a first data writing transistor, similar to the transistor WTr in the arithmetic cell MC1. Therefore, for example, the transistor WTr in Figure 11A can be one of the transistors that can be applied to transistors F1, F2, F5, F1D, F2D, and F5D included in the multiply-accumulate unit CA in Figure 8.

[0189] The first terminal of transistor WTr is connected to the first terminal of capacitive element C11, the second terminal of transistor WTr is connected to wiring WBL, and the gate of transistor WTr is connected to wiring WXL. In addition, the second terminal of capacitive element C11 is connected to wiring VCE.

[0190] The VCE wiring, for example, functions as wiring to provide a fixed potential. This fixed potential can be a high-level potential, a positive potential, or the like.

[0191] When writing the first data to the calculation cell MC1, for example, a high-level potential is applied to the wiring WXL to turn on the transistor WTr. Next, the first data can be written to the calculation cell MC1 by sending the first data to the wiring WBL. Specifically, when the first data is "0", a low-level potential is applied to the wiring WBL as the first data. Or, when the first data is "1", a high-level potential is applied to the wiring WBL as the first data.

[0192] Furthermore, after writing the first data to the calculation cell MC1, the first data can be retained in the calculation cell MC1 by applying a low-level potential to the wiring WXL and turning off the transistor WTr.

[0193] When multiplying the first data and the second data in the calculation cell MC1, as an example, first, a low-level potential is precharged onto the wiring WBL. Next, a potential corresponding to the second data is applied to the wiring WXL. For example, when the second data is "0", a low-level potential is applied to the wiring WXL, or when the second data is "1", a high-level potential is applied to the wiring WXL.

[0194] When the second data is "0", the transistor WTr is in the off state, so no current flows from the calculation cell MC1 to the wiring WBL. In other words, no charge redistribution occurs between the first terminal of the capacitive element C11 and the wiring WBL. Also, when the first data is "0" and the second data is "1", the potential of the first terminal of the capacitive element C11 is at a low level, and the potential of the wiring WBL is also at a low level, so no current flows from the calculation cell MC1 to the wiring WBL. Also, when the first data is "1" and the second data is "1", the potential of the first terminal of the capacitive element C11 is at a high level, and the potential of the wiring WBL is at a low level, so a redistribution of the charge held at the first terminal of the capacitive element C11 occurs between the calculation cell MC1 and the wiring WBL. As a result, the potential of the wiring WBL rises according to the amount of charge.

[0195] As shown in the sum-of-products unit CA of the analog processing area ANP3 in Figure 10, by arranging the calculation cells MC1 in a column direction, the potential of the wiring WBL is determined according to the number of calculation cells MC1 whose product of the first data and the second data is "1". By acquiring this potential, the calculation unit FA can obtain the sum-of-products calculation of the multiple first data and multiple second data calculated by the sum-of-products unit CA of the analog processing area ANP3.

[0196] In addition, in the calculation cell MC1 of Figure 11A, a ferroelectric capacitor may be used as the storage element of the FeRAM for the capacitive element C11. In this case, it is preferable that the wiring VCE is a plate wire that provides a variable potential rather than wiring that provides a fixed potential.

[0197] The arithmetic cell MC2 shown in Figure 11B is an example of a circuit that can be applied to the arithmetic cell MC shown in Figure 10, and is a circuit that uses a transistor FTr with a floating layer, which is used in flash memory. The arithmetic cell MC2 has, for example, the function of holding a first data as a binary value of "0" or "1", and the function of multiplying that first data with a second data as a binary value of "0" or "1".

[0198] As described above, the transistor FTr is a transistor equipped with a floating layer, and has the function of holding first data by accumulating electrons in the floating layer.

[0199] The first terminal of transistor FTr is connected to wiring SL, the second terminal of transistor FTr is connected to wiring WBL, and the gate of transistor FTr is connected to wiring WXL.

[0200] Wiring SL functions as a source line for transistor FTr. Specifically, wiring SL functions as wiring that provides a fixed potential. This fixed potential can be a low-level potential, ground potential, etc.

[0201] In transistor FTr, when no electrons are accumulated in the floating layer, the calculation cell MC2 holds "1" as the first data. When writing "0" as the first data to calculation cell MC2, for example, a low-level potential is applied to wiring WBL and a writing potential higher than the high-level potential is applied to wiring WXL to accumulate electrons in the floating layer of transistor FTr.

[0202] When multiplying the first data and the second data in the calculation cell MC2, as an example, first, a high-level potential is applied to the wiring WBL. Next, a potential corresponding to the second data is applied to the wiring WXL. For example, when the second data is "0", a low-level potential is applied to the wiring WXL, or when the second data is "1", a high-level potential is applied to the wiring WXL.

[0203] When the first data is "0", the threshold voltage of transistor FTr is shifted in the positive direction, so no current flows between the source and drain of transistor FTr, even if the potential of wiring WXL is at a low or high level. Also, when the first data is "1" and the second data is "0", transistor FTr is in the off state, so no current flows from calculation cell MC2 to wiring WBL. Also, when the first data is "1" and the second data is "1", transistor FTr is in the on state, so current flows from calculation cell MC2 to wiring WBL.

[0204] To summarize the above, when the product of the first data and the second data is "0", no current flows from the calculation cell MC2 to the wiring WBL. Also, when the product of the first data and the second data is "1", source-drain current flows from the calculation cell MC2 to the wiring WBL through the transistor FTr.

[0205] As shown in the sum-of-products unit CA of the analog processing area ANP3 in Figure 10, by arranging the calculation cells MC2 in a column direction, the sum of the results of multiplying the first data and the second data can be passed as current to the wiring WBL, similar to the calculation cell MC1 in Figure 11A. As a result, the calculation unit FA can acquire this current and calculate the sum-of-products operation of multiple first data and multiple second data.

[0206] In the above description, the transistor FTr was configured to hold binary data, but it may also be configured to hold multi-level data. In this case, the first data can be treated as a continuous value rather than a binary value, thus expanding the range of the multiplication result in the calculation cell MC2.

[0207] The arithmetic cell MC3 shown in Figure 11C is an example of a circuit that can be applied to the arithmetic cell MC shown in Figure 10, and is a circuit that uses memory elements used in ReRAM. For example, the arithmetic cell MC3 has the function of holding a first data as a binary value of "0" or "1", and the function of multiplying that first data with a second data as a binary value of "0" or "1".

[0208] The calculation cell MC3 includes, for example, a resistive switching element RV and a transistor WTr.

[0209] The transistor WTr functions as a first data writing transistor, similar to the transistor WTr in the arithmetic cell MC1. Therefore, the transistor WTr in Figure 11C can be, for example, the same transistor that can be applied to the transistor WTr shown in Figure 11A.

[0210] The first terminal of transistor WTr is connected to the first terminal of resistive switching element RV, the second terminal of transistor WTr is connected to wiring SL, and the gate of transistor WTr is connected to wiring WXL. In addition, the second terminal of resistive switching element RV is connected to wiring WBL.

[0211] Wiring SL, for example, functions as wiring for providing a fixed potential. This fixed potential can be a low-level potential, ground potential, or the like.

[0212] The resistive switching element RV can change its resistance value by applying a positive or negative pulse voltage between its first and second terminals. By assigning this changing resistance value as "0" or "1" as the first data, the calculation cell MC3 can store the first data using the resistive switching element RV.

[0213] Furthermore, by applying a potential corresponding to the second data to the wiring WXL, the transistor WTr can be turned on or off according to the second data. This allows the calculation cell MC3 to supply a current to the wiring WBL corresponding to the multiplication result of the first data and the second data.

[0214] As shown in the sum-of-products unit CA of the analog processing area ANP3 in Figure 10, by arranging the calculation cells MC3 in a column direction, the sum of the results of multiplying the first data and the second data can be passed as current to the wiring WBL, similar to the calculation cell MC1 in Figure 11A or the calculation cell MC2 in Figure 11B. As a result, the calculation unit FA can acquire this current and calculate the sum-of-products operation of multiple first data and multiple second data.

[0215] Furthermore, the calculation cell MC3 in Figure 11C may be changed to the calculation cell MC4 shown in Figure 11D. The calculation cell MC4 differs from the calculation cell MC3 in that the first terminal of the resistive switching element RV is connected to the wiring WXL, the transistor WTr is not provided, and the wiring SL does not extend. For this reason, the calculation cell MC4 has a smaller circuit area compared to the calculation cell MC3, and the cell density when using the calculation cell MC4 can be higher than the cell density when using the calculation cell MC3.

[0216] Furthermore, the resistive switching element RV can hold a continuous resistance value rather than a binary value, thereby allowing the first data to be held as a continuous value. Similarly, the potential applied to the wiring WXL can also be a continuous potential rather than just two possibilities (low-level potential or high-level potential), allowing the second data to also be held as a continuous value. Here, by applying a ground potential to the wiring WBL, and setting the conductance of the resistive switching element as G as the first data and the potential applied to the wiring WXL as V as the second data, the current I flowing through the resistive switching element RV becomes I = GV. In other words, the current I can be a value corresponding to the result of multiplying the first data and the second data, and therefore the calculation cell MC4 can perform the multiplication of the first data and the second data.

[0217] The resistance-changing element RV of the calculation cell MC4 may be replaced with an MTJ element, which will be described later. In particular, it is preferable that the MTJ element here can continuously change its resistance value, similar to the resistance-changing element RV of the calculation cell MC4.

[0218] Furthermore, the resistive switching elements RV in each of the calculation cells MC3 and MC4 may be replaced with phase-change memory (PCM) (not shown).

[0219] The arithmetic cell MC5 shown in Figure 11E is an example of a circuit that can be applied to the arithmetic cell MC shown in Figure 10, and is a circuit that uses an MTJ element used in STT-MRAM (Spin Transfer Torque Magnetoresitive Random Access Memory). The arithmetic cell MC5 has, as an example, the function of holding a first data as a binary value of "0" or "1", and the function of multiplying that first data with a second data as a binary value of "0" or "1".

[0220] The calculation cell MC5 has the same configuration as the calculation cell MC3 in Figure 11C, but with the resistive switching element RV replaced by the MTJ element RM1. Therefore, the connection configuration of the calculation cell MC5 can be found by referring to the explanation of the calculation cell MC3 in Figure 11C.

[0221] Furthermore, the MTJ element RM1 has a free layer and a fixed layer, and its resistance can be changed by the TMR (tunnel magnetoresistance) effect between the free layer and the fixed layer. Therefore, by assigning the magnitude of the resistance value of the MTJ element RM1 as "0" or "1" as the first data, the calculation cell MC5 can hold the first data using the MTJ element RM1.

[0222] Furthermore, by applying a potential to the wiring WXL corresponding to the second data, the transistor WTr can be turned on or off according to the second data. As a result, the calculation cell MC5 can, like the calculation cell MC3, supply current to the wiring WBL according to the result of multiplying the first data and the second data.

[0223] As shown in the sum-of-products unit CA of the analog processing area ANP3 in Figure 10, by arranging the calculation cells MC3 in a column direction, the sum of the results of multiplying the first data and the second data can be passed as current to the wiring WBL, similar to calculation cells MC1, MC2, MC3, or MC4. As a result, the calculation unit FA can acquire this current and calculate the sum-of-products operation of multiple first data and multiple second data.

[0224] The arithmetic cell MC6 shown in Figure 11F is an example of a circuit that can be applied to the arithmetic cell MC shown in Figure 10, and is a circuit using an MTJ element used in SOT-MRAM (Spin Orbit Torque Magnetoresitive Random Access Memory). The arithmetic cell MC6 has, for example, the function of holding a first data as a binary value of "0" or "1", and the function of multiplying the first data by a second data as a binary value of "0" or "1". Depending on the structure of the MTJ element, the arithmetic cell MC6 can hold the first data as a continuous value. Also, depending on the situation, the potential corresponding to the second data applied to the wiring WXL may be a continuous value.

[0225] The calculation cell MC6 includes, as an example, an MTJ element RM2, a transistor WTr1, a transistor WTr2, and a transistor WTr3.

[0226] Transistors WTr1 and WTr2 function as first data writing transistors, similar to the transistor WTr in the calculation cell MC1. Furthermore, transistors WTr1 and WTr3 function as transistors for outputting the result of multiplication as current. For example, transistors applicable to the transistor WTr shown in Figure 11A can be used as transistors WTr1 to WTr3.

[0227] Furthermore, the MTJ element RM2 is a three-terminal MTJ element that changes the resistance value of the TMR effect by generating a spin current through the spin Hall effect and determining the magnetization direction of the free layer. Here, it is assumed that the magnetization direction of the free layer can be determined by the direction of the current flowing between the first and second terminals of the MTJ element RM2, thereby determining the resistance value. Also, to read data from the MTJ element RM2, a fixed voltage can be applied between the first and third terminals, and the amount of current flowing between the first and third terminals can be measured.

[0228] The first terminal of transistor WTr1 is connected to the first terminal of MTJ element RM2, the second terminal of transistor WTr1 is connected to wiring WBL, and the gate of transistor WTr1 is connected to wiring WSL1. The first terminal of transistor WTr2 is connected to the second terminal of MTJ element RM2, the second terminal of transistor WTr1 is connected to wiring SL, and the gate of transistor WTr2 is connected to wiring WSL2. The first terminal of transistor WTr3 is connected to the third terminal of MTJ element RM2, the second terminal of transistor WTr3 is connected to wiring WXL, and the gate of transistor WTr3 is connected to wiring WSL3.

[0229] Wiring SL functions, for example, as wiring that provides a fixed potential. This fixed potential can be, for example, an intermediate potential that is higher than the low-level potential provided by wiring WBL and lower than the high-level potential provided by wiring WBL.

[0230] Each of the wirings WSL1 to WSL3 functions as a wiring that transmits a signal to control the switching between the on and off states of transistors WTr1 to WTr3.

[0231] When writing the first data to the calculation cell MC6, for example, a high-level potential is applied to wiring WSL1 and WSL2 to turn on transistors WTr1 and WTr2, and a low-level potential is applied to wiring WSL3 to turn off transistor WTr3. Next, the first data can be written to the calculation cell MC6 by transmitting the first data to wiring WBL. Specifically, for example, when the first data is "0", a low-level potential is applied to wiring WBL as the first data. Or, when the first data is "1", a high-level potential is applied to wiring WBL as the first data.

[0232] When multiplying the first data and the second data in the calculation cell MC6, for example, a high-level potential is applied to wiring WSL1 and WSL3 to turn on transistors WTr1 and WTr3, and a low-level potential is applied to wiring WSL2 to turn off transistor WTr2. Next, a readout potential is applied to wiring WBL, and the second data is transmitted to wiring WXL, thereby enabling the calculation cell MC6 to multiply the first data and the second data.

[0233] Specifically, the tunnel magnetoresistance between the first and second terminals of the MTJ element RM2 is determined by the first data ("0" or "1"). Furthermore, the voltage V between the first and third terminals of the MTJ element RM2 is the difference between the potential corresponding to the second data and the readout potential. Therefore, when the conductance between the first and second terminals of the MTJ element RM2 is G, the current I flowing between the first and second terminals of the MTJ element RM2 is I = GV. In other words, the current I can be a value corresponding to the result of multiplying the first data and the second data, and the calculation cell MC6 can perform the multiplication of the first data and the second data.

[0234] As shown in the sum-of-products unit CA of the analog processing area ANP3 in Figure 10, by arranging the calculation cells MC3 in a column direction, the sum of the results of multiplying the first data and the second data can be passed as current to the wiring WBL, similar to calculation cells MC1, MC2, MC3, MC4, or MC5. As a result, the calculation unit FA can acquire this current and calculate the sum-of-products operation of multiple first data and multiple second data.

[0235] <<Digital Processing Area DNP>> Next, we will explain a specific configuration example of the Digital Processing Area DNP described above.

[0236] Figure 12 is a block diagram showing an example configuration of the digital processing area (DNP) shown in Figures 1A to 7. The digital processing area (DNP) shown in Figure 12 has an arithmetic circuit (DGP). Figure 12 also shows a memory unit (SPD) to illustrate the operation of the arithmetic circuit (DGP).

[0237] A DGP (Digital Programming Circuit) is a digital arithmetic circuit that, for example, performs calculations upon input data, which is digital data, and outputs the result of those calculations as digital data. For instance, a DGP can perform multiply-accumulate operations in an artificial neural network and output the result of those operations as digital data.

[0238] Here, the memory unit SPD functions as a memory circuit that stores input data for calculations performed by the arithmetic circuit DGP. The memory unit SPD also functions as a memory circuit that stores output data, which is the result of calculations performed by the arithmetic circuit DGP. Here, the memory unit SPD is described as a memory circuit that holds digital data.

[0239] The arithmetic circuit DGP includes, for example, a switching unit SLC, a multiply-accumulate unit MUCA, and an arithmetic unit FC. The storage unit SPD includes, for example, a memory circuit unit ME11 and a memory circuit unit ME12.

[0240] The input terminal TM1i of the switching unit SLC is connected to wiring ILA, the input terminal TM2i of the switching unit SLC is connected to wiring ILB, and the output terminal TMo of the switching unit SLC is connected to wiring MLA. In addition, the input terminal TN1i of the sum-of-accumulate unit MUCA is connected to wiring MLA, the input terminal TN2i of the sum-of-accumulate unit MUCA is connected to wiring MLB, and the output terminal TNo of the sum-of-accumulate unit MUCA is connected to wiring CNL. The calculation unit FC is connected to wiring POL.

[0241] Memory circuit section ME11 is connected to wiring ILB. Memory circuit section ME11 is also connected to wiring CNL. Memory circuit section ME11 is also connected to wiring POL. Memory circuit section ME12 is connected to wiring MLB.

[0242] The wiring ILA functions, for example, as wiring for inputting external input data from the digital processing area DNP to the input terminal TM1i of the switching unit SLC. In Figure 12, "Pin" is shown as this input data. Pin can be the input value from a neuron in the input layer of an artificial neural network to a neuron in the next layer.

[0243] The ILB wiring, for example, functions as wiring for inputting input data read from the memory circuit section ME11 to the input terminal TM2i of the switching section SLC. In Figure 12, this input data is labeled "Phd". Phd can be the input value from a hidden layer neuron in an artificial neural network to the neuron of the next layer.

[0244] The MLA wiring, as an example, functions as a wiring for inputting digital data output from the output terminal TMo of the switching unit SLC to the input terminal TN1i of the multiply-accumulate unit MUCA. In Figure 12, this digital data is labeled as "Pin or Phd".

[0245] The MLB wiring, for example, functions as a wiring for inputting digital data read from the memory circuit section ME12 to the input terminal TN2i of the multiply-accumulate unit MUCA. Here, the digital data can be, for example, the weight coefficients in an artificial neural network. In Figure 12, these weight coefficients are represented as "W".

[0246] The wiring CNL functions, for example, as wiring for inputting digital data output from the output terminal TNo of the sum-of-accumulate unit MUCA to the memory circuit ME11. Here, the digital data can be, for example, the data resulting from a sum-of-accumulate operation performed in the sum-of-accumulate unit MUCA. In Figure 12, this data is labeled "Pma".

[0247] The wiring POL functions, for example, as wiring for inputting digital data read from the memory circuit ME11 to the arithmetic unit FC. Here, the digital data can be, for example, data input to the activation function in an artificial neural network within the arithmetic unit FC. In Figure 12, this data is labeled "Pma".

[0248] Furthermore, the wiring POL may also function, for example, as wiring for transmitting digital data processed by the arithmetic unit FC to the memory circuit unit ME11. Here, the digital data can be, for example, the data resulting from the activation function calculation in the artificial neural network performed by the arithmetic unit FC. In Figure 12, this data is labeled "Phd".

[0249] [Switching Unit SLC] The switching unit SLC has the function of selecting one of the input terminals TM1i and TM2i and outputting the data input to the selected terminal to the output terminal TMo. In other words, the switching unit SLC has the function of making one of the input terminals TM1i and TM2i conductive with the output terminal TMo, and making the other of the input terminals TM1i and TM2i non-conductive with the output terminal TMo.

[0250] In Figure 12, one input terminal TM1i and one input terminal TM2i of the switching unit SLC are shown, but the number of input terminals TM1i and TM2i of the switching unit SLC may be more than one. Similarly, in Figure 12, one output terminal TMo of the switching unit SLC is shown, but the number of output terminals TMo of the switching unit SLC may be more than one.

[0251] [Multiply-Accumulate Unit MUCA] The Multiply-Accumulate Unit MUCA has the function of calculating the product of digital data input to input terminal TN1i and digital data input to input terminal TN1i, as an example. The Multiply-Accumulate Unit MUCA also has the function of summing up the calculated products and outputting digital data corresponding to the value (result of the sum of products) to output terminal TNo.

[0252] An example of a multiply-accumulate MUCA is shown in Figure 13A. The multiply-accumulate MUCA shown in Figure 13A includes a multiplication circuit MP, an addition circuit AP, and a register RG.

[0253] In the multiply-accumulate unit MUCA shown in Figure 13A, the multiplication circuit MP calculates the product of digital data input from wiring MLA (e.g., Pin or Phd) and digital data input from wiring MLB (e.g., weight coefficient W). The result of the multiplication circuit MP is input to the adder circuit AP, and the output result of the adder circuit AP is held in register RG. After the output result of the adder circuit AP is held in register RG, when another product is calculated in the multiplication circuit MP, the value of that product and the value held in register RG are added together in the adder circuit AP, and the result is input to register RG. This operation is repeated to perform the multiply-accumulate operation. The result of the multiply-accumulate operation, Pma, is output as digital data to wiring CNL. Register RG is controlled by the clock signal input to wiring CLKL and the reset signal input to wiring RSTL.

[0254] For example, if the multiply-accumulate unit MUCA in Figure 13A is configured to perform a multiply-accumulate operation on 8-bit input data, the digital data processed by the multiply-accumulate unit MUCA in Figure 13A can be as shown in Figure 13B. Specifically, when the multiplier circuit MP receives 8-bit digital data from wiring MLA and 8-bit digital data from wiring MLB, the multiplier circuit MP outputs 16-bit digital data as the multiplication result. Similarly, when the adder circuit AP receives 16-bit digital data from the multiplier circuit MP and 17+α-bit digital data output from register RG, the adder circuit AP outputs 17+α-bit digital data as the addition result. Note that α represents the carry that occurs when addition is performed in the adder circuit AP.

[0255] In the digital processing area DNP shown in Figure 12, the multiply-accumulate unit MUCA is configured to perform multiply-accumulate operations based on the data transmitted to the wiring MLA and wiring MLB, respectively. However, for example, when performing multiply-accumulate operations in the multiply-accumulate unit MUCA, the same weight coefficient may be used repeatedly.

[0256] Therefore, the following describes a configuration in which multiple sum-of-products (MUCA) units, as shown in Figure 13A, are provided, and multiple sum-of-products operations are performed simultaneously using multiple identical weight coefficients.

[0257] Figure 14A shows an example configuration of the switching unit SLC and the multiply-accumulate unit MUCA shown in Figure 12. Figure 14A also shows the memory circuit unit ME12.

[0258] In Figure 14A, the sum-of-accumulate unit MUCA includes, as an example, sum-of-accumulate units MUCA_1 to MUCA_k (where k is an integer of 1 or more). For example, the circuits shown in Figure 13A can be applied to sum-of-accumulate units MUCA_1 to MUCA_k. Specifically, the sum-of-accumulate unit MUCA_h (where h is an integer between 1 and k) shown in Figure 14B can be applied to sum-of-accumulate units MUCA_1 to MUCA_k. For details on sum-of-accumulate unit MUCA_h, please refer to the explanation of the sum-of-accumulate unit MUCA in Figures 13A and 13B.

[0259] Furthermore, wiring ILA includes, for example, wiring ILA_1 to wiring ILA_k. Furthermore, wiring ILB includes, for example, wiring ILB_1 to wiring ILB_k. Furthermore, wiring MLA includes, for example, wiring MLA_1 to wiring MLA_k. Furthermore, wiring CNL includes, for example, wiring CNL_1 to wiring CNL_k.

[0260] Each of the multiple output terminals TMo of the switching unit SLC is connected one-to-one to wiring MLA_1 through MLA_k.

[0261] The input terminal TN1i of the sum-of-accumulate unit MUCA_1 is connected to wiring MLA_1, the input terminal TN2i of the sum-of-accumulate unit MUCA_1 is connected to wiring MLB, and the output terminal TNo of the sum-of-accumulate unit MUCA_1 is connected to wiring CNL_1. In addition, the input terminal TN1i of the sum-of-accumulate unit MUCA_k is connected to wiring MLA_k, the input terminal TN2i of the sum-of-accumulate unit MUCA_k is connected to wiring MLB, and the output terminal TNo of the sum-of-accumulate unit MUCA_k is connected to wiring CNL_k.

[0262] In other words, the input terminal TN1i of each of the multiply-accumulate units MUCA_1 to MUCA_k is connected one-to-one with each of the multiple output terminals TNo of the switching unit SLC.

[0263] Multiple digital data contained in a pin are transmitted to each of the wirings ILA_1 through ILA_k. Specifically, for example, multiple digital data contained in a pin are transmitted to each of the wirings ILA_1 through ILA_k, which are to be multiplied by the weight coefficients of the sum-of-products calculation performed in the sum-of-products calculation units MUCA_1 through MUCA_k.

[0264] Furthermore, multiple digital data contained in Phd are transmitted collectively to each of the wiring ILB_1 through ILB_k. Specifically, for example, multiple digital data contained in Phd are transmitted to each of the wiring ILB_1 through ILB_k, which are to be multiplied by the weight coefficients of the sum-of-accumulate calculation performed in the sum-of-accumulate calculation unit MUCA_1 through MUCA_k.

[0265] The switching unit SLC here, as an example, has the function of selecting either input terminal TM1i connected to wiring ILA_1 or input terminal TM2i connected to wiring ILB_1, and outputting the data input to the selected terminal to output terminal TMo connected to wiring MLA_1. Similarly, the switching unit SLC, as an example, has the function of selecting either input terminal TM1i connected to wiring ILA_k or input terminal TM2i connected to wiring ILB_k, and outputting the data input to the selected terminal to output terminal TMo connected to wiring MLA_k.

[0266] Wiring MLA_1 functions, for example, as a wire for inputting digital data output from the first output terminal TMo of the switching unit SLC to the input terminal TN1i of the sum-of-accumulate unit MUCA_1. Similarly, wiring MLA_k functions, for example, as a wire for inputting digital data output from the kth output terminal TMo of the switching unit SLC to the input terminal TN1i of the sum-of-accumulate unit MUCA_k. In Figure 14A, this digital data is labeled A(1) and A(k), respectively. Furthermore, A(1) and A(k) can be some of the digital data in Pin or some of the digital data in Phd as described above.

[0267] Wiring CNL_1 functions, for example, as wiring for inputting digital data output from output terminal TNo of the sum-of-accumulate unit MUCA_1 to the memory circuit unit ME12. Similarly, wiring CNL_k functions, for example, as wiring for inputting digital data output from output terminal TNo of the sum-of-accumulate unit MUCA_k to the memory circuit unit ME12. The digital data referred to here can be, for example, the data resulting from a sum-of-accumulate operation performed in the sum-of-accumulate unit MUCA. In Figure 14A, this data is indicated as Pma(1) and Pma(k). Note that the aforementioned Pma can be a combination of Pma(1) to Pma(k).

[0268] By applying the configuration of the switching unit SLC and the sum-of-accumulate unit MUCA shown in Figure 14A to the digital processing area DNP in Figure 12, multiple identical weight coefficients can be input to each of the sum-of-accumulate units MUCA_1 to MUCA_k, and the sum-of-accumulate operation can be performed simultaneously in each of the sum-of-accumulate units MUCA_1 to MUCA_k.

[0269] [Calculation Unit FC] The calculation unit FC has the function of performing calculations on an activation function for which Pma, read from the memory circuit unit ME11, is assigned as a variable. The calculation unit FC also has the function of transmitting Phd, which is the result of the calculation of the activation function, to the memory circuit unit ME11. In addition to activation functions, the calculation unit FC may also have the function of performing pooling and normalization calculations.

[0270] [Memory Circuit Section ME11 and Memory Circuit Section ME12] The memory circuit section ME11 functions as a storage device for holding input data Phd for input to the multiply-accumulate unit MUCA and output data Pma output from the multiply-accumulate unit MUCA in the digital processing area DNP. The memory circuit section ME12 functions as a storage device for holding weight coefficients W for input to the multiply-accumulate unit MUCA.

[0271] In particular, the memory circuit section ME12 is preferably located near the sum-of-accumulate unit MUCA because it reads out the weight coefficient W and transmits it to the sum-of-accumulate unit MUCA. For example, the memory circuit section ME12 is preferably stacked above or below the sum-of-accumulate unit MUCA.

[0272] For information on circuits applicable to memory circuit section ME11 and memory circuit section ME12, please refer to the description of storage section SPD.

[0273] <<Example Configuration of Memory Unit SPD>> Next, we will explain a specific example configuration of the memory unit SPD described above.

[0274] The memory circuit MEX in Figure 15A is an example of the circuit configuration of the memory circuit in the storage unit SPD.

[0275] The memory circuit MEX has a cell array MEA. The cell array MEA has memory cells MD arranged in a matrix of u rows and v columns (where u is an integer greater than or equal to 1, and v is an integer greater than or equal to 1). Figure 15A shows, in part, memory cells MD[1,1], MD[u,1], MD[1,v], and MD[u,v]. Figure 15A also shows wiring WWL_1 to WWL_u, wiring RWL_1 to RWL_u, wiring WL_1 to WL_v, and wiring RL_1 to RL_v. Furthermore, Figure 15A shows circuits WWD, RBD, WBD, and RBD. Finally, Figure 15A shows wiring DIL connected to circuit WBD and wiring DOL connected to circuit RBD.

[0276] The memory cell MD[h,k] located in the h row and k column (where h is an integer between 1 and u, and k is an integer between 1 and v) is connected to the wiring WWL_h, RWL_h, WL_k, and RL_k.

[0277] Circuit WWD is connected to each of the wirings WWL_1 through WWL_u. Similarly, circuit RWD is connected to each of the wirings RWL_1 through RWL_u. Furthermore, circuit WBD is connected to each of the wirings WL_1 through WL_v. And circuit RBD is connected to each of the wirings RL_1 through RL_v.

[0278] Circuit WWD functions, for example, as a write word line driver circuit. Similarly, circuit RWD functions, for example, as a read word line driver circuit. Furthermore, circuit WBD functions, for example, as a write bit line driver circuit. And circuit RBD functions, for example, as a read bit line driver circuit.

[0279] Furthermore, the circuit WBD has the function of receiving input data transmitted to wiring DIL and transmitting said input data to one of the wirings WL_1 to WL_v selected from the wirings. In addition, the circuit WBD has the function of selecting one of the wirings RL_1 to RL_v and transmitting the read data from the memory cell MD flowing through the selected wiring to wiring DOL.

[0280] For example, when the memory circuit MEX shown in Figure 15A is applied to the memory circuit ME11 in Figure 12, the wiring ILB is connected to the wiring DOL in Figure 15A, and the wiring CNL is connected to the wiring DIL in Figure 15A. Also, when the memory circuit MEX shown in Figure 15A is applied to the memory circuit ME12 in Figure 12, the wiring MLB is connected to the wiring DOL in Figure 15A.

[0281] Next, we will explain the memory cells that can be applied to memory cell MD.

[0282] Figure 15B illustrates an example of a circuit configuration applicable to each of the memory cells MD[1,1] to MD[u,v] of the memory circuit MEX. In Figure 15B, memory cell MD has transistor M1, transistor M2, transistor M3, and a capacitive element C1. The memory cell MD shown in Figure 15B has a gain cell configuration with three transistors. In particular, when transistors M1 and M3 are OS transistors, memory cell MD may be called NOSRAM (registered trademark).

[0283] In particular, by using OS transistors in one or more of the transistors M1 to M3 selected from among transistors M1 to M3, the leakage current of the selected transistors can be suppressed, thereby reducing the power consumption of the arithmetic circuit. Specifically, when transistor M1 is in a non-conductive state, the leakage current from the holding nodes (for example, the first terminal of transistor M1, the first terminal of the capacitive element C1, and the gate of transistor M2) to the wiring WL can be made very small, so the refresh operation of the potential of the holding nodes can be reduced. Furthermore, by reducing the refresh operation, the power consumption of the arithmetic circuit can be reduced. In particular, by using IO transistors, which are a type of OS transistor, in one or more of the transistors M1 to M3 selected from among transistors M1 to M3, the on-current of the selected transistors can be increased. By increasing the on-current, the transmission speed of signals input and output to the memory cell MD can be increased, and as a result, the driving speed of the memory circuit MEX can be increased.

[0284] Furthermore, it is preferable that each of the circuits WWD, RWD, WBD, and RBD includes a CMOS circuit. It is also preferable that the CMOS circuit has a configuration that includes a Si transistor. For example, when fabricating a p-channel type transistor, it is preferable to use a Si transistor rather than an OS transistor from the viewpoint of reliability. For this reason, it is preferable that the circuits WWD, RWD, WBD, and RBD are fabricated on a semiconductor substrate made of silicon, and that the memory cell MD is fabricated above the circuits WWD, RWD, WBD, and RBD.

[0285] Incidentally, when semiconductor devices are highly integrated onto a chip, heat may be generated on the chip due to the operation of the circuits. This heat can cause the temperature of transistors to rise, which can change the characteristics of those transistors, leading to changes in field-effect mobility and a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so changes in field-effect mobility due to temperature changes are less likely to occur, and a decrease in operating frequency is also less likely. Furthermore, OS transistors tend to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage, even at high temperatures. Therefore, by using OS transistors, calculations and processing can be easily performed even in high-temperature environments. For this reason, when constructing a semiconductor device that is resistant to heat generated by drive circuits such as WWD, RWD, WBD, and RBD on a semiconductor substrate made of silicon, it is preferable to use OS transistors as the transistors included in the circuits provided above the drive circuits.

[0286] In Figure 15B, back gates are shown for transistors M1 to M3. Although the connection configuration of the back gates is not shown, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor with a back gate, the gate and the back gate may be connected in order to increase the on-current of the transistor. That is, for example, the gate and the back gate of transistor M1 may be connected. Alternatively, in a transistor with a back gate, for example, in order to change the threshold voltage of the transistor or to reduce the off-current of the transistor, wiring may be provided to connect the back gate of the transistor to an external circuit, and the external circuit may be configured to apply a potential to the back gate of the transistor.

[0287] Furthermore, although transistors M1 to M3 shown in Figure 15B have back gates, the memory cell MD in Figure 15B may have a configuration in which transistors M1 to M3 do not have back gates, that is, single-gate transistors. Also, some transistors may have a configuration in which they have back gates, while other transistors may not have back gates. The presence or absence of back gates in transistors can be explained similarly for other transistors in this specification.

[0288] The transistors M1 to M3 shown in Figure 15B are n-channel transistors, but the configuration of the memory cell MD is not limited to this. For example, transistors M2 and M3 may be n-channel transistors, and transistor M1 may be replaced with a p-channel transistor. The polarity (also called conduction type) of whether a transistor is p-channel or n-channel can be explained similarly for other transistors in this specification.

[0289] The first terminal of transistor M1 is connected to the gate of transistor M2 and the first terminal of capacitive element C1. The second terminal of transistor M1 is connected to wiring WL, and the gate of transistor M1 is connected to wiring WWL. Also, the first terminal of transistor M2 is connected to the first terminal of transistor M3, and the second terminal of transistor M2 is connected to wiring CVLB. The second terminal of transistor M3 is connected to wiring RL, and the gate of transistor M3 is connected to wiring RWL.

[0290] Wiring CVLA functions as wiring that supplies a fixed potential. This fixed potential can be, for example, a high-level potential, a low-level potential, a ground potential, or a negative potential. Similarly, wiring CVLB also functions as wiring that supplies the fixed potentials listed above. Note that the potential transmitted to wiring CVLA and wiring CVLB may not be a fixed potential, but rather a variable potential (for example, also called a pulse voltage or pulse signal).

[0291] In the memory cell MD shown in Figure 15B, by using an OS transistor for transistor M1, the current flowing between the source and drain of the off-state transistor M1 (sometimes called leakage current) can be made extremely small. In other words, the memory cell MD shown in Figure 15B can be used as a non-volatile memory by applying an OS transistor for transistor M1 and using its characteristic of extremely low leakage current to hold charge corresponding to the data within the memory circuit.

[0292] Furthermore, in addition to the storage cell MD shown in Figure 15B, the storage cell MD shown in Figure 15C can be applied to the storage cells MD[1,1] to MD[u,v] of the memory circuit MEX in Figure 15A. The storage cell MD in Figure 15C differs from the storage cell MD in Figure 15B in that the wiring WL and wiring RL are combined into a single wiring WR. The configuration of the storage cell MD shown in Figure 15C allows for fewer wirings extending in the column direction compared to the configuration of the storage cell MD shown in Figure 15B, thus reducing the circuit area. In some cases, it may also allow for a higher recording density in the memory storage section.

[0293] The circuit configurations applicable to the memory circuit MEX in Figure 15A are not limited to the storage cell MD shown in Figures 15B and 15C. For example, the storage cell MD shown in Figure 16A can be applied to the memory circuit MEX in Figure 15A. In Figure 16A, the storage cell MD has a transistor M1 and a capacitive element C1. The storage cell MD shown in Figure 16A has a configuration with one transistor. Circuits composed of one transistor and one capacitive element in this way are sometimes called DRAM. In particular, when transistor M1 is an OS transistor, the storage cell MD is sometimes called DOSRAM (registered trademark).

[0294] Figure 16A shows a memory cell MD having a transistor M1 and a capacitive element C1. The aforementioned OS transistor can be used for transistor M1. Furthermore, transistor M1 has the functions of both a write transistor and a read transistor.

[0295] In Figure 16A, the first terminal of transistor M1 is connected to the first terminal of capacitive element C1, the second terminal of transistor M1 is connected to wiring WR, and the gate of transistor M1 is connected to wiring WWL. Also, the second terminal of capacitive element C1 is connected to wiring CVLA.

[0296] The wiring WWL shown in Figure 16A functions as a write word line and a read word line. Therefore, when applying the storage cell MD of Figure 16A to the storage cell MD of the memory circuit MEX of Figure 15A, it is preferable that the circuit WWD shown in Figure 15A functions as a write word line driver circuit and a read word line driver circuit. In this case, the memory circuit MEX of Figure 15A does not need to be provided with the circuit RWD and wiring RWL_1 to wiring RWL_u.

[0297] Furthermore, the wiring WR shown in Figure 16A combines wiring WL and wiring RL into a single wiring, and functions as a write bit line and a read bit line. For this reason, when applying the storage cell MD of Figure 16A to the storage cell MD of the memory circuit MEX of Figure 15A, it is preferable that each of the wirings WL_1 to WL_v shown in Figure 15A is connected to the circuit RBD as wiring WR_1 to WR_v. In this case, the memory circuit MEX of Figure 15A does not need to have wirings RL_1 to RL_v.

[0298] Furthermore, a circuit configuration applicable to the memory circuit MEX in Figure 15A may be, for example, a 2T (transistor) 1C (capacitor element) type NOSRAM circuit configuration, as shown in the memory cell MD in Figure 16B. Figure 16B illustrates a memory circuit MEX having transistors M1, M2 and C1. Transistors M1 and M2 can be the OS transistors described above. Transistor M1 functions as a write transistor, and transistor M2 functions as a read transistor.

[0299] In Figure 16B, the first terminal of transistor M1 is connected to the gate of transistor M2 and the first terminal of capacitive element C1. The second terminal of transistor M1 is connected to wiring WL, and the gate of transistor M1 is connected to wiring WWL. The first terminal of transistor M2 is connected to wiring RL, and the second terminal of transistor M2 is connected to wiring SL. The second terminal of capacitive element C1 is connected to wiring RWL.

[0300] The wiring SE shown in Figure 16B functions as a source wire. Note that a fixed or variable potential may be supplied to the wiring SE. Furthermore, an arbitrary amount of current may be supplied to the wiring SE.

[0301] Furthermore, although Figure 16B shows the circuit configuration of a 2T1C type NOSRAM, a memory cell according to one aspect of the present invention may also have the configuration of a 2T0C type NOSRAM. Specifically, the memory cell MD shown in Figure 16C can be applied to the memory cell MD of the memory circuit MEX in Figure 15A.

[0302] The memory cell MD in Figure 16C differs from the memory cell MD in Figure 16B in that it does not have a capacitive element C1. Also, although the wiring RWL is not shown in Figure 16C, the wiring RWL can be connected to the back gate of transistor M2, for example. By connecting the wiring RWL to the back gate of transistor M2, the threshold voltage of transistor M2 can be adjusted by the potential supplied by the wiring RWL. This allows control of switching between the on and off states of transistor M2, and thus transistor M2 can be selected as a readout transistor by the wiring RWL.

[0303] A circuit configuration applicable to the memory circuit MEX in Figure 15A may be, for example, a circuit combining NOSRAMs having three transistors, as shown in the memory cell MD in Figure 16D. The memory cell MD in Figure 16D has a memory cell MCP and a memory cell MCN. The memory cells MCP and MCN hold data with their logic inverted relative to each other. In other words, the memory cells MCP and MCN function as complementary memory cells.

[0304] The configurations of memory cells MCP and MCN can be found by referring to the description of memory cell MD shown in Figure 15B. The differences between memory cells MCP and MCN shown in Figure 16D and memory cell MD shown in Figure 15B are described below.

[0305] The gates of transistor M1, which contains memory cells MCP and MCN, are connected to wiring WWL. The second terminals of capacitive elements C1, which also contain memory cells MCP and MCN, are connected to wiring CVLA. The gates of transistor M3, which also contains memory cells MCP and MCN, are connected to wiring RWL. The second terminal of transistor M2, which also contains memory cells MCP and MCN, is connected to wiring CVLB.

[0306] In the memory cell MCP, the second terminal of transistor M1 is connected to wiring WLP. Also, the second terminal of transistor M3 is connected to wiring RLP.

[0307] Furthermore, in the memory cell MCN, the second terminal of transistor M1 is connected to wiring WLN. Also, the second terminal of transistor M3 is connected to wiring RLN.

[0308] The wiring WLP and WLN shown in Figure 16D function as write bit lines, similar to the wiring WL shown in Figure 15A. Furthermore, the wiring RLP and RLN shown in Figure 16D function as read bit lines, similar to the wiring RL shown in Figure 15A.

[0309] Furthermore, transistor M3 can be the same OS transistor as transistors M1 and M2, as described above.

[0310] A circuit configuration applicable to the memory circuit MEX in Figure 15A can be, for example, a circuit including transistor M1, transistor Mp, transistor Mn, and capacitive element C1, as shown in the memory cell MD in Figure 16E. The memory cell MD in Figure 16E is a type of sample-and-hold circuit and has the function of outputting data with the logic of the held data inverted as read data.

[0311] Transistors M1 and Mn are n-channel transistors, while transistor Mp is a p-channel transistor. Transistors M1 and Mp can be Si transistors or OS transistors, and transistor Mn can be a Si transistor.

[0312] The first terminal of transistor M1 is connected to the first terminal of capacitive element C1, the gate of transistor Mp, and the gate of transistor Mn. The second terminal of transistor M1 is connected to wiring WL, and the gate of transistor M1 is connected to wiring WWL. The first terminal of transistor Mp is connected to the first terminal of transistor Mn and wiring RL. The second terminal of transistor Mp is connected to wiring VDE, and the second terminal of transistor Mn is connected to wiring VSE. The second terminal of capacitive element C1 is connected to wiring CVLA.

[0313] Wiring VDE, for example, functions as wiring that provides a fixed potential. This fixed potential can be, for example, a high-level potential. Wiring VSE, for example, also functions as wiring that provides a fixed potential. This fixed potential can be, for example, a low-level potential.

[0314] As shown in Figure 16D, the connection configuration of transistor Mp and transistor Mn, along with the potential supplied by wiring VDE and wiring VSE, allows transistor Mp and transistor Mn to function as an inverter.

[0315] In Figure 16D, wiring WL functions as a write bit line. Wiring RL functions as a read bit line. Wiring WWL functions as a write word line.

[0316] The CVLA wiring functions as wiring that supplies a fixed potential. This fixed potential can be, for example, a high-level potential, a low-level potential, a ground potential, or a negative potential. The potential transmitted to the CVLA wiring may not be a fixed potential, but rather a variable potential (for example, a data-dependent potential, also called a pulse voltage or pulse signal).

[0317] Furthermore, the memory cell MD shown in Figure 16D can sometimes be treated as an arithmetic cell, similar to the arithmetic cell MC in Figure 10 described above. In other words, the memory cell MD in Figure 16D can sometimes be used as an arithmetic cell MC in the analog processing area ANP3 of Figure 10.

[0318] Aside from the memory cell MD shown in Figures 16A to 16D, a circuit configuration applicable to the memory circuit MEX in Figure 15A can be an SRAM having the configuration of the arithmetic cell MC1 shown in Figure 11A. The memory cell MD shown in Figure 16F is an example of a memory cell provided in an SRAM, and includes a transistor M1, a transistor M1b, inverters IV1 and IV2, a capacitive element C2, a capacitive element C2b, a transistor M4, and a transistor M4b.

[0319] The first terminal of transistor M4 is connected to the first terminal of transistor M1, the input terminal of inverter IV1, and the output terminal of inverter IV2. The second terminal of transistor M4 is connected to the first terminal of capacitive element C2. The first terminal of transistor M4b is connected to the first terminal of transistor M1b, the output terminal of inverter IV1, and the input terminal of inverter IV2. The second terminal of transistor M4b is connected to the first terminal of capacitive element C2b. The second terminals of capacitive element C2 and C2b are connected to wiring CVLC. The gates of transistor M4 and transistor M4b are connected to wiring BKL.

[0320] Furthermore, in the memory cell MD of Figure 16F, wiring WL and wiring WLb function as write / read bit lines. In particular, wiring WL and wiring WLb form a data line pair for complementary data handling. Also, wiring WWL functions as a write word line, similar to the memory cell MD of Figures 16A to 16E. Therefore, by applying a high-level potential to wiring WWL to turn on transistors M1 and M1b, and writing data from wiring WL and wiring WLb, the memory cell MD can complementaryly hold the data through an inverter loop including inverters IV1 and IV2.

[0321] CVLC wiring, for example, functions as wiring that provides a fixed potential. This fixed potential can be, for example, a high-level potential, a low-level potential, or a ground potential.

[0322] Furthermore, in the memory cell MD of Figure 16F, the wiring BKL has the function of a wiring for temporarily backing up the data held in the inverter loop of the memory cell MD to the capacitive elements C2 and C2b, and also the function of a wiring for restoring the data backed up in the capacitive elements C2 and C2b to the inverter loop. By backing up the data held in the inverter loop with transistors M4 and M4b and capacitive elements C2 and C2b, the inverter loop, consisting of inverters IV1 and IV2, can be temporarily stopped. As a result, even if the power supply to the inverter loop is stopped, the data can be retained by transistors M4 and M4b and capacitive elements C2 and C2b.

[0323] Furthermore, the storage cell in the SRAM according to one aspect of the present invention may not include a capacitive element C2, a capacitive element C2b, a transistor M4, and a transistor M4b.

[0324] By using OS transistors in the memory cell MD shown in Figures 16A to 16E and the arithmetic cell MC1 (SRAM) in Figure 11A, and by using OS transistors in the analog processing area ANP and the digital processing area DNP, the memory unit SPD and the analog processing area ANP and digital processing area DNP can be manufactured in the same process. This reduces the number of steps required to manufacture processor NP1 or processor NP2, thereby lowering production costs. Furthermore, in the processor NPA shown in Figure 4, the circuit area of ​​the processor NPA can be reduced by stacking the multiply-accumulate unit CA above the memory unit SPD.

[0325] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0326] (Embodiment 2) In this embodiment, an example of the cross-sectional configuration of the semiconductor device described in the above embodiment will be explained.

[0327] <Example of Cross-Sectional Device Configuration> Figure 17 is a schematic cross-sectional diagram showing an example of the configuration of the analog processing region (ANP) described in the above embodiment. In Figure 17, the analog processing region (ANP) includes, as an example, a circuit layer PHRL and a circuit layer OMAL located above the circuit layer PHRL.

[0328] Furthermore, the following cross-sectional configuration example describes an example where the circuit layer OMAL includes the calculation cell IM. Note that the following cross-sectional configuration example can also be applied to the drive cell IMD, which has a circuit configuration similar to that of the calculation cell IM.

[0329] The circuit layer PHRL can be constructed, for example, by providing circuit elements such as transistors and capacitive elements on a substrate. Furthermore, a semiconductor substrate (for example, a single-crystal substrate made of silicon or germanium) can be used as the substrate. In addition to semiconductor substrates, other materials that can be used include, for example, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, or base film.

[0330] In particular, by using a silicon semiconductor substrate as the substrate included in the circuit layer PHRL, the transistors included in the drive circuits WCS, XCS, and WSD, the multiply-accumulate unit CA, the calculation unit FA, and the AD conversion unit ADC shown in Figure 8 can be formed on the semiconductor substrate as Si transistors. Since Si transistors have high field-effect mobility, they can carry large on-currents. This makes it possible to increase the driving speed of each of the drive circuits listed above, widen the signal range, and so on.

[0331] In Figure 17, transistor 100, which is part of the circuit layer PHRL, is shown as an example of a Si transistor. By using a Si transistor for transistor 100, a CMOS (Complementary MOS) circuit including p-channel and n-channel transistors can be configured in the circuit layer PHRL. In particular, it is preferable that each of the drive circuits described in the above embodiment be formed in the circuit layer PHRL as such a CMOS circuit.

[0332] Furthermore, the laminated structure of circuit layer PHRL and circuit layer OMAL can be fabricated by directly forming circuit layer OMAL on top of circuit layer PHRL. Alternatively, circuit layer OMAL can be fabricated by mounting the substrate on top of circuit layer PHRL, with circuit elements such as transistors and capacitive elements provided on the substrate. When circuit layer OMAL is directly formed on top of circuit layer PHRL, it is preferable that circuit layer OMAL includes an OS transistor. An I / O transistor can be used as the OS transistor. Since the OS transistor can be formed on a substrate such as a semiconductor substrate, an insulating substrate, or a conductive substrate, or on a film such as a conductive film, an insulating film, or a semiconductor film, it can be easily provided on a substrate (on circuit layer PHRL) on which a Si transistor is formed.

[0333] Alternatively, a p-channel transistor may be provided as a Si transistor in the circuit layer PHRL, and an n-channel transistor may be provided as an OS transistor in the circuit layer OMAL, thereby configuring a CMOS circuit in the analog processing region ANP.

[0334] Furthermore, when forming circuit elements such as transistors and capacitive elements on a substrate as the circuit layer OMAL, and mounting the substrate on the circuit layer PHRL, a flip-chip bonding method or a wire bonding method can be used. Alternatively, the circuit layer OMAL may be mounted on the circuit layer PHRL by providing a first bonding layer on the circuit layer PHRL side, providing a second bonding layer on the circuit layer OMAL substrate, and bonding the first bonding layer and the second bonding layer using either or both of the surface activation bonding method and the hydrophilic bonding method. In particular, when copper (Cu) is used as the conductor in both the first and second bonding layers, and the copper of the first bonding layer and the copper of the second bonding layer are directly bonded, this is called Cu-Cu (copper-copper) direct bonding.

[0335] The transistor 100 is provided on a substrate 101 and includes a conductive layer 131 that functions as a gate, an insulating layer 161 and an insulating layer 111 that functions as a gate insulating film, a semiconductor region 171 that includes a part of the substrate 101, and a low-resistance region 172a and a low-resistance region 172b that include a part of the substrate and function as a source region or drain region.

[0336] Furthermore, the semiconductor region 171, the low-resistance region 172a, and the low-resistance region 172b shown in Figure 17 are each formed by providing an element isolation layer 102 on the substrate 101. It can also be said that the element isolation layer 102 is provided to separate the multiple transistors formed on the substrate 101. The element isolation layer 102 can be formed, for example, using the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, or the mesa isolation method.

[0337] Furthermore, the transistor 100 shown in Figure 17 may, as an example, have a convex shape in the semiconductor region 171 (part of the substrate 101) where the channel is formed, as shown in the schematic cross-sectional view of Figure 18. Figure 18 is a schematic cross-sectional view of the transistor 100 in the channel width direction. The side and top surfaces of the semiconductor region 171 are covered by a conductive layer 131 via an insulating layer 161. The conductive layer 131 may be made of a material that adjusts the work function. Such a transistor 100 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulating layer that is in contact with the upper part of the convex portion and functions as a mask for forming the convex portion. In addition, although the case of forming the convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0338] Furthermore, in Figure 18, a conductive layer 136 is provided so as to be in contact with the conductive layer 131 and to fill the opening formed in the insulating layer 112. The conductive layer 136 functions as a contact plug or wiring.

[0339] Note that the transistor 100 shown in Figures 17 and 18 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0340] The analog processing region (ANP) may include a wiring layer with interlayer films, wiring, and plugs. Multiple wiring layers may be provided depending on the design. Furthermore, in this specification, the wiring and the plugs connected to the wiring may be integrated into a single unit. That is, there may be cases where a portion of the conductive layer functions as wiring, and cases where a portion of the conductive layer functions as a plug.

[0341] For example, on the transistor 100, insulating layers 112, 181, and 113 are sequentially stacked as interlayer films. A conductive layer 132 is embedded in the insulating layer 112. A conductive layer 133 is embedded in the insulating layer 181 and the insulating layer 113. The conductive layers 132 and 133 function as contact plugs or wiring.

[0342] Furthermore, the insulating layer, which functions as an interlayer film, may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulating layer 112 may be planarized by a planarizing treatment using chemical mechanical polishing (CMP) to improve its flatness.

[0343] Wiring layers may be provided on the insulating layer 113 and the conductive layer 133. For example, in Figure 17, insulating layers 182, 114, 115, 183, 116, and 211 are sequentially laminated on the insulating layer 113 and the conductive layer 133. Furthermore, a conductive layer 134 is formed on insulating layers 182, 114, and 115, and a conductive layer 230 is formed on insulating layers 183, 116, and 211. Note that conductive layers 134 and 230 each function as contact plugs or wiring.

[0344] An insulating layer 281 is provided on the insulating layer 211. Preferably, contact plugs or wiring for connecting to an upper circuit (for example, a circuit element included in a circuit included in the circuit layer OMAL) are embedded in the insulating layer 116, insulating layer 211, and insulating layer 281.

[0345] Next, we will describe an example of the configuration of a calculation cell included in the circuit layer OMAL shown in Figure 17. Note that the calculation cell shown in Figure 17 is an example of the calculation cell IM shown in Figure 18, and Figure 17 shows transistors F1, F2, and F5.

[0346] In the circuit layer OMAL of Figure 17, transistors F2 and F5 are formed on the insulating layer 281. Transistor F1 is formed on the insulating layer 284. Capacitive element C5 is formed on the insulating layer 287. The insulating layer 287 is located above the insulating layer 284, and the insulating layer 284 is located above the insulating layer 281. Therefore, it can be said that the capacitive element C5 is located above transistor F1, and transistor F1 is located above transistors F2 and F5.

[0347] Incidentally, each of the insulating layers 181 to 183 and the insulating layers 281 to 287 shown in FIG. 17 preferably functions as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, the insulating layers 181 to 183 and the insulating layers 281 to 287 preferably use an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N ２ O, NO or NO ２ ), and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules) (the above oxygen is difficult to permeate). Regarding the materials applicable to each of the insulating layers 181 to 183 and the insulating layers 281 to 287, reference can be made to the description of the insulating layer of the constituent material of the transistor.

[0348] Further, on one of the source or drain of the transistor F2, a conductive layer serving as a contact plug is connected to a conductive layer that becomes the wiring VE0. Also, the other of the source or drain of the transistor F2 is formed so as to be shared with one of the source or drain of the transistor F5. Further, on the other of the source or drain of the transistor F5, one of the source or drain of the transistor F1 is connected via a conductive layer 234_4, a conductive layer 235_2, and a conductive layer 235_4 that function as contact plugs. In FIG. 17, as an example, a conductive layer that becomes the wiring WCL is provided between the conductive layer 234_4 and the conductive layer 235_2.

[0349] Further, the gate electrode of the transistor F1, as an example, extends along the direction from the front to the back in FIG. 17 as a conductive layer that becomes the wiring WSL.

[0350] Furthermore, the gate electrode of transistor F2 is connected to the other source or drain electrode of transistor M1 via conductive layers 234_3, 235_1, and 235_3, which function as contact plugs. In Figure 17, as an example, a conductive layer is provided between conductive layer 235_1 and conductive layer 235_3, which is one of the pair of electrodes of the capacitive element C5.

[0351] The conductive layer that functions as one of the pair of electrodes of the capacitive element C5 is formed to be embedded in the insulating layer 219 on the insulating layer 287. Above the conductive layer that is one of the pair of electrodes of the capacitive element C5, an insulating layer 441 that functions as the dielectric of the capacitive element C5 is provided. Above the insulating layer 441, a conductive layer that will become the wiring XCL is provided. The region of the conductive layer that will become the wiring XCL that overlaps with the conductive layer that will become one of the pair of electrodes of the capacitive element C5 functions as the other of the pair of electrodes of the capacitive element C5.

[0352] By embedding the conductive layer, which functions as one of the pair of electrodes of the capacitive element C5, into the insulating layer 219, the conductive layer and the insulating layer 219 can be made flush and planar. As a result, the insulating layer, which functions as a dielectric, and the conductive layer, which functions as the other of the pair of electrodes of the capacitive element C5, can be formed with good flatness on the upper surfaces of the conductive layer and the insulating layer 219, which have good flatness. By improving the flatness of both of the pair of electrodes of the capacitive element C5 and the insulating layer, which functions as a dielectric, localized electric field concentration can be suppressed, and as a result, leakage current between the pair of electrodes of the capacitive element C5 can be prevented. Furthermore, one of the pair of electrodes of the capacitive element C5 (the lower electrode in this case) is provided in a smaller area than the other of the pair of electrodes of the capacitive element C5 (the upper electrode in this case). This configuration makes it possible to suppress localized electric field concentration that can be applied to the dielectric film (insulating film sandwiched between a pair of electrodes) of the capacitive element C5, thereby enabling the realization of a highly reliable semiconductor device.

[0353] For example, in the calculation cell IM in Figure 8, by configuring the capacitive element C5 as described above, leakage current between the pair of electrodes of the capacitive element C5 that occurs between the gate of transistor F2 and the wiring XCL can be prevented. Therefore, in the calculation cell IM, fluctuations in the gate potential of transistor F2 due to this leakage current can be prevented, and the potential can be maintained for a long period of time. In addition, localized electric field concentration can be suppressed with respect to the dielectric of the capacitive element C5, thereby increasing the reliability of the calculation cell IM. The same applies to the capacitive element C5D of the drive cell IMD in Figure 8.

[0354] Furthermore, in the configuration example shown in Figure 17, the conductive layer functioning as wiring XCL and the conductive layer functioning as wiring WSL each extend along the direction from the front to the back of Figure 17.

[0355] As shown in Figure 17, a conductive layer functioning as a back gate may be provided below the island-shaped semiconductor layer of each transistor F1, F2, and F5. By providing a back gate to each transistor and changing the potential of the back gate, the threshold voltage of that transistor can be changed. For example, by providing a back gate to transistor F1, the influence of the external electric field is reduced, and it can maintain a stable off state. Therefore, the data written to the capacitive element C5 can be held stably. In this way, by providing a back gate, the operation of the arithmetic cell IM is stabilized, and the reliability of the circuit layer OMAL including the arithmetic cell IM can be increased. When a back gate is provided to a transistor, it is preferable not to provide a conductive layer near the back gate in order to avoid the formation of parasitic capacitance with the back gate.

[0356] It is preferable that each of transistors F1, F2, and F5 is an OS transistor in which an oxide semiconductor, a type of metal oxide, is used in the semiconductor layer where the channel is formed. Since oxide semiconductors have a band gap of 2 eV or more, the off-current is significantly low. Therefore, the power consumption of the arithmetic cell can be reduced. Therefore, the power consumption of the analog processing region ANP, which includes the arithmetic cell IM, can be reduced.

[0357] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit minimal characteristic fluctuations. For example, the off-current hardly increases even in high-temperature environments. Specifically, the off-current hardly increases even in environments between room temperature (e.g., 25°C) and 200°C. Also, the on-current does not easily decrease even in high-temperature environments. In addition, the arithmetic cell shown in Figure 17 can hold the first data, thus also functioning as a memory device. For this reason, the arithmetic cell operates stably even in high-temperature environments, resulting in high reliability.

[0358] In particular, by using indium oxide for the oxide semiconductor mentioned above, that is, by making transistors F1, F2, and F5 each I / O transistors, it is possible to create transistors with low off-current and high on-current. This can sometimes enable the realization of an analog processing domain that combines high reliability and fast operating speed. The same applies to the transistors included in the drive cell IMD in Figure 8.

[0359] <<Transistor Configuration Example 1>> Next, we will describe a specific configuration example of a transistor called a GL (Gate Last) structure (also known as a TGSA (Trench Gate Self Align or Top Gate Self Align) structure) that can be applied to transistors F1, F2, and F5 shown in Figure 17. Transistor 200 shown in Figures 19A and 19B is an example of a GL structure transistor. In particular, Figure 19A shows a schematic cross-sectional view of transistor 200 in the channel length direction, and Figure 19B shows a schematic cross-sectional view of transistor 200 in the channel width direction.

[0360] As shown in Figures 19A and 19B, the transistor 200 includes, for example, a semiconductor layer 251a, a semiconductor layer 251b, a conductive layer 231, a conductive layer 232a, a conductive layer 232b, a conductive layer 233, insulating layers 261 to 264, insulating layers 281 to 283, and insulating layers 212 to 214. However, the transistor 200 may not have all of the above-mentioned components. For example, although the conductive layer 231 functions as a back gate electrode in the transistor 200, the transistor 200 can also be configured without the conductive layer 231.

[0361] The conductive layer 231 (conductive layer 231a and conductive layer 231b) and the insulating layer 212 are arranged on top of the substrate (not shown). In particular, it is preferable that the conductive layer 231 is embedded in the insulating layer 212. Specifically, it is preferable that the conductive layer 231a is provided in contact with the bottom surface and side wall of an opening provided in the insulating layer 212. It is also preferable that the conductive layer 231b is provided so as to be embedded in a recess formed in the conductive layer 231a. In the transistor 200 shown in Figures 19A and 19B, the height of the upper surface of the conductive layer 231b is approximately the same as the height of the upper surface of the conductive layer 231a and the height of the upper surface of the insulating layer 212.

[0362] The insulating layer 212, for example, functions as a planarizing film that flattens steps caused by plugs and the like, similar to the insulating layer 112. Therefore, the insulating layer 212 can be made of a material that functions as a planarizing film, similar to the insulating layer 112.

[0363] Furthermore, by using a material with a low dielectric constant for the insulating layer 212, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide nitride, or silicon nitride can be used for the insulating layer 212. Alternatively, for example, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, or porous silicon oxide can be used for the insulating layer 212. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or porous silicon oxide are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating. Alternatively, for example, resin can be used for the insulating layer 212. The material used for the insulating layer 212 may also be an appropriate combination of the insulating materials described above.

[0364] In this specification, "oxide-nitride" refers to a material whose composition contains more oxygen than nitrogen, and "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen. For example, "silicon oxynitride" refers to a material whose composition contains more oxygen than nitrogen, and "silicon nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0365] Furthermore, the semiconductor layer 251 and the conductive layer 233 are arranged in a region that overlaps with the conductive layer 231. The semiconductor layer 251b is arranged on top of the semiconductor layer 251a. The conductive layers 232a and 232b are arranged on top of the semiconductor layer 251b, spaced apart from each other. The insulating layer 213 is arranged on top of the conductive layers 232a and 232b. In particular, the insulating layer 213 has an opening formed in the region between the conductive layers 232a and 232b. The conductive layer 233 is arranged within this opening. The insulating layer 264 is arranged between the semiconductor layer 251b, the conductive layer 232a, the conductive layer 232b, and the insulating layer 213, and the conductive layer 233. Here, as shown in Figures 19A and 19B, it is preferable that the upper surface of the conductive layer 233 substantially coincides with the upper surface of the insulating layer 264 and the insulating layer 213. In the following, conductive layers 231a and 231b may be collectively referred to as conductive layer 231. Also, semiconductor layers 251a and 251b may be collectively referred to as semiconductor layer 251. Furthermore, conductive layers 232a and 232b may be collectively referred to as conductive layer 232.

[0366] Furthermore, as shown in Figure 19A, a low-resistance region 271a may be formed at and near the interface between the semiconductor layer 251b and the conductive layer 232a. Similarly, a low-resistance region 271b may be formed at and near the interface between the semiconductor layer 251b and the conductive layer 232b. In this case, region 271a functions as either a source region or a drain region, and region 271b functions as either a source region or a drain region. In addition, a channel is formed in the region sandwiched between region 271a and region 271b. Hereafter, this region will be referred to as the channel-forming region.

[0367] It is preferable to use a metal oxide that functions as an oxide semiconductor and includes a channel formation region for the semiconductor layer 251. As the metal oxide that forms the channel formation region of the transistor 200, it is preferable to use one with a band gap of 2 eV or more, preferably 2.5 eV or more. Specifically, for example, in the case of the transistor 200 shown in Figures 19A and 19B, it is preferable to use a metal oxide that functions as an oxide semiconductor for the semiconductor layer 251.

[0368] Metal oxide structures can be classified into single-crystal structures and other structures (non-single-crystal structures). Examples of non-single-crystal structures include CAAC (c-axis aligned crystalline) structures, polycrystalline structures, nanocrystalline structures, a-like (amorphous-like) structures, and amorphous structures. The structure of the metal oxide in one aspect of the present invention is not particularly limited, and any of the above structures may be used. However, using crystalline metal oxides such as CAAC structures and nc structures is preferable because it allows for the creation of highly reliable semiconductor devices.

[0369] Furthermore, it is preferable that the above metal oxide contains at least indium. It may also contain indium and zinc. In addition to these, it may also contain element M. Element M can be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, it is preferable that element M contains one or more selected from aluminum, gallium, yttrium, or tin.

[0370] As the above metal oxides, indium oxide (also called indium oxide, IO), gallium oxide (also called gallium oxide), zinc oxide (also called zinc oxide), indium zinc oxide (In-Zn oxide), indium tin oxide, indium titanium oxide, indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide (also called In-Ga-Zn oxide, IGZO), indium gallium tin zinc oxide, indium gallium aluminum zinc oxide, etc. can be used. Alternatively, indium tin oxide, gallium tin oxide, aluminum tin oxide, etc. containing silicon can be used.

[0371] In particular, the above metal oxide preferably contains indium. Specifically, it is preferable to use indium oxide as described in Embodiment 3, and it is even more preferable to use crystalline indium oxide.

[0372] Metal oxides can be suitably formed using sputtering or ALD (Atomic Layer Deposition). When metal oxides are formed by sputtering, films with high crystallinity or high film density can be formed. When metal oxides are formed using the ALD method, atoms can be deposited layer by layer, resulting in film formation with fewer defects such as pinholes, excellent coverage, and the ability to form films at low temperatures. Furthermore, it is preferable to perform an impurity removal treatment after the formation of the metal oxide to remove impurities (typically water, hydrogen, carbon, nitrogen, etc.) from the metal oxide film. Examples of impurity removal treatments include plasma treatment and heat treatment. Microwave plasma treatment is an example of plasma treatment.

[0373] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0374] Although the transistor 200 is shown with a configuration in which two semiconductor layers, semiconductor layer 251a and semiconductor layer 251b, are stacked in the channel formation region and its vicinity, the present invention is not limited to this. For example, a single-layer structure of semiconductor layer 251b or a stacked structure of three or more layers may be provided. Furthermore, each of semiconductor layer 251a and semiconductor layer 251b may have a stacked structure of two or more layers.

[0375] The conductive layer 233 functions as the first gate electrode of the transistor (also called the top gate electrode or front gate electrode), and as described above, the conductive layers 232a and 232b function as the source electrode or drain electrode, respectively. As described above, the conductive layer 233 is formed to be embedded in the opening of the insulating layer 213 and in the region sandwiched between the conductive layers 232a and 232b. Here, the conductive layer 233, conductive layer 232a, and conductive layer 232b are formed in a self-aligned manner with respect to the opening of the insulating layer 213. In other words, in the transistor 200, the first gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductive layer 233 can be formed without providing a positional margin, the occupied area of ​​the transistor 200 can be reduced. This makes it possible to increase the density of calculation cells in the multiply-accumulate unit CA.

[0376] The transistor 200 can be formed by first forming an island-shaped laminate on an insulating layer 262 (described later), including an insulating layer 263 (described later), a semiconductor layer 251, and conductive layers that will become conductive layers 232a and 232b; then stacking insulating layers 282 and 213 (collectively referred to here as the interlayer film) above the island-shaped laminate and above the insulating layer 262 in that order; and then forming an opening in the region of the interlayer film that overlaps the island-shaped laminate, and providing an insulating layer 264 and a conductive layer 233 in that order in the opening. In particular, it is preferable to form the conductive layers 232a and 232b simultaneously by forming the opening in the interlayer film. In this specification, a transistor structure in which, after the formation of the island-shaped laminate and the interlayer film, an opening reaching the island-shaped laminate is provided in the interlayer film, and a conductive layer that will become the first gate electrode of the transistor is provided to fill the opening is referred to as the GL structure. This type of structure is sometimes also called a TGSA structure.

[0377] In Figures 19A and 19B, the conductive layer 233 is shown as a two-layer structure. Here, it is preferable that the conductive layer 233 has a conductive layer 233a and a conductive layer 233b disposed on top of the conductive layer 233a. For example, it is preferable that the conductive layer 233a is arranged to enclose the bottom and sides of the conductive layer 233b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 233a.

[0378] It is preferable to use a conductive material for the conductive layer 233a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen. Furthermore, by having the function of suppressing the diffusion of oxygen in the conductive layer 233a, it is possible to suppress the oxidation of the conductive layer 233b by oxygen contained in the insulating layer 213, etc., which reduces the conductivity. As a conductive material that has the function of suppressing the diffusion of oxygen, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0379] Furthermore, it is preferable to use a conductive layer with high conductivity for the conductive layer 233b. For example, the conductive layer 233b can be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductive layer 233b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0380] For conductive layers 232a and 232b, it is preferable to use conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of conductive layers 232a and 232b. When conductive materials containing metal and nitrogen are used as conductive layers 232a and 232b, conductive layers 232a and 232b become conductive layers having at least a metal and nitrogen. For example, as materials to be applied to conductive layers 232a and 232b, conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen can be selected from the materials that can be applied to conductive layers 233a and 233b respectively as described above.

[0381] Conductive layers 235a and 235b can be made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, conductive layers 235a and 235b can have a laminated structure having multiple layers. In particular, it is preferable that the laminated structure consists of a conductive material having the function of suppressing the permeation of impurities such as water and hydrogen, and a highly conductive material, laminated together.

[0382] Furthermore, the conductive layer 231 may function as a second gate electrode (also called a bottom gate electrode or back gate electrode). In this case, by independently changing the potential applied to the conductive layer 231, separate from the potential applied to the conductive layer 233, the threshold voltage V of the transistor 200 can be controlled. ｔｈ This can be controlled. In particular, by applying a negative potential to the conductive layer 231, the V of the transistor 200 can be controlled. ｔｈThis makes it possible to increase the voltage and decrease the off-current. Therefore, by applying a negative potential to the conductive layer 231, the drain current when the potential of the conductive layer 233 is 0V can be reduced.

[0383] The conductive layer 231 should be larger than the channel formation region in the semiconductor layer 251. In particular, as shown in Figure 19B, it is preferable that the conductive layer 231 extends as wiring even in the region outside the edge that intersects with the channel width direction of the semiconductor layer 251. That is, it is preferable that the conductive layer 231 and the conductive layer 233 are superimposed on the outside of the side surface in the channel width direction of the semiconductor layer 251 with an insulating layer in between.

[0384] As shown in Figure 19A, the conductive layer 233 preferably has a conductive layer 233a provided inside the insulating layer 264 and a conductive layer 233b provided so as to be embedded inside the conductive layer 233a. Although Figures 19A and 19B show the conductive layer 233 as a two-layer laminated structure, the present invention is not limited thereto. For example, the conductive layer 233 may be a single-layer structure or a laminated structure of three or more layers.

[0385] For the conductive layer 231 and conductive layer 233, for example, materials applicable to conductive layer 233a and conductive layer 233b described above can be selected and used.

[0386] As shown in Figures 19A and 19B, the transistor 200 preferably includes an insulating layer 211 disposed on a substrate (not shown), an insulating layer 281 disposed on the insulating layer 211, an insulating layer 212 disposed on the insulating layer 281, a conductive layer 231 disposed so as to be embedded in the insulating layer 212, an insulating layer 261 disposed on the insulating layer 212 and the conductive layer 231, an insulating layer 262 disposed on the insulating layer 261, and an insulating layer 263 disposed on the insulating layer 262. It is preferable that a semiconductor layer 251a is disposed on the insulating layer 263.

[0387] Furthermore, as shown in Figures 19A and 19B, it is preferable that an insulating layer 282 is placed between the insulating layer 262, insulating layer 263, semiconductor layer 251a, semiconductor layer 251b, conductive layer 232a, conductive layer 232b, and insulating layer 213. Here, as shown in Figures 19A and 19B, it is preferable that the insulating layer 282 is in contact with the side surface of the insulating layer 264, the top and side surface of the conductive layer 232a, the top and side surface of the conductive layer 232b, the semiconductor layer 251a, semiconductor layer 251b, the side and top surface of the insulating layer 263, and the top surface of the insulating layer 262.

[0388] Furthermore, insulating layer 264 functions as a first gate insulating film in transistor 200. In addition, insulating layers 261 to 263 function as second gate insulating films. For these gate insulating films, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies can be used. In addition, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO) can be used. ３ ) or (Ba, Sr)TiO ３ An insulating layer containing a so-called high-k material such as (BST) can be used in a single layer or a multilayer configuration. Furthermore, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above insulating layer material. Alternatively, these insulating layers may be subjected to nitriding treatment.

[0389] Preferably, insulating layers 283 and 214, which function as interlayer films, are arranged on the transistor 200. Here, it is preferable that the insulating layer 283 is arranged in contact with the upper surfaces of the conductive layer 233, the insulating layer 264, and the insulating layer 213. In this case, it is preferable that the upper surface of the insulating layer 213 is flattened.

[0390] It is preferable that a conductive layer 235 (conductive layer 235a and conductive layer 235b) is provided, which connects to the transistor 200 and functions as a plug. For this reason, the conductive layer 235 is provided in contact with the inner wall of the opening of the insulating layer 282, insulating layer 213, insulating layer 283, and insulating layer 214. In particular, a first conductive layer of the conductive layer 235 may be provided in contact with the inner wall, and a second conductive layer of the conductive layer 235 may be provided on the side surface of the first conductive layer. Here, the height of the upper surface of the conductive layer 235 and the height of the upper surface of the insulating layer 214 can be made to be approximately the same.

[0391] Specifically, for example, a first conductive layer of conductive layer 235a is provided in contact with one inner wall of two openings in insulating layer 214, insulating layer 283, insulating layer 213 and insulating layer 282, and a second conductive layer of conductive layer 235a is formed in contact with its side surface. A conductive layer 232a is located in a part of the bottom of the opening, and conductive layer 235a is in contact with conductive layer 232a. Similarly, for example, a first conductive layer of conductive layer 235b is provided in contact with the other inner wall of two openings in insulating layer 214, insulating layer 283, insulating layer 213 and insulating layer 282, and a second conductive layer of conductive layer 235b is formed in contact with its side surface. A conductive layer 232b is located in a part of the bottom of the opening, and conductive layer 235b is in contact with conductive layer 232b.

[0392] Although the transistor 200 shows a configuration in which a first conductive layer and a second conductive layer of the conductive layer 235 are stacked, the present invention is not limited thereto. For example, the conductive layer 235 may be provided as a single layer or as a stacked structure of three or more layers.

[0393] As shown in Figure 19B, in the region of the semiconductor layer 251b that does not overlap with the conductive layer 232, in other words, in the channel formation region of the semiconductor layer 251, the side surface of the semiconductor layer 251 is covered by the conductive layer 233. This makes it easier to apply the electric field of the conductive layer 233, which functions as the first gate electrode, to the side surface of the semiconductor layer 251, and as a result, the channel formation region of the semiconductor layer 251 can be electrically surrounded by the electric field of the conductive layer 233. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.

[0394] For example, it is preferable to use a material with a lower dielectric constant than that of the insulating layer 262 for the insulating layer 213 in order to reduce parasitic capacitance that occurs between the wiring. For this reason, the insulating layer 213 can be made of a material with a low dielectric constant that can be used for the insulating layer 212.

[0395] Furthermore, the GL structure transistor described above can be applied to transistors in other circuits provided on the processor, which is a semiconductor device, such as the digital processing area (DNP), memory unit (SPD), and other areas, in addition to the analog processing area (ANP). Similarly, the configuration of the capacitive element C5 described above can also be applied to capacitive elements in other circuits provided on the processor, which is a semiconductor device.

[0396] <<Transistor Configuration Example 2>> In the schematic cross-sectional view of Figure 17, transistors F1, F2, and F5 are described as having a GL structure, but the structure of these transistors according to one aspect of the present invention is not limited to a GL structure. As an alternative to the GL structure, these transistors according to one aspect of the present invention can have, for example, the structure of a vertical channel type transistor described below.

[0397] Figures 20A to 20C show examples of the configuration of a vertical channel transistor. In a vertical channel transistor, the source electrode and drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction).

[0398] The transistors shown in Figures 20A to 20C may also be called VFETs (Vertical Field Effect Transistors), vertical transistors, or vertical channel transistors, in addition to being vertical channel transistors. Furthermore, in this specification, in vertical channel transistors, one of the source electrode or drain electrode located at the bottom may be referred to as the bottom electrode. Also, the other of the source electrode or drain electrode located at the top may be referred to as the top electrode.

[0399] In particular, Figure 20A shows a schematic plan view of an example of a vertical channel type transistor 300, and Figures 20B and 20C show schematic cross-sectional views of the transistor 300. Figure 20B is a schematic cross-sectional view along the dashed-dotted line A1-A2 shown in Figure 20A, and Figure 20C is a schematic cross-sectional view along the dashed-dotted line A3-A4 shown in Figure 20A. Figure 21 shows a schematic perspective view of the transistor 300 and its surrounding wiring as shown in Figures 20A to 20C.

[0400] The transistor 300 shown in Figures 20A to 20C and Figure 21 includes, as an example, a conductive layer 331 that functions as wiring or an electrode, a conductive layer 332 that functions as wiring or an electrode, a semiconductor layer 351 that is the active layer of the transistor 300, an insulating layer 361 that functions as the gate insulating film of the transistor 300, a conductive layer 333 that functions as the gate of the transistor 300, and a conductive layer 334 that functions as wiring.

[0401] The conductive layer 331 is provided above the insulating layer 311, which functions as an interlayer film. Furthermore, since the conductive layer 331 functions as wiring, it extends along the dashed line A3-A4 in the schematic plan view of Figure 20A.

[0402] For example, the conductive layer 331 can be a conductive layer applicable to transistors F1, F2, and F5 as described above. The same applies to conductive layers 332 to 334, which will be described later.

[0403] An insulating layer 312 and a conductive layer 332, which function as an interlayer film, are formed in this order on the insulating layer 311 and the conductive layer 331. In Figure 20B, the insulating layer 312 has a three-layer structure consisting of two barrier insulating films that suppress the diffusion of impurities, and an interlayer film sandwiched between these barrier insulating films. Preferably, the barrier insulating films have a function to suppress the diffusion of oxygen to prevent oxidation of the conductive layer 331 or the conductive layer 332. Furthermore, since the conductive layer 332 functions as wiring, it extends along the direction of the dashed line A1-A2 in the schematic plan view of Figure 20A.

[0404] Furthermore, the insulating layer 312 and the conductive layer 332 have openings that reach the conductive layer 331 in the region overlapping with the conductive layer 331. Semiconductor layers 351 are formed on the sides and bottom of these openings. In other words, the semiconductor layer 351 is formed on the upper surface of the conductive layer 331, the side surface of the insulating layer 312, and the side surface of the conductive layer 332. The semiconductor layer 351 is also formed on a part of the upper surface of the conductive layer 332. The insulating layer 361 is provided so as to be in contact with the conductive layer 332, the semiconductor layer 351, and the insulating layer 312 both inside and outside the openings. Furthermore, conductive layers 333 are formed on the upper and side surfaces of the insulating layer 361 so as to fill the openings.

[0405] Furthermore, an insulating layer 313, which functions as an interlayer film, is formed on the upper surface of the insulating layer 361 and the upper surface of the conductive layer 333. In addition, an opening that reaches the conductive layer 333 is formed in the region of the insulating layer 313 that overlaps with the conductive layer 333. Conductive layers 334 are embedded in the sides and bottom of the opening. A portion of the conductive layer 334 may be formed on the upper surface of the insulating layer 313. Furthermore, an insulating layer 314, which functions as an interlayer film, is formed on both the insulating layer 313 and the conductive layer 334.

[0406] Furthermore, since the conductive layer 334 functions as wiring, it extends along the dashed line A3-A4 in the schematic plan view of Figure 20A.

[0407] For insulating layers 311 to 314, it is preferable to use an insulating material with a low relative permittivity. By using an insulating material with a low relative permittivity as the interlayer film, parasitic capacitance occurring between wiring can be reduced. For this reason, each of the insulating layers 311 to 314 can be made from a material applicable to the insulating layer 212 or insulating layer 213 described above.

[0408] Furthermore, since the insulating layer 361 functions as a gate insulating film, the insulating layer 361 can be made of a material that can be used for the insulating layer 264, for example.

[0409] A portion of the conductive layer 331 functions as either the source electrode or the drain electrode in the transistor 300. A portion of the conductive layer 332 functions as the other source electrode or drain electrode in the transistor 300. Furthermore, a portion or all of the conductive layer 333 functions as the gate electrode in the transistor 300.

[0410] As described above, by forming an insulating layer, a conductive layer, and a semiconductor layer, a vertical channel transistor can be formed in which the channel length has a component in the height direction (vertical direction). Furthermore, the channel length of transistor 300 depends on the thickness of the insulating layer 312; the thinner the insulating layer 312, the shorter the channel length, and thus the on-current of transistor 300 can be increased. On the other hand, the thicker the insulating layer 312, the longer the channel length, and thus the off-current of transistor 300 can be decreased.

[0411] Furthermore, the wiring connecting the source, drain, or gate of the vertical channel transistor is not formed by the same process, but by different processes. As a result, the wiring connecting the source, drain, or gate of the vertical channel transistor has overlapping regions in a plan view. Since the wiring connecting the source, drain, or gate of the vertical channel transistor is provided at different heights, the parasitic capacitance occurring in each wiring can be reduced. This allows for a higher drive frequency of the transistor 300, and also allows for faster drive speeds of the analog processing area (ANP), etc.

[0412] Furthermore, the vertical channel transistors described above can also be applied to transistors in other circuits on a semiconductor device processor, such as the digital processing area (DNP), memory unit (SPD), and other areas, in addition to the analog processing area (ANP).

[0413] Note that the present embodiment can be appropriately combined with the same or other embodiments described in this specification. For example, the configurations, structures, methods, etc. shown in the present embodiment can be used in appropriate combination with other configurations, other structures, other methods, etc. shown in this present embodiment. Further, for example, the configurations, structures, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments and the like.

[0414] (Embodiment 3) In the present embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device according to one aspect of the present invention will be described.

[0415] Note that, in this specification and the like, indium oxide having at least a crystal part or a crystal region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). For example, examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, microcrystalline indium oxide, and the like.

[0416] Indium oxide is a semiconductor material having physical properties completely different from those of oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0417] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO will be described. FIG. 22A is a schematic diagram showing the carrier concentration dependence of the hole mobility for silicon (Si) and indium oxide (InO Ｘ ) and FIG. 22B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0418] First, as shown by the arrow in Fig. 22B, IGZO shows a tendency that the hole mobility increases as the carrier concentration increases. On the other hand, as shown by the arrow in Fig. 22A, indium oxide shows a tendency that the hole mobility increases as the carrier concentration decreases (see Non-Patent Document 2). This tendency is the same as that of silicon. The lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility becomes. That is, the higher the purity and intrinsic nature of indium oxide, the higher the hole mobility. From this result, it can be said that indium oxide has physical properties similar to those of silicon, unlike IGZO. Note that the characteristics of indium oxide shown in Fig. 22A are for the case of assuming a single crystal. Therefore, when indium oxide is non-single crystal (for example, polycrystal), it may differ from the characteristics shown in Fig. 22A.

[0419] In Fig. 22A, since the hole mobility is extremely high in the range R1 where the carrier concentration is low, it can be said that it is a range of carrier concentration suitable for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range including a carrier concentration value of 1×10 １５ cm −３ and, for example, 1×10 １４ cm −３ or more and 1×10 １８ cm −３ [[ID=1**]] or less. By sufficiently reducing the carrier concentration, it can be expected that the value of the hole mobility can be increased to about 270 cm ２ / (V·s).

[0420] In indium oxide, the region where the carrier concentration is in the range R1 can contain an element that lowers the carrier concentration. Examples of the element that lowers the carrier concentration include magnesium, calcium, zinc, cadmium, copper, etc. By these elements substituting indium, the carrier concentration can be lowered. Also, examples of the element that lowers the carrier concentration include nitrogen, phosphorus, arsenic, antimony, etc. For example, by nitrogen, phosphorus, arsenic, or antimony substituting oxygen, the carrier concentration can be lowered.

[0421] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or for resistors or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0422] In the case of indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. As for the supply method of elements that increase the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. In this specification, unless otherwise specified, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions by mass separation is called ion implantation, and a method of supplying ions without mass separation is called ion doping.

[0423] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain can form in the source and drain regions due to stress on the electrodes in contact with IGZO, and n-type regions may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require strain to form in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 22A within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0424] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0425] In addition, the i-type nature of a semiconductor means that the Fermi level (Ef) and the intrinsic Fermi level (Ei) are the same (Ef = Ei). As shown in Figure 22B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is reached, there are no carriers left (in other words, the material has properties similar to an insulator), and it may cease to function as a transistor. On the other hand, in indium oxide, as shown in Figure 22A, the lower the carrier concentration, the higher the hole mobility, and when Ef = Ei is reached, the hole mobility is maximized. That is, transistors containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Furthermore, because transistors containing indium oxide have a low carrier concentration, they tend to be normally off. Therefore, transistors containing indium oxide can be normally off and achieve high field-effect mobility.

[0426] Normally off refers to the state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0V. Normally off can be evaluated using the transistor's threshold voltage (Vth) or shift value (Vsh). Unless otherwise specified, Vth will be calculated using the constant current method. More specifically, Vth is the value of drain current (Id) × channel (L) ÷ channel width (W) in the transistor's Id-Vg characteristic where the current is 1nA (1 × 10⁻¹⁰). −９ Let Vsh be the gate voltage (Vg) when A) is true. Also, Vsh is the tangent to the maximum slope when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically, and Id = 1pA (1 × 10⁻¹⁰). −１２ Vg is the gate voltage (Vg) at the intersection with line A), or the Vg at the intersection of the line extrapolated from the two points where the slope of Id is maximized when Id is expressed logarithmically in the transistor's Id-Vg characteristic, and the line where Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive values, it can be considered a normally-off transistor.

[0427] Furthermore, in transistors containing indium oxide, the film configuration in contact with the indium oxide film is crucial for making the semiconductor i-type, that is, for achieving Ef = Ei. For example, in transistors containing indium oxide, a film configuration can be obtained in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in contact with the indium oxide film. By using this film configuration, it is possible to create a semiconductor device that satisfies Ef = Ei and is highly reliable.

[0428] Furthermore, in the above film configuration, oxygen-containing films such as silicon oxide-nitride films, silicon oxide nitride films, aluminum oxide films, and gallium oxide films can be used instead of the silicon oxide film. Also, in the above film configuration, silicon oxide nitride films, silicon oxide nitride films, etc. can be used instead of the silicon nitride film. In addition, the hafnium oxide film located on the indium oxide side of the silicon nitride film functions as a hydrogen gettering site.

[0429] Furthermore, the above film configuration can also be viewed as a layered structure consisting of a film that can supply oxygen to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film), and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. Also, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. In addition, the silicon nitride film provides a film configuration that minimizes the intrusion of oxygen and hydrogen from the outside. In other words, with the above film configuration, the indium oxide film can be made closer to type i. Therefore, transistors having the above indium oxide film have high field-effect mobility and high reliability.

[0430] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0431] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0432] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0433] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. Alternatively, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0434] The channel formation region refers to the area within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0435] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0436] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0437] Furthermore, the indium oxide film described herein has a high film density. The theoretical value of the film density of the indium oxide film is 7.18 g / cm³. ３ In this specification, the range of film density for indium oxide films is 6.70 g / cm³. ３ 7.18g / cm or more ３ The following, preferably 6.90 g / cm³ ３ 7.18g / cm or more ３ The following, and more preferably 7.00 g / cm³ ３ 7.18g / cm or more ３ The following applies:

[0438] Furthermore, film density can be evaluated using methods such as Rutherford backscattering (RBS) or X-ray reflectivity (XRR). Differences in film density can sometimes be evaluated using transmission electron microscopy (TEM) images of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image.

[0439] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0440] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 22C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. ＯIf oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0441] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0442] Furthermore, as shown in Figure 22C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or by reacting with oxygen contained in the film, and released as water molecules. The above-mentioned oxygen and hydrogen diffuse through the indium oxide film by heat treatment. The temperature of the heat treatment is 200°C to 700°C, preferably 350°C to 650°C, and more preferably 400°C to 500°C.

[0443] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0444] Table 1 shows single crystal indium oxide (here, In ２ O ３The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Also, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0445]

[0446] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0447] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L１ is the length of the unit lattice vector or lattice constant of the crystal possessed by the formed film, L ２ is the length of the unit lattice vector or lattice constant of the crystal possessed by the seed layer.

[0448] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably as small as possible in absolute value, and most preferably 0. For example, Δa can be −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0449] Here, the crystal of indium oxide has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the YSZ crystal having a cubic crystal structure is within the range of −2% or more and 2% or less, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0450] Note that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not have the same crystal system or crystal orientation. For example, a film having a hexagonal crystal structure or a trigonal crystal structure can be used under an indium oxide film having a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the lower surface of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. As the hexagonal or trigonal crystal, for example, there are wurtzite-type structures, YbFe ２ O ４ type structures, Yb ２ [[ID=1(18]]Fe ３ O ７ type structures, and modified structures thereof. YbFe ２ O ４ type structure or Yb ２ Fe ３ O ７An example of a crystal with a crystalline structure is IGZO. Indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Silicon crystals have a diamond structure. Thus, in terms of single crystals, indium oxide and silicon have similar properties. However, when comparing indium oxide and silicon from the perspective of whether single crystals can be formed on insulating films, they have different properties.

[0451] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0452] (Embodiment 4) This embodiment describes an electronic component that can use the semiconductor device described in the above embodiment. An electronic component using a semiconductor device according to one aspect of the present invention is effective in improving performance, such as reducing power consumption.

[0453] [Electronic Components] A perspective view of the electronic component 1700 is shown in Figure 23A. The electronic component 1700 shown in Figure 23A comprises a substrate 1701, a semiconductor device 1710 on the substrate 1701, and a mold 1711. In particular, the semiconductor device 1710 is sealed by the mold 1711. Note that in Figure 23A, some details have been omitted in order to show the inside of the electronic component 1700.

[0454] For example, the substrate 1701 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0455] The electronic component 1700 is provided with, for example, a lead frame 1712. A portion of the lead frame 1712 located on the substrate 1701 is covered by a mold 1711, while another portion of the lead frame 1712 is exposed to the outside of the mold 1711. In particular, the lead frame 1712 exposed to the outside of the mold 1711 functions, for example, as a terminal for mounting the electronic component 1700 onto a printed circuit board.

[0456] Within the mold 1711, electrode pads 1713 are provided on the lead frame 1712, and the electrode pads 1713 are connected to the semiconductor device 1710 via wires 1714. The electronic component 1700 is mounted on the printed circuit board, for example, by bringing the lead frame 1712 into contact with the wiring on the printed circuit board side. In this way, multiple electronic components are combined and connected on the printed circuit board to complete the mounted circuit board.

[0457] Next, the semiconductor device 1710 will be described. For example, as shown in Figure 23B, the semiconductor device 1710 has a drive circuit layer 1715 and a storage layer 1716. The storage layer 1716 can be configured by stacking multiple cell arrays. The cell array can include the arithmetic cells, drive cells, and storage cells described in the above embodiment. The configuration in which the drive circuit layer 1715 and the storage layer 1716 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technology (for example, TSV (Through Silicon Via)) and bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 1715 and the storage layer 1716 in a monolithic stack configuration, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory. For example, by configuring the processor described in the above embodiment as an on-chip memory, the transmission speed of the first or second data from the memory to the processor can be increased.

[0458] Furthermore, by using an on-chip memory configuration, it is possible to reduce the size of connection wiring and other components compared to technologies that use through-hole electrodes such as TSVs, thus increasing the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0459] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 1716 using I / O transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or the memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 1716, it is difficult to create a monolithic stack configuration compared to I / O transistors. Therefore, in a monolithic stack configuration, I / O transistors can be said to have a superior structure compared to Si transistors.

[0460] Furthermore, the semiconductor device 1710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0461] Next, Figure 23C shows an example of a modification of the electronic component 1700. Unlike the electronic component 1700, the electronic component 1700A shown in Figure 23C does not use a lead frame 1712, and instead has electrodes 1733 provided at the bottom of the substrate 1701. The electrodes 1733 function as connection terminals for mounting the electronic component 1700A onto the printed circuit board.

[0462] Figure 23C shows an example in which the electrode 1733 is formed with solder balls. By arranging solder balls in a matrix at the bottom of the substrate 1701, BGA (Ball Grid Array) mounting can be realized. For this purpose, the substrate 1701 is provided with through-hole vias, and a conductive layer 1732 that functions as wiring is provided on these vias. On the substrate 1701, the electrode pad 1713 is provided in contact with the conductive layer 1732 above, and on the substrate 1701, the electrode 1733 is provided in contact with the conductive layer 1732 below.

[0463] Alternatively, the electrodes 1733 may be formed with conductive pins instead of solder balls. By arranging conductive pins in a matrix at the bottom of the substrate 1701, PGA (Pin Grid Array) mounting can be realized.

[0464] Furthermore, the electronic component 1700A can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0465] Furthermore, an electronic component according to one aspect of the present invention may be in the form of a SiP (System in Package) or an MCM (Multi-Chip Module). For example, the electronic component 1700C shown in Figure 23D has an interposer 1731 provided on a package substrate 1734 (printed circuit board), and a semiconductor device 1735 and a plurality of semiconductor devices 1710 are provided on the interposer 1731.

[0466] In Figure 23D, the electronic component 1700C shows, as an example, an example in which the semiconductor device 1710 is used as a high-bandwidth memory (HBM). For example, as in the above embodiment, the semiconductor device 1710 can be configured to have memory cells included in the memory unit SPD. Also, as an example, the semiconductor device 1735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, GPU, NPU, or FPGA (Field Programmable Gate Array). Furthermore, the semiconductor device 1710 can be the digital processing area (DNP) described in the above embodiment, and the semiconductor device 1735 can be the analog processing area (ANP) described in the above embodiment.

[0467] The package substrate 1734, like the substrate 1701, can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 1731 can be, for example, a silicon interposer or a resin interposer.

[0468] The interposer 1731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 1731 also has the function of connecting integrated circuits provided on the interposer 1731 to electrodes provided on the package substrate 1734. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 1731, and these through electrodes may be used to connect the integrated circuits and the package substrate 1734. Furthermore, in silicon interposers, through electrode technology such as TSV can be used to form the through electrodes.

[0469] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0470] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit placed on the silicon interposer and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0471] On the other hand, when connecting multiple integrated circuits with different terminal pitches using through-electrodes formed by silicon interposers and TSVs, space such as the width of the terminal pitch is required. Therefore, when trying to reduce the size of the electronic component 1700C, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as described above, a monolithic stacked configuration using I / O transistors is preferable. Furthermore, for example, a memory cell array stacked using through-electrode technology such as TSVs can be combined with a monolithic stacked memory cell array. In addition, a structure that combines a memory cell array stacked using through-electrode technology such as TSVs with a monolithic stacked memory cell array is sometimes called a composite structure.

[0472] Furthermore, if the temperature of the electronic component 1700C rises due to heat generated during operation, the characteristics of the circuit elements (such as transistors) provided in the electronic component 1700C may deteriorate. Therefore, it is preferable to provide a heat sink (heat dissipation plate) on top of the electronic component 1700C. When a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 1731. For example, in the electronic component 1700C shown in this embodiment, it is preferable to align the heights of the semiconductor device 1710 and the semiconductor device 1735.

[0473] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0474] (Embodiment 5) This embodiment describes an electronic device using the electronic components described in the above embodiment, and an information processing system using the electronic device.

[0475] Figure 24 shows an example of the configuration of an information processing system. The information processing system 8000 shown in Figure 24 includes an example of various electronic devices and a server located within the network.

[0476] Figure 24 shows, as examples of such electronic devices, a portable information terminal 8200, a wearable information terminal 8300, a notebook personal computer 8400, an automobile 8500, an industrial robot 8600, and a camera 8700. Figure 24 also shows a network 8100 and a large computer 8110 located within the network 8100.

[0477] The term "large-scale computer 8110" can sometimes refer to multiple computers installed in a server room or similar location. For example, a rack-mount type large-scale computer 8110 is one in which multiple computers are housed in a rack. The large-scale computer 8110 is sometimes referred to as a supercomputer. Furthermore, in the information processing system 8000, the large-scale computer 8110 may also be referred to as a server or cloud server.

[0478] Each of the multiple computers in the large computer 8110 has a motherboard, which is provided with multiple slots, multiple connection terminals, etc. One or more PC cards can be inserted into the slots, for example. A PC card is an example of a processing board equipped with processing units such as a CPU and a GPU. For example, an electronic component 1700 can be used as the processing unit.

[0479] The mainframe computer 8110 can also function as a parallel computer. By using the mainframe computer 8110 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, the training and inference of artificial intelligence.

[0480] When performing wired communication as Network 8100, specifications standardized by IEEE, such as Ethernet (registered trademark), can be used. Examples of communication types include electrical communication using wires such as twisted-pair cables, and optical communication using optical fibers. On the other hand, when performing wireless communication as Network 8100, communication protocols or technologies such as 4G, 5G, 6G, or specifications standardized by IEEE, such as Wi-Fi (registered trademark) and Bluetooth (registered trademark), can be used.

[0481] Network 8100 can be, for example, a PAN (Personal Area Network), LAN (Local Area Network), CAN (Campus Area Network), MAN (Metropolitan Area Network), WAN (Wide Area Network), or GAN (Global Area Network). For example, by using a GAN in network 8100, the Internet, which is the foundation of the World Wide Web (WWW), can be used. Furthermore, if the information processing system 8000 is built on a LAN as network 8100, the possibility of confidential information leakage can be reduced compared to using the Internet.

[0482] Furthermore, a company or individual managing the mainframe computer 8110 can, for example, use the network 8100 to provide services using the information processing system 8000 to users of each electronic device. One example of such services is a usage model called cloud computing. Through this cloud computing, users of the aforementioned electronic devices can utilize the mainframe computer 8110's functions for storing large amounts of data, performing large-scale calculations, and other applications.

[0483] In particular, a semiconductor device according to one aspect of the present invention, when installed in the above-mentioned electronic devices and the large computer 8110, can perform large-scale calculations such as artificial neural networks. Furthermore, this enables the information processing system 8000 to provide services to users in a usage mode called cloud AI or edge AI.

[0484] Cloud AI generally refers to a service where a large-scale computer (8110) performs the training and inference of an artificial neural network. The large-scale computer 8110 is pre-trained on collected data, and each electronic device transmits input data to the large-scale computer 8110 for the artificial neural network, where the large-scale computer 8110 performs inference on that input data. The large-scale computer 8110 also transmits the results of this inference to each electronic device, which can then use. Because training and inference are performed by the large-scale computer 8110, cloud AI is suitable for processing large amounts of data and for handling complex calculations.

[0485] On the other hand, edge AI generally refers to a service where each electronic device performs the learning and inference of an artificial neural network. In this case, the mainframe computer 8110 provides each electronic device with the artificial neural network model, weight coefficients (sometimes called weight data, connection coefficients, etc.), etc. The results of the learning and inference performed on each electronic device are also transmitted to the mainframe computer 8110. Furthermore, a usage model in which the mainframe computer 8110 learns the artificial neural network and each electronic device performs inference using the learned neural network is also sometimes referred to as edge AI.

[0486] Edge AI performs artificial neural network inference on each individual electronic device, thus reducing the communication time required compared to cloud AI. In other words, edge AI is well-suited for real-time analysis of input data. Furthermore, the amount of data transmitted between each electronic device and the mainframe computer 8110 is reduced, lowering data communication costs and power consumption. The reduced data transmission also minimizes security risks such as information leaks. For these reasons, edge AI is suitable for building small-scale systems, for example.

[0487] Furthermore, since the semiconductor device according to one aspect of the present invention consumes extremely low power during standby, it can be suitably used for edge AI. A specific example of an edge AI system is described below.

[0488] [Personal Information Terminal] The personal information terminal 8200 shown in Figure 24 is an electronic device that integrates a display device and a touch panel. The personal information terminal 8200 can also be equipped with electronic component 8201 as the electronic component 1700 mentioned above, thereby enabling large-scale calculations such as artificial neural networks to be performed in the personal information terminal 8200. The personal information terminal 8200 can also be equipped with a camera.

[0489] By equipping the personal digital assistant (PDA) 8200 with a camera, image recognition using edge AI can be performed on images captured by the PDA 8200. The objects that can be recognized include humans, animals, plants, characters, and pictograms. In particular, by performing image recognition on images of human faces, fingerprints, palm prints, irises, and veins, it can be used for biometric authentication.

[0490] [Wearable Information Terminal] The wearable information terminal 8300 shown in Figure 24 is an electronic device that can be worn on a person's head. The wearable information terminal 8300 in Figure 24 has an eye cover, a display device, temples (arms) that hook onto the ears, and earphones, but other examples include HMDs (head-mounted displays) and glasses-type XR devices. The wearable information terminal 8300 can also be equipped with a camera, similar to the portable information terminal 8200.

[0491] Furthermore, the wearable information terminal 8300 can be equipped with the electronic component 8301 as the electronic component 1700 mentioned above, thereby enabling large-scale computations such as artificial neural networks to be performed in the wearable information terminal 8300.

[0492] By equipping the wearable information terminal 8300 with a camera, images captured by the wearable information terminal 8300 can be displayed on a display device in real time. Furthermore, by performing image recognition using edge AI, information about objects included in the image displayed on the display device can be added to the display device. In addition, by performing image recognition on moving objects such as pedestrians, bicycles, cars, and trains displayed on the display device, it is possible to perform risk prediction to determine whether or not there is a risk of collision.

[0493] [Notebook Personal Computer] The notebook personal computer 8400 shown in Figure 24 is an electronic device primarily used on a desktop. The notebook personal computer 8400 can also be equipped with electronic component 8401 as the electronic component 1700 mentioned above, thereby enabling the notebook personal computer 8400 to perform large-scale calculations such as artificial neural networks.

[0494] The 8400 notebook personal computer can, for example, use edge AI as part of its computational processing when using applications. Examples of its applications include upconversion, which increases the screen resolution of images (including still images and videos) displayed on a display device in real time; translation, which converts text into another language; and editing tasks for text or images.

[0495] [Automobile] The automobile 8500 shown in Figure 24 is an example of a mobile device. The automobile 8500 can also be equipped with electronic component 8501 as the electronic component 1700 described above, thereby enabling the automobile 8500 to be used as an electronic device for edge AI.

[0496] Edge AI in the Automobile 8500 can be used for applications such as autonomous driving, hazard prediction in autonomous driving, and in-car air conditioning management.

[0497] In this specification, automobiles are used as an example of a mobile device, but other examples of mobile devices include trains, monorails, ships, and aircraft (e.g., helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). The aforementioned mobile devices can also be used as electronic devices for edge AI.

[0498] [Industrial Robot] The industrial robot 8600 shown in Figure 24 can be deployed, for example, in a production plant. The industrial robot 8600 preferably has multiple drive axes to finely control the drive range. The industrial robot 8600 may also have one or more functions such as grasping, cutting, welding, coating, and attaching objects. In addition, the industrial robot 8600 is preferably equipped with sensors such as an image detection module or a camera to detect the object. Furthermore, the industrial robot 8600 is preferably equipped with a sensor that detects minute currents to determine whether or not it has grasped an object.

[0499] Furthermore, the industrial robot 8600 can be equipped with the electronic component 8601 as the aforementioned electronic component 1700, thereby enabling the industrial robot 8600 to be used as an electronic device for edge AI. The edge AI in the industrial robot 8600 can be used for applications such as image recognition of objects to classify them by type, by size, and inspection to determine whether they are good or defective.

[0500] [Camera] The camera 8700 shown in Figure 24 can be used, for example, as a surveillance camera, security camera, or pet camera. Furthermore, the housing of the camera 8700 is not limited to the ceiling-mounted type shown in Figure 24, but there are various types such as tabletop type and wall-mounted type.

[0501] It should be noted that "surveillance camera," "security camera," and "pet camera" are common terms and do not necessarily limit their use to those purposes. For example, a pet camera may be used as a surveillance camera or security camera, and vice versa. Also, the Camera 8700 is sometimes referred to as a video camera.

[0502] Furthermore, the camera 8700 can be equipped with the electronic component 8701 as the electronic component 1700 mentioned above, thereby enabling the camera 8700 to be used as an edge AI electronic device. The edge AI in the camera 8700 can be used, for example, for security purposes, to detect motion in objects displayed in images (still images and videos) captured by the camera 8700. It can also be used for disaster prevention purposes, such as detecting river flooding and tsunamis.

[0503] Furthermore, the information processing system 8000 can be suitably used in storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as ensuring the immutability of the data. Managing data over the long term requires the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, and securing cooling equipment required for data storage, thus necessitating a large-scale building. In addition, it is preferable for data centers to have a function to perform calculations on data, and it is even more preferable that the speed of such calculations is fast. Furthermore, AI calculations can be used for such calculations. Therefore, by using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to select whether to process using analog circuits or digital circuits, depending on the desired scale of calculations.

[0504] Furthermore, by using I / O transistors as transistors for storing data in memory circuits and cache memory applied to data centers, and by configuring them to maintain a potential corresponding to the data, the frequency of refresh can be reduced, and power consumption can be lowered. In addition, miniaturization is possible by stacking memory cell arrays.

[0505] Furthermore, by applying a semiconductor device according to one aspect of the present invention to one or more selected from the electronic components, electronic devices, large computers, space equipment, and data centers described in the above embodiments, it is expected that power consumption will be reduced. Therefore, given the expected increase in energy demand due to the increased performance or high integration of the above-mentioned components, equipment, and data centers, it is expected that using a semiconductor device according to one aspect of the present invention will reduce carbon dioxide (CO2). ２ It is also possible to reduce greenhouse gas emissions, such as those represented by [specific examples of greenhouse gas emissions]. Furthermore, because the semiconductor device according to one aspect of the present invention consumes little power, it is also effective as a measure against global warming.

[0506] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0507] (Embodiment 6) This embodiment describes space equipment that can use the semiconductor device described in the above embodiment. Space equipment is effective in achieving high performance, such as low power consumption.

[0508] [Space Equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment (for example, equipment having the function of processing and storing information).

[0509] A semiconductor device according to one aspect of the present invention may include an I / O transistor. This I / O transistor exhibits small fluctuations in electrical properties due to radiation exposure. In other words, it has high resistance to radiation and can therefore be suitably used in environments where radiation may be incident. For example, an I / O transistor can be suitably used in outer space.

[0510] Figure 25 shows an example of space equipment, specifically a satellite 6800. The satellite 6800 comprises a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 25, a planet 6804 is shown as an example in outer space. Outer space refers to, for example, an altitude of 100 km or more, but as described herein, outer space includes the thermosphere, mesosphere, and stratosphere.

[0511] Furthermore, although not shown in Figure 25, a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 6805. Using an I / O transistor in the above-mentioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0512] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0513] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel is not exposed to sunlight, or if the amount of sunlight hitting the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to equip the satellite 6800 with a secondary battery 6805. Note that solar panels are sometimes called solar cell modules.

[0514] The satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received, for example, by a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0515] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a processor (e.g., GPU, CPU, NPU, or FPGA) and memory circuits. In particular, it is preferable to use a semiconductor device according to one embodiment of the present invention for the control device 6807. By using, for example, the semiconductor device according to one embodiment of the present invention described in Embodiment 1 for the control device 6807, it is possible to select high-precision AI calculations, high-speed AI calculations, low-power AI calculations, etc., depending on the application or purpose. For example, when analyzing information on celestial bodies (such as cosmic rays) obtained by sensing, high-precision AI calculations can be performed using digital circuits. Alternatively, when performing simple image recognition on celestial body images, low-power AI calculations can be performed using analog circuits. In addition, the IO transistors that can be provided in the semiconductor device according to one embodiment of the present invention exhibit smaller fluctuations in electrical characteristics due to radiation irradiation compared to Si transistors. In other words, they are highly reliable and can be suitably used even in environments where radiation may be incident.

[0516] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0517] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention is also suitable for use in space equipment such as spacecraft, space capsules, and space probes.

[0518] As explained above, I / O transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth and higher radiation resistance.

[0519] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0520] AD: Adder, ADa: Circuit, ADC: AD conversion unit, ANP: Analog processing area, AP: Adder circuit, BKL: Wiring, C11: Capacitance element, CA: Multiply-accumulate unit, CLKL: Wiring, CNL: Wiring, CTU: Arithmetic processing control unit, CV: Conversion unit, CVLA: Wiring, CVLB: Wiring, CVLC: Wiring, DAC: DA conversion unit, DGP: Arithmetic circuit, DIL: Wiring, DNP: Digital processing area, DOL: Wiring, FA: Arithmetic unit, FC: Arithmetic unit, FTC: Floating-point arithmetic unit, FTr: Transistor, IF: Interface, ILA: Wiring, ILB : Wiring, IM: Calculation cell, IMD: Drive cell, IMS: Calculation cell, ITSa: Circuit, IVa: Inverter, IVb: Inverter, IWL: Wiring, IXL: Wiring, LSU: Load / Store Unit, MC: Calculation cell, MCN: Memory cell, MCP: Memory cell, MD: Memory cell, ME11: Memory circuit section, ME12: Memory circuit section, MEA: Cell array, MEX: Memory circuit, MLA: Wiring, MLB: Wiring, Mn: Transistor, Mp: Transistor, MP: Multiplication circuit, MUCA: Multiply-accumulate unit, NPA: Processor, NPB: Processor NPC: Processor, OL: Wiring, OMAL: Circuit Layer, Phd: Input Data, PHRL: Circuit Layer, Pma: Output Data, POL: Wiring, RBD: Circuit, RBL: Wiring, RG: Register, RL: Wiring, RLN: Wiring, RLP: Wiring, RSTL: Wiring, RV: Resistive Switch, RWD: Circuit, RWL: Wiring, SA: Switch, SB: Switch, SE: Wiring, SL: Wiring, SLC: Switching Unit, SPD: Memory Unit, SR: Shift Register, SWCA: Circuit, SWCB: Circuit, SWLA: Wiring, SWLB: Wiring, SWR: Switch, SWS: Switch, SWSb: Switch, TMo: Output terminal, TNo: Output terminal, VCE: Wiring, VDE: Wiring, VEG: Wiring, VSE: Wiring, WBD: Circuit, WBL: Wiring, WBLb: Wiring, WBS: Drive circuit, WCD: Drive circuit, WCL: Wiring, WCS: Drive circuit, WL: Wiring, WLb: Wiring, WLN: Wiring, WLP: Wiring, WR: Wiring, WSD: Drive circuit, WSL: Wiring, WTr: Transistor, WWD: Circuit, WWL: Wiring, WXL: Wiring, XCL: Wiring, XCS: Drive circuit, XCSa: Circuit, XWSD: Drive circuit

Claims

It has a first processing area and a second processing area. The first processing area has the function of performing a first arithmetic operation using the first digital data, The second processing area includes a first function for generating first analog data from second digital data, a second function for generating second analog data from third digital data, a function for generating third analog data by a second arithmetic process using the first analog data and the second analog data, and a third function for generating fourth digital data from the third analog data. Each of the first and second arithmetic operations includes a sum-of-products operation and a function operation. Semiconductor equipment. 　 In claim 1, It has a calculation processing control unit, The arithmetic processing control unit has a function to select either the first arithmetic processing performed in the first processing area or the second arithmetic processing performed in the second processing area, depending on the content of the arithmetic to be processed. Semiconductor equipment. 　 In claim 2, It has a memory unit, The storage unit has a plurality of storage cells that hold the first digital data, the second digital data, the third digital data, and the fourth digital data. The second processing area includes a digital-to-analog conversion unit, a multiply-accumulate unit, an arithmetic unit, and an analog-to-digital conversion unit. The sum-of-accumulate unit has a plurality of calculation cells that hold the first analog data, The digital-to-analog conversion unit has the first function and the second function, The sum-of-accumulate unit has the function of performing the sum-of-accumulate operation using the first analog data and the second analog data with a plurality of calculation cells. The calculation unit has the function of performing calculations on the function using the result of the sum-of-products calculation process performed by the sum-of-products calculation unit. The analog-to-digital conversion unit has the third function, Semiconductor equipment. 　 In claim 3, Multiple calculation cells of the sum-of-accumulate unit are provided in the storage unit. Each of the plurality of calculation cells and the plurality of storage cells has one selected from an inverter loop, a transistor with a floating layer, a capacitive element, a resistive switching element, a magnetic tunnel junction element, a ferroelectric capacitor, and a phase change memory as a circuit or circuit element for holding data. Semiconductor equipment. 　 In claim 3, Each of the aforementioned calculation cells has one selected from an inverter loop, a transistor with a floating layer, a capacitive element, a resistive switching element, a magnetic tunnel junction element, and a phase-change memory as a circuit or circuit element for holding data. Each of the aforementioned memory cells has one selected from an inverter loop, a transistor with a floating layer, a capacitive element, a resistive switching element, a magnetic tunnel junction element, and a phase-change memory as a circuit or circuit element for holding data. Semiconductor equipment. 　 In claim 4 or claim 5, Multiple of the calculation cells have transistors, The transistor has an oxide semiconductor in the channel formation region. The oxide semiconductor contains indium, Semiconductor equipment.

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