Solid state disk data encryption method and solid state disk

Abstract

The application relates to the technical field of electric digital data processing security, and discloses a solid state disk data encryption method and a solid state disk. The method realizes transparent encryption of written data and transparent decryption of read-out data by serially arranging a national secret algorithm hardware encryption and decryption coprocessing module on a data bus between a main control chip and a flash memory particle array; the module is based on an SM4 algorithm and an XTS advanced encryption standard mode, combines a logical address as an adjustment value to perform encryption and decryption, and injects a root key through an out-of-band interface to derive a data key. The system comprises a main control chip, a flash memory array and the coprocessing module, the latter integrates a hardware encryption and decryption engine, a key management unit and data flow control logic. The application realizes high-performance, high-compatibility, high-security national secret hardware-level full-disk encryption without changing a general main control chip.

Description

Technical Field

[0001] This invention belongs to the field of electronic digital data processing security technology, specifically relating to solid-state drive data encryption methods and solid-state drives. Background Technology

[0002] Solid-state drives (SSDs) are the mainstream high-performance storage media, and their built-in data encryption mechanisms are directly related to the ability to protect sensitive information.

[0003] Internationally accepted encryption standards such as AES have been widely integrated into SSD controller chips, and high-speed encryption and decryption operations are achieved through dedicated hardware accelerators, balancing performance and security. However, Chinese national cryptographic algorithms (such as SM2, SM3, and SM4) are mandated for the protection of classified or critical business data, making it difficult for general-purpose SSDs that only support international algorithms to meet compliance requirements.

[0004] The Chinese national cryptographic algorithm differs significantly from international standards such as AES in terms of computational structure, round function design, and key scheduling mechanism.

[0005] Existing SSD controller chips are generally not hardware-optimized for Chinese cryptographic algorithms, forcing them to rely on software simulation when executing SM series algorithms. This approach is not only severely limited by processor computing power but also fails to leverage the advantages of parallel computing, resulting in a sharp drop in encryption / decryption throughput and a significant increase in latency. This makes it difficult to match the read / write bandwidth of SSDs, which can reach several GB / s, creating a significant performance bottleneck.

[0006] Especially in scenarios involving high concurrency and real-time encryption of large amounts of data, the software-implemented national cryptographic algorithms can easily become a limiting factor for the overall efficiency of the system.

[0007] In existing technologies, some solutions attempt to support national cryptographic algorithms by adding external security chips or upgrading firmware, but the former increases hardware costs and system complexity, while the latter still cannot break through the physical limit of software execution efficiency.

[0008] Another study proposed adding an independent national cryptographic hardware acceleration module to the main controller, but such designs often coexist in parallel with the original AES acceleration unit, resulting in chip area redundancy, increased power consumption, and a lack of support for dynamic switching of multiple algorithms.

[0009] When application scenarios need to be compatible with both international standards and national cryptographic specifications, the existing architecture struggles to achieve efficient and flexible algorithm scheduling with limited hardware resources.

[0010] Therefore, there is an urgent need for a solid-state drive data encryption technology solution that can meet the national cryptographic compliance requirements while maintaining a high-performance storage experience. In particular, a reconfigurable and highly integrated hardware acceleration architecture is needed to achieve seamless collaboration and dynamic adaptation between international and national cryptographic algorithm systems. Summary of the Invention

[0011] The technical problem to be solved by this invention is to provide a solid-state drive (SSD) data encryption method and a SSD, aiming to overcome the performance bottleneck caused by the lack of hardware acceleration units in general SSD controller chips when executing national cryptographic algorithms in the prior art, and to provide high-speed, transparent hardware-level data encryption and decryption functions that comply with national cryptographic standards for SSDs without changing the hardware architecture of mainstream SSD controller chips.

[0012] To address the aforementioned technical problems, this invention provides a solid-state drive (SSD) data encryption method, applied to an SSD comprising an SSD controller chip, a hardware encryption / decryption coprocessor module for Chinese cryptographic algorithms, and a flash memory array. The hardware encryption / decryption coprocessor module for Chinese cryptographic algorithms is serially configured on the data bus between the SSD controller chip and the flash memory array. The method includes:

[0013] The national cryptographic algorithm hardware encryption and decryption coprocessing module receives a flash memory write command issued by the solid-state drive main control chip, which carries the target physical page address and the plaintext data to be written.

[0014] The hardware encryption and decryption coprocessing module of the national cryptographic algorithm calls the preset data encryption key in the internal key management unit to drive its built-in hardware data encryption and decryption engine to perform the national cryptographic symmetric encryption algorithm operation on the plaintext data to be written, and generate ciphertext data corresponding to the plaintext data.

[0015] The hardware encryption / decryption coprocessing module of the national cryptographic algorithm writes the generated ciphertext data to the designated physical storage unit of the flash memory array according to the target physical page address in the flash memory write instruction;

[0016] The national cryptographic algorithm hardware encryption and decryption coprocessing module receives a flash memory read instruction carrying the target physical page address issued by the solid-state drive main control chip;

[0017] The hardware encryption and decryption coprocessing module of the national cryptographic algorithm reads the pre-stored ciphertext data from the corresponding physical storage unit of the flash memory chip array according to the target physical page address in the flash memory read instruction;

[0018] The hardware encryption and decryption coprocessing module of the national cryptographic algorithm calls the data encryption key in the internal key management unit to drive the hardware data encryption and decryption engine to perform the national cryptographic symmetric decryption algorithm operation on the read ciphertext data and restore the ciphertext data to the original plaintext data.

[0019] The hardware encryption / decryption coprocessing module of the national cryptographic algorithm returns the restored original plaintext data to the solid-state drive controller chip to complete the response to the flash memory read command.

[0020] As one embodiment of the present invention, the hardware encryption / decryption coprocessing module for the national cryptographic algorithm further includes a key initialization step before receiving the instruction from the solid-state drive controller chip:

[0021] The root key issued by the host system is received through the out-of-band communication interface reserved in the solid-state drive controller chip; the out-of-band communication interface is a serial communication bus independent of the flash memory data bus.

[0022] The key management unit inside the hardware encryption and decryption coprocessing module of the national cryptographic algorithm receives and securely stores the root key, generates a data encryption key for data encryption and decryption based on the root key through a preset key derivation function, and loads the data encryption key into the key register of the hardware data encryption and decryption engine.

[0023] In one embodiment of the present invention, the hardware data encryption and decryption engine executes the national standard symmetric encryption algorithm SM4 block cipher algorithm; the hardware data encryption and decryption engine adopts the XTS advanced encryption standard mode optimized for block storage devices; when the national standard algorithm hardware encryption and decryption coprocessing module performs encryption operations, it also inputs the logical block address information contained in the flash memory write instruction as an adjustment value to the hardware data encryption and decryption engine for encryption operations in the XTS advanced encryption standard mode.

[0024] As one embodiment of the present invention, the hardware encryption / decryption coprocessing module of the national cryptographic algorithm integrates a high-speed data cache.

[0025] The specific steps of receiving the plaintext data to be written are as follows: temporarily storing the entire page of plaintext data transmitted by the solid-state drive controller chip through the flash memory data bus into the high-speed data cache;

[0026] After generating the ciphertext data, the process also includes temporarily storing the generated full-page ciphertext data back to another area of ​​the high-speed data cache.

[0027] The specific steps of writing the encrypted data into the flash memory array are as follows: reading the entire page of encrypted data from the high-speed data cache and writing it into the flash memory.

[0028] As one embodiment of the present invention, the hardware encryption and decryption coprocessing module of the national cryptographic algorithm also integrates an instruction recognition and transparent transmission logic unit;

[0029] This unit monitors all instructions issued by the solid-state drive controller chip in real time. When it recognizes that the instruction type is data write or data read, it triggers encryption and decryption data stream processing.

[0030] When a non-data read / write instruction is identified, including instructions of type block erase, status query, or bad block management, the instruction and related parameters are directly transmitted from its master control side interface to its flash memory side interface and executed directly by the flash memory array.

[0031] To implement the above method, the present invention also provides a solid-state drive, which includes a solid-state drive controller chip, a flash memory array, and a hardware encryption / decryption coprocessing module for Chinese cryptographic algorithms.

[0032] The solid-state drive controller chip is responsible for communicating with the host system, executing the flash memory translation layer logic, and converting upper-layer logic read / write requests into flash memory read / write instructions for physical page addresses.

[0033] The flash memory chip array serves as the physical storage medium for data.

[0034] The hardware encryption / decryption coprocessing module of the national cryptographic algorithm is physically and serially set between the flash channel interface of the solid-state drive controller chip and the physical interface of the flash memory array. It is used to realize transparent encryption of written data and transparent decryption of read data on the data transmission path between the solid-state drive controller chip and the flash memory array.

[0035] As one embodiment of the present invention, the hardware encryption / decryption coprocessing module of the national cryptographic algorithm specifically includes:

[0036] The main controller-side flash memory interface has an interface protocol and timing characteristics that match the interface standard of the flash memory chip array. It is used to receive flash memory read / write commands and plaintext data issued by the solid-state drive main controller chip, and return decrypted plaintext data to it.

[0037] The physical interface on the flash memory side has an interface protocol and timing characteristics that match the interface standard of the flash memory chip array. It is used to write encrypted ciphertext data to the flash memory chip array and read ciphertext data from it.

[0038] The hardware data encryption and decryption engine has a built-in hardware logic circuit for the national cryptographic SM4 algorithm, which is used to perform high-speed encryption and decryption operations on data in a pipeline manner.

[0039] The key management unit has a built-in secure storage medium for storing data encryption keys and providing the hardware data encryption / decryption engine with the keys required for computation according to instructions.

[0040] The data flow control logic unit connects the main control side flash memory interface, the flash memory side physical interface, the hardware data encryption / decryption engine, and the key management unit. It is responsible for parsing instructions from the main control and scheduling the flow of data between units within the module according to the instruction type, and controlling the execution of the entire encryption or decryption process.

[0041] In one embodiment of the present invention, the solid-state drive controller chip is a general-purpose commercial solid-state drive controller chip, whose internal firmware and hardware do not contain any acceleration function of national cryptographic algorithms; the national cryptographic algorithm hardware encryption and decryption coprocessing module is a field-programmable gate array chip or an application-specific integrated circuit chip independent of the solid-state drive controller chip.

[0042] As one embodiment of the present invention, the data flow control logic unit of the national cryptographic algorithm hardware encryption / decryption coprocessing module has the following specific workflow when processing write instructions:

[0043] The write command and address information are detected through the main control side flash memory interface. Then the data channel is switched to receive mode and the plaintext data pages to be transmitted are imported into the internal high-speed data cache.

[0044] After receiving all the data, request the currently valid data encryption key from the key management unit;

[0045] Then, using a preset data block size as the unit, the plaintext data block in the high-speed data cache, along with the key, is sent to the encryption port of the hardware data encryption and decryption engine;

[0046] After the hardware data encryption / decryption engine completes the encryption operation, it writes the output ciphertext data block back to the designated area of ​​the high-speed data cache.

[0047] After the entire data page is encrypted, the data flow control logic unit switches to flash write mode and writes the entire page of encrypted data in the high-speed data cache to the physical page address specified by the instruction through the physical interface on the flash side.

[0048] After the write operation is complete, a completion status signal is returned to the SSD controller chip.

[0049] As one embodiment of the present invention, the data flow control logic unit of the national cryptographic algorithm hardware encryption / decryption coprocessing module has the following specific workflow when processing read instructions:

[0050] The read command and address information are detected through the flash memory interface on the main control side. The address information is then transmitted to the physical interface on the flash memory side, and the flash memory read operation is initiated.

[0051] The encrypted data pages read from the flash memory array are directly sent to the internal high-speed data cache;

[0052] After receiving the data, request the data encryption key from the key management unit;

[0053] Then, in units of data blocks, the ciphertext data blocks in the high-speed data cache are sent together with the key to the decryption port of the hardware data encryption and decryption engine;

[0054] After the hardware data encryption / decryption engine completes the decryption operation, it writes the output plaintext data block back to another area of ​​the high-speed data cache.

[0055] After the entire data page is decrypted, the data flow control logic unit switches to master control response mode and transmits the entire page of plaintext data in the high-speed data cache to the solid-state drive master control chip through the master control side flash memory interface;

[0056] Once the transmission is complete, the entire reading process ends.

[0057] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0058] 1. High-performance encryption and decryption using national cryptographic algorithms are achieved. This invention executes national cryptographic algorithms through a dedicated hardware coprocessing module, completely separating the encryption and decryption operations from the general-purpose processor of the main control chip. By utilizing a hardware pipeline processing mechanism, the data encryption and decryption rate can be matched with the physical read and write rate of the flash memory array, completely eliminating the performance bottleneck caused by software simulation algorithms and ensuring that the solid-state drive still has high-speed read and write performance after enabling national cryptographic encryption.

[0059] 2. Improved compatibility and economy of the solution. This invention allows the direct use of mature, high-performance general-purpose solid-state drive controller chips that do not have hardware acceleration functions for national cryptographic algorithms, without the need to redesign the controller chip or modify its firmware. This greatly reduces the R&D cost and time to market of national cryptographic solid-state drives, while fully utilizing the technical advantages of general-purpose controllers in flash memory management, wear leveling and other aspects.

[0060] 3. Complete transparency to the main control chip is achieved. The hardware encryption and decryption coprocessing module of the national cryptographic algorithm is invisible to the solid-state drive main control chip. The main control chip always believes that it is directly operating the standard flash memory chip array. Its complex core algorithms such as flash memory conversion layer, garbage collection, and bad block management do not need to be modified in any way, ensuring the stability and reliability of the entire solid-state drive system.

[0061] 4. Enhanced key security: This invention integrates key storage and management functions into an independent hardware coprocessing module and injects keys through a dedicated out-of-band channel, achieving physical isolation between the key and the main control chip software operating environment. This reduces the risk of keys being stolen by malware or firmware vulnerabilities and improves the security of the entire encryption system. Attached Figure Description

[0062] Figure 1 This is a schematic diagram of the overall technical solution architecture of the solid-state drive with data encryption function proposed in this invention;

[0063] Figure 2This is a schematic diagram of the core principle framework of the hardware encryption and decryption coprocessing module of the Chinese cryptographic algorithm of this invention;

[0064] Figure 3 This is a flowchart illustrating the logical process of key initialization and secure injection in this invention.

[0065] Figure 4 This is a flowchart illustrating the transparent encryption processing logic for writing data in this invention.

[0066] Figure 5 This is a flowchart illustrating the transparent decryption processing logic for reading data in this invention.

[0067] Figure 6 This is a schematic diagram of the multi-level interaction and data flow between the solid-state drive controller chip, the national cryptographic algorithm hardware encryption / decryption coprocessor module, and the flash memory chip array in this invention. Detailed Implementation

[0068] Please refer to Figures 1 to 6 This invention provides a solid-state drive (SSD) data encryption method and an SSD, aiming to solve the technical problem that the performance of general-purpose SSD controller chips is severely limited when executing national cryptographic standards due to the lack of hardware acceleration capabilities for national cryptographic algorithms.

[0069] This method introduces an independent hardware encryption and decryption coprocessor module based on national cryptographic algorithms, which is serially deployed on the data bus between the solid-state drive controller chip and the flash memory array. This enables transparent encryption of written data and transparent decryption of read data, thereby achieving a high-speed, secure, and transparent data protection mechanism that complies with the standards without modifying the hardware architecture and firmware logic of the controller chip.

[0070] The solid-state drive data encryption method includes the following steps:

[0071] The hardware encryption and decryption coprocessing module of the national cryptographic algorithm receives a flash write command issued by the solid-state drive controller chip, which carries the target physical page address and the plaintext data to be written.

[0072] It calls the preset data encryption key in its internal key management unit, drives the built-in hardware data encryption and decryption engine, performs the national standard symmetric encryption algorithm operation on the plaintext data to be written, and generates the corresponding ciphertext data;

[0073] The generated encrypted data is written to the specified physical storage cell of the flash memory array according to the target physical page address in the flash write instruction;

[0074] When a flash read command carrying the target physical page address is received from the solid-state drive controller chip, the pre-stored encrypted data is read from the flash memory array according to the address.

[0075] The data encryption key in the key management unit is invoked to drive the hardware data encryption and decryption engine to perform the national standard symmetric decryption algorithm on the ciphertext data and restore it to the original plaintext data.

[0076] The restored original plaintext data is returned to the SSD controller chip to complete the response to the flash memory read command.

[0077] Before performing the above data encryption and decryption process, the method also includes a key initialization step.

[0078] This step involves receiving the root key issued by the host system via the out-of-band communication interface reserved on the solid-state drive controller chip.

[0079] The out-of-band communication interface is a serial communication bus independent of the flash data bus. Its physical layer can be implemented using I2C, SPI, or UART protocols. Logically, it is completely isolated from the flash channel of the main control chip, ensuring that the key transmission process is not interfered with by the regular data stream.

[0080] The key management unit inside the hardware encryption and decryption coprocessing module of the national cryptographic algorithm receives and securely stores the root key, and generates a data encryption key for data encryption and decryption based on the root key through a preset key derivation function.

[0081] The key derivation function adopts the KDF algorithm that conforms to the national cryptographic standard. Its input parameters include the root key, the device unique identifier, and the fixed salt value. The output is a data encryption key with a length of 128 bits.

[0082] The generated data encryption key is loaded into the key register of the hardware data encryption / decryption engine for use in subsequent encryption / decryption operations.

[0083] The key management unit integrates a one-time programmable memory or a physically unclonable function circuit to ensure that the key is securely stored and cannot be read or tampered with externally after a power outage.

[0084] The hardware data encryption and decryption engine executes the national standard symmetric encryption algorithm, which is the SM4 block cipher algorithm.

[0085] The algorithm encrypts 128-bit data blocks with a 128-bit key. Its internal structure contains 32 rounds of nonlinear transformations, each round using a fixed S-box and a linear diffusion layer.

[0086] To adapt to the data access characteristics of block storage devices, the hardware data encryption and decryption engine adopts the XTS advanced encryption standard mode.

[0087] In XTS Advanced Encryption Standard mode, the encryption of each data block depends not only on the key, but also on an adjustment value determined by the data block's position in the logical address space.

[0088] Specifically, when performing encryption operations, the hardware encryption and decryption coprocessing module of the national cryptographic algorithm inputs the logical block address information contained in the flash memory write instruction as an adjustment value to the hardware data encryption and decryption engine.

[0089] The logical block address, after being formatted, forms a 128-bit adjustment vector, which is used for second key generation and block encryption perturbation in the XTS advanced encryption standard mode.

[0090] This design ensures that even if two physical pages store the exact same plaintext data, the generated ciphertext will be completely different as long as their logical addresses are different, preventing pattern leakage and replay attacks.

[0091] The hardware encryption / decryption coprocessing module of the national cryptographic algorithm integrates a high-speed data cache, the capacity of which covers at least a complete physical page of flash memory, with a typical value of 16 kilobytes.

[0092] When receiving plaintext data to be written, the solid-state drive controller chip continuously transmits plaintext data in page units through the flash data bus, and the national cryptographic algorithm hardware encryption and decryption coprocessing module temporarily stores the entire page of plaintext data in the first area of ​​the high-speed data cache.

[0093] After the data is received, the hardware data encryption and decryption engine divides the plaintext data in the buffer into blocks of 128 bits and performs SM4-XTS encryption operations in sequence.

[0094] After each data block is encrypted, the generated ciphertext block is written back to the second area of ​​the high-speed data cache.

[0095] Once all the data on the entire page has been encrypted, the data flow control logic unit switches the data channel and writes the entire page of encrypted data in the second area of ​​the high-speed data cache to the target physical page address of the flash memory array through the flash memory side physical interface.

[0096] This caching mechanism avoids direct data contention between the encryption / decryption engine and the flash memory array, ensuring that the encryption / decryption pipeline can run at full speed without being affected by flash write latency.

[0097] During the reading process, when the hardware encryption and decryption coprocessor of the national cryptographic algorithm detects a flash memory read command, it first transmits the target physical page address in the command to the physical interface on the flash memory side, and starts the read operation of the flash memory array.

[0098] The encrypted data pages returned by the flash memory array are directly imported into the first area of ​​the high-speed data cache. After the data reception is complete, the hardware data encryption and decryption engine performs SM4-XTS decryption operations on the encrypted data blocks in 128-bit units, and the decryption results are written to the second area of ​​the high-speed data cache.

[0099] Once the entire page is decrypted, the data flow control logic unit switches to master control response mode and transmits the plaintext data page in the second area back to the solid-state drive master control chip byte by byte through the master control side flash memory interface.

[0100] The entire process is completely transparent to the main control chip. The main control chip only perceives a standard flash memory read operation and does not need to know that the data has undergone encrypted storage and decryption.

[0101] The hardware encryption / decryption coprocessing module of the national cryptographic algorithm also integrates an instruction recognition and transparent transmission logic unit.

[0102] This unit continuously monitors all instruction streams on the master-side flash memory interface and determines their type based on the instruction opcode.

[0103] When a data write or data read instruction is detected, the above encryption / decryption data stream processing flow is triggered; when a non-data read / write instruction such as block erase, status query, bad block marking, ID read, or reset is detected, the instruction and all its parameters are directly transmitted from the main control side interface to the flash memory side physical interface without modification, and then executed directly by the flash memory array.

[0104] This design ensures that the original flash memory management logic of the SSD controller chip, including advanced functions such as garbage collection, wear leveling, and bad block replacement, can run normally without any adaptation or modification.

[0105] The main control chip always assumes that it is directly connected to standard NAND flash memory chips, thereby maintaining the overall stability and compatibility of the system.

[0106] The hardware architecture of the solid-state drive includes a solid-state drive controller chip, a flash memory array, and a hardware encryption / decryption coprocessor module for Chinese cryptographic algorithms.

[0107] The solid-state drive controller chip is a general commercial model, which does not contain any hardware acceleration unit for national cryptographic algorithms, nor does it integrate the SM4 algorithm software implementation in its firmware.

[0108] The main control chip is responsible for communicating with the host system via SATA, PCIe or NVMe protocols, performing flash translation layer functions such as logic-to-physical address mapping, wear leveling, error correction code calculation, and garbage collection, and converting upper-layer logic read and write requests into flash read and write instruction sequences for physical page addresses.

[0109] A flash memory array consists of multiple NAND flash memory chips, which serve as the physical storage medium for data. Its interface standard is ONFI or ToggleMode, and it supports page programming, block erasure, and random read operations.

[0110] The hardware encryption and decryption coprocessing module of the national cryptographic algorithm is physically located between the output end of the flash memory channel of the main control chip and the input end of the flash memory chip array, forming the necessary path for data flow.

[0111] The hardware encryption and decryption coprocessing module for the national cryptographic algorithm specifically includes a main control side flash memory interface, a flash memory side physical interface, a hardware data encryption and decryption engine, a key management unit, and a data flow control logic unit.

[0112] The electrical characteristics, timing parameters, and protocol command set of the main controller's flash memory interface are strictly matched to the standard of the connected flash memory array, making it impossible for the solid-state drive controller chip to distinguish whether its connected object is a real flash memory or a coprocessor module.

[0113] The physical interface on the flash memory side also follows the same standard, ensuring that the coprocessor module can seamlessly drive the back-end flash memory array.

[0114] The hardware data encryption and decryption engine is composed of dedicated logic gate circuits, which solidify all round functions and key expansion logic of the SM4 algorithm, support the completion of one round of encryption operation in a single cycle, and have an overall encryption throughput of more than 2000 megabits per second.

[0115] The key management unit includes a secure storage area, key derivation logic, and access control circuitry. It only allows the data flow control logic unit to read the currently valid key during the encryption and decryption process, and prohibits any form of external access.

[0116] The data flow control logic unit is the state machine-driven control core. It dynamically configures the internal data path according to the instruction type, coordinates cache read and write, engine calls and interface switching, and ensures the atomicity and integrity of the encryption and decryption process.

[0117] During the detailed execution of the write process, the data flow control logic unit first detects the page programming command and its accompanying column and row addresses on the master-side flash memory interface.

[0118] The row address is the target physical page address, and the column address indicates the starting offset of the data.

[0119] The main control chip then begins transmitting plaintext data. The data flow control logic unit switches the data channel to the first area of ​​the high-speed data cache and records the data length.

[0120] Data reception ends upon receiving a page programming confirmation signal.

[0121] At this point, the data flow control logic unit sends a key request to the key management unit to obtain the current data encryption key.

[0122] Then it divides the data in the first area of ​​the high-speed data cache into 128-bit blocks and sends them sequentially to the encryption input port of the hardware data encryption and decryption engine.

[0123] The engine processes data blocks in each clock cycle and outputs ciphertext blocks to a specified output buffer.

[0124] The data flow control logic unit writes the ciphertext block to the corresponding location in the second region of the high-speed data cache.

[0125] After the entire page is encrypted, it constructs standard page programming instructions and writes the encrypted data in the second area into the target physical page of the flash memory array through the flash memory side physical interface.

[0126] After the write operation is completed, the flash memory array returns a status register value, which the coprocessor module transmits back to the main control chip to complete the entire write transaction.

[0127] During the detailed execution of the read process, the data flow control logic unit detects the page read command and the target physical page address on the master-side flash memory interface.

[0128] It immediately sends the address to the flash memory array through the flash memory side physical interface and initiates the read timing.

[0129] After the flash memory array completes the data preparation internally, it begins to output encrypted data pages.

[0130] The coprocessor module directly imports the data stream into the first area of ​​the high-speed data cache.

[0131] After data reception is complete, the data flow control logic unit requests the key management unit to provide the data encryption key and initiates the decryption process. The ciphertext data blocks are fed one by one into the decryption input port of the hardware data encryption and decryption engine. The engine performs the reverse SM4-XTS operation and outputs the plaintext block to the output buffer.

[0132] The plaintext block is written to the second region of the high-speed data cache.

[0133] Subsequently, the data flow control logic unit responds to the data request signal from the main control chip and outputs the plaintext data in the second area in byte order through the main control side flash memory interface.

[0134] Once the output is complete, the entire read transaction ends.

[0135] The hardware encryption / decryption coprocessing module of the national cryptographic algorithm can be implemented using a field-programmable gate array (FPGA) chip or a dedicated integrated circuit (ASIC) chip.

[0136] If a field-programmable gate array (FPGA) chip is used, its logic resources must meet the requirements of 32 rounds of parallel expansion of the SM4 algorithm, and it must integrate a sufficiently large on-chip memory as a high-speed data cache.

[0137] If dedicated integrated circuit chips are used, power consumption and area can be further optimized, and integration can be improved.

[0138] Regardless of the implementation method used, its external interface remains consistent, ensuring compatibility with general-purpose controller chips and flash memory arrays from different manufacturers.

[0139] Throughout the entire data encryption and decryption process, all intermediate states are processed within the coprocessor module and are not exposed to the external bus.

[0140] The key is never presented in plaintext in any storage area accessible to the main control chip, nor is it transmitted via the flash data bus.

[0141] The out-of-band communication interface is only enabled during the system initialization phase. After key injection is completed, it can be physically circuit-broken or logically disabled to prevent key tampering during runtime.

[0142] The hardware data encryption / decryption engine is designed to automatically clear its internal registers when idle to prevent residual data leakage.

[0143] The high-speed data cache performs an overwrite and clear operation after each encryption / decryption task to ensure that plaintext and ciphertext do not remain in the cache for a long time.

[0144] Through the above methods and system architecture, this invention achieves high-performance, high-security, and high-transparency integration of national cryptographic algorithms on a general-purpose solid-state drive platform.

[0145] The encryption and decryption operations are entirely handled by a dedicated hardware coprocessing module. The main control chip does not need to participate in any cryptographic operations, and its original firmware logic remains unchanged.

[0146] The data encryption and decryption rate is determined by the hardware engine, which can match or even exceed the physical bandwidth of high-end flash memory chips, completely eliminating the performance bottleneck caused by software simulation.

[0147] Key management and data processing are physically isolated from the main control unit, significantly improving the system's resistance to attacks.

[0148] This solution is applicable to sectors such as government affairs, finance, and energy, which have mandatory compliance requirements for data security, and can meet the implementation requirements of national cryptographic standards without sacrificing performance.

[0149] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0150] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A solid-state drive data encryption method, characterized in that, The method is applied to a solid-state drive (SSD) comprising a SSD controller chip, a hardware encryption / decryption coprocessor module for Chinese cryptographic algorithms, and a flash memory array, wherein the hardware encryption / decryption coprocessor module for Chinese cryptographic algorithms is serially configured on the data bus between the SSD controller chip and the flash memory array; the method includes: The hardware encryption / decryption coprocessing module of the national cryptographic algorithm receives a flash memory write command issued by the main control chip of the solid-state drive, which carries the target physical page address and the plaintext data to be written. The hardware encryption and decryption coprocessing module of the national cryptographic algorithm calls the preset data encryption key in the internal key management unit to drive its built-in hardware data encryption and decryption engine to perform the national cryptographic symmetric encryption algorithm operation on the plaintext data to be written, and generate ciphertext data corresponding to the plaintext data. The hardware encryption and decryption coprocessing module of the national cryptographic algorithm writes the generated ciphertext data to the designated physical storage unit of the flash memory chip array according to the target physical page address in the flash memory write instruction; The hardware encryption / decryption coprocessing module of the national cryptographic algorithm receives a flash memory read command carrying the target physical page address issued by the main control chip of the solid-state drive; The hardware encryption and decryption coprocessing module of the national cryptographic algorithm reads the pre-stored ciphertext data from the corresponding physical storage unit of the flash memory chip array according to the target physical page address in the flash memory read instruction; The hardware encryption and decryption coprocessing module of the national cryptographic algorithm calls the data encryption key in the internal key management unit to drive the hardware data encryption and decryption engine to perform the national cryptographic symmetric decryption algorithm operation on the read ciphertext data and restore the ciphertext data to the original plaintext data; The hardware encryption and decryption coprocessing module of the national cryptographic algorithm returns the restored original plaintext data to the solid-state drive main controller chip to complete the response to the flash memory read command; The hardware data encryption and decryption engine executes the national standard symmetric encryption algorithm SM4 block cipher algorithm. The hardware data encryption and decryption engine uses the XTS advanced encryption standard mode optimized for block storage devices; When performing encryption operations, the hardware encryption and decryption coprocessing module of the national cryptographic algorithm also inputs the logical block address information contained in the flash memory write instruction as an adjustment value into the hardware data encryption and decryption engine for encryption operations in the XTS advanced encryption standard mode. The hardware encryption and decryption coprocessing module of the national cryptographic algorithm also integrates an instruction recognition and transparent transmission logic unit; This unit monitors all instructions issued by the solid-state drive controller chip in real time. When it recognizes that the instruction type is data write or data read, it triggers encryption and decryption data stream processing. When a non-data read / write instruction is identified, including instructions of type block erase, status query, or bad block management, the instruction and related parameters are directly transmitted from its master control side interface to its flash memory side interface and executed directly by the flash memory array.

2. The solid-state drive data encryption method according to claim 1, characterized in that, Before receiving instructions from the solid-state drive controller chip, a key initialization step is also included: The root key issued by the host system is received through the out-of-band communication interface reserved by the solid-state drive controller chip; the out-of-band communication interface is a serial communication bus independent of the flash memory data bus. The key management unit inside the hardware encryption and decryption coprocessing module of the national cryptographic algorithm receives and securely stores the root key, generates a data encryption key for data encryption and decryption based on the root key through a preset key derivation function, and loads the data encryption key into the key register of the hardware data encryption and decryption engine.

3. The solid-state drive data encryption method according to claim 2, characterized in that, The hardware encryption / decryption coprocessing module of the national cryptographic algorithm integrates a high-speed data cache. The specific steps of receiving the plaintext data to be written are as follows: temporarily storing the entire page of plaintext data transmitted by the solid-state drive controller chip through the flash memory data bus into the high-speed data cache; After generating the ciphertext data, the process also includes temporarily storing the generated full-page ciphertext data back to another area of ​​the high-speed data cache. The specific steps of writing the encrypted data into the flash memory array are as follows: reading the entire page of encrypted data from the high-speed data cache and writing it into the flash memory.

4. The solid-state drive data encryption method according to claim 2, characterized in that, The key derivation function adopts the KDF algorithm that conforms to the national cryptographic standard. Its input parameters include the root key, the device unique identifier, and a fixed salt value, and it outputs the data encryption key. The key management unit integrates a one-time programmable memory or a physically unclonable function circuit for securely storing the root key and the data encryption key.

5. The solid-state drive data encryption method according to claim 1, characterized in that, During the write process, after receiving the page programming confirmation signal, the data flow control logic unit initiates a key request to the key management unit to obtain the current data encryption key, and sequentially sends the plaintext data blocks in the high-speed data cache to the encryption input port of the hardware data encryption and decryption engine. After encryption is complete, the ciphertext data block is written back to the second area of ​​the high-speed data cache, and the entire page of ciphertext data is written to the target physical page address of the flash memory array through the flash memory side physical interface.

6. The solid-state drive data encryption method according to claim 1, characterized in that, During the read process, the data flow control logic unit imports the encrypted data pages returned by the flash memory array into the first area of ​​the high-speed data cache; After receiving the data, request the key management unit to provide the data encryption key, and send the ciphertext data blocks one by one into the decryption input port of the hardware data encryption and decryption engine; The decryption result is written to the second area of ​​the high-speed data cache, and the entire page of plaintext data is transmitted back to the solid-state drive controller chip through the main controller's flash memory interface.

7. A solid-state drive, characterized in that, Solid-state drive (SSD) data encryption is implemented using the SSD data encryption method according to any one of claims 1 to 6, wherein the SSD comprises: Solid-state drive controller chip is used to communicate with the host system, execute flash translation layer logic, and convert upper-layer logic read and write requests into flash read and write instructions for physical page addresses; Flash memory arrays serve as the physical storage medium for data. The hardware encryption and decryption coprocessing module of the national cryptographic algorithm is physically and serially set between the flash channel interface of the solid-state drive controller chip and the physical interface of the flash memory array. It is used to realize transparent encryption of written data and transparent decryption of read data on the data transmission path between the solid-state drive controller chip and the flash memory array.

8. The solid-state drive according to claim 7, characterized in that, The hardware encryption / decryption coprocessing module for the national cryptographic algorithm specifically includes: The main controller-side flash memory interface has an interface protocol and timing characteristics that match the interface standard of the flash memory chip array. It is used to receive flash memory read / write commands and plaintext data issued by the solid-state drive main controller chip, and return decrypted plaintext data to it. The physical interface on the flash memory side has an interface protocol and timing characteristics that match the interface standard of the flash memory chip array. It is used to write encrypted ciphertext data to the flash memory chip array and read ciphertext data from it. The hardware data encryption and decryption engine has a built-in hardware logic circuit for the national cryptographic SM4 algorithm, which is used to perform high-speed encryption and decryption operations on data in a pipeline manner. The key management unit has a built-in secure storage medium for storing data encryption keys and providing the hardware data encryption / decryption engine with the keys required for computation according to instructions. The data flow control logic unit connects the main control side flash memory interface, the flash memory side physical interface, the hardware data encryption / decryption engine, and the key management unit. It is responsible for parsing instructions from the main control and scheduling the flow of data between units within the module according to the instruction type, and controlling the execution of the entire encryption or decryption process.

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