Semiconductor device

Abstract

Provided is a semiconductor device that has high field-effect mobility. The present invention comprises: a metal oxide layer; an oxide semiconductor; first to fourth insulators; and first to third conductors. The second insulator is arranged on the first insulator. The metal oxide layer is arranged on the second insulator. The oxide semiconductor is arranged on the first insulator and covers a wall-like structure composed of the metal oxide layer and the second insulator. The first conductor and the second conductor are arranged on the oxide semiconductor. The third insulator is arranged on the first conductor and the second conductor and has an opening that is superposed on a region between the first conductor and the second conductor. The fourth insulator is disposed within the opening so as to overlap the oxide semiconductor. The third conductor is disposed on the fourth insulator within the opening. In a cross-sectional view in the channel width direction, the height of the wall-like structure is greater than the width of the wall-like structure. The metal oxide layer contains indium and has a crystal. The oxide semiconductor contains indium and has a crystal having a cubic crystal structure.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device using an oxide semiconductor layer. Another aspect of the present invention relates to a method for manufacturing the above-mentioned semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs (Large Scale Integration), CPUs (Central Processing Units), and memory are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) formed on chips by processing semiconductor wafers, and electrodes which are connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that takes advantage of the low leakage current characteristic of transistors using oxide semiconductors. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time by taking advantage of the low leakage current characteristic of transistors using oxide semiconductors.

[0008] Furthermore, Patent Document 3 discloses a transistor with a microstructure in which a source electrode layer and a drain electrode layer are provided in contact with the upper surface of an oxide semiconductor.

[0009] Also, In ２ O ３ Its use in thin-film transistors has been reported (Non-Patent Document 1).

[0010] Japanese Patent Publication No. 2012-257187, Japanese Patent Publication No. 2011-151383, International Publication No. 2016-125052

[0011] Dhananjay and C. W. Chu. “Realization of In2O3 thin film transistors through reactive evaporation process.” Appl. Phys. Lett. 91, 132111 (2007). Takashi Koida, “High-mobility transparent conductive film,” National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0012] One aspect of the present invention aims to provide a semiconductor device with high field-effect mobility. Alternatively, one aspect of the present invention aims to provide a semiconductor device with high operating speed. Alternatively, one aspect of the present invention aims to provide a semiconductor device with high reliability. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Alternatively, one aspect of the present invention aims to provide a semiconductor device with little variation in the electrical characteristics of transistors. Alternatively, one aspect of the present invention aims to provide a semiconductor device with high on-current. Alternatively, one aspect of the present invention aims to provide a semiconductor device with low power consumption. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device. Alternatively, one aspect of the present invention aims to provide a method for manufacturing a highly productive semiconductor device. Alternatively, one aspect of the present invention aims to provide a method for manufacturing a novel semiconductor device.

[0013] Alternatively, one aspect of the present invention aims to provide a storage device that can be miniaturized or highly integrated. Alternatively, one aspect of the present invention aims to provide a storage device with a large storage capacity. Alternatively, one aspect of the present invention aims to provide a storage device with a fast operating speed. Alternatively, one aspect of the present invention aims to provide a storage device with low power consumption. Alternatively, one aspect of the present invention aims to provide a novel storage device.

[0014] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0015] One aspect of the present invention comprises a metal oxide layer, an oxide semiconductor, first to fourth insulators, and first to third conductors, wherein the second insulator is disposed on the first insulator, the metal oxide layer is disposed on the second insulator, the oxide semiconductor is disposed on the first insulator and covers a wall-like structure made of the metal oxide layer and the second insulator, the first and second conductors are disposed on the oxide semiconductor, the third insulator is disposed on the first and second conductors and has an opening that overlaps with the region between the first and second conductors, and the fourth insulator is an oxide semiconductor The semiconductor device is arranged overlapping the body and within the opening, the third conductor is arranged on the fourth insulator within the opening, and in a cross-sectional view in the channel width direction, the height of the wall-like structure is greater than the width of the wall-like structure, the metal oxide layer contains indium and has crystals, the oxide semiconductor contains indium and has crystals with a cubic crystal structure, the oxide semiconductor has a first region in contact with the side surface of the wall-like structure and a second region in contact with the upper surface of the wall-like structure, and the crystal orientation of the crystal grains of the first region and the crystal orientation of the crystal grains of the second region are coincident or substantially coincident.

[0016] In the above, it is preferable that the crystal orientation of the crystal grains in the first region and the crystal orientation of the crystal grains in the second region are <111>.

[0017] Furthermore, in the above, it is preferable that the metal oxide layer has a cubic crystal structure.

[0018] Furthermore, it is preferable that the metal oxide layer contains indium, gallium, and zinc, and has a hexagonal or trigonal crystal structure.

[0019] Furthermore, in the above, it is preferable that the side surface of the metal oxide layer coincides with or substantially coincides with the side surface of the second insulator in a plan view.

[0020] Furthermore, in the above, it is preferable that the second insulator has gallium oxide, aluminum oxide, or silicon oxide.

[0021] Furthermore, in the above, it is preferable that the side surface of the first insulator coincides with or substantially coincides with the side surface of the oxide semiconductor, the side surface of the first conductor, and the side surface of the second conductor in a plan view, and that the film thickness of the first insulator is thicker than the film thickness of the fourth insulator.

[0022] Furthermore, in the above, it is preferable that the lower surface of the third conductor has a portion located below the lower surface of the oxide semiconductor.

[0023] Furthermore, in the above, it is preferable that a fifth insulator is present, and the first conductor and the second conductor each have a first conductive layer and a second conductive layer on the first conductive layer, and the fifth insulator is disposed within the opening of the third insulator and is in contact with the upper surface of the first conductive layer of the first conductor, the side surface of the second conductive layer of the first conductor, the upper surface of the first conductive layer of the second conductor, and the side surface of the second conductive layer of the second conductor, and the shortest distance between the first conductive layer of the first conductor and the first conductive layer of the second conductor is smaller than the shortest distance between the second conductive layer of the first conductor and the second conductive layer of the second conductor.

[0024] Furthermore, in the above, it is preferable that a portion of the side surface of the third insulator coincides with or substantially coincides with the side surface of the second conductive layer of the first conductor and the side surface of the second conductive layer of the second conductor in a plan view.

[0025] Furthermore, in the above, it is preferable that the fifth insulator has silicon nitride.

[0026] Furthermore, it is preferable that the first conductive layer of the first conductor and the first conductive layer of the second conductor each contain indium and tin, respectively.

[0027] According to one aspect of the present invention, a semiconductor device with high field-effect mobility can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with high operating speed can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with little variation in the electrical characteristics of transistors can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with high on-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a method for manufacturing a highly productive semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0028] Alternatively, according to one aspect of the present invention, a storage device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a storage device with a large storage capacity can be provided. Alternatively, according to one aspect of the present invention, a storage device with a fast operating speed can be provided. Alternatively, according to one aspect of the present invention, a storage device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, a novel storage device can be provided.

[0029] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0030] Figure 1A is a plan view showing an example of a semiconductor device. Figures 1B, 1C, and 1D are cross-sectional views showing an example of a semiconductor device. Figures 2A and 2B are cross-sectional views showing an example of a semiconductor device. Figures 3A, 3B, and 3C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 4A and 4B are cross-sectional views showing an example of a semiconductor device. Figure 5 is a cross-sectional view showing an example of a semiconductor device. Figures 6A, 6B, and 6C are cross-sectional views showing an example of a semiconductor device. Figures 7A and 7B are cross-sectional views showing an example of a semiconductor device. Figures 8A, 8B, and 8C are cross-sectional views showing an example of a semiconductor device. Figures 9A, 9B, and 9C are cross-sectional views showing an example of a semiconductor device. Figures 10A and 10B are cross-sectional views showing an example of a semiconductor device. Figure 11A is a plan view showing an example of a semiconductor device. Figures 11B, 11C, and 11D are cross-sectional views showing an example of a semiconductor device. Figure 12A is a plan view showing an example of a semiconductor device. Figures 12B, 12C, and 12D are cross-sectional views showing an example of a semiconductor device. Figures 13A, 13B, and 13C are cross-sectional views showing an example of a semiconductor device. Figure 14A is a plan view showing an example of a semiconductor device manufacturing method. Figures 14B, 14C, and 14D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 15A is a plan view showing an example of a semiconductor device manufacturing method. Figures 15B, 15C, and 15D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 16A is a plan view showing an example of a semiconductor device manufacturing method. Figures 16B, 16C, and 16D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 17A is a plan view showing an example of a semiconductor device manufacturing method. Figures 17B, 17C, and 17D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 18A is a plan view showing an example of a semiconductor device manufacturing method. Figures 18B, 18C, and 18D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 19A is a plan view showing an example of a semiconductor device manufacturing method. Figures 19B, 19C, and 19D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 20A is a plan view showing an example of a semiconductor device manufacturing method. Figures 20B, 20C, and 20D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 21A is a plan view showing an example of a semiconductor device manufacturing method.Figures 21B, 21C, and 21D are cross-sectional views showing an example of a semiconductor device fabrication method. Figure 22A is a plan view showing an example of a semiconductor device fabrication method. Figures 22B, 22C, and 22D are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 23A and 23B are diagrams illustrating the carrier concentration dependence of Hall mobility. Figure 23C is a cross-sectional view illustrating an indium oxide film. Figures 24A and 24B are examples of the configuration of a display device. Figure 25 is an example of the configuration of a display device. Figure 26 is an example of the configuration of a display device. Figure 27 is an example of the configuration of a display device. Figures 28A, 28B, 28C, 28D, 28E, and 28F are examples of the configuration of electronic equipment. Figures 29A, 29B, 29C, 29D, 29E, and 29F are examples of the configuration of electronic equipment. Figures 30A, 30B, 30C, 30D, 30E, 30F, and 30G show examples of electronic device configurations. Figure 31 is a block diagram illustrating an example of a semiconductor device configuration. Figures 32A, 32B, 32C, 32D, 32E, 32F, 32G, and 32H illustrate examples of memory cell circuit configurations. Figures 33A and 33B show examples of electronic components. Figures 34A, 34B, and 34C show examples of large-scale computers. Figure 34D shows an example of space equipment. Figure 34E shows an example of a storage system applicable to data centers. Figures 35A and 35B are perspective views of semiconductor devices. Figure 36 is a perspective view of a semiconductor device.

[0031] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0032] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0033] Furthermore, for the sake of ease of understanding, the position, size, and scope of each component shown in the drawings may not represent their actual position, size, and scope. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0034] Furthermore, in particular, in plan views (also called "top views") or perspective views, the description of some components may be omitted to facilitate understanding of the invention. In addition, the description of some hidden lines may be omitted.

[0035] In this specification, the ordinal numbers "first," "second," etc., are used for convenience only and do not limit the number of components or the order of components (for example, process order or stacking order). Furthermore, the ordinal numbers used for components in one part of this specification may not be the same as those used for the same components in other parts of this specification or in the claims.

[0036] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer." Furthermore, the term "conductor" can be interchanged with the terms "conductive layer" or "conductive film" depending on the context or situation. Similarly, the term "insulator" can be interchanged with the terms "insulating layer" or "insulating film" depending on the context or situation.

[0037] Furthermore, in this specification, "parallel" means a state in which two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" means a state in which two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0038] An opening can include, for example, grooves and slits. Furthermore, the area in which an opening is formed may also be referred to as an opening.

[0039] Furthermore, in the drawings used in this specification, etc., the side walls of the insulator at the opening of the insulator are shown to be perpendicular or substantially perpendicular to the substrate surface or the surface to be formed, but they may also be tapered.

[0040] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface or the surface to be formed (hereinafter sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface do not necessarily have to be perfectly flat, and may be substantially planar with a small curvature, or substantially planar with fine irregularities.

[0041] In this specification, "heights are equal or nearly equal" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, in the manufacturing process of a memory device, the surfaces of one or more layers may be exposed by a planarization process (typically a chemical mechanical polishing (CMP) method). In this case, the surfaces to be processed by the CMP process have a configuration in which the heights from the reference surface are equal. However, the heights of the multiple layers may differ depending on the processing apparatus, processing method, or material of the surface to be processed during the CMP process. In this specification, this case is also treated as "heights are equal or nearly equal." For example, if there are two layers with different heights (here referred to as a first layer and a second layer) with respect to a reference surface, the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less, which is also referred to as "heights are equal or nearly equal."

[0042] In this specification, "side edges coincide or nearly coincide" or "sides coincide or nearly coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer; in this case, it is also referred to as "side edges coincide or nearly coincide" or "sides coincide or nearly coincide."

[0043] In this specification, "planar shapes matching or nearly matching" means that at least a portion of the contours overlaps between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in these cases, it may also be said that the "planar shapes matching or nearly matching." Furthermore, when the planar shapes match or nearly match, it can also mean that the edges are aligned or nearly aligned, or that the side edges match or nearly match.

[0044] In this specification and elsewhere, the cubic crystal structure is sometimes referred to as cubic crystal or cubic structure. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0045] (Embodiment 1) In this embodiment, a semiconductor device having an oxide semiconductor layer and a method for manufacturing the semiconductor device will be described with reference to Figures 1A to 22D.

[0046] <Example of Semiconductor Device Configuration> An example of a semiconductor device configuration will be explained using Figures 1A to 13C. Figures 1A to 1D are plan views and cross-sectional views of a semiconductor device having a transistor 200 on a substrate (not shown).

[0047] Figure 1A is a plan view of the semiconductor device described above. Figures 1B to 1D are cross-sectional views of the same semiconductor device. Here, Figure 1B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Figure 1C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Figure 1D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Here, the dashed line A5-A6 is perpendicular to the dashed lines A1-A2 and A3-A4, and the dashed lines A1-A2 and A3-A4 are parallel to each other. Note that in the plan view of Figure 1A, some elements have been omitted and some elements have been made transparent for clarity. Furthermore, Figure 2A shows an enlarged view of the vicinity of the conductor 260 in Figure 1D. Also, Figure 2B shows an enlarged view of the vicinity of the oxide semiconductor 230 in Figure 1B. Furthermore, Figure 9A shows an enlarged view of the vicinity of the oxide semiconductor 230 in Figure 1C. Note that in this specification, when we refer to a cross-section in the channel width direction, it does not necessarily include the channel formation region of the transistor. In some cases, the term "cross-section in the channel width direction" may include a cross-section parallel to the cross-section in the channel width direction that includes the channel formation region. For example, the cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 1C is called a cross-sectional view in the channel width direction.

[0048] The semiconductor device according to this embodiment includes an insulator 216 on a substrate (not shown), an insulator 221 on the insulator 216, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an insulator 225 on the insulator 224, a metal oxide layer 235 on the insulator 225, an oxide semiconductor 230 disposed on the insulator 224 and covering a wall-like structure made of the metal oxide layer 235 and the insulator 225, conductors 242a (conductors 242a1 and 242a2) and conductors 242b (conductors 242b1 and 242b2) on the oxide semiconductor 230, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250. Furthermore, an insulator 255 is provided between the conductors 242a2, conductors 242b2, insulator 275, and insulator 280 and insulator 250. In the following, the wall-like structure consisting of the metal oxide layer 235 and the insulator 225 may be referred to simply as the wall-like structure. Also, in the following, the conductor 242a and the conductor 242b may be referred to collectively as the conductor 242.

[0049] An insulator 271a is provided on the conductor 242a, and an insulator 271b is provided on the conductor 242b. An insulator 275 is provided on the insulators 271a, 271b, and 222, and an insulator 280 is provided on the insulator 275. An opening 201 is provided in the insulators 280 and 275. The sides of the insulator 280 and the sides of the insulator 275 function as side walls of the opening 201. The sides of the conductors 242a1, 242a2, 242b1, and 242b2 can also be considered as side walls of the opening 201. Insulators 250, 255, and 260 are arranged inside the opening 201. Furthermore, the insulator 224, the metal oxide layer 235, the insulator 225, and a portion of the oxide semiconductor 230 are also arranged inside the opening 201. The opening 201 reaches the oxide semiconductor 230 and the insulator 222, and within the opening 201, the insulator 250 is in contact with the oxide semiconductor 230 and the insulator 222.

[0050] Here, the insulator 255 is formed in the shape of a sidewall that is in contact with the side wall of the opening 201. Since the insulator 255 is provided along the side wall of the opening 201, the insulator 255 can also be considered as part of the side wall of the opening 201.

[0051] An insulator 282 is provided on the insulator 280 and on the conductor 260. An insulator 283 is provided on the insulator 282. An insulator 285 is provided on the insulator 283. An insulator 215 is provided below the insulator 216.

[0052] An insulator 241a is provided in contact with the inner wall of an opening in the insulator 280, and a conductor 240a is provided in contact with the side surface of the insulator 241a. The lower surface of the conductor 240a is in contact with the upper surface of the conductor 242a. In addition, an insulator 241b is provided in contact with the inner wall of an opening in the insulator 280, and a conductor 240b is provided in contact with the side surface of the insulator 241b. The lower surface of the conductor 240b is in contact with the upper surface of the conductor 242b. In the following, conductors 240a and 240b may be collectively referred to as conductor 240. Also, insulators 241a and 241b may be collectively referred to as insulator 241.

[0053] The oxide semiconductor 230 has a region that functions as a channel formation region of the transistor 200. The conductor 260 also has a region that functions as a gate electrode of the transistor 200. The insulator 250 has a region that functions as a gate insulator of the transistor 200.

[0054] Conductor 242a has a region that functions as either the source electrode or the drain electrode of transistor 200. Conductor 240a functions as a plug that connects to conductor 242a. Conductor 242b has a region that functions as either the source electrode or the drain electrode of transistor 200. Conductor 240b functions as a plug that connects to conductor 242b.

[0055] The conductor 242a preferably has a laminated structure of conductor 242a1 and conductor 242a2 on conductor 242a1, and the conductor 242b preferably has a laminated structure of conductor 242b1 and conductor 242b2 on conductor 242b1. The conductors 242a1 and 242b1 that are in contact with the oxide semiconductor 230 are preferably conductors that are not easily oxidized. This prevents the conductors 242a and 242b from becoming highly resistive due to oxygen contained in the oxide semiconductor 230. Therefore, the contact resistance between conductor 242a1 and the oxide semiconductor 230, and the contact resistance between conductor 242b1 and the oxide semiconductor 230 can be reduced. Furthermore, the conductors 242a2 and 242b2 are preferably conductors such as metal layers that have higher conductivity than conductors 242a1 and 242b1. This allows the conductors 242a and 242b to function as highly conductive wiring or electrodes. In this way, a semiconductor device can be provided in which the conductors 242a and 242b, which function as wiring or electrodes, are provided in contact with the upper surface of the oxide semiconductor 230, which functions as an active layer.

[0056] As shown in Figure 2A, in a cross-sectional view of the transistor 200 in the channel length direction, the distance D1 between conductor 242a1 and conductor 242b1 is smaller than the distance D2 between conductor 242a2 and conductor 242b2. Here, distance D2 refers to the shortest distance between the opposing sides of conductor 242a2 and conductor 242b2. The difference between D1 and D2 may coincide with or approximately coincide with twice the film thickness of the insulator 255. Here, the film thickness of the insulator 255 refers to the film thickness in the A5-A6 direction in at least a portion of the insulator 255. With this configuration, the distance between the source and drain can be shortened, and the channel length can be shortened accordingly. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by shortening the channel length, a semiconductor device with a high operating speed can be provided.

[0057] The opening 201 overlaps with the region between conductor 242a2 and conductor 242b2. It can also be considered that parts of conductor 242a1 and conductor 242b1 are formed to protrude into the opening 201. Therefore, the insulator 255 is in contact with the upper surface of conductor 242a1, the upper surface of conductor 242b1, the side surface of conductor 242a2, and the side surface of conductor 242b2 within the opening 201. In addition, the insulator 250 is in contact with the upper surface of insulator 222 and the upper surface of oxide semiconductor 230 in the region between conductor 242a1 and conductor 242b1.

[0058] The insulator 255 is preferably an insulator that is resistant to oxidation, such as a nitride. The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and has the function of protecting the conductor 242a2 and the conductor 242b2. After separating the conductor 242a1 and the conductor 242b1, it is preferable to perform heat treatment in an oxygen-containing atmosphere before forming the insulator 250. At this time, because the insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, it is possible to prevent the conductor 242a2 and the conductor 242b2 from being excessively oxidized.

[0059] The oxide semiconductor 230 is formed by covering a wall-like structure consisting of a metal oxide layer 235 and an insulator 225. As shown in Figures 2B and 9A, the wall-like structure has a high aspect ratio in a cross-sectional view in the channel width direction. Therefore, the wall-like structure can also be said to have a fin-like shape. Here, the aspect ratio of the wall-like structure in a cross-sectional view in the channel width direction refers to the ratio of the length L in the A1-A2 direction of the wall-like structure (which can also be called the width L of the wall-like structure) to the length H in the direction perpendicular to the surface of the wall-like structure (for example, the insulator 224) (which can also be called the height H of the wall-like structure). The aspect ratio of the wall-like structure is preferably as large as possible without causing the insulator 225 to tip over during the manufacturing process of the transistor 200. In the wall-like structure, it is preferable that the height H is greater than the width L.

[0060] A high aspect ratio wall-like structure is covered by an oxide semiconductor 230 and a conductor 242. Near the channel formation region of the transistor 200, as shown in Figure 2B, the oxide semiconductor 230 is provided in a folded state with the wall-like structure in between. As a result, in a cross-sectional view in the channel width direction, the oxide semiconductor 230 and the conductor 260 are provided facing each other with the insulator 250 in between at the top of the wall-like structure, the side on the A1 side, the side on the A2 side, and near the insulator 224. In other words, the top of the oxide semiconductor 230, the side on the A1 side, the side on the A2 side, and near the insulator 224 each function as a channel formation region. Therefore, compared to the case where the wall-like structure is not provided, the channel width of the transistor 200 is increased by the amount of the side on the A1 side and the side on the A2 side of the oxide semiconductor 230.

[0061] As described above, increasing the channel width improves the on-current, transconductance, and frequency characteristics of the transistor 200. This makes it possible to provide a semiconductor device with a high operating speed. It also makes it possible to increase the operating speed of a memory device using this semiconductor device. Furthermore, in the above structure, by covering the wall-like structure with the oxide semiconductor 230, the channel width can be increased without excessively expanding the area occupied by the transistor 200. This makes it possible to miniaturize or highly integrate the semiconductor device. It also makes it possible to increase the storage capacity of a memory device using this semiconductor device. In addition, with the above structure, the area where the sides of the conductor 260 and the oxide semiconductor 230 face each other becomes larger, so the threshold can be controlled to normally turn off the transistor 200.

[0062] Furthermore, as shown in Figure 2B, it is preferable that the film thickness t1 of the insulator 224 within the opening 201 is thicker than the film thickness t2 of the insulator 250. With this configuration, the lower surface (or lower end) of the conductor 260 located in a region within the opening 201 that does not overlap with the oxide semiconductor 230 is located below the lower surface (or lower end) of the oxide semiconductor 230. Therefore, a sufficient electric field can be applied from the conductor 260 to the upper and lower ends of the oxide semiconductor 230. This reduces the leakage current between the source electrode and the drain electrode via the lower end of the oxide semiconductor 230. In addition, it is possible to suppress characteristic defects such as normally-on behavior of the transistor caused by this leakage current. In other words, the electrical characteristics of the transistor 200 can be improved.

[0063] It is preferable that the oxide semiconductor 230 has good crystallinity. This reduces carrier scattering in the oxide semiconductor 230, enabling the realization of a transistor with high field-effect mobility. It also enables the realization of a highly reliable transistor. Furthermore, it is preferable that the metal oxide layer 235 has good crystallinity. The metal oxide layer 235 functions as a seed or nucleus when processing to improve the crystallinity of the oxide semiconductor 230, thus improving the crystallinity of the oxide semiconductor 230.

[0064] The oxide semiconductor 230 has a channel-forming region. The oxide semiconductor 230 further has a source region and a drain region. The source region and drain region are n-type regions (low-resistance regions) with a higher carrier concentration compared to the channel-forming region. The oxide semiconductor 230 may have a single-layer structure or a stacked structure of two or more layers.

[0065] The transistor 200 has a metal oxide that functions as a semiconductor in the oxide semiconductor 230, which includes a channel formation region. In the following, a transistor in which a channel is formed in an oxide semiconductor, such as transistor 200, may be referred to as an OS transistor. In this specification, since the oxide semiconductor 230 has a metal oxide, the oxide semiconductor 230 can be replaced with a metal oxide layer. In addition, a transistor having silicon in the channel formation region may be referred to as a Si transistor.

[0066] OS transistors have oxygen vacancies (V) in the channel formation region of an oxide semiconductor. Ｏ The presence of oxygen vacancies and impurities can easily lead to fluctuations in electrical properties and reduced reliability. Therefore, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region of an oxide semiconductor. In other words, it is preferable that the channel formation region in an oxide semiconductor has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0067] Furthermore, when an excess amount of oxygen is supplied to the oxide semiconductor 230, electron traps caused by the excess oxygen are formed in the insulator 250. As a result, the OS transistor becomes more susceptible to positive drift degradation in +GBT (Gate Bias-Temperature) stress tests. In other words, the amount of positive drift degradation in +GBT stress tests increases.

[0068] Therefore, in a semiconductor device according to one aspect of the present invention, it is preferable that the impurity concentration in the oxide semiconductor 230 is low. It is also preferable that an appropriate amount of oxygen is supplied to the oxide semiconductor 230. Furthermore, it is preferable to reduce the excess amount of oxygen in the oxide semiconductor 230.

[0069] It is preferable to use indium oxide for the oxide semiconductor 230. In this case, the oxide semiconductor 230 contains indium and oxygen. For example, it is preferable that the oxide semiconductor 230 has an indium oxide film. The higher the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor can be. Therefore, by using indium oxide for the oxide semiconductor 230, the transistor can obtain a large on-current and high frequency characteristics.

[0070] Furthermore, it is preferable that the indium oxide film is crystalline. For example, it is preferable that the indium oxide film has crystal grains. Examples of films having crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains. A polycrystalline film is composed of two or more crystal grains, while a single-crystal film can be considered to be composed of one crystal grain. In polycrystalline films, crystal grain boundaries (also called grain boundaries) can be observed, whereas in single-crystal films, crystal grain boundaries cannot be observed.

[0071] Furthermore, unlike polycrystalline films, single-crystal films do not exhibit grain boundaries in the channel formation region. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. Therefore, when grain boundaries are present in the channel formation region, variations in transistor characteristics become large. On the other hand, in a single-crystal film according to one aspect of the present invention, since no grain boundaries are observed in the channel formation region, it exhibits the excellent effect of suppressing variations in transistor characteristics caused by such grain boundaries.

[0072] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel-forming region can be called a single-crystal film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in one direction in the channel-forming region can be called a single-crystal film.

[0073] The channel-forming region refers to a region within a semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. Furthermore, a semiconductor layer in which no grain boundaries are observed in the region between the source electrode and the drain electrode, a semiconductor layer in which the region between the source electrode and the drain electrode is contained within a single crystal grain, or a semiconductor layer in which at least two regions located between the source electrode and the drain electrode have the same crystal axis direction can also be called a single-crystal film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in one direction in the region between the source electrode and the drain electrode can also be called a single-crystal film.

[0074] Furthermore, in the channel formation region, the current path is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientations in the channel formation region, or the region located between the region in contact with the source electrode and the region in contact with the drain electrode, can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0075] The crystallinity of the oxide semiconductor 230 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for the analysis.

[0076] Crystal grains can be identified, for example, using high-resolution transmission electron microscope (TEM) images. Furthermore, crystal grain boundaries can sometimes be identified, for example, using high-resolution TEM images. In other words, crystal grains and crystal grain boundaries can sometimes be observed in high-resolution TEM images of crystalline films. The overall magnification when acquiring TEM images is preferably 2 million times or more, and more preferably 4 million times or more.

[0077] The indium oxide film is more preferably a single-crystal film. Since a single-crystal film does not have grain boundaries, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors with high field-effect mobility. Furthermore, highly reliable transistors can be realized.

[0078] The indium oxide film may be a polycrystalline film or an amorphous film containing crystal grains. In this case, it is preferable that no crystal grain boundaries are observed or that there are few grain boundary components in the channel formation region. For example, by having one crystal grain located in the channel formation region, it is possible to create a configuration in which no crystal grain boundaries are observed in the channel formation region. Even with such a configuration, the same effects as the configuration in which the indium oxide film is a single crystal film can be achieved.

[0079] Furthermore, two or more crystal grains can be located in the channel-forming region. For example, when a first crystal grain and a second crystal grain are located in the channel-forming region, it is preferable that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or approximately coincide. When the crystal orientations of the first and second crystal grains coincide or approximately coincide, a grain boundary may not be observed at the boundary between the first and second crystal grains. By having the crystal orientations of the first and second crystal grains coincide or approximately coincide, the formation of a grain boundary between the first and second crystal grains can be suppressed. Therefore, even in such a configuration, the same effects as in a configuration where the indium oxide film is a single crystal film can be achieved. Note that the coincidence or approximately coincidence of the crystal orientations of the first and second crystal grains can sometimes be confirmed, for example, by a high-resolution TEM image. Specifically, in a high-resolution TEM image, if the lattice fringes of the first crystal grain and the lattice fringes of the second crystal grain are continuously connected at the boundary between the first and second crystal grains, then it can be said that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or nearly coincide.

[0080] In this specification, a grain boundary refers to, for example, a grain boundary formed at the boundary between adjacent grains with different crystal orientations. Therefore, in this specification, a grain boundary formed at the boundary between adjacent grains with the same crystal orientation is not included in the definition of a grain boundary. For example, even if a boundary is observed between two crystal grains in a high-resolution TEM image, if the crystal orientations of the two crystal grains are the same or nearly the same, the boundary may not be referred to as a grain boundary.

[0081] The degree of polycrystalline nature of an indium oxide film can be evaluated by the grain size. The grain size can be calculated, for example, by determining the area of ​​the grain and then determining the diameter of a circle corresponding to that area. This diameter is sometimes referred to as the area-circle equivalent diameter.

[0082] Furthermore, the degree of polycrystalline nature of an indium oxide film can also be evaluated by the length of the grain boundaries. The length of the grain boundaries can be calculated, for example, by extracting a field of view of a specific area from a TEM image of the film acquired at a total magnification where the grain boundaries can be observed, and summing the lengths of the grain boundaries observed in that field of view. An indium oxide film with a grain boundary length of 0 nm can be considered a single-crystal film. Also, a longer grain boundary length indicates a higher proportion of grain boundary components.

[0083] The extended grain boundary length in the indium oxide film is preferably 0 nm to 1500 nm, more preferably 0 nm to 1000 nm, and even more preferably 0 nm to 800 nm. By having an indium oxide film with an extended grain boundary length within the above range in the oxide semiconductor 230, a configuration can be achieved in which no crystal grain boundaries are observed or where there are few grain boundary components in the channel formation region. Unless otherwise specified in this specification, the field of view used to calculate the extended grain boundary length is 90 nm square.

[0084] The film thickness of the oxide semiconductor 230 is more preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. It is sufficient that the oxide semiconductor 230 has regions with the above-mentioned film thickness in at least a portion of it. For example, it is sufficient that the channel-forming region of the oxide semiconductor 230 has regions with the above-mentioned film thickness. By setting the film thickness of the oxide semiconductor 230 within the above range, the crystallinity of the oxide semiconductor 230 can be increased. By increasing the crystallinity of the oxide semiconductor 230, the oxide semiconductor 230 can have crystal grains.

[0085] Furthermore, when a metal oxide contains indium and zinc, it may have a CAAC (c-axis aligned crystal) structure. The CAAC structure has fewer grain boundaries in the a-b plane than the polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In-Zn oxide, also known as IZO®) and indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO).

[0086] In a crystalline oxide semiconductor layer, an indium oxide film is a film that allows hydrogen and / or oxygen to move more easily than, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film that allows hydrogen and / or oxygen to be supplied more easily and expelled more easily than, for example, an IGZO film. Furthermore, it can be said that an indium oxide film is a film with higher permeability to hydrogen and / or oxygen compared to, for example, an IGZO film. In other words, an indium oxide film is a film with lower barrier properties to hydrogen and / or oxygen compared to, for example, an IGZO film.

[0087] In a heat treatment where the indium oxide film is heated to a temperature of 400°C and the treatment time is 8 hours, for example, oxygen levels are 1 × 10⁻⁶. ２０ atoms / cm ３ The above 2 x 10 ２１atoms / cm ３ Hereinafter, preferably 2×10 ２０ atoms / cm ３ or more and 1×10 ２１ atoms / cm ３ It is preferable to have the property of transmitting light below this value. Also, the indium oxide film has, for example, 1×10 ２０ atoms / cm ３ or more and 2×10 ２１ atoms / cm ３ or less, preferably 2×10 ２０ atoms / cm ３ or more and 1×10 ２１ atoms / cm ３ or less, and preferably has the property that oxygen diffuses into the crystal grains.

[0088] By the diffusion of oxygen in the indium oxide film into the crystal grains and grain boundaries, V Ｏ present in the crystal grains or grain boundaries can be reduced. Therefore, the electrical characteristics and reliability of the transistor can be improved.

[0089] The band gap of indium oxide is 2.5 eV or more and 3.7 eV or less. By using indium oxide with a large band gap for the oxide semiconductor 230, the off-current of the transistor can be reduced, and the power consumption of the semiconductor device can be sufficiently reduced.

[0090] The OS transistor is an accumulation-type transistor with electrons as the majority carriers. That is, the carriers in the OS transistor are electrons. Assuming that the relaxation time of the carriers is a constant value, the smaller the effective mass of the electrons (carriers), the higher the electron mobility (carrier mobility). That is, by using a metal oxide with a small effective mass of electrons for the semiconductor layer of the transistor, the on-current, frequency characteristics (also referred to as f characteristics), or field-effect mobility of the transistor can be increased.

[0091] Furthermore, indium oxide has a large effective hole mass. Therefore, by using indium oxide, which has a large effective hole mass, in the oxide semiconductor 230, a transistor with an extremely low off-current can be realized. In addition, the effective hole mass of indium oxide is larger than, for example, the effective hole mass of silicon. Therefore, from the viewpoint of the effective hole mass, the off-current of a transistor using indium oxide in the channel formation region is significantly smaller than the off-current of a Si transistor.

[0092] In a transistor using indium oxide as the oxide semiconductor 230, the off-current value at room temperature per 1 μm channel width is 1 × 10⁻¹⁶ −１７ A / μm or less, preferably 1 × 10 −１８ A / μm or less, more preferably 1 × 10 −１９ It is possible to reduce the A / μm or less. Also, the off-current value at 85°C per 1 μm of channel width is 1 × 10⁻¹⁶ −１６ A / μm or less, preferably 1 × 10 −１７ A / μm or less, more preferably 1 × 10 −１８ It is possible to reduce the A / μm level to less than or equal to 1 / μm.

[0093] Furthermore, miniaturizing the OS transistor can improve the frequency characteristics of the transistor. For example, the cutoff frequency of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher, under room temperature conditions.

[0094] The indium oxide film may contain other elements, as long as the crystal structure of the crystal grains maintains a cubic crystal system. For example, in addition to indium, a first element may be included. The first element may be one or more selected from tin, zinc, antimony, copper, cobalt, and gallium. The content of the first element in the crystal grains is preferably 0.1% or more and less than 30%, more preferably 0.1% or more and less than 20%, more preferably 0.1% or more and less than 10%, and even more preferably 0.1% or more and less than 5%. When elements Mx1 and Mx2 are selected as the first element, the content of the first element in the crystal grains can be calculated as the sum of the content of element Mx1 and the content of element Mx2 in the crystal grains. For example, by adding atoms that can become cations with a valence of 4 or higher (tin, antimony, and cobalt) to indium oxide, these atoms can substitute for indium atoms, resulting in one or more electrons remaining, and the carrier concentration of the oxide semiconductor layer can be increased. Furthermore, by adding atoms that can become divalent or less cations (zinc and copper) to indium oxide, for example, these atoms can substitute for indium atoms, resulting in a deficiency of one or more electrons and thus reducing the carrier concentration in the oxide semiconductor layer.

[0095] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of that metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, then the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A. Ｘ A Ｙ A Ｚ In this case, the content of metal element X is A Ｘ / (A Ｘ +A Ｙ +A Ｚ ) can be shown as follows. Also, the ratio of the number of atoms of metal elements X, Y, and Z in a metal oxide (atomic ratio) is B Ｘ : B Ｙ : B Ｚ When shown as follows, the content of metal element X is B Ｘ / (B Ｘ +B Ｙ +B Ｚ This can be shown by:

[0096] Figures 1A to 1D show an example where the oxide semiconductor 230 has a single-layer structure. However, the oxide semiconductor 230 can also have a stacked structure of two or more layers. For example, in the configuration example shown in Figure 7A, the oxide semiconductor 230 has oxide semiconductor 230_1, oxide semiconductor 230_2 on oxide semiconductor 230_1, and oxide semiconductor 230_3 on oxide semiconductor 230_2. Note that the boundaries between oxide semiconductor 230_1 and oxide semiconductor 230_2, and between oxide semiconductor 230_2 and oxide semiconductor 230_3 may be unclear, so these boundaries are shown with dotted lines in Figure 7A, etc.

[0097] The oxide semiconductors 230_1 to 230_3 preferably contain indium oxide. Furthermore, oxide semiconductors 230_1 and 230_3 may contain indium oxide containing a second element. For example, one or more of the following can be used as the second element: gallium, aluminum, yttrium, scandium, titanium, tungsten, molybdenum, tin, zirconium, hafnium, and tantalum. The second element is preferably one or more selected from gallium, aluminum, scandium, and yttrium, more preferably gallium or aluminum, and even more preferably gallium.

[0098] Oxides containing the second element have a larger band gap than indium oxide. Therefore, the band gap of indium oxide containing the second element may be larger than that of indium oxide. Also, the electron affinity of indium oxide containing the second element may be smaller than that of indium oxide. By making the electron affinity of oxide semiconductor 230_1 and oxide semiconductor 230_3 smaller than that of oxide semiconductor 230_2, the carrier flow path can be moved away from the interface between insulator 250 and oxide semiconductor 230, and the effects of surface scattering can be reduced. As a result, it may be possible to increase the on-current or improve reliability. With such a configuration, the transistor can be made into an embedded channel structure.

[0099] The crystallinity of the metal oxides in oxide semiconductors 230_1 and 230_3 is not particularly limited. For example, oxide semiconductors 230_1 and 230_3 may include one or more amorphous semiconductors (semiconductors having an amorphous structure), single-crystal semiconductors (semiconductors having a single-crystal structure), or semiconductors having crystallinity other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors having crystalline regions in part).

[0100] Next, the crystal structure of the oxide semiconductor 230 will be described. As shown in Figure 1A, the oxide semiconductor 230 and the insulator 224 are formed in an island-like pattern in the transistor 200. Before the oxide semiconductor 230 and the insulator 224 are patterned in an island-like pattern, as shown in Figure 3C, a film that will become the oxide semiconductor 230 (hereinafter referred to as the oxide semiconductor film 230f) and a film that will become the insulator 224 (hereinafter referred to as the insulating film 224f) are deposited. In Figure 3C, an island-like metal oxide layer 235 and an insulator 225 are provided in contact with the upper surface of the insulating film 224f, and the oxide semiconductor film 230f is provided so as to cover the metal oxide layer 235 and the insulator 225.

[0101] The metal oxide layer 235 has crystals. The metal oxide layer 235 functions as a seed or nucleus when performing a treatment to enhance the crystallinity of the oxide semiconductor film 230f. In other words, the metal oxide layer 235 functions as a seed or nucleus when the oxide semiconductor film 230f undergoes crystal growth. In this specification, the metal oxide layer 235, or the crystals contained in the metal oxide layer 235, can be referred to as a seed crystal or a crystal nucleus. Furthermore, since the metal oxide layer 235 has crystals, the metal oxide layer 235 can be referred to as a crystalline portion.

[0102] Indium oxide crystals have a cubic crystal structure (Bixbite type). When using indium oxide in the oxide semiconductor film 230f, it is preferable to use an oxide with a cubic crystal structure as the metal oxide layer 235. By having the metal oxide layer 235 crystals have the same crystal structure as the oxide semiconductor film 230f crystals, the oxide semiconductor film 230f can be epitaxially grown with the metal oxide layer 235 as a nucleus, thereby increasing the crystallinity of the oxide semiconductor film 230f. As the metal oxide layer 235, oxides containing indium (typically indium oxide), oxides containing one or both of yttrium and zirconium, erbium oxide, etc., can be used. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and oxides containing both yttrium and zirconium. Furthermore, as the metal oxide layer 235, a metal oxide containing indium and the first element mentioned above can be used. Examples of such metal oxides include indium tin oxide (In-Sn oxide, also known as ITO). These oxides have a cubic crystal structure.

[0103] When indium oxide is used for the metal oxide layer 235, the oxide semiconductor film 230f can be homoepitaxially grown using the metal oxide layer 235 as a nucleus, thereby increasing the crystallinity of the oxide semiconductor film 230f. In this case, the crystal orientation of the crystals in the metal oxide layer 235 and the crystal orientation of the crystals in the oxide semiconductor film 230f are identical or nearly identical. For example, using the method described later, indium oxide with a crystal orientation of <111> similar to that of the oxide semiconductor film 230f can be formed, and the metal oxide layer 235 can be formed by patterning the indium oxide. This allows for the homoepitaxial growth of an oxide semiconductor film 230f with a crystal orientation of <111> using the metal oxide layer 235 with a crystal orientation of <111> as a nucleus.

[0104] As shown in Figure 3C, it is preferable that the crystal orientation of the crystal grains of the oxide semiconductor film 230f coincides or substantially coincides at all locations. For example, as shown in Figure 3C, it is preferable that the crystal orientation of each crystal grain in the region of the oxide semiconductor film 230f that is in contact with the side surface of the wall-like structure made of the insulator 225 and the metal oxide layer 235, the region that is in contact with the upper surface of the wall-like structure, and the region between adjacent wall-like structures is <111>.

[0105] This is also true for the oxide semiconductor 230 of the transistor 200 shown in Figure 2B, and it is preferable that the crystal orientations of the crystal grains in the region of the oxide semiconductor 230 that is in contact with the side surface of the wall-like structure and the region that is in contact with the top surface of the wall-like structure are the same or approximately the same. Furthermore, it is preferable that the crystal orientation of the crystal grains in the region of the oxide semiconductor 230 that is in contact with the side surface of the wall-like structure and the region that is in contact with the top surface of the wall-like structure is <111>. Here, the crystal orientation <111> of the oxide semiconductor 230 is perpendicular or approximately perpendicular to the surface of the substrate (which can also be said to be the surface of the insulator 224) at all locations. Alternatively, the crystal orientation <111> of the oxide semiconductor 230 can be parallel or approximately parallel to the side surface of the wall-like structure and perpendicular or approximately perpendicular to the top surface of the wall-like structure.

[0106] Crystal orientation can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). Alternatively, it can be evaluated by the pattern (also called the FFT pattern) obtained by performing a Fast Fourier Transform (FFT) on the TEM image. The FFT pattern reflects reciprocal lattice space information similar to that of the diffraction pattern described above.

[0107] For example, in the FFT patterns of crystal grains included in the region in contact with the side surface of the oxide semiconductor 230 wall-like structure (referred to as the first FFT pattern), and the FFT patterns of crystal grains included in the region in contact with the upper surface of the oxide semiconductor 230 wall-like structure (referred to as the second FFT pattern), if the difference between the angle of the first FFT pattern and the angle of the second FFT pattern is -5 degrees or more and 5 degrees or less, preferably -3 degrees or more and 3 degrees or less, and more preferably -2 degrees or more and 2 degrees or less, then it can be said that the crystal orientations of the respective crystal grains are coincident or nearly coincident. When the coincident or nearly coincident crystal orientation is

[111] , the angle of the FFT pattern refers to the angle between the acute angle between the approximate straight line between one or both of the spots originating from the (222) plane or the spots originating from the (-2-2-2) plane and the central spot, and the reference line (for example, a straight line extending in the vertical direction).

[0108] As described above, the oxide semiconductor 230 functions as a channel-forming region both near the top surface and near the side surface of the wall-like structure. Therefore, by making the crystal structure uniform in the region near the top surface and the region near the side surface of the wall-like structure of the oxide semiconductor 230, the electrical characteristics of the transistor 200 can be stabilized. This makes it possible to improve the on-current, field-effect mobility, frequency characteristics, etc. of the transistor 200.

[0109] In this specification, space groups are expressed using international notation (or Hermann-Mauguin notation) in short notation. Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by superscripting numbers, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a superscript. Individual orientations within a crystal are represented by [ ], collective orientations representing all equivalent orientations are represented by < >, individual crystal planes are represented by ( ), and collective planes with equivalent symmetry are represented by {}.

[0110] In this specification, the crystal orientation of a crystal refers to its orientation relative to the surface of the substrate. Therefore, for example, a crystal with a crystal orientation of <100> can be said to be a crystal in which the (100) plane is parallel to the surface of the substrate. However, it is not limited to the above, and the crystal orientation of a crystal can also be the orientation relative to the surface of the metal oxide layer 235, or the surface on which the metal oxide layer 235 is formed.

[0111] Furthermore, it is preferable that the difference (also called lattice mismatch) between the lattice constant or unit cell vector of the crystal nucleus and the lattice constant or unit cell vector of the crystal of the oxide semiconductor film 230f is small. By using an oxide that reduces lattice mismatch for the metal oxide layer 235, the crystallinity of the oxide semiconductor film 230f can be improved.

[0112] One method for evaluating the degree of lattice mismatch is the lattice mismatch index. The lattice mismatch index Δa [%] of the crystals of the forming film relative to the crystals of the film being formed is calculated using the following formula (1). Hereafter, the lattice mismatch index Δa of the crystals of the forming film relative to the crystals of the film being formed may simply be referred to as the lattice mismatch index Δa of the forming film relative to the film being formed.

[0113]

[0114] In formula (1), L １ L is the lattice constant or unit cell vector of the crystal of the formed film. ２ This is the lattice constant or unit cell vector of the crystal of the film to be formed.

[0115] The degree of lattice mismatch Δa of the crystal grains of the oxide semiconductor film 230f with respect to the crystal nucleus is preferably -10% or more and 10% or less, more preferably -5% or more and 5%, and even more preferably -3% or more and 3% or less. By using a material for the metal oxide layer 235 that has a smaller degree of lattice mismatch with respect to the oxide semiconductor film 230f, the crystallinity of the oxide semiconductor film 230f can be improved.

[0116] For example, the lattice constant of indium oxide crystals (Bixbite type) is said to be 1.01194 nm. Also, the lattice constant of yttrium oxide crystals (Bixbite type) is said to be 1.05976 nm. Therefore, the degree of lattice mismatch between the crystals of indium oxide and those of yttrium oxide is -4.5%. Thus, when using indium oxide for the oxide semiconductor film 230f, yttrium oxide can be used as the metal oxide layer 235.

[0117] For example, the lattice constant of an erbium oxide crystal (Bixbyte type) is said to be 1.0582 nm. Therefore, the degree of lattice mismatch between the crystal of indium oxide and that of erbium oxide is -4.4%. Thus, when using indium oxide for the oxide semiconductor film 230f, erbium oxide can be used as the metal oxide layer 235.

[0118] For example, Zr is an example of yttrium zirconium oxide. ０．９ Y ０．１ O １．９５ The lattice constant of the crystal (fluorite type) is 0.51481 nm (see ICSD col.code.248790). Therefore, Zr ０．９ Y ０．１ O １．９５ The lattice mismatch of indium oxide with respect to the crystal is -1.7%. Therefore, when indium oxide is used for the oxide semiconductor film 230f, yttrium zirconium oxide can be suitably used as the metal oxide layer 235. Yttrium zirconium oxide contains yttrium, zirconium, and oxygen.

[0119] The crystal structure of zirconium oxide can be stabilized by adding yttrium or yttrium oxide to zirconium oxide, that is, by increasing the yttrium content in yttrium zirconium oxide to more than 0 atomic percent. However, if the content is too high, the crystal structure of yttrium zirconium oxide may change from a cubic crystal system to another crystal system, so it is preferable that the content not be too high. For example, the yttrium content in yttrium zirconium oxide is preferably 2 atomic percent or more and 15 atomic percent or less, and more preferably 5 atomic percent or more and 10 atomic percent or less.

[0120] Furthermore, the metal oxide layer 235 can also have a hexagonal or trigonal crystal structure. In this case, by having crystals in the metal oxide layer 235 whose crystal orientation with respect to the surface or the surface to be formed on the metal oxide layer 235 is <001>, an oxide semiconductor film 230f having crystals with a crystal orientation of <111> can be formed. When the crystal orientation of the crystals in the metal oxide layer 235 with respect to the surface or the surface to be formed on the metal oxide layer 235 is <001>, the c-axis of the crystal is perpendicular or approximately perpendicular to the surface or the surface to be formed on the metal oxide layer 235. Note that hexagonal or trigonal crystals can sometimes be rephrased as layered crystals, so the above structure can be understood as a structure in which an oxide semiconductor film 230f having cubic crystals is formed on a metal oxide layer 235 having layered crystals. That is, it can also be considered as a layered structure fabricated using heteroepitaxial growth technology or a technology like heteroepitaxial growth.

[0121] Specifically, the metal oxide layer 235 can be zinc oxide, In-Ga oxide, gallium zinc oxide (also written as Ga-Zn oxide, GZO), aluminum zinc oxide (also written as Al-Zn oxide, AZO), In-Al-Zn oxide, In-Ga-Zn oxide, or In-Sn-Zn oxide. It is preferable to use In-Ga-Zn oxide as the metal oxide layer 235. In this case, the metal oxide layer 235 contains indium, gallium, zinc, and oxygen. More specifically, it is preferable to have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to that, or a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or close to that. Metal oxides with these compositions are suitable as the metal oxide layer 235 because they easily form a layered structure.

[0122] In-Ga-Zn oxides and In-Sn-Zn oxides, etc., tend to have a CAAC structure. When an oxide having a CAAC structure is used in the metal oxide layer 235, the c-axis of the crystal nucleus is perpendicular or approximately perpendicular to the surface or the surface on which it is formed in the metal oxide layer 235. In other words, by using an oxide that tends to have a CAAC structure in the metal oxide layer 235, the controllability of the crystal orientation of the crystal nucleus can be improved.

[0123] When an oxide that readily has a CAAC structure is used for the metal oxide layer 235, an oxide semiconductor film 230f having crystals with a crystal orientation of <111> can be formed.

[0124] The materials applicable to the metal oxide layer 235 are not particularly limited. The metal oxide layer 235 may be an insulating material, a semiconductor material, or a conductive material. When a semiconductor material is used as the metal oxide layer 235, the metal oxide layer 235 may be considered as part of the oxide semiconductor film 230f.

[0125] Furthermore, the metal oxide layer 235 can be formed in an island-like shape in a plan view. When the metal oxide layer 235 is formed in an island-like shape, for example, in a plan view, it can be a roughly circular or elliptical shape, a triangle, a quadrilateral (including rectangles, rhombuses, and squares), a pentagon, a star polygon, or a polygon with rounded corners. Also, when sputtering particles are used as the metal oxide layer 235, the metal oxide layer 235 may be triangular or hexagonal in a plan view.

[0126] Furthermore, the metal oxide layer 235 may have a tapered shape in cross-section. For example, the angle between the upper surface of the insulating film 224f and the side surface of the metal oxide layer 235 may be less than 90°, preferably 30° or more and less than 90°. By making the metal oxide layer 235 tapered, the coverage of the oxide semiconductor film 230f is improved, and defects such as porosity can be reduced. In addition, crystal growth of the oxide semiconductor film 230f can be promoted.

[0127] It is preferable that the metal oxide layer 235 has a thin film thickness. For example, it is preferable that the film thickness of the metal oxide layer 235 is thinner than the film thickness of the oxide semiconductor film 230f. Specifically, it is preferable that the metal oxide layer 235 has a region with a film thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a film thickness of 0.5 nm or more and less than 2 nm. By making the film thickness of the metal oxide layer 235 thin, the coverage of the oxide semiconductor film 230f is improved and defects such as porosity can be reduced. In addition, crystal growth of the oxide semiconductor film 230f can be promoted. The metal oxide layer 235 may be in the form of layers or granules.

[0128] It is preferable that the insulator 225 and the insulating film 224f have an amorphous structure. If the insulator 225 and the insulating film 224f have a polycrystalline or single-crystal structure, when forming the oxide semiconductor film 230f, the oxide semiconductor film 230f may crystallize, reflecting the crystal structure of the insulator 225 and the insulating film 224f, and there is a risk that a polycrystalline structure with small crystal grains will be formed. Therefore, by having an amorphous structure for the insulator 225 and the insulating film 224f, it is possible to suppress unintended crystallization of the oxide semiconductor film 230f and obtain an oxide semiconductor film 230f with large crystal grains.

[0129] It is preferable that the side surfaces of the insulator 225 and the upper surface of the insulating film 224f, which are the surfaces on which the oxide semiconductor film 230f is formed, are flat. This configuration suppresses nucleation caused by irregularities on the side surfaces of the insulator 225 and the upper surface of the insulating film 224f, thereby promoting crystal growth of the oxide semiconductor film 230f.

[0130] The insulator 225 and the insulating film 224f preferably have an oxygen supply function. This allows oxygen to be supplied to the oxide semiconductor film 230f, thereby reducing oxygen deficiency. An insulator having an oxygen supply function is, for example, an insulator that has a region containing oxygen that is desorbed by heating (hereinafter sometimes referred to as excess oxygen). In the semiconductor device manufacturing process, oxygen can be supplied from the insulator when heating is performed. Examples of insulators having an oxygen supply function include silicon oxide or silicon oxynitride.

[0131] Furthermore, it is preferable that the insulator 225 and the insulating film 224f have barrier properties against oxygen. This suppresses the detachment of oxygen from the oxide semiconductor film 230f and the formation of oxygen vacancies. Examples of insulators with barrier properties against oxygen include gallium oxide or aluminum oxide.

[0132] It is particularly preferable to use gallium oxide as the insulator 225 and the insulating film 224f. Compared to aluminum, the ionic radius of gallium is close to that of indium. Therefore, when indium oxide is used as the oxide semiconductor film 230f, using gallium oxide as the insulator 225 and the insulating film 224f makes it possible to bring the surface density of metal atoms in the oxide semiconductor film 230f closer to that of the insulator 225 and the insulating film 224f. As a result, the frequency of bonding between the indium atoms in the oxide semiconductor film 230f and the gallium atoms in the insulator 225 and the insulating film 224f via oxygen atoms increases, and the generation of oxygen vacancies or oxygen with dangling bonds at the interface between the oxide semiconductor film 230f and the insulator 225 and the insulating film 224f can be suppressed.

[0133] Furthermore, gallium oxide or aluminum oxide, to which the metal elements contained in the oxide semiconductor film 230f have been added, can also be used as the insulator 225 and the insulating film 224f. For example, if the oxide semiconductor film 230f contains indium, gallium oxide containing indium or aluminum oxide containing indium can also be used as the insulator 225 and the insulating film 224f. In this case, the insulator 225 and the insulating film 224f contain gallium or aluminum, indium, and oxygen. Even in this case, it is possible to suppress the generation of oxygen vacancies or oxygen with dangling bonds at the interface between the oxide semiconductor film 230f and the insulator 225 and insulating film 224f. In addition, gallium atoms and aluminum atoms in oxides tend to exist in tetrahedral coordination positions, while indium atoms in oxides tend to exist in octahedral coordination positions. In other words, it is presumed that in gallium oxide containing indium and aluminum oxide containing indium, tetrahedral and octahedral coordination are mixed, resulting in low crystallinity. Therefore, by using gallium oxide containing indium or aluminum oxide containing indium for the insulator 225 and the insulating film 224f, the crystallinity of the insulator 225 and the insulating film 224f can be reduced. Furthermore, the insulator 225 and the insulating film 224f can have an amorphous structure.

[0134] In gallium oxide containing indium, the indium content is preferably 0.5% to 5%, and more preferably 0.5% to 2%. This allows the insulating properties of the insulator 225 and the insulating film 224f to be maintained. Similarly, in aluminum oxide containing indium, the indium content is preferably 0.5% to 5%, and more preferably 0.5% to 2%.

[0135] Furthermore, it is preferable that the insulating film 224f functions as an etching stopper when the insulator 225 is processed by etching or other methods. In other words, it is preferable to use a material for the insulating film 224f that has a suitable etching selectivity ratio with respect to the insulator 225. For example, if gallium oxide is used for the insulator 225, silicon oxide can be used for the insulating film 224f.

[0136] Furthermore, while Figure 3C and other figures show a configuration in which the insulating film 224f and the insulator 225 are formed from different insulating films, the present invention is not limited to this. The insulating film 224f and the insulator 225 may also be integrally molded from the insulating film.

[0137] Furthermore, the insulator 225 and the insulating film 224f are not limited to those described above, and any insulating material listed in the section "<<Insulator>>" described later may be used.

[0138] Figure 3C shows an example where the insulating film 224f has a single-layer structure. However, the insulating film 224f can also have a multilayer structure of two or more layers. When the insulating film 224f has a multilayer structure of two or more layers, it is preferable to use an insulating material applicable to the insulating film 224f (typically silicon oxide) as the layer in contact with the oxide semiconductor film 230f among the two or more layers included in the insulating film 224f. This configuration improves the crystallinity of the oxide semiconductor film 230f.

[0139] Furthermore, as shown in Figure 5, the insulator 225 may have a laminated structure consisting of an insulator 225a and an insulator 225b covering the insulator 225a. In this case, it is preferable that the film thickness of the insulator 225b is thinner than that of the insulator 225a. With this configuration, the insulator 225b can be made into an amorphous, highly flat film using the above-mentioned insulating material, and the insulator 225a can be deposited using a method with a high deposition rate. By depositing the insulator 225a using a method with a high deposition rate, the insulator 225 can be formed with good productivity. For example, silicon oxide or silicon oxynitride can be used for the insulator 225a, and gallium oxide or aluminum oxide can be used for the insulator 225b.

[0140] Next, an example of a method for fabricating an oxide semiconductor film 230f will be described using Figures 3A to 3C. Figures 3A to 3C are cross-sectional views corresponding to Figures 1B and 2B. However, in Figures 3A to 3C, multiple insulators 225 are shown corresponding to multiple transistors 200.

[0141] The layers constituting the semiconductor device (insulating film 224f, metal oxide layer 235, oxide semiconductor film 230f, etc.) can be formed using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), or ALD.

[0142] Unlike film deposition methods in which particles emitted from a target or other source are deposited, the ALD method is a film deposition method in which a film is formed by a reaction on the surface of the workpiece. Therefore, it is less affected by the shape of the workpiece and is a film deposition method that has good stepped coverage. In particular, the ALD method has excellent stepped coverage and excellent thickness uniformity, making it suitable for coating the surface of openings or grooves with a high aspect ratio.

[0143] Furthermore, precursors used in the ALD method may contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain higher levels of carbon or chlorine compared to films formed by other deposition methods. These elements can be quantified using XPS or SIMS. Additionally, when using the ALD method, applying either or both of the following conditions—using a high substrate temperature during deposition and / or impurity removal—may result in lower levels of carbon and chlorine in the film compared to using the ALD method without these conditions.

[0144] Examples of ALD methods include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and plasma-enhanced ALD (PEALD), which uses a plasma-excited reactant.

[0145] A film deposition apparatus using the ALD method alternately introduces a first raw material gas (sometimes called a precursor, metal precursor) and a second raw material gas (sometimes called a reactant, reactant, oxidizer, or nonmetal precursor) into the chamber, and performs film deposition by repeatedly introducing these raw material gases. The switching of the raw material gases can be done, for example, by switching the respective switching valves (sometimes called high-speed valves). Also, when introducing the raw material gases, nitrogen (N) ２ An inert gas such as argon (Ar) or helium (He) may be introduced into the chamber together with the raw material gas as a carrier gas. By using a carrier gas, even if the raw material gas has low volatility or low vapor pressure, it is possible to suppress the adsorption of the raw material gas inside the piping and valves and introduce the raw material gas into the chamber. Furthermore, the uniformity of the formed film is also improved, which is preferable.

[0146] Furthermore, the ALD method allows for the deposition of films with any desired composition by using multiple different types of precursors. Alternatively, when using multiple different types of precursors, films with any desired composition can be deposited by controlling the number of cycles for each precursor.

[0147] First, a substrate (not shown) is prepared, and an insulating film 224f is formed on the substrate. The insulating film 224f has an amorphous structure, and it is preferable that the upper surface of the insulating film 224f is flat.

[0148] The insulating film 224f can be formed, for example, using a sputtering method in an oxygen-containing atmosphere. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. Furthermore, by forming the insulating film 224f using a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating film 224f. Heat applied after the formation of the oxide semiconductor film 230f can supply oxygen from the insulating film 224f to the oxide semiconductor film 230f, thereby reducing oxygen deficiency.

[0149] It is preferable to perform a heat treatment before forming the insulator 225 and the metal oxide layer 235. The heat treatment is performed, for example, at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C.

[0150] The heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm (0.001%) or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have about 20% oxygen gas. The heat treatment may also be carried out under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. By performing the above heat treatment, impurities such as hydrogen or water contained in the insulating film 224f, insulator 225, etc., can be reduced before the deposition of the oxide semiconductor film 230f.

[0151] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb (1 × 10⁻¹⁶). −３ Preferably less than ppm, and 0.1 ppb (1 × 10⁻¹⁰ −４ It is more preferable to have a ppm or less, and 0.05 ppb (5 × 10) −５A concentration of ppm or less is even more preferable. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other substances from being incorporated into the insulating film 224f as much as possible.

[0152] There are no special limitations on the heating device used for heat treatment; it may be a device that heats the workpiece by heat conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0153] Furthermore, it is preferable to perform an oxygen supply treatment before forming the metal oxide layer 235. This supplies oxygen to the insulating film 224f, and the heat applied after the formation of the oxide semiconductor film 230f can supply oxygen from the insulating film 224f to the oxide semiconductor film 230f.

[0154] Examples of oxygen supply processes include heating in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Note that the plasma treatment described herein includes microwave plasma treatment, which will be discussed later. Alternatively, oxygen may be supplied to the insulating film 224f by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere using, for example, a sputtering method. The deposited oxide film may be removed immediately or left as is. If the deposited oxide film is left as is, it can be used as part of the oxide semiconductor film 230f. Note that the oxygen-containing atmosphere may include oxygen gas (O2). ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２The atmosphere includes gases containing oxygen-containing compounds such as O). Furthermore, the substrate temperature during plasma treatment shall be between room temperature (25°C) and 450°C.

[0155] Furthermore, the insulating film 224f may be subjected to a hydrogen addition treatment. For example, the hydrogen addition treatment may be performed after the insulating film 224f has been formed. The hydrogen addition treatment can be carried out using an ion implanter, an ion doping device, or a plasma treatment device. Alternatively, as a hydrogen addition treatment, microwave plasma treatment can be performed in a hydrogen-containing atmosphere. This adds hydrogen to the surface of the insulating film 224f, thereby suppressing nucleation near the insulating film 224f.

[0156] Next, a wall-like structure consisting of an insulator 225 and a metal oxide layer 235 is formed on the insulating film 224f (see Figure 3A). The metal oxide layer 235 serves as a nucleus for crystal growth of the oxide semiconductor film 230f.

[0157] First, an insulating film that will become an insulator 225 is deposited on the insulating film 224f, and then a metal oxide film that will become a metal oxide layer 235 is deposited. As the insulating film that will become the insulator 225, any insulating material that can be used for the insulator 225 as described above may be used. The insulating film that will become the insulator 225 can be deposited using, for example, a sputtering method, a CVD method, a MBE method, a PLD method, or an ALD method. For example, gallium oxide can be deposited as the insulating film that will become the insulator 225 using a sputtering method.

[0158] As the metal oxide film that will become the metal oxide layer 235, any metal oxide material that can be used for the metal oxide layer 235 as described above may be used. The metal oxide film that will become the metal oxide layer 235 can be formed using, for example, sputtering, CVD, MBE, PLD, or ALD. For the method of forming the metal oxide film that will become the metal oxide layer 235, refer to the method of forming the oxide semiconductor film 230f described later.

[0159] Here, it is preferable to perform a treatment to enhance the crystallinity of the metal oxide film that will become the metal oxide layer 235. Oxides with a cubic crystal structure (typically indium oxide) are presumed to grow crystals while maximizing the surface area of ​​the {111} plane. In other words, they are presumed to preferentially orient themselves to the {111} plane. Therefore, by performing a treatment to enhance crystallinity, crystal grains with a crystal orientation <111> parallel to the thickness direction of the insulator 225 (also called <111> oriented crystal grains) can be formed in the metal oxide film that will become the metal oxide layer 235.

[0160] Examples of treatments to enhance the crystallinity of the metal oxide film that forms the metal oxide layer 235 include heat treatment, plasma treatment, microwave treatment (including microwave plasma treatment), and light (e.g., ultraviolet light) irradiation treatment. Multiple of these treatments can be performed simultaneously or sequentially.

[0161] As a treatment to improve the crystallinity of the metal oxide film that forms the metal oxide layer 235, microwave plasma treatment is preferred, and microwave plasma treatment in an oxygen-containing atmosphere is particularly preferred.

[0162] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0163] Microwave plasma treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa being preferred, more preferably 50 Pa to 700 Pa, and even more preferably 100 Pa to 400 Pa. The treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and can be 400°C to 450°C.

[0164] When performing microwave plasma processing, the substrate may be heated. It is preferable that the heating temperature of the substrate be above room temperature (e.g., 25°C), 100°C or higher, 200°C or higher, 300°C or higher, or 400°C or higher, and 500°C or lower, or 450°C or lower. For example, it is preferable that the heating temperature of the substrate be above room temperature and 500°C or lower, more preferably 100°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, and even more preferably 400°C or higher and 450°C or lower.

[0165] Microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. For example, the oxygen flow rate ratio (O) in microwave plasma treatment. ２ / ( O ２ The value of +Ar) is preferably greater than 0% and 10% or less, preferably between 0.5% and 5%, more preferably between 0.5% and 3%, and typically 1%.

[0166] The shorter the processing time for microwave plasma treatment, the higher the productivity. For example, the processing time for microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0167] Next, the laminated film of the insulating film that will become the insulator 225 and the metal oxide film that will become the metal oxide layer 235 is processed to form the insulator 225 and the metal oxide layer 235 on the insulator 225. The insulating film that will become the insulator 225 and the metal oxide film that will become the metal oxide layer 235 can be processed into island shapes using lithography. Dry etching or wet etching can be used for this processing. Dry etching is suitable for microfabrication.

[0168] The above-described microwave plasma treatment may be performed after forming a wall-like structure consisting of an insulator 225 and a metal oxide layer 235 on the insulating film 224f.

[0169] Next, an oxide semiconductor film 230f is formed by covering the wall-like structure consisting of the metal oxide layer 235 and the insulator 225 (see Figure 3A). Since the oxide semiconductor film 230f is formed along the wall-like structure, it is preferable that it has good coverage. Therefore, it is preferable to form the oxide semiconductor film 230f using an ALD method or the like, which has good coverage. Also, since the oxide semiconductor 230 preferably has a high aspect ratio, it is preferable that the oxide semiconductor film 230f has a thin film thickness. Therefore, it is preferable to form the oxide semiconductor film 230f using an ALD method that allows for film thickness adjustment at a thin film thickness. By forming the oxide semiconductor film 230f in this way, the oxide semiconductor film 230f is formed in contact with the upper and side surfaces of the insulator 225.

[0170] For the deposition of the oxide semiconductor film 230f by the ALD method, a source gas and an oxidizing agent can be used. When the source gas contains a precursor containing indium, a film containing indium and oxygen is formed as the oxide semiconductor film 230f. When the precursor contains indium, the thermal ALD method can be used as the ALD method.

[0171] Indium-containing precursors that can be used include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolat)indium.

[0172] Furthermore, inorganic precursors that do not contain hydrocarbons may be used as indium precursors. As inorganic precursors containing indium, halogenated indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide) can be used.

[0173] In the method for forming the oxide semiconductor film 230f, it is preferable to use a high-purity raw material gas with a low impurity concentration. For example, by using a precursor with a purity of 3N (99.9%) or higher, more preferably 4N (99.99%) or higher, even more preferably 5N (99.999%) or higher, and 6N (99.9999%) or higher, the impurities in the oxide semiconductor film 230f can be reduced.

[0174] The gallium and aluminum content of the indium-containing precursor is preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, even more preferably 50 ppm or less, even more preferably 10 ppm or less, and even more preferably 1 ppm or less. By using a precursor with a low gallium content, the gallium concentration in the oxide semiconductor film 230f can be reduced, thereby improving the reliability of the transistor. Furthermore, by using a precursor with a low aluminum content, the aluminum concentration in the oxide semiconductor film 230f can be reduced, thereby improving the crystallinity of the oxide semiconductor film 230f.

[0175] Furthermore, it is preferable that the raw material gas is purified by two or more distillations (also called rectification or precision distillation). Using such a raw material gas makes it easier to form metal oxide films with fewer impurities, which is preferable. Performing distillation multiple times is preferable because it further suppresses the retention of impurities in the raw material gas that originate from the starting materials used in the production of the raw material gas. However, the present invention is not limited to the above, and a raw material gas purified by a single distillation, i.e., simple distillation, may also be used. Using simple distillation is preferable because it can reduce manufacturing costs. By performing distillation one or more times, the aluminum content in the raw material gas can be set to 100 ppm or less, 1 ppm or less, or 1 ppb (0.001 ppm) or less.

[0176] As an oxidizing agent, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２ ) and the like can be used. Preferably, the oxidizing agent contains at least one of ozone and oxygen. By using ozone, oxygen, etc., which do not contain hydrogen, as the oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor film 230f can be reduced. Furthermore, by using water, hydrogen peroxide, etc., which contain hydrogen, as the oxidizing agent, an oxide semiconductor film 230f with low crystallinity can be formed. In addition, nucleation can be suppressed or crystal nuclei other than the crystalline portion 31 can be promoted during the formation of the oxide semiconductor film 230f.

[0177] Unless otherwise specified in this specification, when ozone, oxygen, water, or hydrogen peroxide are used as oxidizing agents, these shall include not only gaseous or molecular states, but also plasma states, radical states, or ionic states.

[0178] When introducing the raw material gas into the reaction chamber, the substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. For example, in the case of a thermal ALD method using triethylindium as the precursor containing indium, the substrate heating temperature can be 100°C to 350°C, preferably 150°C to 300°C. When a metal oxide layer 235 is provided, the substrate heating temperature can be room temperature (25°C) to 300°C, preferably room temperature to 200°C, more preferably room temperature to 150°C. Lowering the substrate heating temperature can reduce the crystallinity of the oxide semiconductor film 230f during film formation.

[0179] Furthermore, the oxide semiconductor film 230f can also be formed using the sputtering method. Hydrogen (H) can be used as the sputtering gas. ２ It is preferable to use a gas containing ). By introducing hydrogen when forming the oxide semiconductor film 230f using the sputtering method, it is possible to form an oxide semiconductor film 230f with low crystallinity, for example, an oxide semiconductor film 230f with an amorphous structure. Furthermore, nucleation can be suppressed or crystal nuclei other than the crystalline portion 31 can be promoted during the formation of the oxide semiconductor film 230f. As the sputtering gas, hydrogen, noble gas (typically argon), and oxygen (O) are preferred. ２ A mixed gas of the following can be used.

[0180] Furthermore, a sputtering gas that does not contain hydrogen may be used. As the sputtering gas, for example, a noble gas or oxygen as a single gas, or a mixture of a noble gas and oxygen, may be used.

[0181] Furthermore, when forming an oxide semiconductor film 230f using the sputtering method, the substrate temperature during film formation of the oxide semiconductor film 230f is preferably between room temperature (25°C) and 250°C, more preferably between room temperature and 200°C, and even more preferably between room temperature and 140°C. For example, setting the substrate temperature to between room temperature and 140°C is preferable because it increases productivity. It is also preferable because it suppresses nucleation. Alternatively, the oxide semiconductor film 230f can be formed at room temperature or without heating the substrate.

[0182] When the oxide semiconductor film 230f has a multilayer structure, the oxide semiconductor film 230f can also be formed using, for example, sputtering and ALD methods. For example, when the oxide semiconductor film 230f has a two-layer structure consisting of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, the first semiconductor layer can be formed by the ALD method and the second semiconductor layer by the sputtering method. Since the ALD method is a film formation method with superior coverage compared to the sputtering method, the coverage of the oxide semiconductor film 230f can be improved by forming the first semiconductor layer by the ALD method. In addition, damage to the substrate (in this case, the insulating film 224f) can be reduced, the formation of a mixed layer at the interface between the substrate and the oxide semiconductor film 230f can be suppressed, and the crystallinity can be increased. Furthermore, productivity can be increased by forming the second semiconductor layer by the sputtering method.

[0183] Alternatively, the first semiconductor layer may be deposited by sputtering and the second semiconductor layer by ALD. Even if pinholes or stepped defects are formed in the first semiconductor layer deposited by sputtering, the overlapping portions can be covered with the second semiconductor layer deposited by the ALD method, which has good coverage.

[0184] Furthermore, as shown in Figure 7A, when the oxide semiconductor 230 is made into a stacked structure of oxide semiconductors 230_1 to 230_3, the above methods can be appropriately used to form each film. For example, the film that will become oxide semiconductor 230_1 and the film that will become oxide semiconductor 230_3 can be formed using the ALD method, and the film that will become oxide semiconductor 230_2 can be formed using the sputtering method. Alternatively, for example, the film that will become oxide semiconductor 230_1 and the film that will become oxide semiconductor 230_3 can be formed using the sputtering method, and the film that will become oxide semiconductor 230_2 can be formed using the ALD method.

[0185] Next, it is preferable to perform a heat treatment. This heat treatment can be performed, for example, at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. By performing this heat treatment, crystal growth can be promoted from the metal oxide layer 235, and crystal grains can be formed in the oxide semiconductor film 230f. Furthermore, the crystal grains in the oxide semiconductor film 230f can be enlarged. Therefore, a crystalline oxide semiconductor film 230f can be formed. In addition, by performing the heat treatment, excess hydrogen in the oxide semiconductor film 230f can be reduced.

[0186] By performing heat treatment, epitaxial growth of the oxide semiconductor film 230f and lateral growth of crystal grains proceed with the metal oxide layer 235 as a nucleus, thereby increasing the crystallinity of the oxide semiconductor film 230f (see Figure 3B). As a result, crystal grains grow along the wall-like structure consisting of the insulator 225 and the metal oxide layer 235, and along the insulating film 224f. This growth of crystal grains can be called lateral growth. Here, as shown in Figure 3B, crystals grow laterally with the metal oxide layer 235 as a nucleus, and region 231c expands. Region 231c is a region with higher crystallinity than region 231a. As the processing time progresses, region 231c expands further along the surface of the substrate.

[0187] The crystal growth described above also occurs in the vicinity of wall-like structures with a high aspect ratio. In other words, the oxide semiconductor film 230f in the region in contact with the side surface of the wall-like structure also undergoes similar lateral growth of crystal grains. As a result, regions 231c with high crystallinity are formed in the oxide semiconductor film 230f in the region in contact with the side surface of the wall-like structure, the region in contact with the top surface of the wall-like structure, and the region between adjacent wall-like structures, just as in the region between adjacent wall-like structures. When region 231c extends throughout the oxide semiconductor film 230f in this way, as shown in Figure 3C, the crystal orientations of the crystal grains in the region in contact with the side surface of the wall-like structure made of the insulator 225 and the metal oxide layer 235, the region in contact with the top surface of the wall-like structure, and the region between adjacent wall-like structures will coincide or nearly coincide. Furthermore, the crystal orientation of each crystal grain will be <111>.

[0188] The heat treatment is preferably carried out under reduced pressure. Furthermore, the gas used in the heat treatment is preferably highly purified. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other substances from being incorporated into the oxide semiconductor film 230f as much as possible. The conditions for the heat treatment can be the same as those described above.

[0189] There are no special limitations on the heating device used for the heat treatment; it may be a device that heats the object to be treated by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA device or a GRTA device can be used. An LRTA device is a device that heats the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0190] By using an RTA (Real-Time Attenuation) device, the heat treatment time can be shortened. The treatment time is preferably 1 minute or more and 10 minutes or less, more preferably 3 minutes or more and 10 minutes or less, and even more preferably 5 minutes or more and 10 minutes or less. When using an RTA device to shorten the heat treatment time, the heating temperature can be set to be above the strain point of the substrate. This further shortens the heat treatment time. The heating temperature is preferably 400°C or more and 750°C or less, and more preferably 450°C or more and 700°C or less.

[0191] Furthermore, the above heat treatment can be performed multiple times under different conditions. For example, the first treatment and the second treatment can be performed in this order as the heat treatment. Specifically, the first treatment can be performed under reduced pressure, and the second treatment can be performed in an oxygen atmosphere using an RTA apparatus. It is also preferable that the temperature of the first treatment is lower than the temperature of the second treatment. By performing the first treatment at a relatively low temperature, crystal growth from the metal oxide layer 235 can be promoted while suppressing nucleation. In addition, the growth rate of crystal grains can be slowed down, and the formation of crystal grain boundaries can be suppressed. Furthermore, the oxygen that has been removed can be replenished by performing the second treatment. The first treatment can be performed, for example, at a temperature of 100°C to 300°C, preferably 120°C to 250°C, and more preferably 150°C to 200°C. Note that only the first treatment may be performed as the heat treatment.

[0192] Alternatively, microwave plasma treatment may be performed instead of the above heat treatment. In this case as well, it may be possible to improve the crystallinity of the oxide semiconductor film 230f. For details of microwave plasma treatment, please refer to the explanation above.

[0193] As a result, the oxide semiconductor film 230f shown in Figure 3C can be fabricated. However, there is a risk that grain boundaries may be formed in the region corresponding to the interface between the growing regions 231c between adjacent wall-like structures. However, when processing the oxide semiconductor film 230f into island shapes to form the oxide semiconductor 230, this region can be removed. This makes it possible to provide an oxide semiconductor 230 with good crystallinity in the transistor 200.

[0194] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities such as hydrogen and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near oxygen vacancies can cause V ＯH can be formed, generating electrons that act as carriers. Therefore, if oxygen vacancies and hydrogen are present in the channel formation region of an oxide semiconductor, the transistor is likely to exhibit normally-on characteristics (a characteristic in which a channel exists and current flows through the transistor even without applying voltage to the gate electrode). Consequently, in the channel formation region of an oxide semiconductor, impurities, oxygen vacancies, and V are present. Ｏ It is preferable that H is reduced as much as possible. In other words, it is preferable that the channel-forming region in the oxide semiconductor has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0195] In contrast, by placing an insulator containing excess oxygen near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V Ｏ H can be reduced. Furthermore, an insulator having a barrier property against hydrogen is formed near the transistor 200, and V in the channel formation region of the oxide semiconductor 230 and its vicinity is reduced. Ｏ It is preferable to reduce H.

[0196] Preferably, at least one of insulators 215, 221, 222, 275, 282, and 283 functions as a barrier insulator against hydrogen. Furthermore, preferably at least one of insulators 215, 221, 222, 275, 282, and 283 functions as a barrier insulator against impurities. Also, preferably at least one of insulators 215, 221, 222, 275, 282, and 283 functions as a barrier insulator against oxygen. Note that it is not necessarily required to provide all of insulators 215, 221, 222, 275, 282, and 283. If sufficient barrier properties are provided against hydrogen, impurities, oxygen, etc., the insulator can be appropriately selected from insulator 215, insulator 221, insulator 222, insulator 275, insulator 282, and insulator 283 to form the insulator.

[0197] In this specification, a barrier insulator refers to an insulator that possesses barrier properties. Furthermore, in this specification, "having barrier properties" means having the property of making it difficult for the corresponding substance to diffuse (also referred to as the property of making it difficult for the corresponding substance to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). Alternatively, it refers to having the function of capturing or fixing the corresponding substance within the insulator (also called gettering). When hydrogen is described as a corresponding substance, it refers to, for example, hydrogen atoms, hydrogen molecules, and water molecules and OH groups. − This refers to at least one substance that is bonded with hydrogen, such as [substance name]. Furthermore, when an impurity is described as a corresponding substance, unless otherwise specified, it refers to an impurity in the channel-forming region or semiconductor layer, such as a hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule (N ２ O, NO, NO ２ It refers to at least one substance, such as a copper atom. Furthermore, when oxygen is listed as a corresponding substance, it refers to at least one substance, such as an oxygen atom or an oxygen molecule.

[0198] As an insulator that has the function of suppressing hydrogen diffusion, it is preferable to use, for example, silicon nitride or silicon nitride oxide. In addition, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, etc. may also be used.

[0199] In this specification, "oxide nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content.

[0200] It is preferable to use insulators 221, 275, and 283 that have a function of suppressing hydrogen diffusion. For example, silicon nitride with higher hydrogen barrier properties may be used for insulators 221, 275, and 283.

[0201] As an insulator having the function of capturing or fixing hydrogen, it is preferable to use metal oxides such as hafnium oxide, aluminum oxide, aluminum and hafnium oxide (hafnium aluminate), or magnesium oxide. The insulator having the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides having such an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen. By adding silicon to the above metal oxide, polycrystallization can be suppressed and it can be made more amorphous. Therefore, it is preferable to use metal oxides to which silicon has been added (for example, hafnium silicate, aluminum silicate, etc.).

[0202] It is preferable to use insulators 222 and 282 that have the function of capturing or fixing hydrogen. For example, aluminum oxide may be used for insulator 282. Also, for example, it is preferable to use hafnium oxide for insulator 222.

[0203] Furthermore, the inorganic insulators listed as having the function of suppressing hydrogen diffusion, and those having the function of capturing or fixing hydrogen, also possess barrier properties against oxygen.

[0204] Furthermore, as shown in Figure 1D, it is preferable to provide an insulator 221 having the function of suppressing hydrogen diffusion and an insulator 222 having the function of capturing or fixing hydrogen below the transistor 200. By providing the insulator 221 below the transistor 200, the diffusion of hydrogen from the lower layer of the transistor 200 can be suppressed. Also, by providing the insulator 222 on top of the insulator 221, hydrogen contained in the insulator 224 and the like can be captured or fixed to the insulator 222. This makes it possible to reduce the hydrogen concentration in the oxide semiconductor 230 and its vicinity.

[0205] Furthermore, as shown in Figure 1D, it is preferable to provide an insulator 275 to cover the oxide semiconductor 230, conductor 242a, conductor 242b, etc. By providing the insulator 275 in this way, it is possible to suppress the diffusion of hydrogen from the insulator 280 to the oxide semiconductor 230, conductor 242a, conductor 242b, etc.

[0206] Furthermore, as shown in Figure 1D, it is preferable to provide an insulator 282 having the function of capturing or fixing hydrogen, and an insulator 283 having the function of suppressing hydrogen diffusion, on top of the transistor 200. By providing the insulator 283 on top of the transistor 200, the diffusion of hydrogen from the upper layer of the transistor 200 can be suppressed. Also, by providing the insulator 282 below the insulator 283, hydrogen contained in the insulator 280 and the like can be captured or fixed to the insulator 282. This makes it possible to reduce the hydrogen concentration in the oxide semiconductor 230 and its vicinity.

[0207] Furthermore, the insulator 215 provided below the transistor 200 may have the same configuration as either one or both of the insulators 282 and 283. In this case, the insulator 215 may have a laminated structure of insulators 282 and 283, and may be configured with insulator 282 at the bottom and insulator 283 at the top, or with insulator 282 at the top and insulator 283 at the bottom.

[0208] In this way, by surrounding the top and bottom of the transistor 200 with a barrier insulator against hydrogen, the diffusion of hydrogen into the oxide semiconductor is reduced, and the V in the channel formation region is reduced. Ｏ This allows for a reduction in H. This, in turn, improves the electrical characteristics and reliability of transistor 200.

[0209] Furthermore, it is preferable to include oxygen that is desorbed by heating in the insulator 280. By supplying this oxygen to the oxide semiconductor 230 via the insulator 250 through the heat treatment, oxygen vacancies in the channel formation region can be reduced. Similarly, it is preferable to include oxygen that is desorbed by heating in the insulator 224. This allows oxygen to be supplied from the insulator 224 to the oxide semiconductor 230, further reducing oxygen vacancies in the channel formation region.

[0210] In this embodiment, oxygen can be added to the insulator 280 by forming the insulator 282 using a sputtering method in an atmosphere containing oxygen gas.

[0211] As described above, by heat-treating the insulator 280, which contains oxygen that is desorbed by heating, oxygen can be supplied to the oxide semiconductor 230 via the insulator 250. In this heat-treating process, since insulators 282 and 283, which have barrier properties against oxygen, are formed on the insulator 280, it is possible to prevent excessive diffusion of oxygen contained in the insulator 280 from the insulator 280.

[0212] If an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current or field-effect mobility of the transistor 200. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface can lead to variations in the characteristics of the semiconductor device containing the transistor. In addition, if the amount of oxygen supplied from the insulator to the oxide semiconductor becomes excessively large, it may adversely affect the electrical characteristics and reliability of the transistor. Moreover, oxygen may diffuse into conductors such as the gate electrode, source electrode, and drain electrode, causing oxidation of these conductors and impairing their conductivity.

[0213] In contrast, since an insulator 275 having barrier properties against oxygen is formed between the insulator 280 and the oxide semiconductor 230, conductor 242a, and conductor 242b, it is possible to prevent oxygen contained in the insulator 280 from excessively diffusing into the oxide semiconductor 230, conductor 242a, and conductor 242b.

[0214] Here, it is preferable that the insulator 250 is configured to diffuse oxygen from the insulator 280 to the oxide semiconductor 230 and to suppress oxidation of the conductors 242a, 242b, and 260.

[0215] As shown in Figures 1B and 1D, the insulator 250 is placed within the opening 201 formed in the insulators 280 and 275. Within the opening 201, the insulator 250 is formed in contact with the upper surface of the insulator 222, the side surface of the insulator 224, the side surface and upper surface of the oxide semiconductor 230, the side surface of the conductor 242a1, the side surface of the conductor 242b1, and the side surface of the insulator 255.

[0216] Here, as shown in Figure 2A, it is preferable that the insulator 250 has a laminated structure consisting of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c.

[0217] It is preferable to use silicon oxide or silicon oxynitride, which have a high dielectric strength, for the insulator 250b. Furthermore, in order to improve the dielectric strength, the film thickness of insulator 250b may be greater than that of insulators 250a and 250d. By using such an oxide insulator, oxygen can be diffused in insulator 250b by performing a high-temperature heat treatment. Therefore, by performing the heat treatment, oxygen contained in insulator 280 can be supplied to the oxide semiconductor 230 via insulator 250b.

[0218] To suppress excessive oxidation of conductors 242a1, 242b1, and 260, it is preferable to provide oxygen barrier insulators near each of them. For example, it is preferable that insulators 250a and 250d are made of insulating materials that have oxygen barrier properties.

[0219] The insulator 250a preferably has barrier properties against oxygen. Preferably, the insulator 250a is less permeable to oxygen than at least the insulator 250b. The insulator 250a has regions that are in contact with the side surfaces of the conductor 242a1 and the conductor 242b1. The oxygen barrier properties of the insulator 250a suppress the excessive oxidation of the side surfaces of the conductor 242a1 and the conductor 242b1, and the formation of an oxide film on those side surfaces. This suppresses a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility. Furthermore, with this configuration, the amount of oxygen in the insulator 250b absorbed by the conductor 242a1 and the conductor 242b1 can be reduced. Therefore, an appropriate amount of oxygen can be supplied from the insulator 250b to the oxide semiconductor 230, and oxygen deficiencies in the channel formation region of the oxide semiconductor 230 can be reduced.

[0220] Furthermore, by providing an insulator 250a between the insulator 280 and the insulator 250b, and between the insulator 250b and the oxide semiconductor 230, it is possible to suppress the excessive supply of oxygen from the insulator 280 to the oxide semiconductor 230 and supply an appropriate amount of oxygen to the oxide semiconductor 230. Therefore, the amount of oxygen in the channel formation region of the oxide semiconductor 230 and its vicinity can be controlled to an appropriate amount, thereby preventing excessive positive shift of the transistor 200 and improving reliability. In addition, it is possible to suppress excessive oxidation of the source region and drain region, which can cause a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility.

[0221] Therefore, it is preferable that the insulator 250a has a film thickness that does not excessively hinder the diffusion of oxygen from the insulator 280 to the insulator 250b, and from the insulator 250b to the oxide semiconductor 230. For example, the film thickness of the insulator 250a is preferably 0.1 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and less than 3.0 nm, and even more preferably 0.5 nm or more and 2.0 nm or less.

[0222] As described above, it is preferable to allow for a moderate amount of oxygen diffusion from the insulator 280 to the insulator 250b and from the insulator 250b to the oxide semiconductor 230, while suppressing the diffusion of oxygen from the insulator 250b to the conductors 242a1 and 242b1 as much as possible. In this embodiment of the semiconductor device, the contact area between the insulator 250a and the conductor 242a1, and the contact area between the insulator 250a and the conductor 242b1 are much smaller than the contact area between the insulator 250a and the oxide semiconductor 230. In other words, it is presumed that the amount of oxygen that diffuses from the insulator 250b to the conductors 242a1 and 242b1 via the insulator 250a is less than the amount of oxygen that diffuses from the insulator 250b to the oxide semiconductor 230 via the insulator 250a. Therefore, by controlling the amount of oxygen contained in the insulator 280 and ensuring that a suitable amount of oxygen is supplied from the insulator 280 to the insulator 250b and the oxide semiconductor 230, excessive oxidation of the conductor 242a1 and conductor 242b1 can be reduced.

[0223] The insulator 250a in contact with the channel formation region in the oxide semiconductor 230 preferably has the function of capturing or fixing hydrogen. This makes it possible to reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. Ｏ By reducing H, the channel-forming region can be made i-type or substantially i-type.

[0224] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulator 250a. An example of a high-k material is an oxide containing either or both aluminum and hafnium. By using a high-k material as the insulator 250a, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It also becomes possible to thin the equivalent oxide thickness (EOT) of the insulator that functions as a gate insulator. In this embodiment, a hafnium oxide film is used as the insulator 250a. Hafnium oxide has the function of capturing or fixing hydrogen and has barrier properties against oxygen, making it suitable for use as the insulator 250a.

[0225] It is preferable that the insulator 250d also has barrier properties against oxygen. The insulator 250d is provided between the channel-forming region of the oxide semiconductor 230 and the conductor 260, and between the insulator 280 and the conductor 260. With this configuration, it is possible to suppress the diffusion of oxygen contained in the channel-forming region of the oxide semiconductor 230 into the conductor 260, thereby preventing the formation of oxygen vacancies in the channel-forming region of the oxide semiconductor 230. Furthermore, it is possible to suppress the diffusion of oxygen contained in the oxide semiconductor 230 and the oxygen contained in the insulator 280 into the conductor 260, thereby preventing the oxidation of the conductor 260. It is preferable that the insulator 250d is at least less permeable to oxygen than the insulator 250b. It is also preferable that the insulator 250d has a function to suppress the diffusion of hydrogen. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide semiconductor 230. For example, it is preferable to use a silicon nitride film as the insulator 250d.

[0226] Furthermore, as shown in Figure 2A, it is preferable to have a structure in which an insulator 250c is provided on top of the insulator 250b. In this case, the insulator 250c can be an insulator that can be used for insulator 250a. For example, hafnium oxide can be used as the insulator 250c. By providing the insulator 250c between the insulator 250d and the insulator 250b, hydrogen contained in the insulator 250b and the like can be captured and fixed more effectively.

[0227] By adopting the above configuration, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with good electrical characteristics. Furthermore, with the above configuration, good electrical characteristics can be maintained even when the semiconductor device is miniaturized or highly integrated. In addition, the frequency characteristics can be improved by miniaturizing the transistor 200. Specifically, the cutoff frequency can be improved.

[0228] Insulators 250a to 250d function as part of the gate insulator. Insulators 250a to 250d are provided together with the conductor 260 in the opening formed in the insulator 280. In order to miniaturize the transistor 200, it is preferable that the film thickness of insulators 250a, 250c, and 250d be thin. The film thickness of insulators 250a, 250c, and 250d is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that insulators 250a, 250c, and 250d each only need to have a region with the above-mentioned film thickness in at least a part of it.

[0229] To make the film thickness of insulators 250a to 250d as described above, it is preferable to deposit the film using the ALD method. Furthermore, to form insulators 250a to 250d with good coverage within openings such as insulator 280, it is preferable to deposit the film using the ALD method.

[0230] In the above description, the insulator 250 has been described as having a four-layer structure of insulators 250a to 250d, but the present invention is not limited to this. The insulator 250 can have a configuration having at least one of the insulators 250a to 250d. By configuring the insulator 250 with one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0231] The insulator 225 is formed in contact with the upper surface of the insulator 224. The wall-like structure consisting of the insulator 225 and the metal oxide layer 235 has a high aspect ratio shape in a cross-sectional view in the channel width direction, as shown in Figures 2B and 9A. In the wall-like structure, it is preferable that the height H of the wall-like structure is greater than the width L of the wall-like structure. The height H of the wall-like structure can be 1 to 20 times the width L of the wall-like structure, preferably 1.3 to 15 times, and more preferably 1.5 to 10 times. For example, the width L can be 5 nm to 100 nm, preferably 5 nm to 50 nm, and more preferably 8 nm to 30 nm. Also, for example, the height H can be 30 nm to 300 nm, preferably 50 nm to 150 nm.

[0232] Furthermore, as shown in Figure 2B, in a cross-sectional view in the channel width direction, the angle θ between the side surface of the insulator 225 and the upper surface of the insulator 224 is preferably perpendicular or nearly perpendicular. For example, the angle θ is preferably 80° or more and 100° or less, and more preferably 85° or more and 95° or less.

[0233] The metal oxide layer 235 is preferably provided in contact with the upper surface of the insulator 225. The side surface of the metal oxide layer 235 is preferably provided flush with the side surface of the insulator 225. In this case, in a plan view, the side surface of the metal oxide layer 235 coincides with or substantially coincides with the side surface of the insulator 225.

[0234] Furthermore, the upper part of the metal oxide layer 235 may have a curved shape. Having such a curved shape prevents the formation of defects such as pores in the oxide semiconductor 230 and the conductor 242 near the upper part of the metal oxide layer 235.

[0235] An oxide semiconductor 230 and a conductor 242 are provided to cover this high aspect ratio wall-like structure. Near the channel formation region of the transistor 200, as shown in Figure 2B, the oxide semiconductor 230 is provided so as to be folded in half with the wall-like structure in between, and an insulator 250 and a conductor 260 are provided to cover the oxide semiconductor 230. As a result, the channel width of the transistor 200 is increased by the amount of the A1 side and the A2 side of the wall-like structure.

[0236] As described above, increasing the channel width improves the on-current, field-effect mobility, and frequency characteristics of the transistor 200. This makes it possible to provide a semiconductor device with a high operating speed. Furthermore, it is possible to increase the operating speed of a memory device using this semiconductor device. In addition, in the above structure, by providing the insulator 225, the channel width can be increased without increasing the area occupied by the transistor 200. This makes it possible to miniaturize or highly integrate the semiconductor device. Furthermore, it is possible to increase the storage capacity of a memory device using this semiconductor device.

[0237] The insulator 224 has its lower surface in contact with the insulator 222, and its upper surface in contact with the insulator 225 and the oxide semiconductor 230. The planar shape of the insulator 224 is the same as that of the oxide semiconductor 230, and in plan view, the insulator 224 overlaps with the oxide semiconductor 230. In other words, in plan view, the side surface of the insulator 224 coincides with, or substantially coincides with, the side surface of the oxide semiconductor 230. Furthermore, at least a portion of the insulator 224 overlaps with the conductors 242a (conductors 242a1 and 242a2) and conductors 242b (conductors 242b1 and 242b2) in plan view. In other words, at least a portion of the side surface of the insulator 224 coincides with, or substantially coincides with, the side surface of the conductor 242a (conductor 242a1 and conductor 242a2) and the side surface of the conductor 242b (conductor 242b1 and conductor 242b2) in a plan view.

[0238] As shown in Figure 2B, it is preferable that the film thickness t1 of the insulator 224 within the opening 201 is thicker than the film thickness t2 of the insulator 250. With this configuration, the lower surface of the conductor 260 (conductor 260a) located within the opening 201 can be positioned below the lower surface of the oxide semiconductor 230 by the difference in film thickness t1 and film thickness t2 (t1-t2).

[0239] By positioning the lower surface of the conductor 260 below the lower surface of the oxide semiconductor 230, a sufficient gate electric field can be applied from the upper end to the lower end of the oxide semiconductor 230. In other words, within the opening of the insulator 280, the entire oxide semiconductor 230 can be electrically surrounded by the electric field of the conductor 260, allowing it to function as a channel-forming region. This configuration prevents the lower end of the oxide semiconductor 230 from functioning as a parasitic channel, thereby reducing the leakage current between the source electrode and the drain electrode. Furthermore, it is possible to suppress characteristic defects such as normally-on behavior of the transistor caused by the parasitic channel. In short, the electrical characteristics of the transistor 200 can be improved.

[0240] Furthermore, as described above, by making the entire region from the top to the bottom of the oxide semiconductor 230 function as a channel-forming region, the channel width can be increased. This improves the on-current, transconductance, and frequency characteristics of the transistor 200.

[0241] In this specification, the transistor structure in which the channel formation region is electrically surrounded by the electric field of the gate electrode, as described above, is called a surrounded channel (S-channel) structure. In an S-channel structure, the gate electrode is arranged to surround at least two sides of the channel (specifically, two, three, or four sides, etc.). By adopting an S-channel structure, it is possible to increase resistance to short-channel effects, or in other words, to create a transistor in which short-channel effects are less likely to occur.

[0242] Furthermore, since the S-channel structure electrically surrounds the channel formation region, it can be said that it is essentially equivalent to the GAA (Gate All Around) structure or the LGAA (Lateral Gate All Around) structure. By making the transistor 200 an S-channel structure, a GAA structure, or an LGAA structure, it is possible to improve the current density flowing through the transistor, and thus an improvement in the transistor's on-current or an increase in the transistor's field-effect mobility can be expected.

[0243] Furthermore, even if the film thickness of the oxide semiconductor 230 is reduced as described above, the oxide semiconductor 230 can be supported by a wall-like structure by creating a structure in which the oxide semiconductor 230 is provided by covering the insulator 225 with a high aspect ratio. This allows the oxide semiconductor 230 to be formed extending upward relative to the substrate without tilting. Therefore, the channel width can be increased without increasing the occupied area.

[0244] Furthermore, although the above describes an example in which an insulator 224 is provided below the insulator 225, the present invention is not limited to this. As shown in Figure 4A, a configuration without an insulator 224 is also possible. In this case, the insulator 225 and the oxide semiconductor 230 are formed in contact with the upper surface of the insulator 222. Also, when processing the oxide semiconductor 230 into an island shape, or when forming the opening 201, a part of the upper surface of the insulator 222 may be removed. As a result, as shown in Figure 4A, the upper surface of the region of the insulator 222 that overlaps with the oxide semiconductor 230 may be higher than the upper surface of the region of the insulator 222 that does not overlap with the oxide semiconductor 230.

[0245] Furthermore, although the above describes an example in which the side surface of the insulator 225 is located inward from the side surface of the insulator 224, the present invention is not limited to this. As shown in Figure 4B, the side surface of the insulator 225 and the side surface of the insulator 224 can also be formed to be flush. In this case, the lower end of the side surface of the insulator 225 and the upper end of the side surface of the insulator 224 can coincide or substantially coincide.

[0246] Conductive materials described in the section "Conductive Materials" can be used for conductors 242a and 242b. It is preferable to use conductive materials that are not easily oxidized excessively as conductors 242a and 242b. Examples of such conductive materials include conductive oxides and conductive nitrides. By using these, it is possible to suppress excessive oxidation of conductors 242a and 242b, which would reduce the conductivity of conductors 242a and 242b.

[0247] Conductors 242a and 242b are arranged spaced apart from each other via an opening 201 and are provided in contact with the oxide semiconductor 230. Conductor 242 is provided so as to cover a wall-like structure consisting of an insulator 225 and a metal oxide layer 235, which has a high aspect ratio, as shown in Figure 9A and other figures.

[0248] Here, near the source or drain of the transistor 200, as shown in Figure 9A, the oxide semiconductor 230 and the conductor 242a are arranged so as to be folded in half with the wall-like structure in between. As a result, in a cross-sectional view in the channel width direction, the conductor 242a is in contact with the oxide semiconductor 230 at the top of the wall-like structure, the side on the A3 side, the side on the A4 side, and near the insulator 224. Therefore, compared to the case where the wall-like structure is not provided, the contact area between the conductor 242a and the oxide semiconductor 230 is increased by the amount of the side on the A3 side and the side on the A4 side of the wall-like structure. Note that although Figures 9A and 1C show the vicinity of the conductor 242a, the same applies to the conductor 242b. In other words, the contact area between the conductor 242b and the oxide semiconductor 230 is increased, similar to the contact area between the conductor 242a and the oxide semiconductor 230 described above.

[0249] As described above, increasing the contact area between the conductor 242 and the oxide semiconductor 230 reduces the contact resistance between the conductor 242 and the oxide semiconductor 230 without significantly increasing the area occupied by the transistor 200. Therefore, the on-current and frequency characteristics of the transistor 200 can be improved. This makes it possible to provide a semiconductor device with a high operating speed. Furthermore, the operating speed of a memory device using this semiconductor device can be increased. In addition, this makes it possible to miniaturize or highly integrate the semiconductor device. Furthermore, the storage capacity of a memory device using this semiconductor device can be increased.

[0250] As shown in Figures 1D and 2A, it is preferable to have a two-layer structure for the conductor 242a and conductor 242b. Conductor 242a is a laminated film of conductor 242a1 and conductor 242a2 on conductor 242a1, and conductor 242b is a laminated film of conductor 242b1 and conductor 242b2 on conductor 242b1. Conductors 242a1 and conductor 242b1 are provided in contact with the upper surface of the oxide semiconductor 230. Conductor 242a2 is provided in contact with a part of conductor 242a1, and conductor 242a2 is provided in contact with a part of conductor 242b1. In addition, an insulator 255 is provided in contact with another part of conductor 242a1 and another part of conductor 242b1.

[0251] It is preferable to use conductive materials that are not easily oxidized excessively as the layers (conductors 242a1 and 242b1) in contact with the oxide semiconductor 230. This suppresses excessive oxidation of conductors 242a and 242b, which reduces their conductivity. It also suppresses the extraction of oxygen from the oxide semiconductor 230, which can lead to the formation of excessive oxygen vacancies.

[0252] As conductors 242a1 and 242b1, indium tin oxide (In-Sn oxide, also known as ITO), silicon-containing ITO (In-Sn-Si oxide, also known as ITSO), indium zinc oxide (In-Zn oxide, also known as IZO®), indium titanium oxide (In-Ti oxide), ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., can be used. These materials are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, since these materials are conductive metal oxides, the contact resistance between conductor 242a and oxide semiconductor 230, and the contact resistance between conductor 242b and oxide semiconductor 230 can be reduced. By using such a structure, the on-current of transistor 200 can be increased.

[0253] Furthermore, it is preferable to use metal nitrides as conductors 242a1 and 242b1, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing titanium and aluminum, etc. For example, tantalum nitride can be used as conductors 242a1 and 242b1.

[0254] Furthermore, it is preferable that conductors 242a2 and 242b2 have higher conductivity than conductors 242a1 and 242b1. For example, it is preferable to make the film thickness of conductors 242a2 and 242b2 greater than the film thickness of conductors 242a1 and 242b1. As conductors 242a2 and 242b2, for example, conductive materials mainly composed of tungsten, copper, or aluminum can be used. By adopting the above structure, the resistance of conductors 242a2 and 242b2 can be reduced. This makes it possible to increase the on-current of transistor 200 and improve the operating speed of the semiconductor device according to this embodiment.

[0255] For example, ITO can be used as conductors 242a1 and 242b1, and tungsten can be used as conductors 242a2 and 242b2.

[0256] With the above structure, the upper surface of the oxide semiconductor 230 is exposed in the region between the conductor 242a1 and the conductor 242b1, and the insulator 250 is in contact with this region. Here, as shown in Figure 6A, the upper surface of the oxide semiconductor 230 in this region may be lower than that of other regions. In other words, in the oxide semiconductor 230, the upper surface of the region between the conductor 242a1 and the conductor 242b1 may be lower than the upper surface of the region that overlaps with the conductor 242a1 or the conductor 242b1. It is also possible that the film thickness of the oxide semiconductor 230 in the region overlapping with the insulator 250 is thinner than the film thickness of the oxide semiconductor 230 in the region overlapping with the conductor 242a1 or the conductor 242b1. In this case, the film thickness of the oxide semiconductor 230 in the portion in contact with the upper surface of the metal oxide layer 235 may be thinner than the film thickness of the oxide semiconductor 230 in the portion in contact with the side surface of the insulator 225. Furthermore, in some cases, the oxide semiconductor 230 or a portion thereof in contact with the upper surface of the metal oxide layer 235 may be removed, and a portion of the insulator 225 may come into contact with the insulator 250.

[0257] Furthermore, as described above, when the oxide semiconductor 230 is made into a stacked structure of oxide semiconductors 230_1 to 230_3, as shown in Figure 7B, the oxide semiconductor 230_3 may be divided in the region overlapping with the insulator 250. In this case, a part of the upper surface of the oxide semiconductor 230_2 comes into contact with the insulator 250. By using such a structure, it is possible to make it possible to form the structure only on the oxide semiconductor 230_2 of the transistor 200.

[0258] As shown in Figures 1B and 1D, the insulator 255 is positioned within an opening 201 formed in the insulator 280, etc., and is in contact with the side surface of the insulator 280, the side surface of the insulator 275, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the top and side surfaces of the conductor 242a1, the top and side surfaces of the conductor 242b1, and the top surface of the insulator 222. In other words, it is formed in a sidewall shape within the opening 201. Furthermore, in the region within the opening 201 where the insulator 255 is not formed, the insulator 250 is in contact with the oxide semiconductor 230, the insulator 224, and the insulator 222. Although not shown in Figures 1B, etc., depending on the shape of the oxide semiconductor 230, the insulator 255 may also be formed in contact with the side surface of the oxide semiconductor 230.

[0259] The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and is an inorganic insulator that protects the conductor 242a2 and the conductor 242b2. Since the insulator 255 is exposed to an oxidizing atmosphere, an inorganic insulator that is resistant to oxidation is preferred. Furthermore, since the insulator 255 is in contact with the conductor 242a2 and the conductor 242b2, it is preferable that the inorganic insulator 255 is resistant to oxidation of the conductor 242a2 and the conductor 242b2. Therefore, it is preferable that the insulator 255 be an insulating material that can be used for the insulator 250d which has barrier properties against oxygen. For example, silicon nitride deposited using the PEALD method can be used as the insulator 255. However, it is not limited to this, and insulating materials described in the section "<<Insulator>>" described later can be used for the insulator 255.

[0260] By using such an insulator 255, even if heat treatment is performed in an oxygen-containing atmosphere after separating the conductor 242a1 and conductor 242b1 and before forming the insulator 250, the conductors 242a2 and 242b2 will not be excessively oxidized. For example, the thickness of the oxide film on the sides of the conductors 242a2 and 242b2 near the conductor 260 can be set to 0.5 nm or more and 5 nm or less, preferably 0.5 nm or more and 3 nm or less, and more preferably 0.5 nm or more and 2 nm or less.

[0261] Furthermore, it is preferable that the insulator 255 has a film thickness greater than any one of the insulators 250a to 250d. The film thickness of the insulator 255 is preferably 1 nm to 20 nm, more preferably 1 nm to 15 nm, and more preferably 3 nm to 10 nm. For example, the film thickness can be about 5 nm. By making the insulator 255 such a film thickness, the distance between the conductor 260 and the conductor 242a or conductor 242b can be increased, thereby reducing parasitic capacitance. It is sufficient that the insulator 255 has a region with the above-mentioned film thickness in at least a part of it. Also, since the insulator 255 is provided in an opening formed in the insulator 280, it is preferable to deposit it using a method with good coverage, such as the ALD method.

[0262] Furthermore, the insulator 255 may be a laminated structure of two or more layers using inorganic insulators. When the insulator 255 is a laminated structure of two or more layers, at least one layer should be an inorganic insulator that is resistant to oxidation as described above. For example, as shown in Figure 8A, the insulator 255 can be configured to have an insulator 255a and an insulator 255b on the insulator 255a. In this case, silicon oxide can be used as the insulator 255a and silicon nitride can be used as the insulator 255b.

[0263] Furthermore, the insulator 255 functions as part of the mask when separating the conductor 242a1 and the conductor 242b1. Therefore, as shown in Figure 2A, it is preferable that, in a cross-sectional view of the transistor 200, the inner side surface of the insulator 255 coincides with or substantially coincides with the side edge of the conductor 242a1 and the side edge of the conductor 242b1.

[0264] Here, in the conductor 242a1, the portion on which the insulator 255 is formed on the upper surface (hereinafter sometimes referred to as the protruding portion of the conductor 242a1) protrudes toward the conductor 260 side from the conductor 242a2. Similarly, in the conductor 242b1, the portion on which the insulator 255 is formed on the upper surface (hereinafter sometimes referred to as the protruding portion of the conductor 242b1) protrudes toward the conductor 260 side from the conductor 242b2. As shown in Figure 2A, in a cross-sectional view of the transistor 200 in the channel length direction, the distance D1 between the conductor 242a1 and the conductor 242b1 is smaller than the distance D2 between the conductor 242a2 and the conductor 242b2.

[0265] The distance D1 between the conductor 242a1 and the conductor 242b1 is reflected in the channel length of the transistor 200, and therefore it is preferable that it be small. For example, it is preferable that the distance D1 is 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more. For example, it is more preferable that the distance D1 is between 2 nm and 20 nm. With such a configuration, it is possible to shorten the distance between the source and the drain and shorten the channel length accordingly. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by shortening the channel length of the semiconductor device, it is possible to provide a semiconductor device with improved operating speed.

[0266] Furthermore, in the transistor 200 shown in Figure 2A, the opposing sides of conductor 242a1 and conductor 242b1, and the opposing sides of conductor 242a2 and conductor 242b2 are perpendicular or approximately perpendicular to the upper surface of the oxide semiconductor 230, but the present invention is not limited thereto. For example, as shown in Figure 8B, the opposing sides of conductor 242a1 and conductor 242b1, and the opposing sides of conductor 242a2 and conductor 242b2 may be tapered. In this case, the sides of insulator 271a, insulator 271b, insulator 275, and insulator 280 may be tapered. Note that in Figure 8B, the taper angles of insulator 280, insulator 275, insulator 271a, insulator 271b, conductor 242a2, and conductor 242b2 are equal, but the present invention is not limited thereto, and their respective taper angles may be different. For example, the taper angles of the conductors 242a1 and 242b1 may be acuter than the taper angles of the conductors 242a2 and 242b2.

[0267] Furthermore, as shown in Figure 8C, the upper part of the side surface of the insulator 255 may have a curved shape. Also, as shown in Figure 8C, the upper part of the insulator 280 may also have a curved shape that is continuous with or substantially continuous with the curved shape of the side surface of the insulator 255. Here, the insulator 250 may be in contact with the curved parts of the upper part of the insulator 255 and the upper part of the insulator 280.

[0268] In the above, an example was shown in which the conductors 242a and 242b are arranged in a two-layer laminated structure. However, the present invention is not limited to this, and the conductors 242a and 242b can also be arranged in a single layer or a laminated structure of three or more layers. For example, as shown in Figure 6B, the conductors 242a and 242b can be arranged in a single layer structure. In this case, the conductors 242a and 242b can be made of conductive materials that can be used for conductors 242a1 and conductors 242b1. In this case, as shown in Figure 6B, the insulator 255 can be omitted, and the insulators 280 and 275 can be in contact with the insulator 250. Furthermore, as shown in Figure 6C, the conductors 242a and 242b can be arranged in a two-layer laminated structure, similar to the structure shown in Figure 2A, without the insulator 255.

[0269] Insulators 271a and 271b are inorganic insulators that function as etching stoppers during processing of conductors 242a2 and 242b2, protecting them. Furthermore, since insulator 271a is in contact with conductor 242a2 and insulator 271b is in contact with conductor 242b2, it is preferable that insulators 271a and 271b are inorganic insulators that do not easily oxidize conductors 242a2 and 242b2. Therefore, as shown in Figure 2A, it is preferable that insulator 271a has a laminated structure of insulator 271a1 and insulator 271a2 on insulator 271a1, and insulator 271b has a laminated structure of insulator 271b1 and insulator 271b2 on insulator 271b1. Here, it is preferable to use nitride insulators that can be used for insulator 250d for insulators 271a1 and 271b1 so as to prevent oxidation of conductors 242a2 and 242b2. Furthermore, it is preferable to use oxide insulators that can be used for insulator 250b for insulators 271a2 and 271b2 so as to function as etching stoppers.

[0270] Here, insulator 271a1 is in contact with the upper surface of conductor 242a2 and a part of insulator 275, and insulator 271b1 is in contact with the upper surface of conductor 242b2 and a part of insulator 275. In addition, insulator 271a2 is in contact with the upper surface of insulator 271a1 and the lower surface of insulator 275, and insulator 271b2 is in contact with the upper surface of insulator 271b1 and the lower surface of insulator 275. For example, silicon nitride can be used as insulator 271a1 and insulator 271b1, and silicon oxide can be used as insulator 271a2 and insulator 271b2.

[0271] The conductor 260 can be any conductive material as described in the section on "Conductors," similar to conductors 242a and 242b. It is preferable to use a conductive material that is not easily oxidized excessively, or a conductive material that has a function to suppress oxygen diffusion, as the conductor 260. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This helps to suppress a decrease in the conductivity of the conductor 260.

[0272] As shown in Figures 1B and 1D, the conductor 260 is positioned within the opening 201 formed in the insulators 280 and 275. Within the opening 201, the conductor 260 is positioned to cover the upper surface of the insulator 222, the side surface of the oxide semiconductor 230, and the upper surface of the oxide semiconductor 230, via the insulator 250. Furthermore, the upper surface of the conductor 260 is positioned so that its height is the same as or approximately the same as the top of the insulator 255, the top of the insulator 250, and the upper surface of the insulator 280.

[0273] In addition, in the opening 201 where the conductor 260 and the insulator 250 are arranged, the side walls of the opening 201 may be perpendicular or substantially perpendicular to the upper surface of the insulator 222, or they may be tapered. By making the side walls tapered, the covering of the insulator 250 and the like provided in the opening of the insulator 280 is improved, and defects such as porosity can be reduced.

[0274] The conductor 260 functions as the gate electrode of the transistor 200. Here, it is preferable that the conductor 260 extends in the channel width direction, as shown in Figures 1A and 1B. With this configuration, when multiple transistors are provided, the conductor 260 functions as wiring.

[0275] A portion of the conductor 260 is provided in a folded state, sandwiching a wall-like structure made of an insulator 225 and a metal oxide layer 235. As a result, as shown in Figure 2B, in a cross-sectional view in the channel width direction, the oxide semiconductor 230 and the conductor 260 are provided facing each other with the insulator 250 in between, at the top of the oxide semiconductor 230, the side on the A1 side, the side on the A2 side, and near the insulator 224. In other words, the top of the oxide semiconductor 230, the side on the A1 side, the side on the A2 side, and near the insulator 224 each function as a channel-forming region. Therefore, compared to the case where the wall-like structure is not provided, the channel width of the transistor 200 is increased by the amount of the side on the A1 side and the side on the A2 side of the oxide semiconductor 230.

[0276] In Figure 2A and other figures, the conductor 260 is shown as a two-layer structure. Here, it is preferable that the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is arranged to enclose the lower surface and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0277] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules).

[0278] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by oxygen contained in the insulator 280 and the like, which would reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0279] Furthermore, it is preferable to use a highly conductive material for the conductor 260b. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0280] Furthermore, in transistor 200, the conductor 260 is formed in a self-aligning manner so as to fill the opening 201 formed in the insulator 280 or the like. Here, the side surface of the insulator 280 at the opening 201 coincides with, or nearly coincides with, the side surface of the conductor 242a2 and the side surface of the conductor 242b2. Therefore, the conductor 260 can be placed superimposed in the region between the conductor 242a2 and the conductor 242b2 without the need for alignment.

[0281] It is preferable that insulators 216, 280, and 285 each have a lower dielectric constant than insulator 222. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wiring can be reduced.

[0282] For example, it is preferable that insulators 216, 280, and 285 each contain one or more of the following: silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with voids.

[0283] In particular, silicon oxide and silicon oxide-nitride are preferred because they are thermally stable. Materials such as silicon oxide, silicon oxide-nitride, and silicon oxide with vacancies are especially preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0284] Furthermore, the upper surfaces of insulator 216, insulator 280, and insulator 285 may each be flattened.

[0285] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. For example, it is preferable that the insulator 280 has a silicon-containing oxide such as silicon oxide or silicon oxynitride.

[0286] Conductors 240a and 240b are formed within openings in insulators 275, 280, 282, 283, and 285, respectively. These openings are also formed in insulators 271a and 271b. The lower surface of conductor 240a is in contact with the upper surface of conductor 242a, and the lower surface of conductor 240b is in contact with the upper surface of conductor 242b. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 283 are approximately the same.

[0287] The conductor 240 is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Alternatively, the conductor 240 may have a laminated structure in which the first conductor is provided in contact with the side surface of the insulator 241, and the second conductor is provided further inside. In this case, the above-mentioned conductive material can be used as the second conductor. Here, the first conductor corresponds to the conductor 240a1 shown in Figure 9A, and the second conductor corresponds to the conductor 240a2 shown in Figure 9A.

[0288] Furthermore, when the conductor 240 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged near the insulators 285, 283, 282, 280, and 275. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. The conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminate. With such a configuration, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the layer above the insulator 285 into the oxide semiconductor 230 through the conductors 240a and 240b.

[0289] Insulators 241a and 241b are formed in contact with the inner walls of the openings of insulators 275, 280, 282, 283, and 285, respectively. Also, as shown in Figure 9A, insulator 241a is formed in contact with the inner walls of the openings of insulators 271a1 and 271a2. Similarly, insulator 241b is formed in contact with the inner walls of the openings of insulators 271b1 and 271b2. The inner side surface of insulator 241a is in contact with conductor 240a, and the inner side surface of insulator 241b is in contact with conductor 240b.

[0290] As the insulator 241, a barrier insulating film that can be used for the insulator 275 and the like may be used. For example, as the insulator 241, an insulator such as silicon nitride, aluminum oxide, or silicon oxide nitride may be used. By providing the insulator 241, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the insulator 280, etc., into the oxide semiconductor 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because it has high barrier properties against hydrogen. In addition, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0291] When the insulator 241 is made into a laminated structure, it is preferable to use a combination of an oxygen barrier insulating film and a hydrogen barrier insulating film for the first insulator in contact with the inner wall of the opening such as the insulator 280 and the second insulator inside it. For example, aluminum oxide deposited by the thermal ALD method may be used as the first insulator, and silicon nitride deposited by the PEALD method may be used as the second insulator. By using such a configuration, oxidation of the conductor 240 can be suppressed, and furthermore, the contamination of the conductor 240 with hydrogen can be reduced.

[0292] Although the above describes a configuration in which the insulator 241 has a two-layer laminated structure, the present invention is not limited thereto. For example, the insulator 241 may be provided as a single layer or as a laminated structure of three or more layers. Similarly, although the above describes a configuration in which the conductor 240 has a two-layer laminated structure, the present invention is not limited thereto. For example, the conductor 240 may be provided as a single layer or as a laminated structure of three or more layers.

[0293] Although Figure 9A and other figures show a configuration in which the conductor 240a is mainly in contact with the upper surface of the conductor 242a2, the present invention is not limited to this. The conductor 240a may also be configured to cover the sides of the conductor 242a2, the conductor 242a1, the oxide semiconductor 230, and the insulator 224. By using such a configuration, the contact area between the conductor 240a and the conductor 242a can be increased. In the above description, the conductor 240a has been mentioned, but the same applies to the conductor 240b.

[0294] As described above, increasing the contact area between conductor 240 and conductor 242 reduces the contact resistance between conductor 240 and conductor 242. This allows for improved on-current and frequency characteristics of transistor 200 without significantly increasing the area occupied by transistor 200. This enables the provision of a semiconductor device with a high operating speed. Furthermore, it enables the operation speed of a memory device using this semiconductor device. Additionally, it allows for miniaturization or high integration of the semiconductor device. Furthermore, it enables the storage capacity of a memory device using this semiconductor device.

[0295] In the above, as shown in Figure 1A, the shape of the opening for providing the conductor 240 and the insulator 241 is a rectangle in plan view, but it is not limited to this. For example, the opening may be circular, an ellipse or other approximate circular shape, a polygon such as a rectangle, or a polygon with rounded corners in plan view. Also, as shown in Figure 1C, the opening is formed to overlap with the oxide semiconductor 230 and the insulator 225, but it is not limited to this, and it is sufficient that it overlaps with at least the conductor 242a or the conductor 242b. For example, as shown in Figure 9B, a part of the opening (which can also be called a part of the conductor 240) may overlap with the insulator 225, while another part of the opening (which can also be called another part of the conductor 240) may not overlap with the insulator 225. By configuring the conductor 240 so that a part of it overlaps with the insulator 225, the margin for the placement of the conductor 240 can be increased. Furthermore, as shown in Figure 9C, for example, the opening and the conductor 240 can be provided in a region that does not overlap with the insulator 225.

[0296] Furthermore, in Figures 1D, 9B, and 9C, the conductors 240a and 240b are arranged symmetrically around the conductor 260, but the present invention is not limited to this. For example, as shown in Figure 10A, in a cross-sectional view along the channel length, a part of the conductor 240a may overlap with the insulator 225, while the conductor 240b may not overlap with the oxide semiconductor 230. Alternatively, as shown in Figure 10B, in a cross-sectional view along the channel length, the entire or substantially entire conductor 240a may be positioned to overlap with the insulator 225, while the conductor 240b may be positioned not to overlap with the oxide semiconductor 230.

[0297] In Figures 1A to 1D, the insulator 224 is provided only in the region overlapping with the oxide semiconductor 230, but the present invention is not limited to this. For example, as shown in Figures 11A to 11D, the insulator 224 may be provided not only in the region overlapping with the oxide semiconductor 230 but also outside the opening 201. Here, Figures 11A to 11D correspond to Figures 1A to 1D, respectively, so for detailed configurations, please refer to the above description.

[0298] In one embodiment of the present invention, the shape of the insulator 224 in a plan view and the shape of the oxide semiconductor 230 in a plan view should be made to match or substantially match, at least within the opening 201. In other words, it is preferable that the opening 201 reaches the oxide semiconductor 230, and in the vicinity of the oxide semiconductor 230, it reaches the insulator 222. In this case, as shown in Figures 11B to 11D, the insulator 224 is provided between the insulator 222 and the insulator 275.

[0299] Furthermore, while Figures 1A to 1D show that the transistor 200 is provided with one wall-like structure consisting of an insulator 225 and a metal oxide layer 235, the present invention is not limited to this, and a configuration in which multiple wall-like structures are provided on a single transistor 200 is also possible. For example, as shown in Figures 12A to 12D, a first wall-like structure consisting of an insulator 225_1 and a metal oxide layer 235_1 and a second wall-like structure consisting of an insulator 225_2 and a metal oxide layer 235_2 are arranged in the A1-A2 direction, and an oxide semiconductor 230 is provided covering the first and second wall-like structures. Here, Figures 12A to 12D correspond to Figures 1A to 1D respectively, so for detailed configurations, please refer to the above description.

[0300] As shown in Figure 12B, by providing a first wall-like structure and a second wall-like structure, the area in which the oxide semiconductor 230 and the conductor 260 face each other across the insulator 250 can be increased compared to the case where only one wall-like structure is provided. This makes it possible to increase the channel width per unit area. Also, as shown in Figure 12C, by providing a first wall-like structure and a second wall-like structure, the contact area between the oxide semiconductor 230 and the conductor 242a2 (conductor 242b2) can be increased compared to the case where only one wall-like structure is provided. This makes it possible to reduce the contact resistance between the oxide semiconductor 230 and the conductor 242a2 (conductor 242b2).

[0301] In the above description, the first and second wall-like structures are given a rectangular shape extending in the A5-A6 direction, but the present invention is not limited to this. For example, the planar shape of the wall-like structure can be a circumferential shape (which can also be called a frame shape, ring shape, donut shape, or closed curve shape) with both ends coinciding or substantially coinciding. For example, the first and second wall-like structures shown in Figure 12A can be connected at both ends.

[0302] Furthermore, as shown in Figure 13A, the transistor 200, the capacitive element 460, and the transistor 310 formed on the silicon substrate can be used to function as a 2T (transistor) 1C (capacitor) type memory cell. As shown in Figure 13A, a layer containing the transistor 200 and the capacitive element 460 can be provided on top of a layer containing the transistor 310. Also, Figure 13B shows a cross-sectional view of the transistor 200 in the channel width direction, and Figure 13C shows a cross-sectional view of the transistor 310 in the channel width direction.

[0303] The transistor 310 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that includes a part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 310 may be either a p-channel transistor or an n-channel transistor. For example, a single-crystal silicon substrate can be used as the substrate 311.

[0304] As shown in Figure 13C, the transistor 310 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator that is in contact with the upper part of the convex portion and functions as a mask for forming the convex portion. In addition, although the case of forming the convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film with a convex shape may also be formed by processing an SOI (Silicone on Insulator) substrate.

[0305] Note that the transistor 310 shown in Figure 13A is just one example, and its structure is not limited to that; an appropriate transistor can be used depending on the circuit configuration or driving method.

[0306] A wiring layer containing an interlayer film, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the plugs electrically connected to the wiring may be integrated into a single unit. That is, a portion of the conductor may function as wiring, and a portion of the conductor may function as a plug.

[0307] For example, on the transistor 310, insulators 320, 322, 324, and 326 are stacked in order as interlayer films. Conductors such as 328 are embedded in insulators 320 and 322. Conductors such as 330 are embedded in insulators 324 and 326. Conductors 328 and 330 function as contact plugs or wiring.

[0308] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment using the CMP method or the like to improve its flatness.

[0309] A transistor 200 and a capacitive element 460 are provided on the insulator 326. Here, the transistor 200 is the one shown in Figure 1D. The structure of the transistor 200 and the layer on which the transistor 200 is formed is the same as the structure described above, and is indicated by the same hatching pattern and reference numerals. For detailed structure, please refer to the description above. A conductor 413 is formed on the insulator 285 and is electrically connected to the conductor 240a. The conductor 413 can be made of a conductive material that can be used for the conductor 242.

[0310] The capacitive element 460 includes an insulator 425 on an insulator 224, a metal oxide layer 435 on the insulator 425, an oxide semiconductor 230 covering a wall-like structure made up of the insulator 425 and the metal oxide layer 435, a conductor 242b1 on the oxide semiconductor 230, an insulator 454 on the conductor 242b1, and a conductor 456 on the insulator 454. The insulator 454 and the conductor 456 are provided in openings 202 formed in the insulator 280, the insulator 275, etc. Here, the oxide semiconductor 230 and the conductor 242b1 are used in common with the transistor 200. The opening 202 can be formed in the same process as the opening 201. The insulator 425 has the same structure as the insulator 225 and can be formed in the same process. The metal oxide layer 435 has the same structure as the metal oxide layer 235 and can be formed in the same process. The insulator 454 has the same structure as the insulator 250 and can be formed in the same process. The conductor 456 has the same structure as the conductor 260 and can be formed in the same process. The conductor 260 can be extended as described above and function as wiring. Similarly, the conductor 456 can be extended and function as wiring.

[0311] Here, the capacitive element 460 has a conductor 242b1 that functions as a first electrode, a conductor 456 that functions as a second electrode, and an insulator 454 that functions as a dielectric. In other words, the capacitive element 460 constitutes a MIM (Metal-Insulator-Metal) capacitance.

[0312] The wall-like structure of the capacitive element 460, consisting of the insulator 425 and the metal oxide layer 435, has a high aspect ratio structure, similar to the insulator 225. Therefore, the area where the conductor 242b1, insulator 454, and conductor 456 face each other along the top and side surfaces of the wall-like structure can be increased. This allows for an increase in capacitance without significantly expanding the area occupied by the capacitive element 460.

[0313] Furthermore, it is preferable to provide the conductor 458 in the openings formed in the insulators 215, 216, 221, 222, and 224. The conductor 458 can have a structure similar to that of the conductor 240, for example. The upper surface of the conductor 458 is in contact with the lower surface of the oxide semiconductor 230 and can be electrically connected to the conductor 330. In Figure 13A, only one conductor 458 is shown, but this is not limited to this, and two or more conductors may be used to electrically connect the conductor 242b1 and the conductor 330. Alternatively, the conductor 242b1 and a part of the oxide semiconductor 230 may be embedded in the openings formed in the insulators 215, 216, 221, 222, and 224. Furthermore, it is not necessary for the upper surface of the conductor 458 to be in contact with the lower surface of the oxide semiconductor 230. For example, the conductor 458 can be provided such that its upper surface is exposed from the upper surface of the insulator 285, and a conductor similar to the conductor 240 can be provided in contact with the upper surface of the conductor 242b2, and the conductor and the conductor 458 can be electrically connected via wiring.

[0314] By using the structure described above, one of the source and drain of transistor 200, one of the electrodes of capacitive element 460, and the gate of transistor 310 are electrically connected to form a 2T1C type memory cell. A 1T1C type memory cell can also be formed by omitting transistor 310. Furthermore, a 2T0C type memory cell can be formed by omitting capacitive element 460.

[0315] Here, it is preferable that the transistor 310 is provided superimposed on at least one of the transistor 200 and the capacitive element 460. For example, the transistor 310 can be configured to overlap with the transistor 200. By using such a configuration, the occupied area of ​​the memory cell can be reduced.

[0316] Furthermore, although the structure shown in Figure 13A is a configuration in which a transistor 310 formed on a silicon substrate is provided, the present invention is not limited to this. For example, a configuration may be provided in which two transistors having the same structure as the transistor 200 described above are provided.

[0317] Furthermore, while the above describes a configuration for forming a memory cell, it is not limited to this. For example, a CMOS circuit can be constructed by using an n-channel transistor for transistor 200 and a p-channel transistor for transistor 310.

[0318] <Materials for semiconductor devices> The following describes the materials that can be used for semiconductor devices. Each layer constituting the semiconductor device may be a single-layer structure or a multilayer structure.

[0319] <<Substrates>> For example, insulating substrates, semiconductor substrates, or conductive substrates can be used as substrates for forming transistors. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having metal nitrides, substrates having metal oxides, substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates equipped with one or more types of elements may be used. Examples of elements provided on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0320] <<Insulators>> Examples of insulators that can be used for at least one of insulators 215, 216, 221, 222, 224, 225, 241, 250, 255, 271a, 271b, 275, 280, 282, 283, 285, 315, 320, 322, 324, 326, 425, and 454 include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0321] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0322] Examples of insulators with a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxide nitrides having aluminum and hafnium, oxides having silicon and hafnium, oxide nitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0323] Examples of insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resins.

[0324] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing one or more of the following: boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or in a multilayer structure. Specifically, examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride, and silicon nitride.

[0325] Furthermore, the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, by having silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide semiconductor 230, the oxygen vacancies in the oxide semiconductor 230 can be compensated for.

[0326] <<Conductors>> It is preferable to use a conductor that can be used in at least one of conductors 240, 242, 260, 316, 328, 330, 413, 456, and 458 that is a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. Examples of conductors include tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, highly conductive semiconductors such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0327] When using a laminated conductor, for example, a laminated structure combining a material containing the aforementioned metal element and a conductive material containing oxygen, a laminated structure combining a material containing the aforementioned metal element and a conductive material containing nitrogen, or a laminated structure combining a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be applied.

[0328] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen detached from the conductive material is more easily supplied to the channel formation region.

[0329] In particular, it is preferable to use a conductive material containing the metal element and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal element and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. Alternatively, one or more of the following may be used: indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0330] <Example of Semiconductor Device Fabrication Method> An example of a semiconductor device fabrication method according to one embodiment of the present invention will be described using Figures 14A to 22D. Here, the case of fabricating the semiconductor device shown in Figures 1A to 1D will be used as an example.

[0331] (A) in each figure is a plan view. (B) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in (A), and is also a cross-sectional view of transistor 200 in the channel width direction. (C) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in (A), and is also a cross-sectional view of transistor 200 in the channel width direction. (D) in each figure is a cross-sectional view of the area indicated by the dashed line A5-A6 in (A), and is also a cross-sectional view of transistor 200 in the channel length direction. Note that in the plan view (A) of each figure, some elements have been omitted for clarity.

[0332] In the following, insulating materials for forming an insulator, conductive materials for forming a conductor, or semiconductor materials for forming a semiconductor can be deposited using sputtering, CVD, MBE, PLD, ALD, or other appropriate methods.

[0333] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0334] Furthermore, CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. They can also be further divided into metal CVD (MCCVD) and MOCVD depending on the source gas used.

[0335] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitive elements, etc.) in semiconductor devices can be charged up by receiving charge from the plasma. This accumulated charge can damage these components. In contrast, thermal CVD, which does not use plasma, avoids such plasma damage, resulting in higher yields for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition.

[0336] Furthermore, ALD methods that can be used include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants.

[0337] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and are film deposition methods that provide good step-level coverage. In particular, the ALD method has excellent step-level coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods such as the CVD method, which has a faster deposition rate.

[0338] Furthermore, the CVD method allows for the deposition of films with arbitrary compositions by changing the flow rate ratio of the source gases. For example, in the CVD method, by changing the flow rate ratio of the source gases while deposition is occurring, films with continuously changing compositions can be deposited. When deposition is performed while changing the flow rate ratio of the source gases, the deposition time can be shortened compared to deposition using multiple deposition chambers, because time required for transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0339] First, a substrate (not shown) is prepared, and an insulator 215 is deposited on the substrate (see Figures 14A to 14D). As described above, the insulator 215 can be an insulator similar to one or more of the laminated films of insulators 282 and 283. For example, the insulator 215 can be deposited by sputtering, CVD, MBE, PLD, or ALD. It is preferable to use a sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas, because this can reduce the hydrogen concentration in the insulator 215.

[0340] Next, an insulator 216 is deposited on the insulator 215. The deposition of the insulator 216 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate. In this embodiment, silicon oxide is deposited as the insulator 216 using the sputtering method.

[0341] It is preferable to continuously deposit the insulators 215 and 216 without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of the insulators 215 and 216 with reduced hydrogen content in the film, and further reduces the incorporation of hydrogen into the film between each deposition process.

[0342] Next, an insulating film 221 is formed on the insulating film 216 (see Figures 14A to 14D).

[0343] The insulator 221 may be any insulator having barrier properties against oxygen, hydrogen, and water as described above. The insulator 221 can be formed using, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon nitride is formed as the insulator 221 using the PEALD method.

[0344] Next, an insulating film 222 is formed on the insulating film 221 (see Figures 14A to 14D).

[0345] As the insulator 222, it is preferable to form a film of an insulator containing an oxide of either or both aluminum and hafnium. For example, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing both aluminum and hafnium (hafnium aluminate) as the insulator containing an oxide of either or both aluminum and hafnium. Alternatively, it is preferable to use hafnium zirconium oxide. The insulator containing an oxide of either or both aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 222 has barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the structure provided around the transistor through the insulator 222 into the inside of the transistor is suppressed, thereby suppressing the generation of oxygen vacancies in the oxide semiconductor 230.

[0346] The insulator 222 can be formed using, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, hafnium oxide is formed as the insulator 222 using the thermal ALD method.

[0347] In this embodiment, silicon nitride is deposited as the insulator 221 using the PEALD method, and hafnium oxide is deposited as the insulator 222 using the thermal ALD method. By using silicon nitride, which has the function of suppressing hydrogen diffusion, as the insulator 221, the diffusion of hydrogen from the lower layer of the transistor 200 can be suppressed. Furthermore, by using hafnium oxide, which has the function of capturing or fixing hydrogen, as the insulator 222, hydrogen contained in the oxide semiconductor 230 can be captured or fixed to the insulator 222. This makes it possible to reduce the hydrogen concentration in and near the oxide semiconductor 230.

[0348] Next, an insulating film 224f is deposited on the insulator 222 (see Figures 14A to 14D). The insulating film 224f is the insulating film that will become the insulator 224 in a later step. Therefore, any insulating material that can be used for the insulator 224 described above should be used. The insulating film 224f can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. For example, silicon oxide can be deposited as the insulating film 224f using the sputtering method.

[0349] Next, a laminated film of an insulating film that will become an insulator 225 and a metal oxide film that will become a metal oxide layer 235 is formed on the insulating film 224f, and the laminated film is etched to form the insulator 225 and the metal oxide layer 235 on the insulator 225 (see Figures 14A to 14D). The formation of the insulator 225 and the metal oxide layer 235 can be described by referring to the description in Figure 3A above. As the insulating film that will become the insulator 225, any insulating material that can be used for the insulator 225 as described above may be used. The insulating film that will become the insulator 225 can be formed using, for example, a sputtering method, a CVD method, a MBE method, a PLD method, or an ALD method. For example, gallium oxide can be formed as the insulating film that will become the insulator 225 using a sputtering method.

[0350] As the metal oxide film that will become the metal oxide layer 235, any metal oxide material that can be used for the metal oxide layer 235 described above may be used. The metal oxide film that will become the metal oxide layer 235 can be formed using, for example, sputtering, CVD, MBE, PLD, or ALD. For example, as the metal oxide film that will become the metal oxide layer 235, a film can be used indium oxide that has been formed using the ALD method and then crystallized by microwave plasma treatment.

[0351] The insulator 225 and the metal oxide layer 235 can be processed into island shapes using lithography. Dry etching or wet etching can be used for this processing. Dry etching is suitable for microfabrication.

[0352] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, by etching through this resist mask, conductors, semiconductors, or insulators can be processed into the desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology may be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a photomask may not be necessary.

[0353] Furthermore, the resist mask that is no longer needed after processing can be removed by dry etching, such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), wet etching, wet etching after dry etching, or dry etching after wet etching.

[0354] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. For example, in the above case, the aluminum oxide film on the silicon nitride film functions as a hard mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material is formed, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. The etching of the silicon nitride film may be performed after removing the resist mask, or it may be performed while leaving the resist mask in place. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching the silicon nitride film. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask.

[0355] Also, a configuration may be adopted in which an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film are formed between the workpiece and the resist mask. By using the SOC film and the SOG film as masks, the durability of the mask pattern can be improved. For example, lithography can be performed by forming an SOC film, an SOG film, and a resist mask in this order on the workpiece.

[0356] As the etching gas for dry etching, an etching gas containing a halogen can be used. Specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, as the etching gas, C ４ F ６ gas, C ５ F ６ gas, C ４ F ８ gas, CF ４ gas, SF ６ gas, CHF ３ gas, CH <000,0083>F ２ gas, Cl ２ gas, BCl ３ gas, SiCl ４ gas, or BBr ３ gas, etc. can be used alone or in combination of two or more gases. Also, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be appropriately added to the above etching gas. Also, depending on the workpiece to be dry-etched, a gas containing no halogen gas but containing a hydrocarbon gas or hydrogen gas can be used as the etching gas. As the hydrocarbon used in the etching gas, methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C [[ID=5,2]] ３ H ６ ), acetylene (C ２ H [[ID=,58]] ２), and propine (C ３ H ４ One or more of the following can be used. The etching conditions can be set as appropriate according to the object to be etched.

[0357] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. A capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes, or to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes, or to apply multiple different high-frequency voltages to the parallel plate electrodes. Such a CCP etching apparatus is called a dual-frequency excited capacitively coupled plasma (DF-CCP) etching apparatus. In a DF-CCP etching apparatus, a configuration can be used in which high-frequency voltages of different frequencies are applied to each of the parallel plate electrodes, or to apply multiple different high-frequency voltages to one of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus having a high-density plasma source. The etching apparatus can be appropriately configured according to the object to be etched. In addition, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side of the dry etching apparatus to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, thus enabling highly anisotropic etching.

[0358] Furthermore, when indium oxide is used for the metal oxide layer 235 and gallium oxide is used for the insulator 225, silicon oxide is used for the insulating film 224f, which allows the insulating film 224f to function as an etching stopper during the etching process of the insulator 225.

[0359] In the above description, a configuration in which one wall-like structure composed of the insulator 225 and the metal oxide layer 235 is provided for the transistor 200 is shown. However, the present invention is not limited to this. A configuration in which two or more wall-like structures are provided separately can also be adopted. For example, by adopting a configuration in which the insulator 225_1 and the metal oxide layer 235_1 and the insulator 225_2 and the metal oxide layer 235_2 are provided, the transistor 200 having the configuration shown in FIGS. 12A to 12D can be formed.

[0360] Next, an oxide semiconductor film 230f that becomes the oxide semiconductor 230 is formed to cover the insulator 225 and the metal oxide layer 235 (see FIGS. 15A to 15D). The oxide semiconductor film 230f is a metal oxide film that becomes the oxide semiconductor 230 in a later process, and the above-described oxide semiconductor film can be used. The oxide semiconductor film 230f can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0361] For the film formation of the oxide semiconductor film 230f, reference can be made to the description related to FIGS. 3A to 3C above. Thereby, the oxide semiconductor film 230f can be made into indium oxide having a single crystal structure (also referred to as indium oxide) or indium oxide having high crystallinity. By adopting such a configuration, a semiconductor device having a high field-effect mobility can be provided. In addition, a semiconductor device having at least one of good electrical characteristics, frequency characteristics, and reliability can be provided.

[0362] Further, after the film formation of the oxide semiconductor film 230f, at least one of the heat treatment and the microwave plasma treatment described above may be performed. Thereby, the crystallinity of the oxide semiconductor film 230f may be further enhanced.

[0363] Next, a conductive film 242_1f is deposited on the oxide semiconductor film 230f, and a conductive film 242_2f is deposited on the conductive film 242_1f (see Figures 15A to 15D). Conductive film 242_1f is a conductive film that becomes conductor 242a1 and conductor 242b1, and conductive film 242_2f is a conductive film that becomes conductor 242a2 and conductor 242b2. For conductive film 242_1f, a conductive material that can be used for conductor 242a1 and conductor 242b1 may be used, and for conductive film 242_2f, a conductive material that can be used for conductor 242a2 and conductor 242b2 may be used. Hereinafter, conductive film 242_1f and conductive film 242_2f may be collectively referred to as conductive film 242f.

[0364] The conductive films 242_1f and 242_2f can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. For example, ITO can be deposited as conductive film 242_1f using sputtering. Also, for example, tungsten can be deposited as conductive film 242_2f using sputtering. By depositing the conductive film 242f over the oxide semiconductor film 230f, the contact area between the oxide semiconductor film 230f and the conductors 242a and 242b can be increased without increasing the occupied area. This makes it possible to improve the on-current and frequency characteristics of the transistor 200.

[0365] Next, an insulating film 271f is deposited on the conductive film 242_2f (see Figures 15A to 15D). The insulating film 271f can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film 271f that has the function of suppressing oxygen permeation. For example, as the insulating film 271f, a laminated film of a silicon nitride film and a silicon oxide film on the silicon nitride film can be deposited by sputtering. With such a configuration, the insulator 271a (insulator 271b) can be made into a laminated structure of a silicon nitride insulator 271a1 (insulator 271b1) and a silicon oxide insulator 271a2 (insulator 271b2).

[0366] Here, when forming a laminated film of the insulating film 271f, it is preferable to deposit the film continuously without exposing it to the atmosphere. By depositing the film without exposing it to the atmosphere, the interface or vicinity of the interface of the laminated film of insulating film 271f can be kept clean. Furthermore, it is even more preferable to deposit the film continuously from the conductive film 242_1f to the insulating film 271f without exposing it to the atmosphere.

[0367] Furthermore, a heat treatment may be performed before the deposition of the insulating film 271f. This heat treatment may be carried out under reduced pressure, and the insulating film 271f may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the conductive film 242_2f can be removed, and the moisture and hydrogen concentrations in the conductive films 242_1f and 242_2f can be further reduced. The temperature for the heat treatment is preferably between 100°C and 400°C.

[0368] Next, using lithography, the insulating film 224f, oxide semiconductor film 230f, conductive film 242_1f, conductive film 242_2f, and insulating film 271f are processed into island-like structures to form insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A (see Figures 16A to 16D). At this time, insulator 222 is exposed in regions that do not overlap with insulator 271A.

[0369] The above processing can be performed using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. For details on the conditions and equipment for the dry etching method, please refer to the description above. Furthermore, the processing of the insulating film 224f, oxide semiconductor film 230f, conductive film 242_1f, conductive film 242_2f, and insulating film 271f may be performed under different conditions. In addition, a hard mask may be provided on the insulating film 271f when performing the above processing.

[0370] Here, it is preferable to process the insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A together in an island shape. In this case, it is preferable that the side edge of insulator 271A coincides with or substantially coincides with the side edge of conductor 242_1 and the side edge of conductor 242_2. It is preferable that the side edge of conductor 242_1 and the side edge of conductor 242_2 coincides with or substantially coincides with the side edge of oxide semiconductor 230. Furthermore, it is preferable that the side edge of insulator 224 coincides with or substantially coincides with the side edge of oxide semiconductor 230. By adopting such a configuration, the number of processes for the semiconductor device according to one aspect of the present invention can be reduced. Therefore, a method for manufacturing a semiconductor device with good productivity can be provided.

[0371] As described above, by processing the insulator 224 into an island shape, the lower surface of the conductor 260 in the transistor 200 can be positioned below the lower surface of the oxide semiconductor 230. This allows a sufficient electric field to be applied from the conductor 260 to the entire oxide semiconductor 230. Therefore, the electrical characteristics of the transistor 200 can be improved.

[0372] The sides of the insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A may be configured to be perpendicular or approximately perpendicular to the upper surface of the insulator 222. Such a configuration makes it possible to reduce the area and increase the density when providing multiple transistors.

[0373] However, the above is not limited to the above, and the sides of the insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A may be tapered. The taper angle of the sides of the insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A may be, for example, 60° or more and less than 90°. By making the sides tapered in this way, the coverage of the insulator 275 and the like can be improved in subsequent processes, and defects such as porosity can be reduced.

[0374] Furthermore, as shown in Figure 4A, a configuration without the insulator 224 is also possible. In this case, when the oxide semiconductor 230 is processed into an island shape, a portion of the upper surface of the insulator 222 may be removed. As a result, as shown in Figure 4A, the upper surface of the region of the insulator 222 that overlaps with the oxide semiconductor 230 may be higher than the upper surface of the region of the insulator 222 that does not overlap with the oxide semiconductor 230.

[0375] Furthermore, the dry etching of the insulator 271A, conductor 242_2, conductor 242_1, oxide semiconductor 230, and insulator 224 can be carried out continuously without exposure to the outside air. Here, when a metal oxide is used for conductor 242_1, it is preferable to perform plasma treatment after the dry etching of conductor 242_2. This plasma treatment can be carried out, for example, in a mixed atmosphere of argon gas and oxygen gas.

[0376] When a metal oxide is used for the conductor 242_1, the oxygen contained in the conductor 242_1 may oxidize the metal contained in the conductor 242_2, and a metal oxide layer (hereinafter sometimes referred to as the interfacial oxide layer) may be formed at the interface between the conductor 242_1 and the conductor 242_2. For example, when ITO is used for the conductor 242_1 and tungsten is used for the conductor 242_2, tungsten oxide may be formed as the interfacial oxide layer. The interfacial oxide layer may not be removed by the etching process of the conductor 242_2 and may remain. If the remaining interfacial oxide layer functions as a mask in the etching process of the conductor 242_1, etc., then a portion of the conductor 242_1, the oxide semiconductor 230, and the insulator 224 will not be removed by the etching process and will remain as residue.

[0377] In contrast, the interfacial oxide layer can be removed by performing plasma treatment as described above. Therefore, the generation of residue in the etching process of the conductor 242_1, oxide semiconductor 230, and insulator 224 can be suppressed.

[0378] Next, an insulator 275 is formed by covering the insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A, and then an insulator 280 is formed on top of the insulator 275 (see Figures 17A to 17D). The insulators 275 and 280 can be the insulators described above.

[0379] In this case, it is preferable that the insulator 275 is in contact with the upper surface of the insulator 222.

[0380] Preferably, the insulator 280 is formed by creating an insulating film that will serve as the insulator 280, and then performing a CMP treatment on the insulating film to form an insulator with a flat top surface. Alternatively, silicon nitride may be deposited on the insulator 280, for example, by sputtering, and then the silicon nitride may be subjected to a CMP treatment until it reaches the insulator 280.

[0381] The insulators 275 and 280 can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD.

[0382] It is preferable to use an insulator 275 that has the function of suppressing oxygen permeation. For example, it is preferable to deposit silicon nitride as the insulator 275 using the PEALD method. Alternatively, it is preferable to deposit aluminum oxide as the insulator 275 using the sputtering method, and then deposit silicon nitride on top of it using the PEALD method. By making the insulator 275 such a structure, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0383] In this way, the oxide semiconductor 230, conductor 242_1, and conductor 242_2 can be covered with an insulator 275 that has the function of suppressing oxygen diffusion. This makes it possible to suppress the direct diffusion of oxygen from the insulator 280, etc., into the oxide semiconductor 230, conductor 242_1, and conductor 242_2 in a later process.

[0384] Furthermore, it is preferable to deposit silicon oxide as the insulator 280 using a sputtering method. By depositing the insulating film that will become the insulator 280 using a sputtering method in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. In addition, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. Before depositing the insulating film, a heat treatment may be performed. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed, and the moisture concentration and hydrogen concentration in the oxide semiconductor 230 can be further reduced. The heat treatment conditions described above can be used for this heat treatment.

[0385] Next, the conductor 242_2, insulator 271A, insulator 275, and insulator 280 are processed using lithography to form an opening 201 that reaches the conductor 242_1 and insulator 222 (see Figures 18A to 18D). Here, the conductor 242_2 is divided to form the conductors 242a2 and 242b2. Also, the insulator 271A is divided to form the insulators 271a and 271b. The opening 201 is formed so that at least a portion of it overlaps with the oxide semiconductor 230. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening 201 is D2, which corresponds to the distance D2 between the conductors 242a2 and 242b2 described above. In other words, the width D2 of the opening 201 is greater than the distance D1 between the conductors 242a1 and 242b1 described above.

[0386] The lithography method can be appropriately adapted to the above method. To finely process the aperture of the insulator 280, it is preferable to use a lithography method that uses short-wavelength light such as i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), ultraviolet light, KrF laser light, ArF laser light, EUV light, or an electron beam.

[0387] The above processing is preferably carried out using a dry etching method. Since the dry etching method allows for anisotropic etching, it is suitable for forming an opening 201 with a high aspect ratio. For details regarding the conditions and apparatus for the dry etching method, please refer to the above description.

[0388] Furthermore, although the above describes the process of forming island-shaped insulators 224 in the process shown in Figures 16A to 16D, it is also possible to form the insulator 224 by processing the insulating film 224f in the process shown in Figures 18A to 18D. In this case, the insulating film 224f can be further etched after etching the insulator 275. This removes the region of the insulator 224 that does not overlap with the oxide semiconductor 230 within the opening 201, and forms an opening that reaches the insulator 222. With this configuration, a transistor 200 with the configuration shown in Figures 11A to 11D can be formed.

[0389] Next, an insulating film 255A is formed by covering the insulator 280, the conductor 242_1, and the insulator 222 (see Figures 19A to 19D). The insulating film 255A is an insulating film that will become the insulator 255 in a later step, and the above-mentioned insulators can be used. The insulating film 255A can be formed using, for example, a sputtering method, a CVD method, a MBE method, a PLD method, or an ALD method.

[0390] Since the insulating film 255A is formed along the opening 201, it is preferable that it has good coverage. Therefore, it is preferable to form the insulating film 255A using a method such as ALD that has good coverage. For example, it is preferable to form silicon nitride as the insulating film 255A using the PEALD method.

[0391] Next, a portion of the insulating film 255A is removed by anisotropic etching to form an insulator 255 in contact with the side wall of the opening 201. Furthermore, the conductor 242_1 is etched using the insulator 255 as a mask to form conductors 242a1 and 242b1 (see Figures 20A to 20D). As a result, the opening 201 becomes an opening that reaches the oxide semiconductor 230 and the insulator 222.

[0392] Here, in a cross-sectional view of the transistor 200 in the channel length direction, if the distance between the insulator 255 on the A1 side and the insulator 255 on the A2 side is D1, this corresponds to the distance D1 between the conductor 242a1 and the conductor 242b1 described above. Since the insulator 255 is formed inside the opening 201, the distance D1 between the conductor 242a1 and the conductor 242b1 is shorter than the distance D2 between the conductor 242a2 and the conductor 242b2. The difference between D1 and D2 may coincide with or be substantially the same as twice the film thickness of the insulator 255.

[0393] The above processing is preferably performed using a dry etching method. Since the dry etching method enables anisotropic etching, it is suitable for performing fine processing such as the opening of the insulator 255 inside the opening 201. For the conditions of the dry etching method and the dry etching apparatus, reference can be made to the above description.

[0394] Also, in the etching of the insulating film 255A, the generated ions may collide with the corners of the edges of the openings of the insulator 280 and the insulator 255. As a result, as shown in FIG. 8C and the like, the above corners may be polished into a shape having a curved surface. For example, by including an easily ionizable gas such as argon in the etching gas or applying a bias voltage to the electrode on the substrate side, the above corners can be easily removed.

[0395] As described above, by using anisotropic etching to form the insulator 255 on the conductor 242_1 and using the insulator 255 as a mask to divide the conductor 242_1, the insulator 255 that functions as a mask can be formed self-alignedly. Thereby, in the manufacturing process of the semiconductor device shown in the present embodiment, the number of masks and the number of processes can be reduced. Therefore, a method for manufacturing a highly productive semiconductor device can be provided.

[0396] Furthermore, by using the above method, the island-shaped oxide semiconductor 230 can be exposed to dry etching only during the processing of the conductor 242_1. In other words, the upper surface of the island-shaped oxide semiconductor 230 can be prevented from being exposed to dry etching during the formation of the insulator 255. This reduces the damage (for example, damage due to ion collisions) that the oxide semiconductor 230, which functions as the channel formation region of the transistor 200, suffers from dry etching. During the dry etching process of the conductor 242_1, the damage to the oxide semiconductor 230 can be further reduced by lowering the bias power midway through the process.

[0397] Furthermore, recesses may be formed in the portions of the oxide semiconductor 230 that are exposed from the conductors 242a1 and 242b1. For example, if indium oxide is used for the oxide semiconductor 230 and ITO is used for the conductor 242_1, both the oxide semiconductor 230 and the conductor 242_1 contain indium oxide, making it difficult to selectively etch the conductor 242_1 relative to the oxide semiconductor 230. In this case, as shown in Figure 6A, the film thickness of the oxide semiconductor 230 in the region overlapping with the insulator 250 becomes thinner than the film thickness of the oxide semiconductor 230 in the region overlapping with the conductor 242a1 or conductor 242b1.

[0398] Furthermore, Figure 20B shows an example in which an insulator 255 is formed in a sidewall-like manner on the side surface of the insulator 280 and the side surface of the insulator 275 that form the side wall of the opening 201, but it is not limited to this. For example, an insulator 255 may remain on the side surface of the oxide semiconductor 230 inside the opening 201.

[0399] As described above, conductors 242a2 and 242b2 with a distance D2 from each other, and conductors 242a1 and 242b1 with a distance D1 from each other can be formed. By using this configuration, the distance between the source and drain of the transistor 200 can be shortened, thereby improving the frequency characteristics of the transistor 200 and the operating speed of the semiconductor device.

[0400] Furthermore, an ashing treatment using oxygen plasma may be performed after processing the conductor 242_1 and after processing the conductor 242_2. By performing such oxygen plasma treatment, impurities generated during the etching process and diffused into the oxide semiconductor 230 can be removed. These impurities may be caused by components contained in the workpiece subjected to the etching process and components contained in the gas used for etching. Examples include chlorine, fluorine, tantalum, silicon, and hafnium. By removing these impurities attached to the oxide semiconductor 230, the electrical characteristics and reliability of the transistor can be improved.

[0401] Furthermore, the above-mentioned oxygen plasma treatment may cause at least a portion of the insulator 255 to be oxidized. In other words, the insulator 255 may contain oxygen. Note that if the oxidation of the insulator 255 progresses, at least a portion of the insulator 255 may become silicon oxidized nitride or silicon nitride oxide after the formation of the transistor 200.

[0402] Furthermore, the processing of the insulating film 255A and the conductor 242_1, as well as the oxygen plasma treatment, can be carried out continuously without exposure to the atmosphere. For example, the processing can be performed without exposure to the atmosphere using a multi-chamber etching apparatus.

[0403] Furthermore, a cleaning process may be performed to remove impurities and other substances that have adhered to the surface of the oxide semiconductor 230 during the etching process described above. Cleaning methods include wet cleaning using a cleaning solution (which can also be called wet etching), plasma treatment using plasma, and cleaning by heat treatment, and these cleaning methods may be combined as appropriate. Note that the grooves may become deeper as a result of this cleaning process.

[0404] For wet cleaning, an aqueous solution may be used in which one or more of oxalic acid, phosphoric acid, and hydrofluoric acid are diluted with carbonated water or distilled water. Alternatively, wet cleaning may be used in which ammonia water is diluted with carbonated water or distilled water. Alternatively, wet cleaning may be used with distilled water or carbonated water. Or, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate. Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time the cleaning process is performed.

[0405] It is preferable to perform a heat treatment after etching or cleaning as described above. The temperature of the heat treatment should be between 100°C and 650°C, preferably between 250°C and 600°C, more preferably between 300°C and 550°C, and even more preferably between 350°C and 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. It is preferable to perform the heat treatment in an atmosphere containing oxygen, for example, by setting the flow rate ratio of nitrogen gas to oxygen gas to 4:1 and performing the treatment at a temperature of 350°C for 1 hour. This allows oxygen to be supplied to the oxide semiconductor 230, thereby reducing oxygen deficiency. Furthermore, by performing such a heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. In addition, the supplied oxygen reacts with the hydrogen remaining in the oxide semiconductor 230, thereby converting the hydrogen into H ２ It can be removed as O (dehydrated). As a result, the hydrogen remaining in the oxide semiconductor 230 recombines with the oxygen vacancy and V ＯThe formation of H can be suppressed. Therefore, the electrical characteristics of the transistor provided with the oxide semiconductor 230 can be improved, and its reliability can be enhanced. In addition, variations in the electrical characteristics of multiple transistors formed on the same substrate can be suppressed. The above heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an oxygen atmosphere, and then continuously in a nitrogen atmosphere without exposure to the atmosphere. Furthermore, the above heat treatment can also serve as a heat treatment for the oxide semiconductor film 230f. Therefore, the crystalline region of the oxide semiconductor 230 may grow as a result of the above heat treatment.

[0406] Here, as described above, an insulator 255 having an inorganic insulator that is resistant to oxidation is provided in contact with the side surfaces of the conductor 242a2 and the conductor 242b2. This prevents the conductors 242a2 and 242b2 from being excessively oxidized by the heat treatment, even if relatively easily oxidized tungsten films or the like are used for the conductors 242a2 and 242b2. Furthermore, it prevents the interfaces between the conductor 242a2 and conductor 242a1, and between the conductor 242b2 and conductor 242b1 from being excessively oxidized.

[0407] Furthermore, when heat treatment is performed on the oxide semiconductor 230 while the conductors 242a and 242b are in contact, the sheet resistance may decrease in the regions of the oxide semiconductor 230 that overlap with conductor 242a and the regions that overlap with conductor 242b, respectively. Also, the carrier concentration may increase. Therefore, the resistance of the regions of the oxide semiconductor 230 that overlap with conductor 242a and the regions that overlap with conductor 242b can be reduced.

[0408] Furthermore, processing of the conductor 242_1 as described above, or subsequent cleaning treatment, may remove a portion of the upper surface of the oxide semiconductor 230 in the region between conductor 242a1 and conductor 242b1. As a result, as shown in Figure 6A, the upper surface of the region between conductor 242a1 and conductor 242b1 in the oxide semiconductor 230 may be lower than the upper surface of the region overlapping with conductor 242a1 or conductor 242b1.

[0409] Next, an insulating film 250A, which will become an insulator 250, is formed along the side and bottom surfaces of the opening 201 formed in the insulator 280 or the like (see Figures 21A to 21D). Here, the insulating film 250A is in contact with the insulator 255, the conductor 242a1, the conductor 242b1, the insulator 222, the insulator 224, and the oxide semiconductor 230.

[0410] The insulating film 250A can be deposited using sputtering, CVD, MBE, PLD, or ALD. For example, it is preferable to deposit the insulating film 250A using the ALD method. Similar to the insulator 250 described above, it is preferable to form the insulating film 250A with a thin film thickness, and it is necessary to minimize variations in film thickness. In contrast, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (e.g., an oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Furthermore, the insulating film 250A needs to be deposited with good coverage on the bottom and sides of the opening. By using the ALD method, layers of atoms can be deposited one by one on the bottom and sides of the opening, so the insulating film 250A can be formed with good coverage on the opening.

[0411] Furthermore, when the insulating film 250A is deposited by the ALD method, ozone (O) is used as the oxidizing agent. ３ ), oxygen (O ２ ), water (H ２ O) can be used. Hydrogen-free ozone (O) ３ ), oxygen (O ２ By using oxidizing agents such as ), the amount of hydrogen diffusing into the oxide semiconductor 230 can be reduced.

[0412] The insulator 250 can be made into a laminated structure, as shown in Figure 2A. For example, as shown in Figure 2A, the insulator 250 can be made into a laminated structure of insulators 250a to 250d. In this case, aluminum oxide can be deposited as insulator 250a by thermal ALD, silicon oxide can be deposited as insulator 250b by PEALD, hafnium oxide can be deposited as insulator 250c by thermal ALD, and silicon nitride can be deposited as insulator 250d by PEALD. Furthermore, the insulator 250 is not limited to a four-layer laminated structure. For example, it can also be made into a three-layer laminated structure of insulator 250a, insulator 250b on insulator 250a, and insulator 250d on insulator 250b.

[0413] Furthermore, it is preferable to perform microwave plasma treatment in an oxygen-containing atmosphere after the deposition of the insulating film 250A, or after the deposition of any of the insulators constituting the insulating film 250A.

[0414] By performing microwave plasma treatment in an oxygen-containing atmosphere, the oxygen gas is converted into plasma using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied to the region of the oxide semiconductor 230 between the conductor 242a and the conductor 242b. Due to the action of the plasma, microwaves, etc., the V in that region Ｏ H can be separated into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. Here, when using the structure shown in Figure 2A, it is preferable to use an insulating film (for example, aluminum oxide) that has the function of capturing or fixing hydrogen as the insulator 250a. With such a configuration, the hydrogen generated by microwave plasma treatment can be captured or fixed to the insulating film 250A. In this way, the V included in the channel formation region Ｏ H can be reduced. As a result, oxygen deficiency in the channel formation region and V can be reduced. Ｏ This reduces H and lowers the carrier concentration. Furthermore, by supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0415] The oxygen injected into the channel-forming region can take various forms, including oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, which are atoms, molecules, or ions with unpaired electrons). The oxygen injected into the channel-forming region may be one or more of the above forms, with oxygen radicals being particularly preferred. Furthermore, the film quality of the insulator 250 can be improved, thereby increasing the reliability of the transistor. Additionally, the above microwave plasma treatment can supply oxygen to the insulators 250a and 250b. Excess oxygen from the insulators 250a and 250b can be supplied to the channel-forming region of the oxide semiconductor 230 by subsequent heat treatment.

[0416] Furthermore, by performing microwave plasma treatment, impurities such as carbon in the oxide semiconductor 230 can also be removed. By removing carbon, which is an impurity in the oxide semiconductor 230, the crystallinity of the oxide semiconductor 230 can be improved. In particular, when the oxide semiconductor 230 is deposited by the ALD method, carbon contained in the precursor may be incorporated into the oxide semiconductor 230, so it is preferable to remove the carbon by microwave plasma treatment.

[0417] On the other hand, the oxide semiconductor 230 has a region that overlaps with either the conductor 242a or the conductor 242b. This region can function as a source region or a drain region. Here, it is preferable that the conductors 242a and 242b function as shielding films against the effects of microwaves, high frequencies such as RF, and oxygen plasma when performing microwave plasma processing in an oxygen-containing atmosphere.

[0418] Conductors 242a and 242b shield against the effects of microwaves, RF or other high-frequency waves, oxygen plasma, etc., so these effects do not extend to the region of the oxide semiconductor 230 that overlaps with either conductor 242a or conductor 242b. As a result, the microwave plasma treatment does not affect the source region and drain region. Ｏ Because H is reduced and excessive oxygen supply does not occur, a decrease in carrier concentration can be prevented.

[0419] Here, an insulator 255 is provided in contact with the sides of the conductors 242a2 and 242b2, and has barrier properties against oxygen. This makes it possible to suppress the formation of an oxide film on the sides of the conductors 242a2 and 242b2 by microwave plasma treatment.

[0420] As described above, oxygen vacancies and V are selectively formed in the channel formation region of the oxide semiconductor. Ｏ By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, it is possible to suppress the supply of excess oxygen to the region that functions as the source or drain region, and maintain the conductivity (low resistance state) before microwave plasma treatment. This suppresses variations in the electrical properties of the transistor and prevents variations in the electrical properties of the transistor within the substrate surface.

[0421] Furthermore, by performing microwave plasma treatment to modify the film quality of the insulator 250, the diffusion of hydrogen, water, impurities, etc., can be suppressed. Therefore, in subsequent processes such as deposition of a conductive film to become the conductor 260, or post-treatment such as heat treatment, the diffusion of hydrogen, water, impurities, etc., into the oxide semiconductor 230, etc., via the insulator 250 can be suppressed. In this way, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0422] When the insulator 250 is formed into a laminated structure of insulators 250a to 250d, it is preferable to perform microwave plasma treatment after the deposition of insulator 250b. Furthermore, microwave plasma treatment may be performed again after the deposition of insulator 250c. Thus, microwave plasma treatment in an oxygen-containing atmosphere may be performed multiple times (at least twice). In addition, the above microwave plasma treatment may also serve as a heat treatment for the oxide semiconductor film 230f. Therefore, the above microwave plasma treatment may cause the crystalline region of the oxide semiconductor 230 to grow.

[0423] Alternatively, a heat treatment may be performed while maintaining a reduced pressure state after microwave plasma treatment. By performing such treatment, hydrogen in the insulating film and oxide semiconductor 230 can be efficiently removed. Alternatively, the step of performing a heat treatment while maintaining a reduced pressure state after microwave plasma treatment may be repeated multiple times. By repeating the heat treatment, hydrogen in the insulating film and oxide semiconductor 230 can be removed even more efficiently. The heat treatment temperature is preferably 300°C to 500°C. Furthermore, the above heat treatment can also serve as a heat treatment for the oxide semiconductor film 230f. Therefore, the crystalline region of the oxide semiconductor 230 may grow as a result of the above heat treatment.

[0424] Next, a conductive film 260A, which will become the conductor 260, is deposited (see Figures 21A to 21D). The conductive film 260A is deposited so as to fill the openings 201 formed in the insulator 280 or the like. The conductive film 260A can be deposited using, for example, sputtering, CVD, MBE, PLD, plating, or ALD. For example, as shown in Figure 2A, when a laminated structure of conductor 260a and conductor 260b is formed, titanium nitride can be deposited as the conductive film that will become conductor 260a using the ALD method. Furthermore, tungsten can be deposited as the conductive film that will become conductor 260b using the CVD method. Note that the deposition of the conductive film 260A may be carried out while heating the substrate. Heating the substrate can also serve as a heat treatment for the oxide semiconductor film 230f mentioned above. Therefore, the crystalline region of the oxide semiconductor 230 may grow due to the above substrate heating.

[0425] The conductive film that will become the conductor 260a can be formed by thermal ALD using an inorganic precursor, without using a hydrogen-containing gas. For example, TiCl ４ In this case, NH can be used as the nitride agent. ３ A gas can be used. By forming the film using the method described above, the conductor 260a can be made into a conductive film with a low hydrogen concentration as described above. Therefore, these conductive films can act as a hydrogen source, preventing hydrogen from diffusing into the oxide semiconductor.

[0426] Here, the conductor 260a overlaps with the oxide semiconductor 230 via a thin insulator 250, and is close to the channel formation region of the oxide semiconductor 230. Therefore, if a hydrogen-containing treatment is performed during the film formation process of the conductor 260a, hydrogen will easily diffuse into the channel formation region of the oxide semiconductor 230. For this reason, it is preferable to make the conductor 260a a conductive film with a low hydrogen concentration, as described above.

[0427] Next, the insulating film 250A and the conductive film 260A are polished by CMP treatment until the insulator 280 is exposed. In other words, the portions of the insulating film 250A and the conductive film 260A that are exposed from the opening 201 are removed. As a result, the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) are formed inside the opening 201 (see Figures 22A to 22D).

[0428] As a result, the insulator 250 is provided within the opening 201 in contact with the insulator 255, the conductor 242a1, the conductor 242b1, the oxide semiconductor 230, the insulator 224, and the insulator 222. The conductor 260 is provided so as to fill the opening 201 via the insulator 250. In this way, the transistor 200 is formed.

[0429] Next, an insulator 282 is formed on the insulator 255, the insulator 250, the conductor 260, and the insulator 280 (see Figures 1A to 1D). The insulator 282 can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit the insulator 282 using the sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0430] Here, by using the sputtering method to deposit the insulator 282 in an oxygen-containing atmosphere, oxygen can be added to the insulator 280 while the film is being deposited. This allows the insulator 280 to contain excess oxygen. At this time, it is preferable to deposit the insulator 282 while heating the substrate.

[0431] Furthermore, the insulator 282 can also be made into a laminated structure. In this case, it is preferable to make the lower layer a thin aluminum oxide film deposited by the ALD method and the upper layer a thick aluminum oxide film deposited by the sputtering method. By depositing an aluminum oxide film on top of the thin aluminum oxide film using the sputtering method in this way, the amount of oxygen injected into the insulator 280 can be controlled. This makes it possible to supply a sufficient amount of oxygen to the oxide semiconductor 230 while preventing an excessive amount of oxygen from being supplied to the oxide semiconductor 230.

[0432] Next, an insulator 283 is formed on the insulator 282. The insulator 283 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit the insulator 283 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is deposited as the insulator 283 using sputtering.

[0433] In this embodiment, silicon nitride is deposited as the insulator 283, and aluminum oxide is deposited as the insulator 282. By using silicon nitride, which has the function of suppressing hydrogen diffusion, as the insulator 283, the diffusion of hydrogen from the upper layer of the transistor 200 to the oxide semiconductor 230 can be suppressed. Furthermore, by using aluminum oxide, which has the function of capturing or fixing hydrogen, as the insulator 282, hydrogen contained in the insulator 280 and the like can be captured or fixed to the insulator 282. As a result, the hydrogen concentration in and near the oxide semiconductor 230 can be reduced.

[0434] Next, an insulator 285 is formed on the insulator 283 (see Figures 20A to 20D). The insulator 285 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit the insulator 285 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced. In this embodiment, silicon oxide is deposited as the insulator 285 using sputtering.

[0435] Here, it is preferable to deposit the insulators 282, 283, and 285 continuously by sputtering without exposing them to the atmospheric environment. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulators 282, 283, and 285, and to keep the interface or vicinity of the interface between insulator 282 and insulator 283, and the interface or vicinity of the interface between insulator 283 and insulator 285 clean.

[0436] Next, openings reaching the conductor 242a and openings reaching the conductor 242b are formed in insulators 275, 280, 282, 283, and 285 (see Figures 1A to 1D). These openings may be formed using lithography. It is preferable to process the workpiece using a dry etching method when forming these openings. Dry etching is suitable for forming openings with a high aspect ratio because it allows for anisotropic etching. When performing anisotropic etching, it is preferable to perform reactive ion etching, for example. The conditions for the dry etching method and the dry etching apparatus can be found in the description above. In Figure 1A, the shape of the opening is shown as a rectangle in plan view, but it is not limited to this. For example, the opening may be circular, an ellipse or other approximate circular shape, a rectangle or other polygon, or a rectangle or other polygon with rounded corners in plan view.

[0437] Next, after the formation of the openings, a heat treatment may be performed. The temperature of the heat treatment can be 100°C to 600°C, preferably 250°C to 550°C, and more preferably 350°C to 450°C. The heat treatment is preferably performed in an atmosphere of nitrogen gas or an inert gas. Furthermore, since the heat treatment is performed with the conductors 242a and 242b exposed, it is preferable to perform it in an atmosphere that does not contain oxidizing gases or oxygen gas. For example, it is preferable to perform a heat treatment in a nitrogen gas atmosphere at a temperature of 400°C for 1 hour. The heat treatment may also be performed under reduced pressure. The heat treatment allows oxygen contained in the insulator 280 to be supplied to the oxide semiconductor 230 via the insulator 250. This reduces oxygen vacancies in the channel formation region of the oxide semiconductor 230. In addition, the heat treatment can also serve as a heat treatment for the oxide semiconductor film 230f. Therefore, the crystalline region of the oxide semiconductor 230 may grow as a result of the heat treatment.

[0438] Here, since the side surface of the insulator 280 is exposed at the opening, the amount of oxygen contained in the insulator 280 can be controlled by the heat treatment by diffusing the oxygen contained in the insulator 280 outward. On the other hand, since insulators 282 and 283, which have barrier properties against oxygen, are provided on top of the insulator 280, oxygen does not diffuse outward from the upper surface of the insulator 280. This prevents excessive oxygen from diffusing outward from the insulator 280 and prevents the formation of oxygen vacancies in the insulator 280. In addition, the oxide semiconductor 230, conductor 242a and conductor 242b are covered by the insulator 275. This prevents an excessive amount of oxygen from directly diffusing from the insulator 280 to the oxide semiconductor 230, conductor 242a and conductor 242b during the heat treatment.

[0439] In this way, the amount of oxygen in the insulator 280 can be more favorably adjusted, and a suitable amount of oxygen can be supplied to the oxide semiconductor 230. This reduces oxygen deficiency in the oxide semiconductor 230 and prevents an excessive amount of oxygen from being supplied to the oxide semiconductor 230. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. Furthermore, since the step of exposing the side surface of the insulator 280 can be combined with the step of forming the openings for embedding the conductors 240a and 240b, the manufacturing process of the semiconductor device can be simplified.

[0440] Next, an insulating film to become the insulator 241 is formed, and the insulating film is anisotropically etched to form an insulator 241a at the openings reaching the conductor 242a, and an insulator 241b at the openings reaching the conductor 242b (see Figures 1A to 1D). The insulating film to become the insulator 241 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film to become the insulator 241. For example, it is preferable to form silicon nitride using the PEALD method. Silicon nitride is preferred because it has high barrier properties against hydrogen.

[0441] Furthermore, for the anisotropic etching of the insulating film that will become the insulator 241, a dry etching method, for example, can be used. By providing the insulator 241 on the side walls of the opening, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b that will be formed next can be prevented. In addition, impurities such as water and hydrogen contained in the insulator 280 can be prevented from diffusing into the conductors 240a and 240b. Note that, as a result of this anisotropic etching, recesses may be formed on a part of the upper surface of the conductors 242a and 242b.

[0442] Next, conductive films that will become conductors 240a and 240b are formed. It is desirable that the conductive films that will become conductors 240a and 240b have a laminated structure containing a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. can be formed. The conductive films that will become conductors 240a and 240b can be formed using sputtering, CVD, MBE, PLD, or ALD methods.

[0443] Next, by performing CMP processing, a portion of the conductive film that will become the conductors 240a and 240b is removed, exposing the upper surface of the insulator 283. As a result, the conductive film remains only in the openings, making it possible to form conductors 240a and 240b with flat upper surfaces (see Figures 1A to 1D). Note that in some cases, a portion of the upper surface of the insulator 283 may be removed by this CMP processing.

[0444] As described above, by providing a conductor 240a in contact with conductor 242a, the conductor 240a, which functions as one of the source and drain of transistor 200, can be electrically connected to the wiring. Furthermore, by providing a conductor 240b in contact with conductor 242b, the conductor 240b, which functions as the other of the source and drain of transistor 200, can be electrically connected to the wiring.

[0445] Furthermore, conductive films that function as wiring or conductive films that function as plugs can be formed on the conductors 240a and 240b.

[0446] Based on the above, the semiconductor device shown in Figure 1 can be fabricated.

[0447] The semiconductor device according to this embodiment has an OS transistor. In this embodiment, by using a single-crystal indium oxide or a highly crystalline indium oxide as the oxide semiconductor layer of the OS transistor, a semiconductor device with high field-effect mobility can be provided. For example, the electrical characteristics, on-current, S value (Subthreshold swing value), and frequency characteristics of the transistor can be improved. Furthermore, a highly reliable semiconductor device can be provided.

[0448] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0449] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0450] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0451] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0452] This section describes the carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO. Figure 23A shows silicon (Si) and indium oxide (InO2). Ｘ Figure 23B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0453] First, as indicated by the arrows in Figure 23B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 23A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 2). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 23A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 23A.

[0454] In Figure 23A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0455] Furthermore, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0456] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or resistors, or transparent conductive films. Range R2 is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0457] In the case of indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. As for the supply method of elements that increase the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. In this specification, unless otherwise specified, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions by mass separation is called ion implantation, and a method of supplying ions without mass separation is called ion doping.

[0458] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In IGZO, however, strain can form in the source and drain regions due to stress on the electrodes in contact with the IGZO, and n-type regions may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 23A within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0459] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0460] In addition, a semiconductor being i-type means that the Fermi level (Ef) and the intrinsic Fermi level (Ei) are the same (Ef = Ei). As shown in Figure 23B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is reached, there are no carriers left (in other words, the material has properties similar to an insulator), and it may cease to function as a transistor. On the other hand, in indium oxide, as shown in Figure 23A, the lower the carrier concentration, the higher the hole mobility, and when Ef = Ei is reached, the hole mobility is maximized. That is, transistors containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Furthermore, because transistors containing indium oxide have a low carrier concentration, they tend to be normally off. Therefore, transistors containing indium oxide can be normally off and achieve high field-effect mobility.

[0461] Normally off refers to the state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0V. Normally off can be evaluated using the transistor's threshold voltage (Vth) or shift value (Vsh). Unless otherwise specified, Vth will be calculated using the constant current method. More specifically, Vth is the value of drain current (Id) × channel length (L) ÷ channel width (W) in the transistor's Id-Vg characteristic, where Vth is 1nA (1 × 10⁻¹⁰). −９ Let Vg be the gate voltage (Vg) when A) is true. Also, Vsh is the tangent to the maximum slope when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically, and Id = 1pA (1 × 10⁻¹⁰). −１２ Vg is the gate voltage (Vg) at the intersection with line A), or the Vg at the intersection of the line extrapolated from the two points where the slope of Id is maximized when Id is expressed logarithmically in the transistor's Id-Vg characteristic, and the line where Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive values, it can be considered a normally-off transistor.

[0462] Furthermore, in transistors containing indium oxide, the film configuration in contact with the indium oxide film is crucial for making the semiconductor i-type, that is, for achieving Ef = Ei. For example, in transistors containing indium oxide, a film configuration can be obtained in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in contact with the indium oxide film. By using this film configuration, it is possible to create a semiconductor device that satisfies Ef = Ei and is highly reliable.

[0463] Furthermore, in the above film configuration, oxygen-containing films such as silicon oxide-nitride films, silicon oxide nitride films, aluminum oxide films, and gallium oxide films can be used instead of the silicon oxide film. Also, in the above film configuration, silicon oxide nitride films, silicon oxide nitride films, etc. can be used instead of the silicon nitride film. In addition, the hafnium oxide film located on the indium oxide side of the silicon nitride film functions as a hydrogen gettering site.

[0464] Furthermore, the above film configuration can also be viewed as a layered structure consisting of a film that can supply oxygen to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film), and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. Also, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. In addition, the silicon nitride film provides a film configuration that minimizes the intrusion of oxygen and hydrogen from the outside. In other words, by using the above film configuration, the indium oxide film can be made closer to type i. Therefore, transistors having the above-described indium oxide film have high field-effect mobility and high reliability.

[0465] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0466] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0467] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0468] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0469] The channel formation region refers to the area within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0470] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0471] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0472] Furthermore, the indium oxide film described herein has a high film density. The theoretical value of the film density of the indium oxide film is 7.18 g / cm³. ３ In this specification, the range of film density for indium oxide films is 6.70 g / cm³. ３ 7.18g / cm or more ３ The following, preferably 6.90 g / cm³ ３ 7.18g / cm or more ３ The following, and more preferably 7.00 g / cm³ ３ 7.18g / cm or more ３ The following applies:

[0473] Furthermore, film density can be evaluated using methods such as Rutherford backscattering (RBS) or X-ray reflectivity (XRR). Differences in film density can sometimes be evaluated using transmission electron microscopy (TEM) images of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image.

[0474] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0475] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 23C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. ＯIf oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0476] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0477] Furthermore, as shown in Figure 23C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or by reacting with oxygen contained in the film, and released as water molecules. The above-mentioned oxygen and hydrogen diffuse through the indium oxide film by heat treatment. The temperature of the heat treatment is 200°C to 700°C, preferably 350°C to 650°C, and more preferably 400°C to 500°C.

[0478] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0479] Table 1 shows single crystal indium oxide (here, In ２ O ３The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Also, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0480]

[0481] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0482] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L１ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0483] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0484] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0485] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal with a crystalline structure is IGZO. Indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Silicon crystals have a diamond structure. Thus, in terms of single crystals, indium oxide and silicon have similar properties. However, when comparing indium oxide and silicon from the perspective of whether single crystals can be formed on insulating films, they have different properties.

[0486] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0487] (Embodiment 3) This embodiment describes an example of the configuration of a display device to which a transistor according to one aspect of the present invention can be applied.

[0488] Since the transistor according to one aspect of the present invention can be made extremely small, a display device to which the transistor according to one aspect of the present invention is applied can be an extremely high-resolution display device. For example, the display device according to one aspect of the present invention can be used in the display section of information terminals (wearable devices) such as wristwatches and bracelets, and in the display section of head-mounted displays (HMDs) such as VR (Virtual Reality) devices such as head-mounted displays and AR (Augmented Reality) devices such as glasses.

[0489] [Display Module] Figure 24A shows a perspective view of the display module 580. The display module 580 includes a display device 500A and an FPC 590. Note that the display panel of the display module 580 is not limited to the display device 500A, but may also be the display device 500B described later.

[0490] The display module 580 has substrates 591 and 592. The display module 580 has a display unit 581. The display unit 581 is an area for displaying an image.

[0491] Figure 24B shows a schematic perspective view illustrating the configuration of the substrate 591. A circuit section 582, a pixel circuit section 583 on the circuit section 582, and a pixel section 584 on the pixel circuit section 583 are stacked on the substrate 591. A terminal section 585 for connecting to the FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel section 584. The terminal section 585 and the circuit section 582 are electrically connected by a wiring section 586, which is composed of multiple wires.

[0492] The pixel section 584 has a plurality of pixels 584a arranged periodically. An enlarged view of one pixel 584a is shown on the right side of Figure 24B. The pixel 584a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0493] The pixel circuit section 583 has a plurality of periodically arranged pixel circuits 583a. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices that one pixel 584a has. A single pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device. For example, each pixel circuit 583a may have at least one selection transistor, one current control transistor (drive transistor), and a capacitive element. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix type display panel.

[0494] The circuit section 582 has circuits for driving each pixel circuit 583a of the pixel circuit section 583. For example, it is preferable to have one or both of a gate line drive circuit and a source line drive circuit. In addition, it may have at least one of the following: an arithmetic circuit, a memory circuit, and a power supply circuit. Furthermore, transistors provided in the circuit section 582 may constitute a part of the pixel circuit 583a. That is, the pixel circuit 583a may be composed of transistors in the pixel circuit section 583 and transistors in the circuit section 582.

[0495] The FPC 590 functions as wiring for supplying video signals and power potential, etc., to the circuit section 582 from an external source. An IC may also be mounted on the FPC 590.

[0496] The display module 580 can be configured such that one or both of the pixel circuit section 583 and the circuit section 582 are superimposed on the lower side of the pixel section 584, thereby making the aperture ratio (effective display area ratio) of the display section 581 extremely high. For example, the aperture ratio of the display section 581 can be 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. Furthermore, it is possible to arrange the pixels 584a at an extremely high density, making the resolution of the display section 581 extremely high. For example, it is preferable that the pixels 584a in the display section 581 are arranged at a density of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, with a resolution of 20000 ppi or less, or 30000 ppi or less.

[0497] Because such a display module 580 is extremely high-resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration where the display part of the display module 580 is viewed through lenses, the display module 580 has an extremely high-resolution display part 581, so even when the display part is magnified with lenses, pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 580 is not limited to this, and can be suitably used in electronic devices with relatively small display parts. For example, it can be suitably used in the display part of wearable electronic devices such as wristwatches.

[0498] [Display device 500A] The display device 500A shown in Figure 25 has a substrate 210, a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitive element 140, and a transistor 520.

[0499] Substrate 210 corresponds to substrate 591 in Figure 24A.

[0500] The transistor 520 is a transistor in which an oxide semiconductor is applied to the semiconductor layer where the channel is formed. The transistor 520 has an oxide semiconductor 230, an insulator 222, an insulator 224, an insulator 225, a metal oxide layer 235, a conductor 242a, a conductor 242b, an insulator 250, and a conductor 260, etc. Interlayer films are formed on the substrate 210 in the order of insulator 215, an insulator 216, an insulator 222, an insulator 280, an insulator 282, an insulator 283, and an insulator 285. Conductors 240 and insulator 241 are formed inside openings formed in insulators 280, 282, 283, and 285.

[0501] The transistor 520 can be any of the various transistors exemplified in Embodiment 1. This reduces the parasitic capacitance and leakage current of the transistor 520. As a result, the power consumption of the display device 500A can be reduced.

[0502] Furthermore, although the transistor 520 is simplified in Figure 25, the structure of the transistor 200 and its vicinity as shown in Figure 9A can also be used. For example, as shown in Figure 9A, an insulator having barrier properties against impurities such as hydrogen can be provided on the upper and lower layers of the transistor. This prevents hydrogen contained in the substrate and its vicinity, as well as in the light-emitting element and its vicinity, from diffusing into the transistor 520. Also, by providing an insulator 241 to cover the side surface of the conductor 240 and using a conductive film with reduced hydrogen concentration on the conductor 240, it is possible to prevent hydrogen contained in the light-emitting element and its vicinity from diffusing into the insulator 280 via the conductor 240. This prevents impurities, oxygen vacancies, and V in the channel formation region of the oxide semiconductor 230. Ｏ By reducing H and other parameters, the electrical characteristics and reliability of the transistor 520 can be improved. Therefore, a display device with good display performance and reliability can be provided. The conductor 240 and the insulator 241 correspond to the conductor 240a, conductor 240b, insulator 241a, and insulator 241b described in Embodiment 1, respectively.

[0503] Furthermore, a capacitive element 140 is provided on the insulator 285. The capacitive element 140 has a conductive layer 141, a conductive layer 145, and an insulating layer 143 located between them. The conductive layer 141 functions as one electrode of the capacitive element 140, the conductive layer 145 functions as the other electrode of the capacitive element 140, and the insulating layer 143 functions as the dielectric of the capacitive element 140.

[0504] The conductive layer 141 is provided on the insulator 285 and embedded in the insulating layer 154. The conductive layer 141 is electrically connected to the conductor 242a of the transistor 520 by the conductor 240. The insulating layer 143 is provided covering the conductive layer 141. The conductive layer 145 is provided in the region that overlaps with the conductive layer 141 via the insulating layer 143.

[0505] The capacitive element 140 can be configured to have an insulator covering it that provides a barrier against impurities such as hydrogen. This prevents hydrogen contained in the light-emitting element and its vicinity from diffusing to the lower transistor 520. Thus, a highly reliable display device can be provided.

[0506] Furthermore, as shown in Figure 9A, a wiring layer can also be provided on top of the capacitive element 140. Also, the connection relationships of circuit elements, wiring, vias, etc., in the display device according to this embodiment are not limited to those shown in Figure 25. The connection relationships of circuit elements, wiring, vias, etc., can be appropriately set to match the pixel circuit of the display device.

[0507] An insulating layer 155a is provided to cover the capacitive element 140, an insulating layer 155b is provided on the insulating layer 155a, and an insulating layer 155c is provided on the insulating layer 155b.

[0508] Insulating layers 155a, 155b, and 155c can each preferably be made of inorganic insulating films. For example, it is preferable to use silicon oxide films for insulating layers 155a and 155c, and silicon nitride films for insulating layer 155b. This allows insulating layer 155b to function as an etching protective film. In this embodiment, an example is shown in which a part of insulating layer 155c is etched and a recess is formed, but the insulating layer 155c does not necessarily have to have a recess.

[0509] A light-emitting element 110R, a light-emitting element 110G, and a light-emitting element 110B are provided on the insulating layer 155c.

[0510] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting elements 110R, 110G, and 110B.

[0511] The organic layer 112R of the light-emitting element 110R contains at least a luminescent organic compound that emits red light. The organic layer 112G of the light-emitting element 110G contains at least a luminescent organic compound that emits green light. The organic layer 112B of the light-emitting element 110B contains at least a luminescent organic compound that emits blue light. The organic layers 112R, 112G, and 112B can each also be called EL layers and each contains at least a luminescent organic compound (luminescent layer).

[0512] The display device 500A has different light-emitting devices for each light-emitting color, resulting in minimal change in chromaticity between low-brightness and high-brightness illumination. Furthermore, because the organic layers 112R, 112G, and 112B are separated, crosstalk between adjacent sub-pixels can be suppressed even in high-resolution display panels. Therefore, a display panel with high resolution and high display quality can be realized.

[0513] An insulating layer 125, a resin layer 126, and a layer 128 are provided in the region between adjacent light-emitting elements.

[0514] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductor 242a of the transistor 520 by a plug 156 embedded in the insulating layer 155a, insulating layer 155b, and insulating layer 155c, a conductive layer 141 embedded in the insulating layer 154, and a conductor 240. The height of the upper surface of the insulating layer 155c and the height of the upper surface of the plug 156 are the same or approximately the same. Various conductive materials can be used for the plug.

[0515] Furthermore, a protective layer 121 is provided on the light-emitting elements 110R, 110G, and 110B. The substrate 170 is bonded to the protective layer 121 by an adhesive layer 171.

[0516] There is no insulating layer covering the upper edge of the pixel electrode 111 between two adjacent pixel electrodes 111. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made.

[0517] [Display Device 500B] The following describes a display device with some configurations different from those described above. Note that parts common to the above will be referred to and may be omitted from the explanation.

[0518] The display device 500B shown in Figure 26 has a configuration in which a transistor 520A on a substrate 210 and a transistor 520B on top of transistor 520A are stacked. Here, transistors 520A and 520B have the same configuration as transistor 520. In other words, the display device 500B has a structure in which, in the display device...

Claims

It comprises a metal oxide layer, an oxide semiconductor, first to fourth insulators, and first to third conductors. The second insulator is placed on the first insulator. The metal oxide layer is disposed on the second insulator. The oxide semiconductor is disposed on the first insulator and covers a wall-like structure consisting of the metal oxide layer and the second insulator. The first conductor and the second conductor are arranged on the oxide semiconductor. The third insulator is arranged on the first conductor and the second conductor and has an opening that overlaps with the region between the first conductor and the second conductor. The fourth insulator is placed in the opening, overlapping the oxide semiconductor. The third conductor is placed on the fourth insulator within the opening. In a cross-sectional view in the channel width direction, the height of the wall-like structure is greater than the width of the wall-like structure. The metal oxide layer contains indium and has crystals. The oxide semiconductor contains indium and has a cubic crystal structure. The oxide semiconductor has a first region in contact with the side surface of the wall-like structure and a second region in contact with the upper surface of the wall-like structure. The crystal orientation of the crystal grains in the first region and the crystal orientation of the crystal grains in the second region are identical or substantially identical. Semiconductor equipment. 　 In claim 1, The crystal orientation of the crystal grains in the first region and the crystal orientation of the crystal grains in the second region are <111>. Semiconductor equipment. 　 In claim 1, The metal oxide layer has a cubic crystal structure. Semiconductor equipment. 　 In claim 1, The metal oxide layer comprises indium, gallium, and zinc, and has a hexagonal or trigonal crystal structure. Semiconductor equipment. 　 In claim 1, The side surface of the metal oxide layer coincides with or substantially coincides with the side surface of the second insulator in a plan view. Semiconductor equipment. 　 In claim 1, The second insulator has gallium oxide, aluminum oxide, or silicon oxide. Semiconductor equipment. 　 In claim 1, The side surface of the first insulator coincides with or substantially coincides with the side surface of the oxide semiconductor, the side surface of the first conductor, and the side surface of the second conductor in a plan view. The thickness of the first insulator is greater than the thickness of the fourth insulator. Semiconductor equipment. 　 In claim 7, The lower surface of the third conductor has a portion located below the lower surface of the oxide semiconductor. Semiconductor equipment. 　 In any one of claims 1 to 8, It has a fifth insulator, The first conductor and the second conductor each have a first conductive layer and a second conductive layer on the first conductive layer. The fifth insulator is positioned within the opening of the third insulator and is in contact with the upper surface of the first conductive layer of the first conductor, the side surface of the second conductive layer of the first conductor, the upper surface of the first conductive layer of the second conductor, and the side surface of the second conductive layer of the second conductor. The shortest distance between the first conductive layer of the first conductor and the first conductive layer of the second conductor is smaller than the shortest distance between the second conductive layer of the first conductor and the second conductive layer of the second conductor. Semiconductor equipment. 　 In claim 9, A portion of the side surface of the third insulator coincides with or substantially coincides with the side surface of the second conductive layer of the first conductor and the side surface of the second conductive layer of the second conductor in a plan view. Semiconductor equipment. 　 In claim 9, The fifth insulator has silicon nitride, Semiconductor equipment. 　 In claim 9, The first conductive layer of the first conductor and the first conductive layer of the second conductor each contain indium and tin, respectively. Semiconductor equipment.

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