Field-effect transistor and method for manufacturing same

Abstract

This field-effect transistor is first provided with a columnar part (131) on a substrate (101), and a channel layer (102) and a barrier layer (103) are formed in the columnar part (131). A gate electrode (104) is formed on the columnar part (131). A source electrode (105) and a drain electrode (106) are formed on the substrate (101) on both sides of the columnar part (131).

Description

Field-Effect Transistor and Method for Manufacturing the Same

[0001] The present invention relates to a field-effect transistor and a method for manufacturing the same.

[0002] The terahertz frequency band of 0.3 to 3.0 THz is expected to have a wide range of applications, not only for next-generation high-speed wireless communication, but also for non-destructive inspection by imaging using terahertz waves, security applications by transmission imaging, material analysis using absorption spectra, and acquisition of weather-related information by radiometers mounted on satellites. For this reason, attention has been focused on electronic devices and integrated circuits that can directly handle the terahertz frequency band. Generally, as an electronic device having excellent high-frequency characteristics, a field-effect transistor using a compound semiconductor having a high electron mobility is used.

[0003] A field-effect transistor for high frequencies generally has a structure in which a buffer layer, a channel layer, and a barrier layer made of a compound semiconductor are laminated on a substrate, and ohmic electrodes such as an ohmic cap layer, a source electrode, and a drain electrode are formed on these, and a gate electrode is formed between the source electrode and the drain electrode.

[0004] A carrier supply layer called a δ-doped layer is formed in the barrier layer, and impurities are doped in this layer at a high concentration. Carriers, that is, electrons, generated by ionization of these impurities are accumulated in the channel layer having a smaller band gap than the barrier layer to form a two-dimensional electron gas.

[0005] Since the two-dimensional electron gas in the channel layer is spatially separated from the ionized impurities by the barrier layer, it can travel at high speed between the source and the drain without suffering from mobility degradation due to impurity scattering.

[0006] Also, for the purpose of facilitating carrier injection from the ohmic electrode into the channel layer and carrier conduction from the channel layer to the ohmic electrode, in other words, reducing the source resistance and the drain resistance, the ohmic cap layer may also be doped with impurities in the same manner as the carrier supply layer.

[0007] In the above structure, a voltage is applied to the gate electrode to modulate the band structure directly below the gate electrode, thereby controlling the two-dimensional electron gas concentration in the channel layer and controlling the amount of current flowing between the source and drain. Therefore, in the case of a configuration where the source electrode is grounded, by inputting a high-frequency signal to be amplified to the gate electrode, an amplified signal can be extracted from the drain electrode.

[0008] In particular, when handling high-frequency signals such as terahertz waves, it is crucial to reduce the parasitic resistance and parasitic capacitance of devices that increase the delay time. For example, in a high-frequency field-effect transistor, the current gain cutoff frequency f t , the maximum transmission frequency f max , and the minimum noise factor F min are given by the following equations.

[0009]

[0010] Here, R i , R s , R d , R g are the channel resistance, source resistance, drain resistance, and gate resistance, respectively, g d,int , g m,int are the drain conductance and transconductance in the intrinsic region of the device, respectively, C gs , C gd are the gate-source capacitance and gate-drain capacitance, respectively, K G is a term mainly related to drain noise, and K r is a term mainly related to gate-induced noise.

[0011] f t , f max are important parameters for the circuit application of high-frequency field-effect transistors. For example, when designing a high-frequency front-end IC, a higher value is desirable. Also, F min is an index related to the noise generated by the field-effect transistor itself, and a lower value is desirable in order to amplify without degrading the S / N ratio of the received signal. To meet these requirements, from equations (1) to (3), the resistances R s , R d and the capacitance Cgs , C gd It can be seen that reducing [the element] is effective.

[0012] Generally, in high-frequency field-effect transistors, the gate resistance R due to the skin effect is a factor. g To avoid an increase in R, a T-shaped gate structure as shown in Figure 1A of Patent Document 1 is used. The T-shaped gate structure is R g While effective in reducing C, the head portion needs to be extended in the channel length direction to increase the surface area, which shortens the distance to the source and drain electrodes. gs , C gd There is a trade-off that this will lead to an increase in [something].

[0013] The head portion of the T-type gate electrode is extended in the channel width direction R g As a method to reduce the increase in capacitance while suppressing the increase in capacitance, for example, a cavity structure like the one shown in Fig. 1 of Non-Patent Document 1 has been proposed. This ultimately reduces the relative permittivity of the material between the gate and the source / drain electrodes to 1 by forming a cavity (gap) around the T-type gate electrode, C gs , C gd This is a technology for reducing it.

[0014] Furthermore, in the structure shown in Figure 1A of Patent Document 1, a separate structure is formed to support the head portion, thereby increasing the mechanical stability of the T-type gate electrode. This allows for the formation of a head portion that is long in the height direction, C gs , C gd While suppressing the increase of R g This can reduce C. Furthermore, the structure supporting the head allows the head to be separated from the source / drain electrodes in the height direction while maintaining mechanical stability. gs , C gd This can be reduced.

[0015] Also, R s , R d A simple way to reduce C is to shorten the distance between the gate electrode and the source / drain electrodes. As mentioned above, the gate electrode and the source / drain electrodes are physically close together. gs , C gdAlthough this increases, it can be suppressed to some extent by the structure described above.

[0016] Other R s , R d As a technique to reduce this, the ohmic cap layer regrowth technique shown in Fig. 1 of Non-Patent Document 2 has been proposed. For example, in an InP-based field-effect transistor, which is well known as a field-effect transistor for high frequencies, electrons injected from the source electrode pass through the ohmic cap layer, tunnel through the barrier layer to reach the channel layer, travel from the source to the drain within the channel layer, then tunnel through the barrier layer again, pass through the ohmic cap layer, and reach the drain electrode.

[0017] Here, the tunnel resistance of the barrier layer is R s , R d Although it is an important element that constitutes the channel, by etching the source / drain electrode region down to the channel layer and then regrowing the ohmic cap layer directly above the channel layer, electrons can be injected into the channel without going through the barrier layer, thus R s , R d The tunnel resistance component of the barrier layer in this can be reduced to zero. This technique generally results in a drastic reduction in R compared to shortening the distance between the gate electrode and the source / drain electrodes. s , R d A reduction in this can be expected.

[0018] Patent No. 6713948

[0019] JB Shealy et al., "High-Performance Submicrometer Gatelength GaInAs / InP Composite Channel HEMT's with Regrown Ohmic Contacts", IEEE Electron Device Letters, vol. 17, no. 11, pp. 540-542, 2002.

[0020] For devices where miniaturization has progressed to the point where the gate length is less than 100 nm in order to utilize the terahertz wave band, the resistor R s , R d and capacity C gs , C gd Reducing this is crucial. However, in the regrowth of the ohmic cap layer described above, the source / drain electrodes are generally formed in the same position as before, or slightly higher (i.e., closer to the gate head), so the problem of increased capacitance due to coupling between the gate electrode and the source / drain electrodes cannot be solved.

[0021] While some capacitance reduction is possible by forming special structures such as a support structure for the head portion of the T-type gate electrode or a cavity structure, as long as the source / drain electrodes are formed at the same or slightly higher positions as in conventional designs, it is impossible to reduce capacitance beyond the limits of conventional technology.

[0022] Therefore, in field-effect transistors in the future terahertz wave era, R s , R d At the same time, C is reduced compared to the conventional structure. gs , C gd It is necessary to have a structure that can reduce this.

[0023] This invention was made to solve the above-mentioned problems, and aims to reduce parasitic capacitance by reducing source resistance and drain resistance.

[0024] The field-effect transistor according to the present invention comprises a columnar portion having a channel layer and a barrier layer formed on a substrate, a gate electrode formed on the columnar portion, a source electrode and a drain electrode formed on the substrate on both sides of the columnar portion, a first contact layer that electrically connects the source electrode and the channel layer exposed on the side wall of the columnar portion on the side of the source electrode, and a second contact layer that electrically connects the drain electrode and the channel layer exposed on the side wall of the columnar portion on the side of the drain electrode.

[0025] Furthermore, the method for manufacturing a field-effect transistor according to the present invention comprises: a first step of forming a channel layer and a barrier layer formed on a substrate; a second step of forming a columnar portion of a columnar structure by patterning the channel layer and the barrier layer; a third step of forming a first contact layer and a second contact layer connected to the channel layer exposed on the side walls of the columnar portion on substrates on both sides of the columnar portion; a fourth step of forming a source electrode via the first contact layer and a drain electrode via the second contact layer on substrates on both sides of the columnar portion; and a fifth step of forming a gate electrode on the columnar portion.

[0026] As described above, according to the present invention, since the source electrode and drain electrode are formed on the substrates on both sides of the columnar portion having a channel layer and a barrier layer, the source resistance and drain resistance can be reduced and parasitic capacitance can be reduced.

[0027] Figure 1 is a cross-sectional view showing the configuration of a field-effect transistor according to Embodiment 1. Figure 2A is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining the manufacturing method of a field-effect transistor according to Embodiment 1. Figure 2B is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining the manufacturing method of a field-effect transistor according to Embodiment 1. Figure 2C is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining the manufacturing method of a field-effect transistor according to Embodiment 1. Figure 2D is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining the manufacturing method of a field-effect transistor according to Embodiment 1. Figure 2E is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining the manufacturing method of a field-effect transistor according to Embodiment 1. Figure 2F is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining the manufacturing method of a field-effect transistor according to Embodiment 1. Figure 2G is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining the manufacturing method of a field-effect transistor according to Embodiment 1. Figure 3A shows the capacitance C gs , C gd This is an explanatory diagram to explain the reduction effect of volume C. gs , C gd This is an explanatory diagram to explain the reduction effect. Figure 3C shows the capacity C gs , C gdThis is an explanatory diagram for explaining the reduction effect. Figure 4 is a cross-sectional view showing the configuration of a field-effect transistor according to Embodiment 2. Figure 5A is a cross-sectional view showing the configuration of a field-effect transistor according to Embodiment 3. Figure 5B is an explanatory diagram showing the state of metal particles reached in the vacuum deposition method. Figure 5C is an explanatory diagram showing the state of metal particles reached in the vacuum deposition method. Figure 6A is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining the manufacturing method of a field-effect transistor according to Embodiment 3. Figure 6B is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining the manufacturing method of a field-effect transistor according to Embodiment 3. Figure 6C is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining the manufacturing method of a field-effect transistor according to Embodiment 3. Figure 6D is a cross-sectional view showing the state of a field-effect transistor in an intermediate step for explaining the manufacturing method of a field-effect transistor according to Embodiment 3. Figure 7 is a plan view (a) and a cross-sectional view (b) showing the configuration of a field-effect transistor according to Embodiment 4. Figure 8 is a plan view (a) and a cross-sectional view (b) showing the configuration of another field-effect transistor according to Embodiment 4.

[0028] The embodiments will be described below.

[0029] [Embodiment 1] First, a field-effect transistor according to Embodiment 1 will be described with reference to Figure 1. This field-effect transistor first has a columnar portion 131 on a substrate 101, and a channel layer 102 and a barrier layer 103 are formed on the columnar portion 131. A gate electrode 104 is also formed on the columnar portion 131. In addition, a source electrode 105 and a drain electrode 106 are formed on the substrate 101 on both sides of the columnar portion 131.

[0030] Furthermore, in this field-effect transistor, the source electrode 105 and the channel layer 102 exposed on the side wall (side surface) of the columnar portion 131 on the side of the source electrode 105 are electrically connected by a first contact layer 107. Similarly, the drain electrode 106 and the channel layer 102 exposed on the side wall of the columnar portion 131 on the side of the drain electrode 106 are electrically connected by a second contact layer 108.

[0031] A buffer layer 111 is formed on the substrate 101, and the buffer layer 111 has a convex portion 111a in the region of the columnar portion 131. A channel layer 102 and a barrier layer 103 are formed on the convex portion 111a of the buffer layer 111. A carrier supply layer 109 is formed on the barrier layer 103. A source electrode 105 and a drain electrode 106 are formed on the buffer layer 111 around (on both sides of) the convex portion 111a.

[0032] Furthermore, a cap layer 113 is formed on the barrier layer 103 via a first etching stop layer 112. A recess region 116 is also formed in the cap layer 113. In addition, an insulating layer 114 is formed covering the buffer layer 111, source electrode 105, drain electrode 106, and columnar portion 131. The portion of the insulating layer 114 above the cap layer 113 is formed by being installed on top of the recess region 116.

[0033] Furthermore, a gate opening 115 is formed in the insulating layer 114 that is installed over the recess region 116. The gate electrode 104 is formed on the columnar portion 131 and on the insulating layer 114 on the cap layer 113, with a portion of it fitting into the recess region 116 through the gate opening 115 and reaching the first etching stop layer 112. In this example, the gate electrode 104 is T-shaped in cross-section and has a leg portion that is short in the gate length direction and a head portion that is formed continuously above the leg portion and is longer in the gate length direction than the leg portion. The leg portion fits into the recess region 116 through the gate opening 115.

[0034] Furthermore, a source opening 115a and a drain opening 115b are formed in the insulating layer 114 that covers the source electrode 105 and drain electrode 106 around (both sides of) the convex portion 111a.

[0035] The substrate 101 can be made of, for example, semi-insulating InP. The buffer layer 111 can be made of, for example, InAlAs. The channel layer 102 can be made of, for example, undoped InAs, and its thickness can be 3 to 20 nm. Also, the channel layer 102 is In xGa １－ｘ It can be composed of As, InSb, and InP. Furthermore, the channel layer 102 can be composed of multiple layers having different compositions.

[0036] The barrier layer 103 can be made of, for example, InAlAs, and its thickness can be 5 to 20 nm. The carrier supply layer 109 can be made of, for example, well-known sheet doping, with Si as an impurity of 1 × 10⁻⁶. 19 cm -3 A doped layer (δ-doped layer) can be formed. The cap layer 113 can be made of, for example, InP, InAlAs, InGaAs, etc. The first etching stop layer 112 can be used as an etching stopper when forming a recess region 116 in the cap layer 113.

[0037] The first contact layer 107 and the second contact layer 108 can be made of InGaAs doped with a high concentration of n-type impurities. The gate electrode 104 can be, for example, a metal multilayer structure. This multilayer structure can be made mainly of Au, Pt, Ti, Mo, W, WSi, etc. The source electrode 105 and the drain electrode 106 can be made of metals such as Ni, Ti, Pt, Au, Mo, or composite layers thereof.

[0038] According to the field-effect transistor of Embodiment 1 with the structure described above, the gate electrode 104, the source electrode 105, and the drain electrode 106 can be physically separated compared to the conventional structure, C gs and C gd This can be reduced.

[0039] Furthermore, the first contact layer 107 and the second contact layer 108 provide resistance R s , R d This can be reduced. There are reports that the resistance between the source and drain is reduced to about one-third when comparing a structure with a first contact layer 107 and a second contact layer 108 to a conventional structure. A similar resistance reduction effect can be expected by appropriately forming the first contact layer 107 and the second contact layer 108.

[0040] Next, the method for manufacturing a field-effect transistor according to Embodiment 1 will be described with reference to Figures 2A to 2G.

[0041] First, as shown in Figure 2A, a buffer layer 111, a channel layer 102, a barrier layer 103, a carrier supply layer 109, a first etching stop layer 112, and a cap layer 113 are formed on the substrate 101 (first step). For example, the buffer layer 111, channel layer 102, barrier layer 103, first etching stop layer 112, and cap layer 113 are sequentially stacked on the substrate 101 by crystal growth using methods such as metal-organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE). In addition, a carrier supply layer 109 is formed on the barrier layer 103 by a well-known sheet doping method (δ doping).

[0042] Next, as shown in Figure 2B, a columnar portion 131 of the columnar structure is formed by patterning a portion of the buffer layer 111, the channel layer 102, the barrier layer 103, the first etching stop layer 112, and the cap layer 113 in the thickness direction (second step). For example, the columnar portion 131 can be formed by patterning using a mask pattern (not shown) corresponding to the columnar portion 131, using known wet etching or dry etching methods. For example, layers composed of InGaAs or InAlAs can be wet-etched using citric acid. Layers composed of InP can be wet-etched using a mixture of hydrochloric acid, phosphoric acid, and water.

[0043] Next, as shown in Figure 2C, a first contact layer 107 and a second contact layer 108 are formed on the substrate 101 (buffer layer 111) on both sides of the columnar portion 131. The first contact layer 107 and the second contact layer 108 are formed to connect to the channel layer 102 exposed on the side wall of the columnar portion 131. For example, using a selective growth mask (not shown), a high concentration of n-type impurities is introduced on the buffer layer 111 on both sides of the columnar portion 131. +-By regrowing InGaAs, the first contact layer 107 and the second contact layer 108 can be formed.

[0044] Next, by removing a portion of each of the first contact layer 107 and the second contact layer 108, a shape is formed that follows the side wall of the columnar portion 131 and extends over the buffer layers 111 on both sides of the columnar portion 131, as shown in Figure 2D (third step). For example, the patterning process described above can be performed by wet etching using citric acid using a mask pattern in which the area to be removed is open.

[0045] The first contact layer 107 and the second contact layer 108 may be regrowed to a thickness that reaches (contacts) the side surface of the cap layer 113. However, if the first contact layer 107 and the second contact layer 108 ultimately come into contact with the cap layer 113, the source electrode 105 and the drain electrode 106 will become conductive to the cap layer 113. In this state, the gate electrode 104 and the cap layer 113, the source electrode 105 and the drain electrode 106 will couple, leading to an increase in capacitance, so it is desirable to avoid this. For example, if the layers are regrowed to a thickness exceeding the thickness that reaches (contacts) the side surface of the cap layer 113, they are etched back to a predetermined height.

[0046] Next, as shown in Figure 2E, the source electrode 105 and the drain electrode 106 are formed (fourth step). The source electrode 105 is formed on the substrate 101 (buffer layer 111) on one side (side) of the columnar portion 131 via a first contact layer 107. The drain electrode 106 is formed on the substrate 101 (buffer layer 111) on the other side (side) of the columnar portion 131 via a second contact layer 108.

[0047] For example, a lift-off mask is formed with openings at the locations where each electrode is to be formed. Then, metals such as Ni, Ti, Pt, Au, and Mo are deposited on the formed lift-off mask by electroplating, electroless plating, vacuum deposition, etc., to form these metal layers or composite layers thereof. After this, the source electrode 105 and drain electrode 106 can be formed by removing (lifting off) the lift-off mask.

[0048] Next, as shown in Figure 2F, an insulating layer 114 is formed to cover the columnar portion 131. The insulating layer 114 can be made of SiO2 or SiN, or a composite layer of SiO2 and SiN. For example, the insulating layer 114 can be formed by depositing a predetermined insulating material using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or sputtering.

[0049] Furthermore, a gate opening 115, a source opening 115a, and a drain opening 115b are formed in the insulating layer 114. The gate opening 115, source opening 115a, and drain opening 115b can be formed by selectively etching away the insulating layer 114 using a resist mask pattern formed by a well-known photolithography technique. The source opening 115a and drain opening 115b are so-called contact holes.

[0050] The insulating layer 114 can be etched by dry etching using, for example, CF4, C2F6, or SF6. Alternatively, the insulating layer 114 can be etched by wet etching using HF. Furthermore, the insulating layer 114 can be etched by atomic layer etching (ALE). After forming each opening, the resist mask pattern is removed using, for example, an organic solvent.

[0051] Next, as shown in Figure 2G, a recess region 116 is formed in the cap layer 113. The recess region 116 is formed by applying a predetermined etchant to the cap layer 113 through a gate opening 115 formed in the insulating layer 114 and etching the cap layer 113 laterally. For example, if the cap layer 113 is made of InGaAs, InAlAs, or a composite layer thereof, a citrate-based etchant can be used. The length of the recess region 116 in the gate length direction (recess length) can typically be 50 to 500 nm.

[0052] The recess region 116 is a gap necessary for carriers to travel in the channel layer rather than the cap layer 113 in conventional field-effect transistors where the source electrode 105 and drain electrode 106 are formed on the cap layer 113. Therefore, it is not essential in the field-effect transistor according to this embodiment. It is known that various characteristics of high-frequency field-effect transistors are highly sensitive to the recess length. The recess region 116 can be formed to optimize the performance indicators of the field-effect transistor.

[0053] Next, as shown in Figure 1, a gate electrode 104 is formed on the columnar portion 131 (fifth step). The gate electrode 104 can be formed by a well-known lift-off method, which involves the fabrication of a lift-off mask, metal deposition, and removal of the lift-off mask. For metal deposition, electroplating, electroless plating, vacuum deposition, sputtering, etc., can be used. The metal material to be deposited can be Ni, Ti, Pt, Au, Mo, etc. Furthermore, a multilayer structure using multiple of these metals can be formed.

[0054] Next, using Figures 3A, 3B, and 3C, we will examine the capacity C. gs , C gd The reduction effect will be discussed. Note that the scales of Figures 3A, 3B, and 3C are not consistent.

[0055] Since the structure between each electrode is not a simple parallel plate or cylindrical shape, it is difficult to estimate analytically. Here, we will explain the approximate capacitance reduction effect by focusing on two aspects: the distance between the gate electrode and the source electrode, and the distance between the gate electrode and the cap layer, in the conventional structure and in Embodiment 1.

[0056] As shown in Figure 3A, the standard structure is as follows: a channel layer 202 and a barrier layer 203 are formed on a substrate 201 via a buffer layer 211; a carrier supply layer 209 is formed on the barrier layer 203; a cap layer 213, which functions as a contact layer, is formed on the barrier layer 203 via an etching stop layer 212; a recess region 216 is formed on the cap layer 213; and the configuration includes an insulating layer 214 and a gate electrode 204.

[0057] In the standard structure, the distance from the center of the gate electrode 204 to the source electrode 205 / drain electrode 206 is assumed to be 500 nm. This length is typically around 250 nm to 2.0 μm, and the gate-source distance and gate-drain distance may differ. For simplicity, a symmetrical structure with both the gate-source distance and gate-drain distance of 500 nm is considered here. Due to the symmetrical structure, only the source side of the standard structure is shown in Figure 3B, with various dimensions indicated. The width of the head portion of the gate electrode 204 is assumed to be 500 nm as a typical value, and bilateral symmetry is assumed. The thickness of the insulating layer 214 and the source electrode 205 are both assumed to be 100 nm as typical values. The recess length is assumed to be 100 nm as a typical value.

[0058] Figure 3C shows the dimensions of the structure in Embodiment 1, corresponding to the standard structure shown in Figures 3A and 3B. Assuming a symmetrical structure similar to the standard structure, only the source side is shown. The distance from the center of the gate electrode 104 to the first contact layer 107 is 500 nm, the width of the head portion of the gate electrode 104 is 500 nm, and the thickness of the hard mask for forming the gate electrode is 100 nm, which are the same as the standard structure. The distance from the left end of the columnar portion 131 to the right end of the source electrode 105 is 200 nm, and the distance from the lower end of the channel layer 102 to the upper end of the source electrode 105 is 100 nm. Also, as typical values, the thickness of the channel layer 102 is 10 nm, and the total thickness of the barrier layer 103, etch stop layer 112, and cap layer 113 is 40 nm.

[0059] From Figure 3B, the distance between the gate electrode and the source electrode (a) in the standard structure is 250 nm. Also, the distance between the gate electrode and the cap layer (b) is 100 nm. Since the cap layer 213 is electrically connected to the source electrode 205, parasitic capacitance is also generated between the gate electrode and the cap layer, C gs and C gd It becomes a component of [something].

[0060] In contrast, in Embodiment 1, as shown in Figure 3C, the distance (a) between the gate electrode and the source electrode is given by the following formula.

[0061]

[0062] Furthermore, the distance (b) between the gate electrode and the contact layer is given by the following formula.

[0063]

[0064] Compared to a standard structure, the distance between the gate electrode and source electrode is approximately 2.06 times greater, and the distance between the gate electrode and the cap layer (contact layer) is approximately 2.87 times greater. Although it is not a simple parallel-plate capacitor, assuming that the capacitance of each electrode is inversely proportional to the distance, the capacitance between the gate electrode and source electrode can be reduced by approximately 51%, and the capacitance between the gate electrode and the cap layer (contact layer) can be reduced by approximately 65%.

[0065] Again, it should be noted that these are rough estimates, as they are not simple parallel-plate capacitors. However, this structure allows the distance between coupling electrodes to be typically more than double that of a standard structure, so a significant reduction in capacitance can be expected.

[0066] [Embodiment 2] Next, a field-effect transistor according to Embodiment 2 will be described with reference to Figure 4. This field-effect transistor first has a columnar portion 131 on a substrate 101, and a channel layer 102 and a barrier layer 103 are formed on the columnar portion 131. A gate electrode 104 is also formed on the columnar portion 131. A source electrode 105 and a drain electrode 106 are formed on the substrate 101 on both sides of the columnar portion 131.

[0067] Furthermore, in this field-effect transistor, the source electrode 105 and the channel layer 102 exposed on the side wall (side surface) of the columnar portion 131 on the side of the source electrode 105 are electrically connected by a first contact layer 107. Similarly, the drain electrode 106 and the channel layer 102 exposed on the side wall of the columnar portion 131 on the side of the drain electrode 106 are electrically connected by a second contact layer 108.

[0068] A buffer layer 111 is formed on the substrate 101, and a convex portion 111b is provided in the region of the columnar portion 131. A channel layer 102 and a barrier layer 103 are formed on the convex portion 111b. A carrier supply layer 109 is formed on the barrier layer 103. A source electrode 105 and a drain electrode 106 are formed on the buffer layer 111 around (on both sides of) the convex portion 111b.

[0069] Furthermore, a cap layer 113 is formed on the barrier layer 103 via a first etching stop layer 112. A recess region 116 is also formed in the cap layer 113. In addition, an insulating layer 114 is formed covering the buffer layer 111, source electrode 105, drain electrode 106, and columnar portion 131. The portion of the insulating layer 114 above the cap layer 113 is formed by being installed on top of the recess region 116.

[0070] Furthermore, a gate opening 115 is formed in the insulating layer 114 that is installed over the recess region 116. The gate electrode 104 is formed on the columnar portion 131 and on the insulating layer 114 on the cap layer 113, with a portion of it fitting into the recess region 116 through the gate opening 115 and reaching the first etching stop layer 112. In this example, the gate electrode 104 is T-shaped in cross-section and has a leg portion that is short in the gate length direction and a head portion that is formed continuously above the leg portion and is longer in the gate length direction than the leg portion. The leg portion fits into the recess region 116 through the gate opening 115.

[0071] Furthermore, a source opening 115a and a drain opening 115b are formed in the insulating layer 114 that covers the source electrode 105 and drain electrode 106 around (both sides of) the convex portion 111b.

[0072] The configuration described above is the same as that of Embodiment 1 described above. In Embodiment 2, a second etching stop layer 117 is provided on the substrate 101 (buffer layer 111), and a convex portion 111b is formed on the second etching stop layer 117. The source electrode 105 and the drain electrode 106 are formed on the buffer layer 111 around (on both sides of) the convex portion 111b via the second etching stop layer 117.

[0073] In the first step described using Figure 2A, a buffer layer is formed on the substrate 101 to a certain extent, then a second etching stop layer 117 is formed, and another buffer layer is formed on the second etching stop layer 117. In the second step, the columnar portion 131 is formed by etching up to the second etching stop layer 117, thereby achieving the structure of Embodiment 2.

[0074] When the buffer layer is made of InAlAs, the second etching stop layer 117 can be made of InP, InAlP, InGaP, etc. Furthermore, multiple etching stop layers can be used. In this case, the etching depth of the buffer layer can be varied. For example, if a stacked structure of buffer layer 1 / etching stop layer 1 / buffer layer 2 / etching stop layer 2 / buffer layer 3 is formed in order from the substrate, in lot A, the etching of the buffer layer can be stopped at etching stop layer 2, and in lot B, etching stop layer 2 can be etched and stopped at etching stop layer 1. By comparing lot A and lot B, it is possible to examine how the various device characteristics change depending on the buffer layer etching depth.

[0075] [Embodiment 3] Next, a field-effect transistor according to Embodiment 3 will be described with reference to Figure 5A. This field-effect transistor first has a columnar portion 131 on a substrate 101, and a channel layer 102 and a barrier layer 103 are formed on the columnar portion 131. A gate electrode 104 is also formed on the columnar portion 131. A source electrode 105 and a drain electrode 106 are formed on the substrate 101 on both sides of the columnar portion 131.

[0076] Furthermore, in this field-effect transistor, the source electrode 105 and the channel layer 102 exposed on the side wall (side surface) of the columnar portion 131 on the side of the source electrode 105 are electrically connected by a first contact layer 107. Similarly, the drain electrode 106 and the channel layer 102 exposed on the side wall of the columnar portion 131 on the side of the drain electrode 106 are electrically connected by a second contact layer 108.

[0077] A buffer layer 111 is formed on the substrate 101, and the buffer layer 111 has a convex portion 111a in the region of the columnar portion 131. A channel layer 102 and a barrier layer 103 are formed on the convex portion 111a of the buffer layer 111. A carrier supply layer 109 is formed on the barrier layer 103. A source electrode 105 and a drain electrode 106 are formed on the buffer layer 111 around (on both sides of) the convex portion 111a.

[0078] Furthermore, a cap layer 113 is formed on the barrier layer 103 via a first etching stop layer 112. A recess region 116 is also formed in the cap layer 113. In addition, an insulating layer 114a is formed covering the buffer layer 111, source electrode 105, drain electrode 106, and columnar portion 131. The portion of the insulating layer 114a above the cap layer 113 is formed by being installed on top of the recess region 116.

[0079] Furthermore, a gate opening 115 is formed in the insulating layer 114a of the portion that is installed on top of the recess region 116. The gate electrode 104 is formed on the columnar portion 131 and on the insulating layer 114a on top of the cap layer 113, with a portion of it fitting into the recess region 116 through the gate opening 115 and reaching the first etching stop layer 112. In this example, the gate electrode 104 is T-shaped in cross-section and has legs that are short in the gate length direction and a head that is formed continuously on top of the legs and is longer in the gate length direction than the legs. The legs are fitted into the recess region 116 through the gate opening 115.

[0080] Furthermore, in Embodiment 3, the gate electrode 104 extends from the upper part of the columnar portion 131 to the region other than the columnar portion 131. The head of the gate electrode 104, which is T-shaped in cross-section, extends from the upper part of the columnar portion 131 to the region other than the columnar portion 131.

[0081] As shown in equations (2) and (3), f max Improvement and F min To reduce this, the gate resistor R g Reducing this is effective. To reduce gate resistance, it is effective to enlarge the head of the gate electrode, which is T-shaped in cross-section. However, this configuration shortens the physical distance between the source electrode and the drain electrode, so C gs , C gd There is a trade-off that this leads to an increase in [something]. Also, increasing the size of the gate electrode head impairs the mechanical stability of the gate electrode itself.

[0082] In Embodiment 3, source electrodes 105 and drain electrodes 106 are formed on both sides of the columnar portion 131, and the physical distance between the gate electrode 104 and the source electrodes 105 and drain electrodes 106 can be increased. Therefore, even if the head portion is made larger, C gs , C gd This can significantly mitigate the increase.

[0083] For example, by forming an insulating layer 114a with a thickness on both sides of the columnar portion 131 that is approximately the same as the columnar portion 131, the head of the gate electrode 104, which is T-shaped in cross-section, extends on the insulating layer 114a from the upper part of the columnar portion 131 to the area other than the columnar portion 131. This configuration ensures the mechanical stability of the extended portion. Furthermore, this configuration allows the extended portion to be made thicker.

[0084] Furthermore, using an insulating layer 114a that is thicker in the upper part of the cap layer 113 also has the effect of suppressing oblique deposition when forming the gate electrode 104 by vacuum deposition. Generally, in vacuum deposition, metal particles are deposited as they advance perpendicularly to the substrate. Some metal particles are incident on the substrate at an oblique angle. Therefore, as shown in Figure 5B, in the case of a thin insulating layer 114, the gate opening 115 is shallow, and the particles 141 that reach the first etching stop layer 112 spread out rather than being perpendicular to the arrival surface. As a result, the actual gate length L eff However, it is formed to be longer than the opening width of the gate opening 115.

[0085] On the other hand, as shown in Figure 5C, in the case of a thick insulating layer 114a, the gate opening 115c becomes deeper, and the particles 141 that reach the first etching stop layer 112 are limited to those that are almost perpendicular to the reaching surface. As a result, L eff This is approximately equal to the opening width of the gate opening 115c. In addition, in order to maximize the distance between the gate electrode 104 and the source electrode 105 and drain electrode 106, the lead-out position is formed away from the gate electrode 104.

[0086] Next, a method for manufacturing a field-effect transistor according to Embodiment 3 will be described. First, as explained with reference to Figures 2A to 2D, the first contact layer 107 and the second contact layer 108 are formed in a shape that extends along the side wall of the columnar portion 131 and onto the buffer layers 111 on both sides of the columnar portion 131. Then, as shown in Figure 6A, the source electrode 105 and the drain electrode 106 are formed by extending outward from the first contact layer 107 and the second contact layer 108.

[0087] Next, as shown in Figure 6B, an insulating layer 114a is formed covering the buffer layer 111, source electrode 105, drain electrode 106, and columnar portion 131. Furthermore, the insulating layer 114a is formed on both sides of the columnar portion 131 with a thickness similar to that of the columnar portion 131. Additionally, the insulating layer 114a on top of the cap layer 113 is made thicker. While the typical thickness of the insulating layer 114 can be around 50 nm to 200 nm, the thickness of the insulating layer 114a can be around 200 nm to 1 μm.

[0088] Next, as shown in Figure 6C, a gate opening 115c, a source opening 118a, and a drain opening 118b are formed in the insulating layer 114a. The gate opening 115c, source opening 118a, and drain opening 118b can be formed by selectively etching away the insulating layer 114 using a resist mask pattern formed by a well-known photolithography technique. Furthermore, a recess region 116 is formed in the cap layer 113. The recess region 116 is formed by applying a predetermined etchant to the cap layer 113 through the gate opening 115a formed in the insulating layer 114a and etching the cap layer 113 laterally.

[0089] Next, as shown in Figure 6D, the gate electrode 104, the source electrode lead-out portion 105a, and the drain electrode lead-out portion 106a are formed. The gate electrode 104 is formed so that the head portion extends beyond the columnar portion 131 in the channel length direction. The method of forming each electrode and the materials are the same as in Example 1.

[0090] [Embodiment 4] Next, Embodiment 4 will be described with reference to Figure 7. Note that Figure 7(b) shows a cross-section of line bb' in the plan view of Figure 7(a). In Embodiment 4, each of the two first regions 151 and second regions 152 arranged in the channel length direction is provided with a columnar portion 131, and the drain electrode 106 or source electrode 105 is common, and a gate electrode 104 is formed on each columnar portion 131. In this example, the drain electrode 106 is common. The configuration of the columnar portion 131 in each of the first region 151 and second region 152 is the same as in Embodiment 1 described above. A source electrode bud 121 is connected to the source electrode 105, and a drain electrode pad 122 is connected to the drain electrode 106. In addition, the gate electrodes 104 of the two regions have their respective head portions formed beyond the columnar portion 131 in the gate width direction and are connected to a common gate electrode pad 123.

[0091] Furthermore, as shown in Figure 8, a connecting portion 119 can be provided to connect the gate electrodes 104 formed on each columnar portion 131, so as to span between each columnar portion 131. Note that Figure 8(b) shows a cross-section of line bb' in the plan view of Figure 8(a). In this structure, the connecting portion 119 is positioned above the drain electrode 106, and a parallel plate capacitor is formed by these. gd This is generally not implemented because it would lead to an increase in C. In contrast, according to this embodiment, since the connecting portion 119 is formed above the columnar portion 131, the physical distance between the connecting portion 119 and the drain electrode 106 is increased, gd This structure can suppress the increase of C. gd While suppressing the increase of the gate resistance R g Because it can reduce f max Increase and F min A reduction in this can be expected.

[0092] As described above, according to the embodiment, since the source electrode and drain electrode are formed on the substrates on both sides of the columnar portion having the channel layer and barrier layer, the source resistance and drain resistance can be reduced, thereby reducing parasitic capacitance.

[0093] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be implemented within the technical concept of the present invention by those with ordinary skill in the art.

[0094] 101...Substrate, 102...Channel layer, 103...Barrier layer, 104...Gate electrode, 105...Source electrode, 106...Drain electrode, 107...First contact layer, 108...Second contact layer, 109...Carrier supply layer, 111...Buffer layer, 111a...Convex portion, 112...First etching stop layer, 113...Cap layer, 114...Insulating layer, 115...Gate opening, 115a...Source opening, 115b...Drain opening, 116...Recess region, 131...Columnar portion.

Claims

1. A field-effect transistor comprising: a columnar portion having a channel layer and a barrier layer formed on a substrate; a gate electrode formed on the columnar portion; a source electrode and a drain electrode formed on the substrate on both sides of the columnar portion; a first contact layer electrically connecting the source electrode and the channel layer exposed on the side wall of the columnar portion on the side of the source electrode; and a second contact layer electrically connecting the drain electrode and the channel layer exposed on the side wall of the columnar portion on the side of the drain electrode.

2. A field-effect transistor according to claim 1, wherein the gate electrode extends from the upper part of the columnar portion to a region other than the columnar portion.

3. A field-effect transistor according to claim 1 or 2, wherein each of two regions arranged in the channel length direction is provided with the columnar portion, the drain electrode or the source electrode is common, and the gate electrode is formed on each of the columnar portions.

4. A field-effect transistor according to claim 3, comprising a connecting portion for connecting the gate electrodes formed on each of the columnar portions so as to span between each of the columnar portions.

5. A method for manufacturing a field-effect transistor, comprising: a first step of forming a channel layer and a barrier layer formed on a substrate; a second step of forming a columnar portion of a columnar structure by patterning the channel layer and the barrier layer; a third step of forming a first contact layer and a second contact layer on the substrate on both sides of the columnar portion, connected to the channel layer exposed on the side walls of the columnar portion; a fourth step of forming a source electrode via the first contact layer and a drain electrode via the second contact layer on the substrate on both sides of the columnar portion; and a fifth step of forming a gate electrode on the columnar portion.

6. A method for manufacturing a field-effect transistor according to claim 5, wherein the first step is to form an etching stop layer on the substrate, then form the channel layer and the barrier layer, and the second step is to form the columnar portion by etching up to the etching stop layer.

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