Display device and electronic apparatus

Abstract

One of the purposes of the present invention is, for example, to improve the performance of a display device.　Provided is a display device having a plurality of pixels, wherein the time required for writing a pixel signal to be supplied to a pixel circuit constituting the pixel in a region where a viewer is not affected by a change in image quality is shorter than the time originally required for writing the pixel signal. The region is, for example, a peripheral region corresponding to the peripheral visual field of the viewer. The region may include, for example, a central region corresponding to the central visual field of the viewer.

Description

Display device and electronic device

[0001] The present technology relates to a display device and an electronic device.

[0002] The performance of display devices is being improved by increasing their resolution and frame rate (HFR). For example, in Patent Document 1 below, among the pixels arranged in a two-dimensional array in the first direction and the second direction intersecting the first direction, which are provided in a display device, the same image signal is supplied to two data lines corresponding to the first sub-pixels that emit the first light, which are provided in two pixels adjacent to each other in the first direction, thereby improving the frame rate.

[0003] International Publication No. 2023 / 062976

[0004] By the way, as technology development progresses, there is a continuing demand for improving the performance of display devices, such as increasing their resolution and frame rate.

[0005] One of the purposes of the present technology is, for example, to improve the performance of a display device.

[0006] The present technology is, for example, a display device having a plurality of pixels, and the time required to write a pixel signal supplied to a pixel circuit constituting the pixel in a region where a viewer is not affected by image quality changes is smaller than the original time required for writing the pixel signal.

[0007] The present technology is, for example, an electronic device having the display device of the present technology.

[0008] Figure 1 is an illustrative diagram of the settling time of the source amplifier. Figure 2 is an illustrative diagram of the characteristics of human vision. Figure 3 is an illustrative diagram of the overview of the present technology. Figure 4 is a diagram showing an example configuration of a display device according to the first embodiment of the present technology. Figure 5 is a diagram showing an example configuration of a pixel writing circuit. Figure 6 is an explanatory diagram of an example notation of a writing timing chart. Figure 7 is a diagram showing an example of operation of a display device according to an embodiment (Embodiment 1). Figure 8 is a diagram showing an example of operation of a display device according to another embodiment (Embodiment 2). Figure 9 is a diagram showing an advanced operation example in another embodiment (Embodiment 2). Figure 10A is a diagram showing an example of operation when the subpixels that are not written are changed for each pixel, Figure 10B is a diagram showing an example of operation when pixels that are thinned and pixels that are not thinned are inserted alternately, and Figure 10C is a diagram showing an example of operation when the same subpixel is not written for all pixels. Figure 11 is an explanatory diagram of a spatial application example (Application Example 1) of the embodiment. Figure 12 is an explanatory diagram of a spatial application example (Application Example 2) of the embodiment. Figure 13 is an explanatory diagram of a temporal application example (Application Example 1) of the embodiment. Figure 14 is an explanatory diagram of a temporal application example (Application Example 2) of the embodiment. Figure 15 is an explanatory diagram of a temporal application example (Application Example 3) of the embodiment. Figure 16 is an exemplary image diagram of the use of the display device according to the first embodiment. Figure 17 is a diagram showing an example of operation of the display device according to the second embodiment. Figure 18A is an explanatory diagram of the case where the signal voltage is uniformly corrected, and Figure 18B is an explanatory diagram of the case where the signal voltage to each subpixel is corrected individually. Figure 19 is a diagram showing an example of configuration when controlling the signal voltage. Figure 20 is a diagram showing an example of operation of the display device according to the third embodiment. Figure 21 is a diagram showing an example of operation of the display device according to the fourth embodiment. Figure 22 is a diagram showing an example of operation of the display device according to the fifth embodiment. Figure 23 is an explanatory diagram of a spatial application example in the fifth embodiment. Figure 24 is an explanatory diagram of a temporal application example in the fifth embodiment. Figure 25A is a graph showing an example of the output waveform of the source amplifier, and Figure 25B is a diagram showing a schematic example of the input side circuit of the source amplifier. Figure 26 is an explanatory diagram of application examples applicable to each embodiment. Figure 27 is a diagram showing an example of a source amplifier configuration.Figure 28A is a diagram showing an example of writing operation with an application example, and Figure 28B is an explanatory diagram of an example of signal voltage adjustment. Figure 29 is a diagram showing an example of horizontal driver configuration (Configuration Example 1). Figure 30 is a diagram showing an example of horizontal driver configuration (Configuration Example 2). Figure 31 is a diagram showing an example of vertical driver configuration (Configuration Example 1). Figure 32 is a diagram showing an example of vertical driver configuration (Configuration Example 2). Figure 33 is a diagram showing one example of pixel circuit configuration. Figure 34 is a diagram showing one example of pixel circuit configuration. Figure 35 is a diagram showing one example of pixel circuit configuration. Figure 36 is a diagram showing one example of pixel circuit configuration. Figure 37 is a diagram showing one example of pixel circuit configuration. Figure 38 is a diagram showing one example of pixel circuit configuration. Figure 39 is a diagram showing one example of pixel circuit configuration. Figure 40 is a diagram showing one example of pixel circuit configuration. Figure 41 is a diagram showing one example of pixel circuit configuration. Figure 42 is a diagram showing one example of pixel circuit configuration. Figure 43 is a perspective view showing an example of the appearance of a head-mounted display. Figure 44 is a perspective view showing an example of the appearance of another head-mounted display. Figure 45A is a front view showing an example of the external appearance of a digital still camera. Figure 45B is a rear view showing an example of the external appearance of a digital still camera. Figure 46 is a perspective view showing an example of the external appearance of a television system. Figure 47 is a perspective view showing an example of the external appearance of a smartphone. Figure 48A is a diagram showing an example of the interior of a vehicle from the rear to the front. Figure 48B is a diagram showing an example of the interior of a vehicle from the diagonal rear to the diagonal front.

[0009] The embodiments of this technology will be described below with reference to the drawings. The description will be given in the following order. In this specification and the drawings, components having substantially the same function or configuration will be denoted by the same reference numerals, and redundant explanations will be omitted as appropriate. In addition, the shape, size, positional relationship, etc. of the components shown in each drawing may be exaggerated depending on the content of the explanation, and reference numerals may be omitted to avoid complexity in the illustrations. <1. Overview of the embodiments of this technology> <2. First embodiment> <3. Second embodiment> <4. Third embodiment> <5. Fourth embodiment> <6. Fifth embodiment> <7. Application examples of each embodiment> <8. Example of horizontal driver / vertical driver configuration> <9. Example of pixel circuit configuration> <10. Modified examples> <11. Application examples>

[0010] <1. Overview of Embodiments of This Technology> Progress is being made in reducing the power consumption of display devices and improving their performance through higher resolution and higher frame rates (HFR). When considering higher resolution and higher frame rates for display devices, it is necessary to consider the settling time in the amplifier used to generate the pixel signal written to the pixels (hereinafter referred to as the source amplifier as appropriate), that is, the time required for the output to stabilize.

[0011] Figure 1 is an illustrative diagram illustrating the settling time of a source amplifier. As shown in Figure 1, for example, suppose a display with a frame rate of 120 Hz uses a source amplifier that requires 5 μs (microseconds) to settle. In this case, for a display with 1200 lines, one horizontal period (1H) is approximately 8.3 / 1200 = 6.9 μs, so there is no shortage of settling time.

[0012] However, if the number of lines is increased to 2000 under the same conditions to achieve higher resolution, the time per hour becomes approximately 8.3 / 2000 = 4.15 μs, resulting in insufficient settling time for the pixels to settle. A similar problem can arise when increasing the frame rate. Thus, as resolution and frame rate are increased, it becomes difficult to allow pixel settling within the time of one horizontal period. In other words, it becomes impossible to secure the time required for optimal writing to the pixels. Therefore, with conventional display device technology, the time constraints of one horizontal period have limited the ability to increase resolution and frame rate, hindering performance improvements. On the other hand, as mentioned above, low power consumption is also desired for display devices.

[0013] Incidentally, human vision has the following characteristics. Figure 2 is an illustrative diagram of the characteristics of the human visual field. Specifically, Figure 2 shows how a paper cup placed on a table appears when a viewer is fixated on it. The human visual field can be divided into the central visual field and the peripheral visual field. The central visual field is the area that is clearly visible (for example, the paper cup in Figure 2), and the peripheral visual field is the area that is blurred (for example, the area outside the paper cup in Figure 2). The central visual field is the area of ​​vision in the vicinity of the viewer's point of fixation (including the point of fixation), and the peripheral visual field is the area of ​​vision outside the vicinity of that point of fixation. Specifically, the central visual field is within a predetermined angle range (for example, about ±10°) at the center of the human visual field, and the peripheral visual field is outside of that.

[0014] Thus, human vision decreases in accuracy as it moves away from the point of focus, and peripheral vision has lower resolution and weaker color discrimination compared to central vision. However, peripheral vision is sensitive to changes in brightness. Therefore, for the peripheral area of ​​the display corresponding to peripheral vision, it is sufficient to focus strongly on suppressing brightness changes compared to the central area corresponding to central vision, and color and resolution can be somewhat neglected. In this way, the peripheral area can be said to be an area where the viewer is not affected by changes in image quality. In this embodiment of the technology, we propose a technology that can achieve high performance through lower power consumption, higher resolution, and higher frame rates, while also reducing power consumption.

[0015] Figure 3 is an illustrative diagram illustrating the overview of this technology. Figure 3 shows the relationship between the image of the display area (display region) of the display device, the image of the reduction in the time of one horizontal period in the peripheral region, and the resulting increase in the settling time of the central region. In the illustrated example, as shown by the dark-colored fill, the line region (region in units of lines) including the central part of the display area is set as the central region, and as shown by the light-colored fill, the line regions on both sides (upper and lower) of the central region are set as peripheral regions.

[0016] Previously, without distinguishing between the central and peripheral regions, sufficient writing time (e.g., settling time) was uniformly ensured within one horizontal period. As a result, as shown in the comparative technique, the time required to write to a pixel in one vertical period (1V) was the same for both the peripheral and central regions.

[0017] In contrast, in the first to fourth embodiments of this technology, the time for one horizontal period in the peripheral region is intentionally shortened compared to the time corresponding to the original writing in the comparative technology described above. As a result, even with the same one vertical period, the time required for writing in the central region can be increased by the amount that the vertical period has been shortened. In other words, by reducing the time required for writing in the peripheral region compared to normal, the time required for writing in the central region can be increased accordingly, thereby achieving higher resolution and higher frame rates. In the fifth embodiment of this technology, the time for one horizontal period is intentionally shortened compared to normal not only in the peripheral region but also in the central region under predetermined conditions. The following describes each embodiment in detail.

[0018] <2. First Embodiment> [2-1. Example of Display Device Configuration] Figure 4 is a diagram showing an example of the configuration of the display device 1 according to the first embodiment of this technology. Note that Figure 4 mainly shows an example of the configuration of the characteristic parts of this technology, and the display device 1 may also include other configurations not shown. The display device 1 is a device that displays various information such as images using light-emitting elements. The light-emitting elements are, for example, LEDs (Light Emitting Diodes). LEDs include LEDs used in micro-LED displays and OLEDs (Organic Light Emitting Diodes) used in organic EL (Electro-Luminescence) displays. Hereinafter, the display device 1 will be described assuming that OLEDs are used as light-emitting elements. The display device 1 is, for example, a display mounted on an electronic device. Specific examples of electronic devices to which the display device 1 can be applied will be described later.

[0019] As shown in Figure 4, the display device 1 is used in connection with, for example, an external device 101. The external device 101 is composed of, for example, an information processing device having a processor. The external device 101 has a storage unit 102 and a transmission unit 103, and transmits various information stored in the storage unit 102 to the display device 1 via the transmission unit 103. This various information includes gaze information and pixel data.

[0020] Eye-line information is, for example, information that identifies the central region in the display device 1 (e.g., coordinate data). Eye-line information is generated, for example, based on the gaze point of a viewer who is viewing the display area of ​​the display device 1. The viewer's gaze point can be acquired, for example, by eye-tracking technology using a sensor. Eye-line information represents, for example, a predetermined angle (e.g., ±20°) within the center of the viewer's field of view. For example, this predetermined angle is changeable and can be adjusted to the optimal range.

[0021] Pixel data is the original data of the pixel signal representing the gradation level (for example, 8-bit gradation) of the luminescence intensity corresponding to the display image of each pixel circuit (specifically, the light-emitting element). The display device 1 receives various information transmitted from the external device 101 and displays an image based on the received information.

[0022] The display device 1 includes a display controller 2, a display panel 3, and a vertical driver (V driver) 4 as circuit blocks related to writing to pixels. The display controller 2 is a control unit that controls various operations in the display device 1 and includes a receiving unit 5, a writing control unit 6, and a source amplifier unit 7. The display panel 3 includes an amplifier switch unit 8 and a pixel unit 9.

[0023] The receiving unit 5 receives and acquires various information transmitted from the transmitting unit 103 of the external device 101. Communication between the external device 101 and the display device 1 can be either wired or wireless. The acquisition of various information is not limited to receiving information transmitted from the external device 101; for example, the display device 1 may generate all or part of the information internally. The receiving unit 5 then outputs the acquired information to the writing control unit 6.

[0024] The write control unit 6 controls the operation of the amplifier switch unit 8 via the vertical driver 4. The write control unit 6 performs various signal processing related to display by the display area using various information input from the receiving unit 5. These various signal processing include a correction process that corrects pixel data according to predetermined display settings, and a peripheral area information generation process that generates peripheral area information representing the peripheral area described above. The peripheral area information is generated using the gaze information received by the receiving unit 5. For example, the central area in the display device 1 is set from the central area identified by the gaze information, and the area outside the set central area is set as the peripheral area. The central area and peripheral area in the display device 1 are set, for example, on a line-by-line basis.

[0025] The method for setting the central and peripheral regions in the display device 1 is not limited to a specific method and can be selected as appropriate. For example, as described here, it is not limited to a dynamic setting that identifies the area the viewer is actually fixating on and sets each region based on that, but may also be a static setting that sets each region on the premise that the viewer's point of fixation is at a predetermined position in the display area (e.g., the center). In the case of a static setting, the peripheral region may be set at all times, or it may be set as needed, such as when the viewer is thought to be fixating on it. In the case of a static setting, since each region only needs to be set in advance, there is no need to use gaze information and resources can be reduced. The central region may be the area containing a specific object displayed in the display area (e.g., a character that is thought to be fixed on), and the other parts may be set as the peripheral region.

[0026] The write control unit 6 outputs the corrected pixel data and the generated peripheral area information to the source amplifier unit 7. The write control unit 6 also generates a vertical driver control signal for the amplifier switch and outputs it to the vertical driver 4. This vertical driver control signal is generated according to a predetermined display setting. The write control unit 6 uses the peripheral area information to determine whether it is writing to the central area or the peripheral area. If it is determined to be writing to the central area, it generates a vertical driver control signal using normal drive; if it is determined to be writing to the peripheral area, it generates a vertical driver control signal using peripheral area drive, which is simpler than normal drive. In other words, the write control unit 6 generates different vertical driver control signals for the amplifier switch depending on whether it is writing signals to the central area or the peripheral area.

[0027] The source amplifier section 7 has multiple source amplifiers, and the amplifier switch section 8 has an amplifier switch circuit corresponding to each source amplifier. These source amplifiers and corresponding amplifier switch circuits constitute a pixel writing circuit that writes signals to pixels.

[0028] The source amplifier section 7 and the amplifier switch section 8 are included, for example, in the horizontal driver (H driver) of the display device 1. The horizontal driver is also called the source driver. The horizontal driver receives various signals from the write control section 6, generates pixel signals based on the received signals, and supplies the generated pixel signals to the pixel section 9 via the signal lines by writing them to the signal lines.

[0029] The configuration of the horizontal driver is not limited to a specific one. For example, it may be configured as a voltage follower type circuit having a voltage follower circuit at the output section to the signal line, or as a RAMPDAC type circuit that uses an analog signal of a ramp waveform to generate the pixel signal output to the signal line. In the following description of the embodiment, the display device 1 will be described as having a voltage follower type horizontal driver. Examples of the configuration of the pixel writing circuit and the horizontal driver will be described later.

[0030] The pixel unit 9, although not shown in the diagram here, has multiple pixels arranged in a matrix and forms a display area. Note that the pixel arrangement does not have to be a matrix. Specifically, the pixels only need to be arranged along a first direction and a second direction intersecting the first direction. Here, the first direction is the row direction and the second direction is the column direction. Each pixel is composed of, for example, three types of subpixels (hereinafter referred to as subpixels as appropriate) representing the three primary colors R (red), G (green), and B (blue), respectively, and represents a color image. Note that the configuration of the pixels in the pixel unit 9 is not limited to a specific one. Specific examples of pixel arrangements, configurations, and operations will be described later.

[0031] Furthermore, the pixel unit 9 has signal lines for each sub-pixel extending along the column direction of the pixel array, and control lines for each sub-pixel extending along the row direction of the pixel array. The signal lines are connected to the output terminal of the corresponding column of the horizontal driver and to the sub-pixel group of the corresponding column, respectively. The control lines are connected to the output terminal of the corresponding row of the vertical driver 4 and to the sub-pixel group of the corresponding row, respectively. A pixel signal is supplied to each signal line. A control signal is supplied to each control line. Note that the types of signal lines and control lines are not limited to specific types, but are changed as appropriate according to the configuration of the pixels in the pixel unit 9.

[0032] The vertical driver 4, although not shown in the diagrams here, generates a control signal for the pixel based on the vertical driver control signal for the pixel supplied from the display controller 2 and outputs it to the pixel unit 9. The configuration of the vertical driver 4 is not limited to a specific one; for example, it may be a shift register type circuit having a shift register circuit in the signal input section, or an address decoder type circuit having an address decoder in the signal input section. Specific configuration examples and operation examples of the vertical driver 4 that drives the pixel unit 9 will be described later.

[0033] Furthermore, the vertical driver 4 changes the time it takes to write signals to the pixel unit 9 by changing the timing of the operation of the amplifier switch circuit in the amplifier switch unit 8. Specifically, the vertical driver 4 generates an amplifier switch control signal based on the vertical driver control signal for the amplifier switch input from the write control unit 6, similar to when driving the pixel unit 9, and outputs the generated amplifier switch control signal to the amplifier switch circuit of the amplifier switch unit 8 to control the operation of the amplifier switch circuit.

[0034] [2-2. Example of Pixel Writing Circuit Configuration] Figure 5 shows an example of the configuration of a pixel writing circuit. Multiple pixel writing circuits are provided along the row direction. Each pixel writing circuit has a source amplifier 7a and an amplifier switch circuit 8a. The source amplifier 7a outputs a pixel signal to be written to a subpixel (more specifically, the pixel circuit of the subpixel), and for example, it constitutes a voltage follower circuit using an operational amplifier. In this way, the pixel signal is generated based on the output of the source amplifier 7a. In other words, the pixel signal is a signal based on the output of the source amplifier 7a. The example shown in Figure 5 shows a case where one source amplifier 7a drives two pixels (six subpixels) in the row direction. In this embodiment, one pixel is composed of three types of subpixels corresponding to the three RGB colors.

[0035] The amplifier switch circuit 8a has six switches SW1 to SW6 corresponding to two pixels. Each of the switches SW1 to SW6 switches the state of writing the pixel signal to the corresponding pixel circuit to either an ON state where the pixel signal is supplied to the pixel circuit or an OFF state where the pixel signal is not supplied to the pixel circuit. The display device 1 controls the writing of the pixel signal to each pixel circuit by controlling these switches SW1 to SW6. The switches SW1 to SW6 are made up of, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). These MOSFETs can be P-type or N-type. Note that the configuration of switches SW1 to SW6 is not limited to these, and they may be made up of other switching elements.

[0036] The output of source amplifier 7a is connected to one end of each of switches SW1 to SW6 (for example, one of the source and drain of a P-type MOSFET, or the other of the source and drain of an N-type MOSFET). The other ends of switches SW1 to SW6 (for example, the other of the source and drain of a P-type MOSFET, or one of the source and drain of an N-type MOSFET) are each connected to signal line SGL. Specifically, the other ends of switches SW1 to SW6 are each connected to one end of signal line SGL(1) to (6).

[0037] The control terminal (for example, the gate of a MOSFET) that controls the on / off state of switch SW1 (controlling whether it is in a conductive or non-conductive state) is connected to the amplifier switch control line SWL(1). Similarly, the control terminals of switches SW2 to SW6 are connected to amplifier switch control lines SWL(2) to SWL(6), respectively. Note that amplifier switch control lines SWL(1) to (6) are all commonly connected to the gates of switches SW1 to SW6 in each amplifier switch circuit 8a. Amplifier switch control signals ASW1 to ASW6 are supplied from the vertical driver 4 to amplifier switch control lines SWL(1) to (6), respectively, to control the on / off state. In the illustrated example, switch SW1 is in the ON state and switches SW2 to SW6 are in the OFF state.

[0038] The other end of signal line SGL(1) is connected to each of the pixel circuits (cells) of the first G subpixel (G1 subpixel) along the column direction. The other end of signal line SGL(2) is connected to each of the pixel circuits of the first R subpixel (R1 subpixel) along the column direction. The other end of signal line SGL(3) is connected to each of the pixel circuits of the first B subpixel (B1 subpixel) along the column direction. The other end of signal line SGL(4) is connected to each of the pixel circuits of the second G subpixel (G2 subpixel) along the column direction. The other end of signal line SGL(5) is connected to each of the pixel circuits of the second R subpixel (R2 subpixel) along the column direction. The other end of signal line SGL(6) is connected to each of the pixel circuits of the second B subpixel (B2 subpixel) along the column direction.

[0039] In this configuration example, the vertical driver 4 controlled by the write control unit 6 controls the amplifier switch unit 8 to write the pixel signal to each subpixel. Specifically, the amplifier switch circuit 8a selects the subpixel to be written to. This technology can be used regardless of the number of SELs (number of output destinations selected by one source amplifier 7a) of the amplifier switch control signal ASW. The pixel writing circuit shown in Figure 5 is merely an example, and other configurations can also be applied.

[0040] [2-3. Explanation of Write Timing Chart and Pixel Arrangement] Figure 6 is an explanatory diagram of an example of the notation for the write timing chart in the configuration example shown in Figure 5. In this figure and subsequent time charts, switches SW1 to SW6 are assumed to be N-type MOSFETs. Therefore, for example, switch SW1 is ON when the amplifier switch control signal ASW1, which is the gate signal, is high level, and OFF when it is low level. In other words, when it is ON (closed), writing is performed to the pixel, and when it is OFF (open), writing is not performed to the pixel. The symbols R, G, and B are used to indicate whether it is an RGB subpixel. Note that the symbols R, G, and B may be omitted for illustrative purposes.

[0041] In this configuration example, since one source amplifier 7a writes to six subpixels, under normal operation, one subpixel at a time is written sequentially, as shown in the figure. In Figure 6, the color differences of each RGB subpixel are represented by differences in shade. The same applies to the subpixels shown in subsequent figures. The illustrated example shows writing in the order GRBGRB (G1, R1, B1, G2, R2, B2), but this technology can be used regardless of the writing order.

[0042] This technology can be used regardless of the pixel configuration. For example, as shown in the figure, the sub-pixels may be arranged in a stripe pattern or in a delta pattern. In addition, it can also be applied to cases where a W (white) sub-pixel is added as a sub-pixel constituting a pixel, or where an infrared laser light IR is added. Hereinafter, an example will be described using a delta array in which three types of RGB sub-pixels are arranged in a delta pattern.

[0043] In this embodiment, the time required for writing in the peripheral area is reduced in terms of sub-pixels. The time required for this writing, for example, in the case of writing the first data (1st data) in FIG. 6, includes the writing time for controlling the switch SW1 to the on state and the switching time (waiting time shown in the figure) for controlling the switch SW1 to the off state. The switching time is the buffer margin time required between consecutive writing operations of pixel signals (for example, between writing the first data and writing the second data). That is, the switching time is the time required for switching to the optimal writing destination. Specifically, in Example 1 below, the writing time is shortened, and in Example 2, writing is not performed. Thereby, the setting time during the operation of the peripheral area is reduced, and the time required for writing in one horizontal period is shortened.

[0044] [2-4. Example 1] FIG. 7 is a diagram showing an operation example of the display device 1 according to the example (Example 1). The upper part of FIG. 7 shows an operation example of writing in normal driving (comparative example), and the lower part of FIG. 7 shows an operation example of writing in the peripheral area according to Example 1. Normal driving is driving based on the time required for the original writing required for writing pixel signals. Specifically, normal driving is driving based on the writing time required to write the gradation that takes the most time for setting. In FIG. 7, the difference in the color tone of each sub-pixel (a slight difference in color) between the case of operating in the comparative example and the case of operating in Example 1 is represented by a subtle difference in shading. The same applies to the following figures.

[0045] In the comparative example of writing operation, the writing time for each subpixel is set to the same amount of time to ensure settling time, in order to optimize the signal written to each RGB subpixel. In other words, under normal operation, the amplifier switch control signals ASW1 to ASW6, which control writing to each subpixel, are all at the same high level for the same amount of time, and all pixels are written to on a subpixel-by-subpixel basis with the same writing time.

[0046] In contrast, the writing operation of Embodiment 1 shortens the writing time of some subpixels (one or more subpixels) among the RGB in the peripheral region to a shorter duration than the normally required writing time (normal driving writing time), thereby creating a gradient. In the illustrated example, the writing time of the B subpixels (B1, B2) is shortened by the amplifier switch control signals ASW3 and ASW6, but the subpixels to be shortened are not limited to these and can be selected as appropriate. For example, the writing time of the B1 and R2 subpixels may be shortened, or the writing time of all cells may be shortened.

[0047] As shown in the figure, the process can be simplified by shortening the time the switch is on for each type of subpixel, i.e., the writing time, such as shortening the writing time for the B subpixel (B1, B2). Alternatively, the time the switch is on for multiple types of subpixels can be shortened uniformly, such as shortening the writing time for all RGB subpixels. In this case, the reduction in the length of one horizontal period can be increased efficiently without complicating the process. As shown in the figure, it is preferable that the writing times of the subpixels to be shortened be the same length from the viewpoint of efficiency, but they may be different. Thus, in this embodiment, although the color of the shortened subpixels may change slightly by shortening the writing time, the length of one horizontal period in the surrounding area can be shortened by the same amount.

[0048] [2-5. Example 2] FIG. 8 is a diagram showing an operation example of the display device 1 according to another example (Example 2). The upper part of FIG. 8 shows an operation example of writing in normal driving (comparative example), and the lower part of FIG. 8 shows an operation example of writing in the peripheral area according to Example 2. In FIG. 8, sub-pixels that do not perform writing are represented by diagonal hatching. The same applies to the sub-pixels in the subsequent figures.

[0049] In the writing operation according to the comparative example, writing is performed on all of the RGB sub-pixels, whereas in Example 2, writing is intentionally not performed on some of the RGB sub-pixels (one or more sub-pixels) in the peripheral area. That is, a switch that is to be in an on state in the original writing is turned off. In the illustrated example, the case where the B (B1 and B2) sub-pixels are not written is exemplified, but the sub-pixels that are not written are not limited to this, and may be appropriately selected. For example, it is also possible to not write all of them. That is, in this embodiment, a switch that is originally to be in an on state corresponding to one or more sub-pixels that do not perform this writing is turned off. Thereby, various writing modes are possible.

[0050] Thus, in this embodiment, by not writing to some subpixels, the duration of one horizontal period in the peripheral region can be shortened by the amount that was not written to. Note that when writing is not performed in this way, the data from the previous write is retained within the pixel circuit (e.g., in the retention capacitor). To avoid undesirable light emission resulting from this, as an advanced example of operation, the light emission of the pixel circuit of the subpixel that is not written to may be appropriately controlled. In other words, the light emission of the pixel circuit that does not write the pixel signal may be controlled in accordance with the change in brightness due to not writing. This can suppress changes in brightness in the peripheral region. For example, as described below, the pixel circuit of the subpixel corresponding to the switch that is turned off to prevent writing (in other words, the pixel circuit that does not write the pixel signal) may be extinguished. Note that this light emission control is not limited to any specific method, as long as it can suppress changes in brightness. Light emission control may be performed by, for example, extinguishing, changing the duty cycle, or changing the dynamic range (e.g., increasing brightness due to an expansion of the dynamic range). For example, light emission control by duty cycle changes suppresses brightness changes by changing the light emission duty cycle of the pixel circuit (specifically, the light-emitting element) in accordance with the brightness changes described above, while light emission control by dynamic range changes suppresses brightness changes by changing the dynamic range in accordance with the brightness changes described above.

[0051] Figure 9 shows an example of advanced operation in another embodiment (Embodiment 2). In Figure 9, subpixels that are not written to and are extinguished are indicated by a mesh hatch. In the illustrated example, the RGBB (R1, G1, G2, B2) subpixels are written to in order, and the BR (B1, R2) subpixels that are not written to are extinguished.

[0052] The extinguishing of subpixels is controlled, for example, by a control signal supplied from the vertical driver 4 to the pixel unit 9. Specifically, the extinguishing control is performed as appropriate according to the configuration and operation of the pixel circuit (specific examples will be described later). It is also possible to extinguish only a portion of the subpixels that are not written to. In this applied example, the undesirable light emission described above can be avoided by extinguishing the subpixels that are not written to. Furthermore, it can be used, for example, as a so-called PenTile display, where subpixels of a specific color are thinned out compared to subpixels of other colors. This applied example can also be applied when shortening the writing time of the above-described embodiment 1.

[0053] [2-6. Application Examples of the Embodiments] Figure 10 shows a specific application example of another embodiment (Embodiment 2). Here, we will explain an application example where some of the subpixels are not written (where the subpixels to be written are reduced), referring to Figure 10, but the same can be applied when shortening the writing time (as in Example 1). Furthermore, Example 1 and Example 2 may be applied in combination.

[0054] Figure 10A shows an example of operation when the subpixels that are not written to are changed for each pixel. In this example, the type of subpixel that is not written is changed for adjacent pixels in the row and column directions. In the illustrated example, pixels that are not written to as R subpixels and pixels that are not written to as B subpixels are alternately swapped one pixel at a time in the row and column directions. Note that this swapping is not limited to one pixel at a time; for example, it could be two pixels at a time, and it does not have to be regular. Furthermore, the patterns in the row and column directions may be different, or only the row direction may be swapped. If it is regular, the change in image quality can be distributed on average and made less noticeable. Note that the subpixels to be swapped as described above are not limited to two types such as R and B, but may be three or more types.

[0055] Figure 10B shows an example of operation when pixels to be thinned and pixels that are not thinned are inserted alternately. In this example, in both the row and column directions, pixels that have subpixels that are not written to (thinned pixels) and pixels that do not have subpixels that are not written to and to which all RGB is written (non-thinned pixels) are positioned alternately. In the illustrated example, in both the row and column directions, pixels that do not write to the B subpixel and pixels that do not write to the R subpixel are alternately swapped, and non-thinned pixels are positioned between pixels that have B subpixels that are not written to and pixels that have R subpixels that are not written to. Note that the alternation of pixels to be thinned and non-thinned is not limited to one pixel at a time; for example, it could be two pixels at a time, and it does not have to be regular. Furthermore, it may differ between the row and column directions, or only in the row direction. If it is regular, the change in image quality can be distributed on average and made less noticeable. Also, the subpixels that are not written to are not limited to those shown in the illustration.

[0056] Figure 10C shows examples of operation when the same subpixel is not written to all pixels in the surrounding area. For example, the upper figure shows an example where only the G subpixel is written to all pixels in the surrounding area (the B and R subpixels are not written). The lower left figure shows an example where only the G and B subpixels are written (the R subpixel is not written). The lower right figure shows an example where only the G and R subpixels are written (the B subpixel is not written).

[0057] It should be noted that the application examples described above are merely illustrative and do not exclude other application examples. For example, as mentioned above, it is also possible to not write any of the RGB subpixels, including the case where none of the RGB subpixels are written, or to not write the G subpixel, which is more noticeable than the RG subpixel, and various combinations are possible. Furthermore, as mentioned above, extinction control may be appropriately applied to the subpixels that are not written to.

[0058] [2-7. Spatial Application Examples] (Spatial Application Example 1) Figure 11 is an explanatory diagram of a spatial application example (Application Example 1) of the embodiment. As shown in the figure, the method of lighting subpixels may be changed in the spatial direction. In other words, the operation to reduce the time required to write the pixel signal may be changed in the spatial direction of the display area. This makes the change in image quality in the peripheral area less noticeable. Specifically, multiple decimation areas are set by dividing the peripheral area in stages according to the distance from the central area. The central area is driven normally, and the decimation method is set so that the decimation increases as the distance from the central area increases for the peripheral area (for example, the change in image quality becomes larger compared to normal driving).

[0059] For example, as shown in the figure, in decimation region A, which is close to the central region, the settling decimation (e.g., the amount of reduction in the settling time per horizontal period) is reduced by performing the operation shown in Figure 10A, while in decimation region B, which is far from the central region, the settling decimation is increased compared to decimation region A by performing the operation shown in the upper part of Figure 10C. Furthermore, as shown in the figure, if there are multiple decimation regions, it is preferable to uniformly shorten the time of one horizontal period in each region. This simplifies the process.

[0060] The method of thinning each thinning region is not limited to that shown in the figure. Also, the number of divisions of the surrounding region may be two or more. Furthermore, although Figure 11 illustrates the case where the operation example of Embodiment 2 described above is applied, it is not limited to this, and the operation may also be the operation using the operation example of Embodiment 1, or an operation using both Embodiment 1 and Embodiment 2.

[0061] (Spatial Application Example 2) Figure 12 is an explanatory diagram of a spatial application example (Application Example 2) of the embodiment. As shown in the figure, the method of lighting subpixels may be changed in the spatial direction. Specifically, the method of light emission is alternately changed by changing the decimation method on a line-by-line basis in the peripheral area. In the illustrated example, R subpixels are not written on odd-numbered lines and B subpixels are not written on even-numbered lines, so the decimation method is alternately changed for each line. This makes the change in color in the peripheral area less noticeable.

[0062] Furthermore, the unit in which the thinning method is changed is not limited to every line; for example, it may be changed every two lines or every other line, and the change does not have to be regular as long as it is done on a line-by-line basis. If it is done regularly, the changes in image quality can be distributed on average and made less noticeable. In addition, the types of thinning are not limited to two, but may be three or more. Moreover, the subpixels to be thinned are not limited to those shown in the figure. Figure 12 illustrates the case where the operation example of Embodiment 2 described above is applied, but it is not limited to this, and the operation may also be the operation example of Embodiment 1, or an operation which applies both Embodiment 1 and Embodiment 2.

[0063] [2-8. Temporal Application Examples] The temporal application examples described below involve changing the lighting method of subpixels in the time direction. In other words, the operation to reduce the time required to write the pixel signal is changed in the time direction. This makes it possible to adjust the image quality changes in the peripheral areas over time. Note that the following temporal application examples illustrate the case where Example 2 (an example in which some subpixels in the peripheral areas are not written) is applied, but Example 1 (an example in which the writing time of some subpixels in the peripheral areas is shortened) may also be applied, or a combination of Example 1 and Example 2 may be applied.

[0064] (Temporal Application Example 1) Figure 13 is an explanatory diagram of a temporal application example (Application Example 1) of the embodiment. If settling decimation is performed on the peripheral area immediately after the central area changes, the viewer may notice the change in image quality. Therefore, in this application example, the settling decimation operation on the peripheral area is performed after waiting for a certain number of frames. In addition, the settling decimation of pixels that have been in the decimation area for a relatively long period of time is made more severe as time progresses.

[0065] For example, in the example shown in Figure 13, if the frame at the time of change in the central region is set to frame zero (0F), then settling decimation of the surrounding region begins at frame n (where n is a natural number) after an appropriate amount of time has elapsed. For example, this decimation is assumed to be small. In the illustrated example, normal operation is performed without settling decimation from frame 0 to (n-1), and then a relatively small decimation as shown in Figure 10A is performed from frame n onwards.

[0066] Then, at (n+m) frames (where m is a natural number), after an appropriate time has elapsed since n frames, the decimation is changed to a larger settling decimation. In the illustrated example, from (n+m) frames onward, a larger decimation is performed as shown in the lower left figure of Figure 10C, than the decimation shown in Figure 10A. Then, at (n+m+l) frames (where l is a natural number), after an even more appropriate time has elapsed, the decimation is changed to an extra-large settling decimation. In the illustrated example, from (n+m+l) frames onward, a larger decimation is performed as shown in the upper figure of Figure 10C, than the decimation shown in the lower left figure of Figure 10C.

[0067] In this way, by sequentially changing the settling decimation level from small to bold and then severe after a predetermined time has elapsed since the central region changed, it is possible to make it less likely for the viewer to perceive a change in image quality. Note that the settling decimation level is not limited to the three stages shown in the diagram; one stage (decimation after standby only) or more is sufficient.

[0068] (Temporal Application Example 2) Figure 14 is an explanatory diagram of a temporal application example (Application Example 2) of the embodiment. This application example changes the method of thinning in the peripheral region over time. Specifically, the thinning method is changed periodically on a frame-by-frame basis.

[0069] For example, in the example shown in Figure 14, in the first frame 0, the peripheral area is written using decimation as shown in Figure 10A (R and B subpixels are erased one by one alternately before writing), and in the next frame 1, decimation is written as shown in the upper part of Figure 10C (only the G subpixel is written). Then, in the next frame 2, decimation is written as shown in the lower left part of Figure 10C (only the G and B subpixels are written), and in the next frame 3, decimation is written as shown in the lower right part of Figure 10C (only the G and R subpixels are written). Subsequently, this operation from frame 0 to frame 3 is repeated sequentially.

[0070] In this way, by changing the thinning method according to time, it is possible to make it less likely for the viewer to perceive changes in image quality. Note that there are not limited to four types of settling thinning; two or more types are sufficient. Also, the timing of changing the thinning method is not limited to every frame; for example, it could be every two frames or every other frame, and it does not have to be regular. If it is done regularly, the changes in image quality can be distributed on average and made less noticeable.

[0071] In this application example 2, it is particularly preferable to alternate between complementary decimation methods. For example, decimation of the peripheral region of the second frame (writing only G and B subpixels) and decimation of the peripheral region of the third frame (writing only G and R subpixels) can be considered complementary decimation methods. By making the decimation method complementary, changes in image quality can be suppressed.

[0072] (Temporal Application Example 3) Figure 15 is an explanatory diagram of a temporal application example (Application Example 3) of the embodiment. In this application example, the presence or absence of settling decimation in the peripheral area is alternately switched on a frame-by-frame basis. For example, in the example shown in Figure 15, in the first frame 0, settling decimation as shown in Figure 10A is performed, and in the next frame 1, settling decimation is not performed. Then, in the next frame 2, settling decimation as shown in Figure 10A is performed, and in the next frame 3, settling decimation is not performed. Thereafter, this operation from frame 0 to frame 3 is repeated sequentially. In this way, changes in image quality can be suppressed by alternately performing the operation of having settling decimation on a frame-by-frame basis. Note that the switching of the presence or absence of decimation is not limited to every frame, but may be every multiple frames, and does not have to be regular. If it is made regular, the changes in image quality can be averaged out and made less noticeable. The pixels to be decimated can also be changed as appropriate. This application example is effective, for example, when there is no time to set up the whole system, as it only requires adjusting the presence or absence of decimation. Furthermore, as an example of further application, spatial and temporal applications may be combined.

[0073] [2-9. Summary of the First Embodiment] Figure 16 is an illustrative image of the display device 1 in use according to this embodiment. Specifically, Figure 16 shows the time-series appearance of the panel when the data changes from all white to all black, as an example of the worst-case scenario when the pixel writing time of the B (B1, B2) subpixels in the peripheral area is shortened. The basic concept is the same for other image data changes and the case of decimation in Embodiment 2.

[0074] As illustrated, even when the displayed data changes from all white to all black, it is thought that viewers will not perceive a change in image quality even if the writing time of the surrounding areas is shortened. Initially, the writing time of the B subpixels in the surrounding areas is shortened, causing the surrounding areas to appear slightly bluish. However, since color changes are difficult to perceive in the surrounding areas, the blue (color) is not recognized (appearance S1).

[0075] Over time, the peripheral areas gradually darken as the charge held in the pixel circuits disappears. This change in brightness may be perceived due to the characteristics of the peripheral field of view. However, even if it is perceived, the change in brightness is not abrupt, so it does not cause any discomfort (appearance S2). Furthermore, this can be addressed by adjusting the downsampling method so that it is not perceived. As more time passes, the difference between the peripheral and central fields of view disappears (appearance S3).

[0076] As described above, in the display device 1 according to this embodiment, the time required to write the pixel signal supplied to the pixel circuit of the subpixel constituting the pixel is shorter than the time required for the actual writing of the pixel signal. Specifically, the writing time for writing the pixel signal to the pixel circuit of the peripheral area on a subpixel basis is shortened compared to the writing time required for the actual writing in the case of normal operation. Alternatively, the pixel signal is not written to the pixel circuit that writes the pixel signal in the actual writing of the peripheral area on a subpixel basis. By doing so, the time required for writing to the peripheral area in one horizontal period can be shortened without any noticeable difference. Since the time of one horizontal period in the peripheral area is shorter than the time of one horizontal period for the actual writing, even if the time of one vertical period does not change, the time required for writing to the central area in one horizontal period can be increased. Therefore, for example, even in cases where there was insufficient settling time due to increased resolution and frame rate, there will be no more insufficient settling time. As a result, it is possible to achieve higher resolution and higher frame rates. For example, the central area for the viewer can be kept at high resolution, and a higher frame rate can be achieved without affecting image quality. Furthermore, since the time required for writing during one horizontal period can be shortened, more efficient operation can be achieved, leading to lower power consumption. Specifically, power consumption can be reduced by decreasing the writing time.

[0077] <3. Second Embodiment> In the first embodiment, the horizontal period in the peripheral region was shortened by adjusting the writing time to subpixels in the peripheral region, but the shortening of the horizontal period in the peripheral region is not limited to this. In this embodiment and subsequent embodiments, the configuration example of the display device 1 of the first embodiment is basically used. Therefore, the following description will explain the differences from the first embodiment.

[0078] The display device 1 according to this embodiment has an offset time (time to write the offset voltage Vofs) that corrects the threshold voltage Vth of the drive transistor in the pixel circuit of the subpixel as the writing operation period within one horizontal period. The offset voltage Vofs is a pixel signal used to correct the threshold voltage of the drive transistor. The drive transistor drives the light-emitting element. More specifically, the drive transistor is a transistor that controls the current flowing through the light-emitting element. As this display device 1, for example, a pixel circuit with a 4Tr2C (four transistors and two capacitors) configuration as shown in Figure 34, which will be described later, can be used. In the configuration example in Figure 34, transistor MP14 corresponds to the drive transistor. Note that the display device 1 according to this embodiment only needs to have a time to write the offset voltage Vofs within the writing operation period of one horizontal period, and the pixel configuration, operation, control method, etc., are not limited to any particular ones.

[0079] Figure 17 is a diagram showing an example of operation of the display device 1 according to the second embodiment. The upper part of Figure 17 shows an example of operation under normal driving conditions (comparative example), and the lower part of Figure 17 shows an example of operation in a peripheral area according to this embodiment.

[0080] In the writing operation according to the comparative example, within one horizontal period, the writing operation includes a time for writing a pixel signal with an offset voltage Vofs, separate from the pixel signal representing the gradation level of the luminous intensity described above. Specifically, an offset (Vofs) period is provided before the time for writing the first data to the G1 subpixel, and the offset voltage Vofs is written to all subpixels (all of G1, R1, B1, G2, R2, and B2) to correct the threshold voltage Vth of the drive transistor in each subpixel. This eliminates the variation in the threshold voltage Vth of the drive transistor in each subpixel, thereby improving image quality.

[0081] In contrast, the display device 1 of this embodiment intentionally does not write the offset voltage Vofs in the peripheral region. In other words, in this embodiment, the pixel signal that reduces the writing time is the signal that writes the offset voltage Vofs. As a result, variations in image quality may occur in each subpixel due to differences in the threshold voltage Vth of the drive transistor, but the time required to write to the peripheral region in one horizontal period can be shortened compared to normal driving. Therefore, as in the first embodiment, higher resolution, higher frame rate, and lower power consumption can be achieved. Note that similar effects may also be obtained by shortening the offset time in the peripheral region.

[0082] If the offset voltage Vofs is not written in the peripheral region in this way, a difference in brightness may occur compared to when the offset voltage Vofs is written during normal operation. In this case, this can be corrected by controlling the signal voltage Vsig of the pixel signal that represents the grayscale level of the luminous intensity, as described above.

[0083] Figure 18 is an illustrative diagram illustrating the control of the signal voltage Vsig. Figure 18A illustrates the case where the signal voltage Vsig is uniformly corrected, while Figure 18B illustrates the case where the signal voltage Vsig is corrected individually for each subpixel.

[0084] In Figure 18A, the vertical axis represents the value of the signal voltage Vsig, and the horizontal axis represents the vertical line number (which line it is). For example, if the peripheral region becomes brighter compared to when the offset voltage Vofs is written because it is not written, the signal voltage Vsig of the next frame is adjusted accordingly (for example, made larger as shown in the figure) to make it darker. Specifically, the reference potential when generating the signal voltage Vsig of the peripheral region is made higher than that of the central region. If the peripheral region becomes darker compared to when the offset voltage Vofs is written, the signal voltage Vsig of the next frame is adjusted accordingly (for example, made smaller) to make it brighter. In this way, the brightness difference is corrected by uniformly raising or lowering the signal voltage Vsig of the peripheral region.

[0085] The upper part of Figure 18B shows the potentials in the case of normal operation, and the lower part of Figure 18B shows the potentials when the offset voltage Vofs is not written. As shown in the upper part of Figure 18B, when the offset voltage Vofs is written, for example, the target potential is set using the offset voltage Vofs as the reference potential. When the offset voltage Vofs is not written, as shown in the lower part of Figure 18B, the offset voltage Vofs does not become the reference potential, and the target potential from the previous frame becomes the reference potential, so the signal voltage Vsig is calculated and generated to match that.

[0086] Figure 19 shows an example configuration for controlling the signal voltage Vsig. This example configuration is common to both cases where the signal voltage Vsig is corrected uniformly and where each subpixel is corrected individually.

[0087] In the illustrated example, the source amplifier 7a has a Vsig generation block 7b for generating the signal voltage Vsig on its input side. The Vsig generation block 7b is supplied with peripheral area information from the write control unit 6 and the voltage from the previous frame. The Vsig generation block 7b operates using this peripheral area information and the voltage from the previous frame to perform the correction described above. As a result, the source amplifier 7a outputs the corrected signal voltage Vsig. With this configuration and operation, the brightness difference caused by reducing the time required to write the offset voltage Vofs can be corrected by adjusting the signal voltage Vsig of the pixel signal.

[0088] <4. Third Embodiment> Figure 20 is a diagram showing an example of operation of the display device 1 according to the third embodiment. The upper part of Figure 20 shows an example of writing operation in the case of a comparative example with normal drive, and the lower part of Figure 20 shows an example of writing operation in the peripheral area according to this embodiment.

[0089] As shown in the upper part of Figure 20, while normally signals are written to each subpixel individually, in this embodiment, as shown in the lower part of Figure 20, multiple subpixels are written to simultaneously. Specifically, the switches SW1 to SW6 of the amplifier switch circuit 8a simultaneously write pixel signals to the pixel circuits of multiple subpixels of the same type. In this embodiment, by writing with fewer write cycles than in the original writing process, the time required for writing in one horizontal period is shortened compared to the time required for original writing. In the illustrated example, the G subpixels are written independently. That is, the G1 and G2 subpixels are written separately as the first data and fourth data, respectively. In contrast, multiple R and B subpixels are written simultaneously. That is, the R1 and R2 subpixels are written simultaneously as the second and third data, and the B1 and B2 subpixels are written simultaneously as the fifth and sixth data.

[0090] The signal voltage Vsig used for simultaneous writing may be the level voltage of any one of the subpixels being written simultaneously, or it may be the average level voltage of the subpixels being written simultaneously. In the former case, the processing can be simplified, and in the latter case, the image quality changes caused by simultaneous writing can be averaged out. Depending on the number of selects supported by the source amplifier 7a, the number of subpixels used for simultaneous writing is not limited to the two shown in the figure, but may be three or more. Also, the subpixels used for simultaneous writing may be other than those shown in the figure. For example, one of the RGB colors may be written simultaneously, or two or more other combinations of RGB colors may be written simultaneously.

[0091] In this embodiment, pixel signals are simultaneously written to the pixel circuits of multiple subpixels of the same type in the peripheral region. This reduces the number of writes to the subpixels, thus shortening the time required to write to the peripheral region in one horizontal period compared to normal driving. Therefore, as in the first embodiment, higher resolution, higher frame rate, and lower power consumption can be achieved. In this embodiment, the case in which pixel signals are simultaneously written to the pixel circuits of multiple subpixels of the same type has been described, but this is not limited to this, and the operation may also be performed to simultaneously write pixel signals to the pixel circuits of multiple subpixels of different types, for example, by simultaneously writing to the R1 subpixel and the B2 subpixel. This also reduces the number of writes, so the same effect can be achieved. Furthermore, "simultaneous" here is not limited to the start and end times of writing coinciding, but is sufficient as long as there is a period in which writing is performed simultaneously. In other words, various modes of operation are permissible as long as the time required for writing in one horizontal period is shorter than the time required for writing in one horizontal period of normal driving (original writing operation).

[0092] <5. Fourth Embodiment> Figure 21 is a diagram showing an example of operation of the display device 1 according to the fourth embodiment. The upper part of Figure 21 shows an example of writing operation in the case of a comparative example with normal drive, and the lower part of Figure 21 shows an example of writing operation in the peripheral area according to this embodiment.

[0093] As shown in the upper part of Figure 21, in a normal drive write operation, a switching time is provided between each write of data from the first to the sixth data. As mentioned above, this switching time is the time required for the appropriate on / off switching of each switch SW1 to SW6. By providing this switching time, it is possible to prevent data from a previously written subpixel from being written when writing to a subpixel.

[0094] In contrast, in this embodiment shown in the lower part of Figure 21, the switching time is reduced by eliminating it on a sub-pixel basis in the peripheral region. Note that instead of eliminating the switching time, it may be shortened. In other words, in this embodiment, the time during which the amplifier switch 8a is in the off state due to the switching time is reduced. To put it another way, in this embodiment, the time from when SELn is turned down to when SEL(n+1) is turned up is reduced. As a result, when writing to a subpixel, the data of a previously written subpixel may be written for a moment and have an impact, but the time of one horizontal period in the peripheral region can be shortened. For example, as shown in the figure, the impact can be reduced by writing the same color consecutively (in the illustrated example, in the order of GGRRBB) in relation to the writing order. Note that in the illustrated example, a switching time is provided only between the writing time of the G2 subpixel (second data) and the writing time of the R1 subpixel (third data). Thus, in this embodiment, the switching time may be reduced for some subpixels, or it may be reduced for all subpixels.

[0095] In the display device 1 of this embodiment, the writing operation is performed in which the switching time between continuous writing operations of pixel signals in the peripheral region is made smaller than the switching time included in the time required for the original writing, on a subpixel basis. As a result, the time required to write to subpixels is reduced, and the time required to write to the peripheral region in one horizontal period can be shortened compared to normal driving. Therefore, as in the first embodiment, higher resolution and higher frame rates can be achieved.

[0096] <6. Fifth Embodiment> Figure 22 is a diagram showing an example of operation of the display device 1 according to the fifth embodiment. In the first to fourth embodiments described above, the case of shortening one horizontal period in the peripheral region was explained, but in the display device 1 of this embodiment, the amplifier switch circuit 8a is controlled to reduce the time required for writing in subpixel units not only in the peripheral region but also in the central region, as shown in the illustrated example. In other words, the one horizontal period is shortened not only in the peripheral region but also in the central region. Specifically, the one horizontal period is shortened uniformly across the entire display area, including both the peripheral and central regions. Note that Figure 22 illustrates the shortening of one horizontal period according to Example 1 of the first embodiment, which shortens the writing time of the B (B1, B2) subpixels, but the method of shortening may be other than this, for example, according to Example 2.

[0097] This embodiment can be applied, for example, when the viewer's visual ability deteriorates, or when the resolution decreases. This embodiment can be applied, for example, when the user shakes their head while wearing an XR (Cross Reality, also called Extended Reality) set such as a head-mounted display worn on the head, or when the viewer blinks. Furthermore, it is not limited to these cases, and can be used during normal use, not just when the viewer's visual ability deteriorates, as long as there is no impact on image quality due to shortening by controlling the amplifier switch circuit 8a in the time direction. The period during which the viewer's visual ability deteriorates, or the period during which there is no impact on image quality due to shortening, can be determined, for example, based on sensor output or simulation results, and the amplifier switch circuit 8a can be controlled based on the determination result. Specifically, instead of the visual information described above, information representing this determination result can be used. In this way, the area in which the viewer is not affected by changes in image quality can be expanded not only to the peripheral area, but also to, for example, the entire display area. In other words, the area in which this technology can be applied can be set as appropriate.

[0098] In this case, if we only shorten the horizontal period in the peripheral region, the circuit operation becomes complex because the horizontal period changes within the vertical period. In this embodiment, since the horizontal period is shortened uniformly in both the peripheral and central regions, the same effect as in the first embodiment can be easily obtained with simple circuit operation. Note that the methods for shortening the central and peripheral regions may be different. Also, the shortening of the horizontal period in the central and peripheral regions does not necessarily have to be uniform.

[0099] (Spatial Application Example) Figure 23 is an explanatory diagram of a spatial application example in this embodiment. This application example is based on spatial application example 1 of the first embodiment described above. In this application example, the amplifier switch circuit 8a is controlled for each arbitrary region to change the method of thinning. In this application example, for example, the duration of one horizontal period is unified to the closest one among the thinning methods. This makes the circuit operation simple as described above. Alternatively, the duration of one horizontal period may be set to match the one with the longest duration. The same applies to other spatial application examples.

[0100] Specifically, in the operation shown in Figure 23, the peripheral region is divided into two regions (thinning region A and thinning region B), thereby creating three regions: the central region, thinning region A, and thinning region B. The central region is operated as shown in Figure 10A, thinning region A, which is outside the central region, is operated as shown in the lower left diagram of Figure 10C, and thinning region B, which is outside thinning region A, is operated as shown in the upper diagram of Figure 10C.

[0101] In this way, by spatially changing the thinning method, it is possible to make the change in image quality less noticeable. Note that the division of the region is not limited to the illustrated example. For example, the peripheral region only needs to be divided into one or more sections. Alternatively, the central region may be divided into two or more sections, and the thinning method may be changed for each section. Furthermore, any of the embodiments described above may be used to shorten the horizontal period in the central and peripheral regions, respectively.

[0102] (Temporal Application Example) Figure 24 is an explanatory diagram of a temporal application example in this embodiment. This application example is based on temporal application example 2 of the first embodiment described above. In this application example, the amplifier switch circuit 8a is controlled for each region in any frame to change the method of decimation. Specifically, the decimation method for the peripheral region and the central region are adjusted, respectively. The method for unifying the time of one horizontal period is the same as in the spatial application example described above.

[0103] Specifically, in the operation example shown in Figure 24, the peripheral region operates in the same way as in the operation example shown in Figure 14. Therefore, the operation of the peripheral region will not be explained here. On the other hand, in this operation example, the central region operates as follows.

[0104] Regarding the central region, in the first frame (frame 0), the write operation shown in the upper part of Figure 10C is performed, and in the next frame (frame 1), normal operation is performed. Then, in the following frame (frame 2), the write operation shown in the lower left part of Figure 10C is performed, and in the following frame (frame 3), the write operation shown in Figure 10A is performed. Subsequently, the operations from frame 0 to frame 3 are repeated in order to perform decimation.

[0105] Thus, by changing the thinning method over time, it is possible to make the change in image quality less noticeable. In this temporal application example, as mentioned above, it is preferable to alternate complementary thinning methods. Furthermore, the shortening of the horizontal period in the central and peripheral regions can be achieved using any of the embodiments described above. In addition, spatial and temporal application examples may be combined.

[0106] <7. Application Examples of Each Embodiment> [7-1. Application Example 1] Figure 25 is an explanatory diagram of an application example (Application Example 1) applicable to each embodiment. Figure 25A is a graph showing an example of the output waveform of the source amplifier 7a, and Figure 25B shows a schematic example of the input side circuit of the source amplifier 7a. In Figure 25A, the vertical axis represents voltage, and the horizontal axis represents time. In Figure 25A, the dark line waveform L shows an example of the waveform when no overdrive is performed, and the light line waveforms L1 and L2 show examples of the waveforms when overdrive is performed, respectively.

[0107] In this application example, the output of the source amplifier 7a is overdriven in accordance with the settling time. In other words, as described above, when the settling time is shortened compared to normal operation, the output of the source amplifier 7a is intentionally overdriven so that writing can be completed in a short time. For example, in the period a from time t0 when the output starts to time t1 after a predetermined time has elapsed, as shown in Figure 25A, the output is set higher than the target output to shorten the time it takes to approach the target output. Then, in the period b after period a (after time t1), the control is set to output the target output. Note that period a is, for example, shorter than the settling time of waveform L.

[0108] As shown in Figure 25B, the Vsig generation block 7b includes a ladder resistor circuit 7c in which multiple resistor elements are connected in a ladder-like manner, and a selector circuit 7d that selects a desired voltage from the ladder resistor circuit 7c and outputs it to the source amplifier 7a. The selector circuit 7d, for example, selects a voltage higher than the target output voltage (voltage in section a) during period a, and selects the target output voltage (voltage in section b) during period b and outputs it to the source amplifier 7a.

[0109] Thus, in this application example, by overdriving the output of the source amplifier 7a in accordance with the settling time, it is possible to ensure that writing is completed in time even when the settling time is shorter than in normal operation. Note that the method of overdriving is not limited to this. For example, the transistors and capacitors in the source amplifier 7a could be intentionally made unstable (for example, those that produce outputs like waveforms L1 and L2) to quickly swing to the target output.

[0110] [7-2. Application Example 2] Figure 26 is an explanatory diagram of an application example (Application Example 2) applicable to each embodiment. Figure 27 is a diagram showing an example of the configuration of the source amplifier 7a. When reducing the writing time to the subpixel (shortening it or not writing at all) as described in each embodiment, the performance of the source amplifier 7a may be intentionally suppressed (the performance of the source amplifier 7a is reduced). In other words, when generating a pixel signal that is written in a shorter time than originally intended, the performance of the source amplifier 7a may be reduced.

[0111] As shown in Figure 26, a bias circuit 7e is connected to each source amplifier group, which consists of multiple source amplifiers 7a. A bias voltage is supplied from the bias circuit 7e to each source amplifier 7a in the source amplifier group. Each source amplifier 7a uses this bias voltage to control the gate voltage of the transistor within the source amplifier 7a, thereby controlling the bias current flowing through the transistor.

[0112] For example, in the case of the source amplifier 7a shown in Figure 27, bias voltages are supplied from the bias circuit 7e to the gates of six transistors in order to obtain the amplifier output. Note that the configuration of the source amplifier 7a is not limited to that shown.

[0113] Methods for suppressing the performance of the source amplifier 7a include, for example, weakening the bias current and turning off the source amplifier 7a. In the case of weakening the bias current, the gate voltage of the transistors in the source amplifier 7a is controlled by the bias voltage to reduce the bias current. In the case of turning off the source amplifier 7a, it is conceivable to completely stop the transistors in the source amplifier 7a by controlling the bias voltage to the voltage of the power line VSS or the voltage of the power line VDD, thereby stopping the bias current. Alternatively, a switch may be provided in the bias circuit 7e or at the gate of the transistors in the source amplifier 7a, and the source amplifier 7a may be stopped by turning off the switch (making it non-conductive). Alternatively, a switch may be provided between the power line VDD or power line VSS and the bias circuit 7e, taking IR drop into consideration, and the source amplifier 7a may be stopped by turning off the switch. The methods for suppressing the performance of the source amplifier 7a are not limited to these and can be selected as appropriate. For example, the bias current may be reduced by switching the number of transistors in the source amplifier 7a using a switching circuit or the like.

[0114] Thus, in this application example, the performance of the source amplifier 7a is reduced when the writing time to the subpixel is shortened or when no writing is performed. This reduces the bias current and enables lower power consumption.

[0115] [7-3. Application Example 3] Figure 28 is an explanatory diagram of an application example (Application Example 3) applicable to each embodiment. Figure 28A shows an example of writing operation to which this application example is applied, and Figure 28B is an explanatory diagram of an example of adjusting the signal voltage Vsig during the operation in Figure 28A. Note that Figure 28A illustrates a technique for shortening the time of one horizontal period, which involves changing the subpixels that are not written for each pixel, as explained with reference to Figure 10A, but other shortening techniques of this technique may also be used.

[0116] This application example combines the technology of each embodiment with other peripheral vision display technologies. Examples of peripheral vision display technologies include foveal motion technology, specifically, a technology that lowers the resolution of the peripheral region compared to the central region by simultaneously writing multiple lines in the peripheral region. For example, in the example shown in Figure 28A, the operation described with reference to Figure 10A is performed, which involves changing the subpixels that are not written for each pixel, and simultaneously writing to two adjacent lines (simultaneous writing (1), (2)). In other words, in this operation example, the time required to write the above-mentioned pixel signal is reduced in the row direction (first direction) of the region in which the viewer is not affected by the change in image quality, and the same pixel signal is simultaneously written to multiple pixel circuits in the column direction (second direction) of the same region. In this operation example, for example, an entire line is simultaneously written after settling. In simultaneous writing (1), decimation is performed in the order of B, R, B, ... from left to right, and in simultaneous writing (2), decimation is performed in the order of R, B, R, ... from left to right. In this way, by having simultaneous writing (1) and simultaneous writing (2) complement each other in terms of settling decimation methods, it is possible to improve the appearance.

[0117] While the technologies of each embodiment described above control signals in the column direction, the Foveal operation technology controls signals in the row direction. Since they are independent of each other, they can coexist in this way. In other words, the writing of subpixels to the pixel circuit, which is a feature of this technology, is performed line by line along the row direction via signal lines SGL along the column direction. In contrast, in Foveal operation, for example, the same writing is performed simultaneously on multiple adjacent lines along the row direction. Therefore, both can be operated in combination. Note that Foveal operation is not limited to a specific case; for example, the number of lines on which simultaneous writing is performed is not limited to two, but may be three or more. Also, for example, the order may be 2 rows, 3 rows, 3 rows, 2 rows, or simultaneous writing may be performed irregularly.

[0118] In this case, if Foveal operation technology is employed, flicker due to brightness differences may be a concern. Therefore, as shown in Figure 28B, when performing decimation in combination with Foveal operation, the range of the signal voltage Vsig in the decimation region may be narrower than the range of the signal voltage Vsig in normal operation. In this way, by reducing the range of the signal voltage Vsig at the same time as decimation, the occurrence of flicker can be suppressed. This application example can also be applied when shortening the writing time on a subpixel basis, such as in Example 1 of the first embodiment. Note that the operations of each application example 1 to 3 may be combined as appropriate.

[0119] <8. Examples of Horizontal and Vertical Driver Configurations> [8-1. Example of Horizontal Driver Configuration] (Configuration Example 1) Figure 29 shows an example of the configuration of the horizontal driver 10 (Configuration Example 1). The horizontal driver 10 shown in Figure 29 is a voltage follower type circuit having a voltage follower circuit at the output section to each signal line SGL. The horizontal driver 10 has a shift register section (S / R) 21, a 1ST latch section 22, a 2ND latch section 23, a level shifter section 24, a DAC section 25, and an output buffer section 26.

[0120] The shift register unit 21 sequentially shifts the pixel data (DATA) corrected by the write control unit 6 and outputs a number of pixel data corresponding to the number of subpixels in the row direction. The 1st latch unit 22 is composed of the corresponding number of 1st latch circuits 22A as described above, and latches each pixel data input from the shift register unit 21 based on the latch clock LATCLK. The 2nd latch unit 23 is composed of the corresponding number of 2nd latch circuits 23A as described above, and sequentially converts each latched data of the 1st latch circuit 22A into line sequential data using the line pulse LINECLK.

[0121] The level shifter section 24 is composed of a group of level shifter circuits (not shown) and converts the level of each pixel data sequentially processed by the 2ND latch circuit 23A from a logic level to analog level data corresponding to the drive level. The DAC section 25 is composed of multiple DAC (Digital-to-Analog Converter) circuits 25A and receives a gradation voltage corresponding to the gamma resistance set by the gamma resistance section 27 and converts the pixel data level-converted by each level shifter circuit from digital data to analog data. The output buffer section 26 is composed of a voltage follower consisting of multiple operational amplifiers 26A and a demultiplexer circuit 26B and outputs the pixel signal obtained by conversion by each DAC circuit 25A to the signal line SGL connected to each subpixel of the pixel section 9 in a time-division manner during each horizontal period.

[0122] In this configuration example, for example, the operational amplifier 26A corresponds to the source amplifier 7a, and the demultiplexer circuit 26B corresponds to the amplifier switch circuit 8a.

[0123] (Configuration Example 2) Figure 30 shows a configuration example (Configuration Example 2) of the horizontal driver 10. The horizontal driver 10 shown in Figure 30 is configured as a RAMPDAC type circuit that uses an analog signal of a ramp waveform to generate the pixel signal output to the signal line SGL. This horizontal driver 10 has the shift register section (S / R) 21, 1ST latch section 22 and 2ND latch section 23 described above. This horizontal driver 10 also has a synchronous counter 28, a DLL (delay-locked loop) circuit 29, a comparator section 30, a PWM generation section 31, a level shifter section 32, a ramp processing section 33 and a switch section 34.

[0124] The synchronous counter 28 receives the main clock signal MCLK via the DLL circuit 29. The synchronous counter 28 performs a down count or up count in synchronization with the main clock signal MCLK and outputs a signal of the count result.

[0125] The comparator unit 30 is composed of the corresponding number of digital comparators 30A mentioned above. Each digital comparator 30A compares the latch data of each 2ND latch circuit 23A with the output from the synchronous counter 28 and outputs the comparison result. The PWM generation unit 31 is composed of the corresponding number of PWM generation circuits 31A mentioned above. Each PWM generation circuit 31A generates a PWM (pulse width) signal corresponding to the grayscale data of each subpixel in response to the start pulse RAMPST.

[0126] The level shifter unit 32 is composed of the corresponding number of level shifter circuits 32A described above, and converts the level of the PWM signal converted by each PWM generation circuit 31A into a drive level (voltage level) signal. This signal is used to control the PWM switch 34A in the switch unit 34. The lamp processing unit 33 generates a lamp signal whose voltage level changes over time and outputs it to the switch unit 34 via the lamp wiring RL. In this way, the lamp signal generated by the lamp processing unit 33 is supplied to the lamp wiring RL.

[0127] The switch unit 34 is composed of the corresponding number of PWM switches 34A mentioned above. Each PWM switch 34A is provided between each signal line SGL connected to a subpixel of the pixel unit 9 and the lamp wiring RL, and controls the connection between the lamp wiring RL and each corresponding signal line SGL. Specifically, each PWM switch 34A samples the lamp waveform by turning off (closed) at a timing corresponding to the gradation to be written to the subpixel according to the output voltage of each level shifter circuit 32A, thereby determining the signal voltage to be written to the subpixel.

[0128] In this configuration example, for example, the amplifier included in the circuitry of the lamp processing unit 33 corresponds to the source amplifier 7a, and the switch unit 34 can be configured to correspond to the amplifier switch circuit 8a. In other words, the switch unit 34 can be configured to perform the same operation as the amplifier switch circuit 8a described above. Note that the amplifier switch circuit 8a may be provided separately from the switch unit 34.

[0129] [8-2. Example Configuration of a Vertical Driver] (Example Configuration 1) Figure 31 shows an example configuration of a vertical driver 4 (Example Configuration 1). The vertical driver 4 shown in Figure 31 is composed of a shift register type circuit having a shift register circuit in the signal input section. The vertical logic section 14 that constitutes this vertical driver 4 has a shift register section 41 and a logic circuit section 42. The vertical analog section 15 has a level shifter section 51 and an output buffer section 52.

[0130] The shift register section 41 is composed of a number of shift registers 41A corresponding to the number of subpixels in the column direction. The start pulse VST is synchronized with the clock signal CLK and propagated sequentially, outputting as shift signals SR0, SR1, ... for each row.

[0131] The logic circuit section 42 is composed of the corresponding number of logic circuits (LOGICs) 42A mentioned above, and performs logic operations as needed according to the input control signals (not shown). The level shifter section 51 is composed of the corresponding number of level shifters 51A mentioned above, and converts the levels of each signal SR0, SR1, ... that have undergone logic operations into drive level signals (control signals). The output buffer section 52 is composed of the corresponding number of buffer circuits 52A mentioned above, and outputs the control signals in a buffer.

[0132] (Configuration Example 2) Figure 32 shows an example configuration of the vertical driver 4 (Configuration Example 2). This vertical driver 4 has an address decoder 40 instead of the shift register section 41 of the vertical driver 4 shown in Figure 31. Thus, the vertical driver 4 shown in Figure 32 is configured as an address decoder type circuit having an address decoder 40 in the signal input section. The other configurations are the same as those of the vertical driver 4 in Figure 31.

[0133] The address decoder 40 decodes the address based on the address information COUNT supplied from the display controller 2 and outputs the decoded result corresponding to the logic circuit 42A of each row. The shift register unit 41 described above is configured to shift in a predetermined order, such as from top to bottom or bottom to top, but the address decoder 40 can sequentially specify and scan between predetermined addresses, such as incrementing from an arbitrary address to a certain address.

[0134] <9. Examples of Pixel Circuit Configurations> The following describes examples of pixel circuit configurations (specifically, subpixel configurations). Note that the following configuration examples are merely illustrative and do not exclude other configurations.

[0135] (Configuration Example 1) Figure 33 shows an example configuration of a pixel (pixel circuit) PIX (specifically, a subpixel) in the pixel unit 9. The pixel PIX includes a capacitor C01, transistors MN02 to MN03, and a light-emitting element EL. Transistors MN02 to MN03 are N-type MOSFETs. The gate of transistor MN02 is connected to the control line WSL, the other of its source and drain is connected to the signal line SGL, and one of its source and drain is connected to the gate of transistor MN03 and one end of capacitor C01. One end of capacitor C01 is connected to one of the source and drain of transistor MN02 and the gate of transistor MN03, and the other end is connected to one of the source and drain of transistor MN03 and the anode of the light-emitting element EL. The gate of transistor MN03 is connected to one of the source and drain of transistor MN02 and one end of capacitor C01, the other source and drain is connected to the power line VCCP, and one of the source and drain is connected to the other end of capacitor C01 and the anode of light-emitting element EL. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN03 and the other end of capacitor C01, and its cathode is connected to the power line Vcath. The voltage of the power line VCCP is switched as appropriate between a first voltage and a second voltage lower than the first voltage.

[0136] In this configuration, when transistor MN02 is turned on in a pixel PIX, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During the period when the voltage of power line VCCP is the first voltage, transistor MN03 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C01. The light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. During the period when the voltage of power line VCCP is the second voltage, the light-emitting element EL is extinguished.

[0137] (Configuration Example 2) Figure 34 shows another configuration example of a pixel PIX. This pixel PIX has capacitors C11 and C12, transistors MP12 to MP15, and light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to the control line WSL, one of its source and drain is connected to the signal line SGL, and the other of its source and drain is connected to the gate of transistor MP14 and the other end of capacitor C12. One end of capacitor C11 is connected to the power line VCCP, and the other end is connected to one end of capacitor C12, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14, and the other end is connected to the other of the source and drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, one of its source and drain is connected to the power line VCCP, and the other of its source and drain is connected to one of the source and drain of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the other of the source and drain of transistor MP12 and the other end of capacitor C12, one of its source and drain is connected to the other of the source and drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the other of its source and drain is connected to the anode of the light-emitting element EL and one of the source and drain of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP14 and the anode of the light-emitting element EL, and the other of its source and drain is connected to the power line VSS.The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP14, and to one of the source and drain of transistor MP15, while the cathode is connected to the power line Vcath.

[0138] In this configuration, in a pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal from control line DSL. Transistor MP14 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C12 while transistor MP13 is on. The light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal from control line AZSL. While transistor MP15 is on, the voltage at the anode of the light-emitting element EL is initialized by being set to the voltage of power line VSS.

[0139] Transistors MP12 to MP15 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP12 and MP15 may be a transistor made of oxide semiconductor. Furthermore, the other of the source and drain of transistor MP15 may be connected to the power line Vcath to which the cathode of the light-emitting element EL is connected, instead of the power line VSS.

[0140] This configuration example corresponds to one in which an offset voltage writing period is included in the horizontal period described above. Known techniques can be used for this offset voltage writing operation, and their explanation is omitted here. In this configuration example, transistor MP14 corresponds to the drive transistor, and the extinction control of the light-emitting element EL is performed, for example, by the control signals of control line DSL and control line AZSL.

[0141] (Configuration Example 3) Figure 35 shows another configuration example of a pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to the control line WSL, the other of its source and drain is connected to the signal line SGL, and one of its source and drain is connected to the gate of transistor MN24 and one end of capacitor C21. One end of capacitor C21 is connected to one of the source and drain of transistor MN22 and the gate of transistor MN24, and the other end is connected to one of the source and drain of transistor MN24, the other of the source and drain of transistor MN25, and the anode of the light-emitting element EL. The gate of transistor MN23 is connected to the control line DSL, the other of its source and drain is connected to the power line VCCP, and one of its source and drain is connected to the other of the source and drain of transistor MN24. The gate of transistor MN24 is connected to one of the source and drain of transistor MN22 and one end of capacitor C21, the other source and drain is connected to one of the source and drain of transistor MN23, and one source and drain is connected to the other end of capacitor C21, the other source and drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN25 is connected to the control line AZSL, the other source and drain is connected to one of the source and drain of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and one source and drain is connected to the power line VSS. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN24, the other end of capacitor C21, and the other source and drain of transistor MN25, and its cathode is connected to the power line Vcath.

[0142] In this configuration, in a pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal from control line DSL. Transistor MN24 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C21 while transistor MN23 is on. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal from control line AZSL. While transistor MN25 is on, the voltage at the anode of the light-emitting element EL is initialized by being set to the voltage of power line VSS.

[0143] Transistors MN22 to MN25 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MN22 and MN25 may be a transistor made of oxide semiconductor. Furthermore, one of the source and drain of transistor MN25 may be connected to the power line Vcath to which the cathode of the light-emitting element EL is connected, instead of the power line VSS.

[0144] (Configuration Example 4) Figure 36 shows another configuration example of a pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to the control line WSL, one of its source and drain is connected to the signal line SGL, and the other of its source and drain is connected to the gate of transistor MP33, the other of its source and drain of transistor MP34, and the other end of capacitor C31. One end of capacitor C31 is connected to the power line VCCP, and the other end is connected to the other of its source and drain of transistor MP32, the gate of transistor MP33, and the other of its source and drain of transistor MP34. The gate of transistor MP33 is connected to the other source and drain of transistor MP32, the other source and drain of transistor MP34, and the other end of capacitor C31. One source and drain is connected to the power line VCCP, and the other source and drain is connected to one source and drain of transistor MP35 and one source and drain of transistor MP34. The gate of transistor MP34 is connected to the control line AZSL1, and one source and drain is connected to the other source and drain of transistor MP33 and one source and drain of transistor MP35. The other source and drain is connected to the other source and drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to the control line DSL, and one source and drain is connected to the other source and drain of transistor MP33 and one source and drain of transistor MP34. The other source and drain is connected to one source and drain of transistor MP36 and the anode of the light-emitting element EL.The gate of transistor MP36 is connected to the control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP35 and to the anode of the light-emitting element EL, and the other of its source and drain is connected to the power line VSS. The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP35 and to one of the source and drain of transistor MP36, and its cathode is connected to the power line Vcath.

[0145] In this configuration, in a pixel PIX, when transistor MP32 is turned ON, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned ON or OFF based on the signal from control line DSL. Transistor MP33 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C31 while transistor MP35 is ON. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. Transistor MP34 is turned ON or OFF based on the signal from control line AZSL1. While transistor MP34 is ON, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned ON or OFF based on the signal from control line AZSL2. While transistor MP36 is ON, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of power line VSS.

[0146] Transistors MP32 to MP36 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP32, MP34, and MP36 may be a transistor made of oxide semiconductor. Furthermore, the other of the source and drain of transistor MP36 may be connected to the power line Vcath to which the cathode of the light-emitting element EL is connected, instead of the power line VSS.

[0147] (Configuration Example 5) Figure 37 shows another configuration example of a pixel PIX. One end of capacitor C48 is connected to the signal line SGL1, and the other end is connected to the power line VSS. One end of capacitor C49 is connected to the signal line SGL1, and the other end is connected to the signal line SGL2. Transistor MP49 is a P-type MOSFET, with its gate connected to the control line WSL2, one of its source and drain connected to the signal line SGL1, and the other of its source and drain connected to the signal line SGL2.

[0148] Each pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to the control line WSL1, one of its source and drain is connected to the signal line SGL2, and the other of its source and drain is connected to the gate of transistor MP43 and the other end of capacitor C41. One end of capacitor 41 is connected to the power line VCCP, and the other end is connected to the other of its source and drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the other of its source and drain of transistor MP42 and the other end of capacitor C41, one of its source and drain is connected to the power line VCCP, and the other of its source and drain is connected to one of its source and drain of transistors MP44 and MP45. The gate of transistor MP44 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP43, and one of the source and drain of transistor MP45, and the other of its source and drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP43, and one of the source and drain of transistor MP44, and the other of its source and drain is connected to one of the source and drain of transistor MP46 and the anode of the light-emitting element EL. The gate of transistor MP46 is connected to control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP45 and the anode of the light-emitting element EL, and the other of its source and drain is connected to power line VSS. The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP45 and one of the source and drain of transistor MP46, and its cathode is connected to power line Vcath.

[0149] In this configuration, in a pixel PIX, when transistor MP42 is turned ON, the voltage across capacitor C41 is set based on the pixel signal supplied to signal line SGL1. Transistor MP45 is turned ON or OFF based on the signal on control line DSL. Transistor MP43 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C41 while transistor MP45 is ON. The light-emitting element EL emits light based on the current supplied by transistor MP43. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. Transistor MP44 is turned ON or OFF based on the signal on control line AZSL1. While transistor MP44 is ON, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned ON or OFF based on the signal on control line AZSL2. While transistor MP46 is ON, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line VSS.

[0150] Furthermore, transistors MP42 to MP46 and MP49 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP42, MP46, and MP49 may be a transistor made of oxide semiconductor. In addition, the other of the source and drain of transistor MP46 may be connected to the power line Vcath to which the cathode of the light-emitting element EL is connected, instead of the power line VSS.

[0151] (Configuration Example 6) Figure 38 shows another configuration example of a pixel PIX. Multiple pixels PIX are arranged in a matrix in the display area 100, and the display area 100 is located between the first control unit 91 and the second control unit 92.

[0152] The first control unit 91 includes transmission gates TG45 and TG46, transistors MP50 and MP51, and capacitor C50. Transistors MP50 and MP51 are P-type MOSFETs. A pixel signal is supplied to one end of transmission gate TG45, and the other end of transmission gate TG45 is connected to signal line 93a. One end of transmission gate TG46 is connected to signal line 93b, and the other end of transmission gate TG46 is connected to power line Vorst. One end of capacitor C50 is connected to signal line 93a, and the other end is connected to power line VSS1. The gate of transistor MP50 is connected to control line INIL, one of its source and drain is connected to power line Vini, and the other of its source and drain is connected to signal line 93b. The gate of transistor MP51 is connected to control line ELL, one of its source and drain is connected to power line Vel, and the other of its source and drain is connected to signal line 93b.

[0153] The second control unit 92 includes a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. One end of the transmission gate TG72 is connected to the signal line 93a, and the other end is connected to the other of the source and drain of the transistor MP73, and to one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, one of the source and drain is connected to the power line Vref, and the other of the source and drain is connected to the other end of the transmission gate TG72 and to one end of the capacitor C82. One end of the capacitor C82 is connected to the other end of the transmission gate TG72 and the other of the source and drain of the transistor MP73, and the other end is connected to the signal line 93b.

[0154] Each pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. Transistors MP121 to MP125 are P-type MOSFETs. The gate of transistor MP122 is connected to the control line WSL, one of its source and drain is connected to the signal line 93b, and the other of its source and drain is connected to the gate of transistor MP121 and the other end of capacitor C132. One end of capacitor C132 is connected to the power line Vel, and the other end is connected to the other of its source and drain of transistor MP122 and the gate of transistor MP121. The gate of transistor MP121 is connected to the other of its source and drain of transistor MP122 and the other end of capacitor C132, one of its source and drain is connected to the power line Vel, and the other of its source and drain is connected to one of its source and drain of transistors MP123 and MP124. The gate of transistor MP123 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP121, and one of the source and drain of transistor MP124, and the other of its source and drain is connected to the signal line 93b. The gate of transistor MP124 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP121, and one of the source and drain of transistor MP123, and the other of its source and drain is connected to one of the source and drain of transistor MP125 and the anode of the light-emitting element EL. The gate of transistor MP125 is connected to the control line AZSL, the other of its source and drain is connected to the power line Vorst, and one of its source and drain is connected to the other of the source and drain of transistor MP124 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP124 and one of the source and drain of transistor MP125, and its cathode is connected to the power line Vcath.

[0155] In this configuration, in a pixel PIX, when transistor MP122 is turned ON, the voltage across capacitor C132 is set based on the pixel signal supplied to one end of transmission gate TG45. Transistor MP124 is turned ON or OFF based on the signal on control line DSL. Transistor MP121 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C132 during the period when transistor MP124 is ON. The light-emitting element EL emits light based on the current supplied by transistor MP121. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. Transistors MP123 and MP125 are turned ON or OFF based on the signal on control line AZSL. During the period when transistor MP123 is ON, the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124 are connected to signal line 93b. During the period when transistor MP125 is ON, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line Vorst. Furthermore, transistor MP50 is switched on and off based on the signal of control line INIL, transistor MP51 is switched on and off based on the signal of control line ELL, and transistor MP73 is switched on and off based on the signal of control line REFL. When transistor MP50 is turned on, signal line 93b is set to the voltage of power line Vini, and when transistor MP51 is turned on, signal line 93b is set to the voltage of power line Vel. When transistor MP73 is turned on, one end of capacitor C82 is initialized by being set to the voltage of power line Vref.

[0156] Furthermore, transistors MP121 to MP125, MP50, and MP51 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP122 and MP125 may be a transistor made of oxide semiconductor. In addition, the other of the source and drain of transistor MP125 may be connected to the power line Vcath to which the cathode of the light-emitting element EL is connected, instead of the power line Vorst.

[0157] (Configuration Example 7) Figure 39 shows another configuration example of a pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to the control line WSL, one of its source and drain is connected to the signal line SGL, and the other of its source and drain is connected to the other of its source and drain of transistor MP53 and one of its source and drain of transistor MP54. The gate of transistor MP53 is connected to the control line DSL, one of its source and drain is connected to the power line VCCP, and the other of its source and drain is connected to the other of its source and drain of transistor MP52 and one of its source and drain of transistor MP54. The gate of transistor MP54 is connected to one of the source and drain of transistor MP55, the other of the source and drain of transistor MP57, and the other end of capacitor C51. One of the source and drain is connected to the other of the source and drain of transistors MP52 and MP53, and the other of the source and drain is connected to one of the source and drain of transistors MP58 and MP59. One end of capacitor C51 is connected to the power line VCCP, and the other end is connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other of the source and drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel with each other. The gate of transistor MP55 is connected to the control line AZSL1, one of the source and drain is connected to the gate of transistor MP54, the other of the source and drain of transistor MP57, and the other end of capacitor C51, and the other of the source and drain is connected to one of the source and drain of transistor MP56. The gate of transistor MP56 is connected to control line AZSL1, one of its source and drain is connected to the other of its source and drain of transistor MP55, and the other of its source and drain is connected to power line VSS.The gate of transistor MP57 is connected to the control line WSL, the other of its source and drain is connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other end of capacitor C51, and one of its source and drain is connected to the other of its source and drain of transistor MP58. The gate of transistor MP58 is connected to the control line WSL, the other of its source and drain is connected to one of the source and drain of transistor MP57, the other of its source and drain is connected to the other of its source and drain of transistor MP54, and one of its source and drain is connected to one of its source and drain of transistor MP59. The gate of transistor MP59 is connected to the control line DSL, the other of its source and drain is connected to the other of its source and drain of transistor MP54, and one of its source and drain is connected to one of its source and drain of transistor MP58, and the other of its source and drain is connected to one of its source and drain of transistor MP60, and the anode of the light-emitting element EL. The gate of transistor MP60 is connected to the control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP59 and to the anode of the light-emitting element EL, and the other of its source and drain is connected to the power line VSS. The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP59 and to one of the source and drain of transistor MP60, and its cathode is connected to the power line Vcath.

[0158] In this configuration, in the pixel PIX, the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL when transistors MP52, MP54, MP58, and MP57 are turned ON. Transistors MP53 and MP59 are turned ON and OFF based on the signal from control line DSL. Transistor MP54 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C51 while transistors MP53 and MP59 are ON. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistors MP55 and MP56 are turned ON and OFF based on the signal from control line AZSL1. While transistors MP55 and MP56 are ON, the gate voltage of transistor MP54 is initialized by being set to the voltage of power line VSS. Transistor MP60 is turned ON and OFF based on the signal from control line AZSL2. During the period when transistor MP60 is ON, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of the power line VSS.

[0159] Transistors MP52 to MP60 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP55 to MP58 and MP60 may be a transistor made of oxide semiconductor. Furthermore, the other of the source and drain of transistor MP60 may be connected to the power line Vcath to which the cathode of the light-emitting element EL is connected, instead of the power line VSS.

[0160] (Configuration Example 8) Figure 40 shows another configuration example of a pixel PIX. The signals of control line WSNL and control line WSPL are inverted signals of each other.

[0161] Each pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, MN65-MN67, and light-emitting element EL. Transistors MN63, MN65-MN67 are N-type MOSFETs, and transistor MP64 is a P-type MOSFET. The gate of transistor MN63 is connected to the control line WSNL, and the other of its source and drain is connected to the signal line SGL and one of the source and drain of transistor MP64. The other of its source and drain is connected to the other of the source and drain of transistor MP64, one end of capacitors C61 and C62, and the gate of transistor MN65. The gate of transistor MP64 is connected to the control line WSPL, and the other of its source and drain is connected to the signal line SGL and the other of the source and drain of transistor MN63. The other of its source and drain is connected to one of the source and drain of transistor MN63, one end of capacitors C61 and C62, and the gate of transistor MN65. Capacitor C61 is constructed using, for example, a MOM (Metal Oxide Metal) capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C62, and the gate of transistor MN65, and the other end connected to the power line VSS2. Capacitor C61 may also be constructed using, for example, a MOS capacitor or a MIM (Metal Insulator Metal) capacitor. Capacitor C62 is constructed using, for example, a MOS capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power line VSS2. Capacitor C62 may also be constructed using, for example, a MOM capacitor or a MIM capacitor. The other end of capacitor C62 may also be connected to the power line VSS3 (not shown).The gate of transistor MN65 is connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, and one end of capacitors C61 and C62. The other of the source and drain is connected to the power line VCCP, and the other of the source and drain is connected to the other of the source and drain of transistors MN66 and MN67. The gate of transistor MN66 is connected to the control line AZL, and the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN67, and the other of the source and drain is connected to the power line VSS1. The gate of transistor MN67 is connected to the control line DSL, and the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN66, and the other of the source and drain is connected to the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to one of the source and drain of transistor MN67, and its cathode is connected to the power line Vcath. Alternatively, transistor MN67 and control line DSL may be omitted, and one of the source and drain of transistor MN65 may be connected to the other of the source and drain of transistor MN66, and to the anode of the light-emitting element EL.

[0162] In this configuration, at least one of transistors MN63 and MP64 is turned on in the pixel PIX, setting the voltage across capacitors C61 and C62 based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal from control line DSL. Transistor MN65 supplies a current to the light-emitting element EL corresponding to the voltage across capacitors C61 and C62 during the period when transistor MN67 is on. The light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal from control line AZL. Transistor MN66 may also function as a resistive element having a resistance value corresponding to the signal from control line AZL. In this case, transistors MN65 and MN66 constitute a so-called source follower circuit.

[0163] Transistors MN63, MP64, and MN65-MN67 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MN63, MP64, and MN66 may be a transistor made of oxide semiconductor. Furthermore, one of the source and drain of transistor MN66 may be connected to the power line Vcath to which the cathode of the light-emitting element EL is connected, instead of the power line VSS1.

[0164] (Configuration Example 9) Figure 41 shows another configuration example of a pixel PIX. This pixel PIX has a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are N-type MOSFETs. The gate of transistor MN72 is connected to the control line WSL, the other of its source and drain is connected to the signal line SGL, and one of its source and drain is connected to one of the source and drain of transistor MN74 and the other of the source and drain of transistor MN75. One end of capacitor C71 is connected to the gate of transistor MN74 and one of the source and drain of transistor MN76, and the other end is connected to the other of the source and drain of transistor MN77, one of the source and drain of transistor MN75, and the anode of the light-emitting element EL. The gate of transistor MN73 is connected to control line DSL1, the other of its source and drain is connected to power line VCCP, and one of its source and drain is connected to the other of its source and drain of transistor MN74 and the other of its source and drain of transistor MN76. The gate of transistor MN74 is connected to one of its source and drain of transistor MN76 and one end of capacitor C71, the other of its source and drain is connected to one of its source and drain of transistor MN73 and the other of its source and drain of transistor MN76, and one of its source and drain is connected to one of its source and drain of transistor MN72 and the other of its source and drain of transistor MN75. The gate of transistor MN75 is connected to control line DSL2, the other of its source and drain is connected to one of the source and drain of transistor MN72 and one of the source and drain of transistor MN74, and one of its source and drain is connected to the other end of capacitor C71, the other of the source and drain of transistor MN77 and the anode of light-emitting element EL.The gate of transistor MN76 is connected to the control line AZSL, and the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN74, with one of its source and drain connected to the gate of transistor MN74 and one end of capacitor C71. The gate of transistor MN77 is connected to the control line AZSL, and the other of its source and drain is connected to the other end of capacitor C71, one of the source and drain of transistor MN75 and the anode of light-emitting element EL, with one of its source and drain connected to the power line VSS. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN75, the other of the source and drain of transistor MN77 and the other end of capacitor C71, and its cathode is connected to the power line Vcath.

[0165] In this configuration, in the pixel PIX, the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL when transistors MN72, MN74, and MN76 are turned on. Transistor MN73 is turned on and off based on the signal from control line DSL1, and transistor MN75 is turned on and off based on the signal from control line DSL2. Transistor MN74 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C71 while transistors MN73 and MN75 are turned on. The light-emitting element EL emits light based on the current supplied from transistor MN74. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistor MN77 is turned on and off based on the signal from control line AZSL. While transistor MN77 is turned on, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of power line VSS.

[0166] Transistors MN72 to MN77 may be transistors made of low-temperature polycrystalline silicon (LTPS). Transistor MN76 may be a transistor made of oxide semiconductor. In addition, one of the source and drain of transistor MN77 may be connected to the power line Vcath to which the cathode of the light-emitting element EL is connected, instead of the power line VSS.

[0167] <10. Modifications> Although embodiments of this technology have been described in detail above, the content of this technology is not limited to the embodiments described above, and various modifications are possible based on the technical concept of this technology. For example, the configurations, methods, processes, materials, shapes, and numerical values ​​of the embodiments described above can be combined or replaced with each other, as long as they do not deviate from the spirit of this technology. It is also possible to divide one thing into two or more, and to omit parts of it. Furthermore, if this technology is applicable, each of the above-described configurations may be deleted, changed, or replaced with other configurations as appropriate, or replaced with alternative configurations. In addition, this technology may be a combination of the technologies described in each of the embodiments described above, to the extent possible.

[0168] For example, in the first to fourth embodiments, examples were given in which the duration of one horizontal period in the peripheral region is shortened compared to the original duration, and the duration of one horizontal period in the central region is lengthened by the same amount, in order to achieve higher resolution and higher frame rates. In the fifth embodiment, examples were given in which the duration of one horizontal period in both the central and peripheral regions is shortened compared to the original duration, in order to achieve higher resolution and higher frame rates. However, this technology is not limited to adjusting the duration of one horizontal period in this way; it may also be driven while maintaining the original duration of one horizontal period. Even in this case, the writing time and number of write cycles are reduced, thus enabling lower power consumption. Thus, this technology can be applied to various technologies that can achieve lower power consumption by controlling the writing by the amplifier switch circuit 8a on a sub-pixel basis.

[0169] For example, in the embodiments described above, a single viewer such as a near-eye display was assumed, but the system is not limited to this, and there may be multiple viewers, such as when watching a television. In the case of multiple viewers, for example, a central area can be set for each viewer, and a peripheral area can be set for each of them to operate accordingly. Thus, the display device 1 may be configured to operate assuming multiple independent central areas.

[0170] For example, as a technique to shorten the time of one horizontal period, in the first embodiment described above, the writing time of the signal voltage Vsig was adjusted, and in the second embodiment, the writing time of the offset voltage Vofs was adjusted. However, the time to adjust the writing is not limited to these, and other writing times that arise depending on the pixel configuration example and operation example may be adjusted.

[0171] For example, this technology can be applied to various displays. This technology can be applied to display panels such as SXRD (Silicon X-tal Reflective Display: registered trademark) used in projectors, and to phase-modulated panels using SLM (Spatial Light Modulator) for hologram display. Furthermore, this technology can be applied to panels such as LCOS (Liquid Crystal On Silicon, LCoS is a trademark) and HTPS (High Temperature Poly-Silicon).

[0172] For example, in the embodiment described above, the horizontal driver 10 is shown to output a pixel signal representing brightness using voltage to the pixel unit 9. However, the horizontal driver 10 may also output a pixel signal representing brightness using current. In other words, the horizontal driver 10 acts as a current source (voltage source in the embodiment described above) when generating the pixel signal.

[0173] Figure 42 shows an example configuration of a pixel PIX when this current-based adjustment is performed. This pixel PIX has a capacitor C81, transistors MP81 to MP84, and a light-emitting element EL. Transistors MP81 to MP84 are P-type MOSFETs. The gate of transistor MP81 is connected to the control line WSL and the gate of transistor MP84, one of its source and drain is connected to the signal line SGL, and the other of its source and drain is connected to one end of capacitor C81, the other of its source and drain of transistor MP82, and one of its source and drain of transistor MP83. One end of capacitor C81 is connected to the other of its source and drain of transistors MP81 and MP82, and one of its source and drain of transistor MP83, and the other end is connected to the gate of transistor MP83 and one of its source and drain of transistor MP84. The gate of transistor MP82 is connected to the control line DSL, one of its source and drain is connected to the power line VCCP, and the other of its source and drain is connected to one end of capacitor C81, the other of the source and drain of transistor MP81, and one of the source and drain of transistor MP83. The gate of transistor MP83 is connected to the other end of capacitor C81 and one of the source and drain of transistor MP84, one of its source and drain is connected to one end of capacitor C81, the other of the source and drain of transistors MP81 and MP82, and the other of its source and drain is connected to the other of the source and drain of transistor MP84 and the anode of the light-emitting element EL. The gate of transistor MP84 is connected to the control line WSL and the gate of transistor MP81, one of its source and drain is connected to the other end of capacitor C81 and the gate of transistor MP83, and the other of its source and drain is connected to the other of the source and drain of transistor MP83 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to the other of the source and drain of transistors MP83 and MP84, and the cathode is connected to the power line Vcath.Furthermore, the signal line SGL is supplied with a signal (IDATA) from the horizontal driver 10 indicating a current value corresponding to the brightness.

[0174] In this configuration, at the pixel PIX, transistor MP82 is turned off, followed by transistors MP81 and MP84 being turned on. Then, a pixel signal of pixel current IData corresponding to the pixel is supplied from the signal line SGL, and transistors MP81 and MP84 are turned off again. As a result, the voltage across the capacitor C81 is set based on the pixel signal supplied from the signal line SGL. Transistor MP83 supplies a current to the light-emitting element EL corresponding to the voltage across the capacitor C81 while transistor MP82 is on. The light-emitting element EL emits light based on the current supplied from transistor MP83. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal.

[0175] Furthermore, transistors MP81 to MP84 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP81 or MP84 may be a transistor made of oxide semiconductor.

[0176] <11. Application Examples> Next, application examples of the display device 1 described in the above embodiments and modified examples will be explained.

[0177] (Application Example 1) Figure 43 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, a glasses-shaped display unit 111 and ear hooks 112 on both sides for attachment to the user's head. The technology according to the above embodiment can be applied to such a head-mounted display 110.

[0178] (Application Example 2) Figure 44 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a transmissive head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. This display unit emits image light of the displayed image. The arm 122 connects the main body 121 and the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 towards the user's eyes through the lenses 129 of the eyeglasses 128. The technology according to the above embodiment can be applied to such a head-mounted display 120.

[0179] This head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this; for example, it may be a so-called birdbath type head-mounted display. This birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0180] (Application Example 3) Figures 45A and 45B show an example of the external appearance of a digital still camera 130, with Figure 45A showing a front view and Figure 45B showing a rear view. This digital still camera 130 is a single-lens reflex type camera with interchangeable lenses and comprises a camera body 131, an imaging lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The imaging lens unit 132 is an interchangeable lens unit and is located approximately in the center of the front of the camera body 131. The grip 133 is located on the left side of the front of the camera body 131, and the photographer holds this grip 133. The monitor 134 is located to the left of approximately the center of the rear of the camera body 131. The electronic viewfinder 135 is located on the rear of the camera body 131, above the monitor 134. The photographer can look through the electronic viewfinder 135 to see the light image of the subject guided by the shooting lens unit 132 and determine the composition. The technology according to the above embodiment can be applied to the electronic viewfinder 135.

[0181] (Application Example 4) Figure 46 shows an example of the appearance of a television device 140. The television device 140 has an image display screen section 141 including a front panel 142 and a filter glass 143. The technology according to the above embodiments can be applied to this image display screen section 141.

[0182] (Application Example 5) Figure 47 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like for receiving user input. The technology according to the above embodiment can be applied to this display unit 151.

[0183] (Application Example 6) Figures 48A and 48B show an example of a vehicle configuration to which the technology of this disclosure is applied. Figure 48A shows an example of the interior of the vehicle as seen from the rear of the vehicle 200, and Figure 48B shows an example of the interior of the vehicle as seen from the left rear of the vehicle 200.

[0184] The vehicle in Figures 48A and 48B has a center display 201, a console display 202, a head-up display 203, a digital rear mirror 204, a steering wheel display 205, and a rear entertainment display 206.

[0185] The center display 201 is located on the dashboard 261, facing the driver's seat 262 and the passenger seat 263. Figure 48A shows an example of a horizontally elongated center display 201 extending from the driver's seat 262 to the passenger seat 263, but the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display images captured by an image sensor, distance images to obstacles in front of and to the side of the vehicle measured by a ToF sensor, and the body temperature of occupants detected by an infrared sensor. The center display 201 can be used to display at least one of the following: safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information.

[0186] Safety-related information includes data based on sensor detection results, such as drowsiness detection, distraction detection, detection of mischief by passengers, seatbelt usage status, and detection of unattended occupants. Operation-related information includes information on occupant gestures detected using sensors. Gestures may include operation of various in-vehicle equipment, such as air conditioning, navigation systems, AV (Audio Visual) systems, and lighting systems. Lifelogs include the lifelogs of all occupants. For example, lifelogs include records of each occupant's actions. By acquiring and saving lifelogs, it is possible to check the condition of occupants in the event of an accident. Health-related information includes the occupant's body temperature detected using temperature sensors, and information on the occupant's health status inferred from the detected body temperature. Alternatively, information on the occupant's health status may be inferred based on the occupant's face captured by an image sensor. Furthermore, information on the occupant's health status may be inferred based on the occupant's responses obtained by conversing with the occupant using automated voice. Authentication / identification-related information includes information such as keyless entry functions that use sensors for facial recognition and functions that automatically adjust seat height and position based on facial recognition. Entertainment-related information includes information on AV equipment operation by occupants detected by sensors, and information on content to be displayed that is appropriate for occupants detected and recognized by sensors.

[0187] The console display 202 can be used, for example, to display life log information. The console display 202 is located near the shift lever 265 in the center console 264 between the driver's seat 262 and the passenger seat 263. The console display 202 can also display information detected by various sensors. In addition, the console display 202 may display images of the area around the vehicle captured by an image sensor, or it may display distance images to obstacles around the vehicle.

[0188] The head-up display 203 is virtually displayed behind the windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 203 is often virtually positioned in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as vehicle speed, fuel level, and battery level.

[0189] The digital rearview mirror 204 can not only display the area behind the vehicle, but also show the condition of the rear-seat passengers. Therefore, it can be used, for example, to display life log information of rear-seat passengers.

[0190] The steering wheel display 205 is positioned near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of the following: safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, or information related to the operation of AV equipment, air conditioning equipment, etc.

[0191] The rear entertainment display 206 is mounted on the back of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear-seat passengers. The rear entertainment display 206 can be used to display at least one of the following: safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the rear entertainment display 206 is in front of the rear-seat passengers, it displays information relevant to the rear-seat passengers. For example, the rear entertainment display 206 may display information related to the operation of AV equipment or air conditioning equipment, or it may display the results of temperature sensor measurements of the rear-seat passengers' body temperature, etc.

[0192] The technologies described in the above embodiments can be applied to these center displays 201, console displays 202, head-up displays 203, digital rear mirrors 204, steering wheel displays 205, and rear entertainment displays 206.

[0193] Furthermore, this technology can also be configured as follows: (1) A display device having multiple pixels, wherein the time required to write the pixel signal supplied to the pixel circuit constituting the pixels in an area where the viewer is not affected by changes in image quality is shorter than the time required for the actual writing required for writing the pixel signal. (2) The display device according to (1), wherein the area is a peripheral area corresponding to the viewer's peripheral field of vision. (3) The display device according to (1) or (2), wherein the time of one horizontal period in the area is shorter than the time of one horizontal period for the actual writing. (4) The display device according to any one of (1) to (3), having a switch that switches the writing state of the pixel signal to the pixel circuit between an ON state in which the pixel signal is supplied to the pixel circuit and an OFF state in which the pixel signal is not supplied to the pixel circuit, and controlling the switch to control the writing of the pixel signal to the pixel circuit. (5) The display device according to any one of (1) to (4), wherein the pixel signal is a signal based on the output of an amplifier. (6) The pixel signal is a signal representing the gradation level of luminescence brightness corresponding to the display image of the pixel circuit. The display device according to any one of (1) to (5). (7) The display device according to any one of (1) to (6), wherein the writing time for writing the pixel signal to the pixel circuit is shorter than the writing time required for the original writing. (8) The display device according to (7), wherein the pixel is composed of multiple types of subpixel pixel circuits, and the writing time is shorter for each type of subpixel. (9) The display device according to (7), wherein the pixel is composed of multiple types of subpixel pixel circuits, and the writing time is uniformly shorter for all multiple types of subpixels. (10) The display device according to any one of (1) to (9), wherein the pixel signal is not written to the pixel circuit that writes the pixel signal in the original writing. (11) The display device according to (10), wherein the pixel is composed of multiple types of subpixel pixel circuits, and the pixel signal is not written to one or more of the subpixel pixel circuits.(12) The display device according to (10) or (11), wherein the light emission of a pixel circuit that does not write the pixel signal is controlled in accordance with the change in brightness due to not writing. (13) The display device according to any one of (1) to (12), wherein the pixel circuit has a drive transistor that drives a light-emitting element, and the pixel signal is a signal that writes an offset voltage used to correct the threshold voltage of the drive transistor. (14) The display device according to any one of (1) to (13), wherein the pixel is composed of a plurality of subpixel pixel circuits, and the pixel signal is written simultaneously to a plurality of the subpixel pixel circuits. (15) The display device according to any one of (1) to (14), wherein the switching time between continuous writing operations of the pixel signal is smaller than the switching time included in the time required for the original writing. (16) The display device according to any one of (1) to (15), wherein the operation to reduce the time required for writing the pixel signal is changed in the spatial direction of the display area. (17) A display device according to any one of (1) to (16), wherein the operation to reduce the time required to write the pixel signal is varied in the time direction. (18) A display device according to any one of (1) to (17), wherein the region includes a central region corresponding to the central field of view of the viewer. (19) A display device according to any one of (5) to (18), wherein the performance of the amplifier is reduced. (20) A display device according to any one of (5) to (19), wherein the output of the amplifier is overdriven according to the settling time. (21) A display device according to any one of (1) to (20), wherein the pixels are arranged in a plurality along a first direction and a second direction intersecting the first direction, the operation to reduce the time required to write the pixel signal in the first direction of the region is performed, and the same pixel signal is written simultaneously to a plurality of pixel circuits in the second direction of the region. (22) A display device according to any one of (13) to (21), wherein a signal representing the gradation level of the luminescence brightness corresponding to the display image of the pixel circuit is corrected according to the brightness difference of the light-emitting element and written to the pixel circuit. (23) An electronic device having a display device according to any one of (1) to (22).

[0194] 1...Display device, 2...Display controller, 3...Display panel, 4...Vertical driver, 6...Write control unit, 7...Source amplifier unit, 7a...Source amplifier, 8...Amplifier switch unit, 8a...Amplifier switch circuit, PIX...Pixel circuit

Claims

1. A display device having multiple pixels, wherein the time required to write the pixel signal supplied to the pixel circuit constituting the pixels in an area where the viewer is not affected by changes in image quality is less than the time required for the actual writing of the pixel signal.

2. The display device according to claim 1, wherein the region is a peripheral region corresponding to the peripheral field of view of the viewer.

3. The display device according to claim 1, wherein the time of one horizontal period in the region is shorter than the time of one horizontal period of the original writing.

4. The display device according to claim 1, which has a switch that switches the writing state of the pixel signal to the pixel circuit between an ON state in which the pixel signal is supplied to the pixel circuit and an OFF state in which the pixel signal is not supplied to the pixel circuit, and controls the writing of the pixel signal to the pixel circuit by controlling the switch.

5. The display device according to claim 1, wherein the pixel signal is a signal based on the output of an amplifier.

6. The display device according to claim 1, wherein the pixel signal is a signal representing the gradation level of luminescence brightness corresponding to the display image of the pixel circuit.

7. The display device according to claim 1, wherein the writing time for writing the pixel signal to the pixel circuit is shorter than the writing time required for the original writing.

8. The display device according to claim 7, wherein the pixel is configured to include a pixel circuit of multiple types of subpixels, and the writing time is shorter for each type of subpixel.

9. The display device according to claim 7, wherein the pixel is configured to include a pixel circuit of a plurality of types of subpixels, and the writing time is uniformly short for the plurality of types of subpixels.

10. The display device according to claim 1, wherein the pixel signal is not written to the pixel circuit that writes the pixel signal in the original writing process.

11. The display device according to claim 10, wherein the pixel is configured to include a plurality of subpixel pixel circuits, and the pixel signal is not written to one or more of the subpixel pixel circuits.

12. The display device according to claim 10, wherein the light emission of a pixel circuit that does not write the pixel signal is controlled in accordance with the change in brightness due to not writing.

13. The display device according to claim 1, wherein the pixel circuit has a drive transistor for driving a light-emitting element, and the pixel signal is a signal for writing an offset voltage used to correct the threshold voltage of the drive transistor.

14. The display device according to claim 1, wherein the pixel is configured to include a plurality of subpixel pixel circuits, and the pixel signal is written simultaneously to a plurality of the subpixel pixel circuits.

15. The display device according to claim 1, wherein the switching time between continuous writing operations of the pixel signal is smaller than the switching time included in the time required for the original writing.

16. The display device according to claim 1, wherein the operation to reduce the time required to write the pixel signal is varied in the spatial direction of the display area.

17. The display device according to claim 1, wherein the operation to reduce the time required to write the pixel signal is varied in the time direction.

18. The display device according to claim 1, wherein the region includes a central region corresponding to the central field of vision of the viewer.

19. The display device according to claim 5, which reduces the performance of the amplifier.

20. Electronic device having the display device described in claim 1.

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