Regression analysis-based circuit characteristic optimization device and method for digital circuit design

Abstract

According to various embodiments of the present invention, a regression analysis-based circuit characteristic optimization device for digital circuit design may: receive, from the outside, information about a digital circuit to be designed, and arbitrarily set a characteristic value for at least one transistor included in the digital circuit; generate a circuit characteristic regression model by mathematically modeling the characteristic of a path included in the digital circuit on the basis of the characteristic value of the transistor included in the digital circuit; obtain an initial coefficient of the circuit characteristic regression model by applying the arbitrarily set characteristic value thereto; and obtain the improved characteristic value for the at least one transistor included in the digital circuit on the basis of the circuit characteristic regression model into which the initial coefficient has been incorporated.

Description

Regression analysis-based circuit characteristic optimization device and method for digital circuit design

[0001] The present invention relates to a device and method for optimizing circuit characteristics based on regression analysis for digital circuit design.

[0002] The research related to the present invention is related to the research project 'Core Development of PIM AI Semiconductor (No. RS-2023-00222085)', which was conducted with funding from the Ministry of Science and ICT and support from the Korea Institute of Information and Communication Technology Planning and Evaluation, and the lead organization is the Yonsei University Industry-Academic Cooperation Foundation. The research project title is 'Development of Memory Module and Memory Compiler for Non-Volatile PIM Optimized for Data Characteristics and Data Access Characteristics of AI Processors', and the research period is from April 1, 2023 to December 31, 2026.

[0003] In addition, the research related to the present invention is related to the 'Nano Device Application Research Institute (No. 2018R1A6A1A03025242)', which is a Basic Research Project in Science and Engineering, Basic Research Infrastructure Establishment Project, and University Key Research Institute Support Project funded by the Ministry of Education and supported by the National Research Foundation of Korea, and the lead institution is the Industry-Academic Cooperation Foundation of Kwangwoon University. The research period is from June 1, 2018 to February 28, 2027.

[0004] Finally, the research related to the present invention is related to the 'Research and Development of Neuro-chip Design Technology Mimicking the Human Nervous System and Neuro-computing Platform (No. 2710007997)', a University ICT Research Center Development Support Project funded by the Ministry of Science and ICT and supported by the Korea Institute of Information and Communication Technology Planning and Evaluation, and the lead organization is the Industry-Academic Cooperation Foundation of Kwangwoon University. The research period is from January 1, 2024 to December 31, 2024.

[0005] The content described in this section merely provides background information regarding the present embodiment and does not constitute prior art.

[0006] Regression analysis is a major technique used in statistics and machine learning to model the relationship between independent and dependent variables. Through this, it is possible to understand data patterns and predict the value of the dependent variable based on the given value of the independent variable. Regression analysis focuses on mathematically explaining the correlation between variables based on data.

[0007] The basic types of regression analysis are divided into simple regression and multiple regression. Simple regression is used to explain the relationship between a single independent variable and a single dependent variable and is based on linear equations. Multiple regression models more complex relationships by including multiple independent variables. In addition, various variations exist, such as non-linear regression, logistic regression, and ridge regression, and the appropriate method is selected depending on the characteristics of the data.

[0008] Regression analysis is useful not only for prediction but also for understanding interactions between variables, identifying important variables, and evaluating the fit of a model. It supports data-driven decision-making and is utilized in various fields such as economics, medicine, and marketing. However, when using regression analysis, it is crucial to ensure the reliability of the model by examining the data distribution and assumptions.

[0009] (Patent Document 0001) Republic of Korea Published Patent Application No. 10-2024-0013343 (January 30, 2024)

[0010] The objective of the present invention is to provide a regression analysis-based circuit characteristic optimization apparatus and method for digital circuit design that can minimize delay by optimizing the characteristic values ​​of transistors in digital circuit design, thereby maximizing the performance and efficiency of the circuit.

[0011] Other unspecified objects of the present invention may be further considered to the extent that they can be easily inferred from the following detailed description and effects.

[0012] A regression analysis-based circuit characteristic optimization device for digital circuit design according to an embodiment of the present invention for achieving the above-described purpose comprises: a memory storing one or more programs for designing a digital circuit; and one or more processors performing operations according to the one or more programs. The processor receives information about a digital circuit to be designed from an external source, arbitrarily determines a characteristic value for each of at least one transistor included in the digital circuit, mathematically models the characteristics of a path included in the digital circuit based on the characteristic value of the transistor included in the digital circuit to generate a circuit characteristic regression model, applies the arbitrarily determined characteristic value to the circuit characteristic regression model to obtain initial coefficients of the circuit characteristic regression model, and obtains an improved characteristic value for each of at least one transistor included in the digital circuit based on the circuit characteristic regression model reflecting the initial coefficients.

[0013] The characteristic value for the above transistor is characterized as the width of the transistor.

[0014] The processor is characterized by performing a simulation using a characteristic value for each of at least one transistor included in the digital circuit to obtain a delay of each of the at least one path included in the digital circuit.

[0015] The processor is characterized by determining a critical path, which is the path with the greatest delay among the multiple paths, when there are multiple paths, and obtaining initial coefficients of a circuit characteristic regression model only for the critical path.

[0016] The processor is characterized by generating a circuit characteristic regression model for each of the paths and obtaining initial coefficients for each of the circuit characteristic regression models using the arbitrarily determined characteristic value or the delay of the path.

[0017] The above processor is characterized by calculating the minimum value of a circuit characteristic regression model reflecting the above initial coefficients, and determining the characteristic value of a transistor that causes the circuit characteristic regression model to achieve the minimum value as an improved characteristic value.

[0018] The processor is characterized by updating the circuit characteristic regression model based on the improvement characteristic value and obtaining an additional improvement characteristic value for each of at least one transistor included in the digital circuit based on the updated circuit characteristic regression model.

[0019] The above processor is characterized by determining the last additional improvement characteristic value as the final improvement characteristic value and terminating the operation when the additional improvement characteristic value is acquired more than a predetermined reference number of times.

[0020] The processor is characterized by obtaining improvement characteristic values ​​for each of at least one transistor included in the digital circuit as a set, based on a circuit characteristic regression model that reflects the initial coefficients.

[0021] The processor can divide the digital circuit into at least two blocks based on information about the digital circuit being designed received from the outside, arbitrarily determine a characteristic value for each of at least one transistor included in each of the at least two blocks, generate a circuit characteristic regression model by mathematically modeling the characteristics of a path included in the block based on the characteristic value of the transistor included in the block, obtain initial coefficients of the circuit characteristic regression model by applying the arbitrarily determined characteristic value to the circuit characteristic regression model, and obtain an improved characteristic value for each of at least one transistor included in the block based on the circuit characteristic regression model reflecting the initial coefficients.

[0022] A method performed in a device comprising a memory storing one or more programs for designing a digital circuit according to an embodiment of the present invention for achieving the above-described purpose and one or more processors performing operations according to said one or more programs may include: receiving information about a digital circuit to be designed from an external source and arbitrarily determining a characteristic value for each of at least one transistor included in said digital circuit; generating a circuit characteristic regression model by mathematically modeling the characteristics of a path included in said digital circuit based on the characteristic value of the transistor included in said digital circuit; applying the arbitrarily determined characteristic value to said circuit characteristic regression model to obtain an initial coefficient of said circuit characteristic regression model; and obtaining an improved characteristic value for each of at least one transistor included in said digital circuit based on the circuit characteristic regression model reflecting the initial coefficient.

[0023] The step of arbitrarily determining a characteristic value for each of at least one transistor included in the digital circuit is characterized by performing a simulation using the characteristic value for each of at least one transistor included in the digital circuit to obtain a delay of the path for each of at least one path included in the digital circuit.

[0024] When there are multiple paths, the step of generating a circuit characteristic regression model by mathematically modeling the characteristics of a path included in the digital circuit based on the characteristic values ​​of a transistor included in the digital circuit is characterized by determining a critical path which is the path with the largest delay among the multiple paths, and the step of obtaining initial coefficients of the circuit characteristic regression model by applying the arbitrarily determined characteristic values ​​to the circuit characteristic regression model, wherein the initial coefficients of the circuit characteristic regression model are obtained only for the critical path.

[0025] The step of arbitrarily determining a characteristic value for each of at least one transistor included in the digital circuit is characterized by generating a circuit characteristic regression model for each of the paths and obtaining the initial coefficients for each of the circuit characteristic regression models using the arbitrarily determined characteristic value or the delay of the path.

[0026] A computer program according to one embodiment of the present invention for achieving the above-described purpose is stored on a computer-readable recording medium and executes any one of the regression analysis-based circuit characteristic optimization methods for digital circuit design described above on a computer.

[0027] As described above, according to one embodiment of the present invention, by applying a regression analysis-based circuit characteristic optimization device and method for digital circuit design, the characteristic value of a transistor in digital circuit design can be optimized to minimize delay, thereby maximizing the performance and efficiency of the circuit.

[0028] Even if an effect is not explicitly mentioned herein, the effects and potential effects described in the following specification expected by the technical features of the present invention are treated as described in the specification of the present invention.

[0029] FIG. 1 is a flowchart illustrating a regression analysis-based circuit characteristic optimization method for digital circuit design according to one embodiment of the present invention.

[0030] FIG. 2 is a flowchart illustrating a regression analysis-based circuit characteristic optimization method for digital circuit design according to another embodiment of the present invention.

[0031] FIG. 3 is a diagram illustrating the blocking process of a digital circuit performed in a regression analysis-based circuit characteristic optimization device for digital circuit design according to an embodiment of the present invention.

[0032] FIG. 4 is a flowchart illustrating a regression analysis-based circuit characteristic optimization method for digital circuit design according to another embodiment of the present invention.

[0033] FIG. 5 is a diagram showing the optimization results obtained by applying a regression analysis-based circuit characteristic optimization method for digital circuit design according to an embodiment of the present invention.

[0034] FIG. 6 is a diagram showing the hardware configuration of a regression analysis-based circuit characteristic optimization device for digital circuit design according to one embodiment of the present invention.

[0035] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The advantages and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the attached drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Unless otherwise defined, all terms used in this specification (including technical and scientific terms) may be used in a meaning that is commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0036] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, terms such as “have,” “may have,” “include,” or “may include” are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Terms including ordinal numbers, such as “second,” “first,” etc., may be used to describe various components, but said components are not limited by said terms.

[0037] The above terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0038] In this specification, identification symbols (e.g., a, b, c, etc.) for each step are used for convenience of explanation and do not indicate the order of the steps; the steps may occur differently from the specified order unless the context clearly indicates a specific order. That is, the steps may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

[0039] This specification describes a machine learning-based optimization methodology for digital circuit design utilizing a circuit-specific regression model.

[0040] The present invention relates to a methodology for optimizing the delay of a digital circuit with less computational power by utilizing machine learning with specialized regression models for design elements that need to be modified based on the designer's experience and knowledge.

[0041] This invention enables accurate delay prediction with fewer training iterations compared to other machine learning models without prior information, through a circuit-specific regression analysis model that considers circuit characteristics. This mitigates the disadvantage of requiring a very large amount of data, which is a problem caused by the high dimensionality of larger circuits. Consequently, effective delay optimization of digital circuits can be performed with less computation time.

[0042] This technology can be applied to products such as digital logic circuits. Additionally, there is potential for partial application in various products, including mobile phones, wireless earphones, IoT home appliances, computers, and autonomous vehicles.

[0043] The demand for integrated circuits is continuously expanding as the use of cutting-edge systems, such as high-performance computers and mobile phones, increases. In particular, delay optimization in integrated circuits can play a significant role in the relevant market by providing faster performance and computing capabilities.

[0044] Various embodiments of the regression analysis-based circuit characteristic optimization apparatus and method for digital circuit design according to the present invention will be described in detail below with reference to the attached drawings.

[0045] FIG. 1 is a flowchart illustrating a regression analysis-based circuit characteristic optimization method for digital circuit design according to one embodiment of the present invention.

[0046] A regression analysis-based circuit characteristic optimization method for digital circuit design can be performed in a device comprising a memory that stores one or more programs for designing a digital circuit and one or more processors that perform operations according to one or more programs. For example, a regression analysis-based circuit characteristic optimization method for digital circuit design can be performed by a regression analysis-based circuit characteristic optimization device for digital circuit design described through FIG. 6.

[0047] In step S110, the processor receives information about the digital circuit to be designed from an external source and can arbitrarily determine the characteristic value for each of at least one transistor included in the digital circuit.

[0048] Information regarding digital circuits may refer to specific data concerning the structure and characteristics of the circuit required for digital circuit design and optimization. Information regarding digital circuits may include the circuit's functional design, components, connection relationships, and performance constraints. For example, information regarding digital circuits may include the location, width, length, operating voltage, clock speed, signal path information, input and output conditions, and delay requirements of each transistor. Furthermore, it may include technical files such as design code written in Hardware Description Language (HDL), circuit layout information, and SPICE simulation data, as well as the circuit diagram itself, which represents the overall operation of the digital circuit and the interactions between its components.

[0049] A characteristic value for a transistor can be the width of the transistor.

[0050] In step S120, the processor can generate a circuit characteristic regression model by mathematically modeling the characteristics of a path included in a digital circuit based on the characteristic values ​​of a transistor included in the digital circuit.

[0051] Here, the characteristic of the path can mean delay.

[0052] In step S130, the processor can obtain initial coefficients of the circuit characteristic regression model by applying randomly determined characteristic values ​​to the circuit characteristic regression model.

[0053] In step S140, the processor can obtain an improved characteristic value for each of at least one transistor included in the digital circuit based on a circuit characteristic regression model that reflects the initial coefficients.

[0054] In step S110, the processor can obtain a path delay for each of at least one path included in the digital circuit by performing a simulation using the characteristic value for each of at least one transistor included in the digital circuit.

[0055] If there are multiple paths, in step S120, the processor determines the critical path which is the path with the greatest delay among the multiple paths, and in step S130, the processor can obtain the initial coefficients of the circuit characteristic regression model only for the critical path.

[0056] In step S120, the processor can generate a circuit characteristic regression model for each path and obtain initial coefficients for each circuit characteristic regression model using an arbitrarily determined characteristic value or a path delay.

[0057] In step S140, the processor can calculate the minimum value of the circuit characteristic regression model reflecting the initial coefficients and determine the characteristic value of the transistor that makes the circuit characteristic regression model achieve the minimum value as the improved characteristic value.

[0058] In step S140, the processor can obtain improvement characteristic values ​​for each of at least one transistor included in the digital circuit as a set based on a circuit characteristic regression model that reflects initial coefficients.

[0059] Following step S140, the processor updates the circuit characteristic regression model based on the improvement characteristic value, and can obtain additional improvement characteristic values ​​for each of at least one transistor included in the digital circuit based on the updated circuit characteristic regression model.

[0060] If the processor acquires additional improvement characteristic values ​​more than a predetermined threshold number of times, it can determine the last additional improvement characteristic value as the final improvement characteristic value and terminate the operation.

[0061] Characteristic values ​​are arbitrarily determined values ​​for each transistor included in a digital circuit, representing the transistor's width or other initial parameters required for design and simulation. Characteristic values ​​are used as inputs to calculate the initial coefficients of the Circuit Characteristic Regression Model (CDRM) and serve as the starting point for the initial circuit modeling and optimization process.

[0062] The improved characteristic value is a new characteristic value of the transistor calculated based on a circuit characteristic regression model that incorporates initial coefficients. The improved characteristic value is obtained by optimizing the regression model based on the initial characteristic value and represents the result of improving the transistor width value with the goal of minimizing delay.

[0063] The additional improvement characteristic value is an additionally optimized characteristic value derived from a circuit characteristic regression model updated based on the improvement characteristic value. The additional improvement characteristic value is calculated through iterative learning and simulation processes and represents a transistor width that is more precisely optimized than the previous improvement characteristic value.

[0064] The final improved characteristic value is the final transistor characteristic value derived by satisfying a predetermined number of iterations or meeting the termination condition. The final improved characteristic value is set based on the last value obtained among the additional improved characteristic values ​​and represents the transistor width at the point when the circuit characteristic regression model reaches an optimal state.

[0065] Prior to step S110, the processor may divide the digital circuit into at least two blocks based on information about the digital circuit being designed, which is received from an external source. Subsequently, the processor may perform operations from step S110 on the divided blocks. That is, for each of the at least two blocks, the processor may arbitrarily determine a characteristic value for each of at least one transistor included in the block, mathematically model the characteristics of the path included in the block based on the characteristic value of the transistor included in the block to generate a circuit characteristic regression model, apply the arbitrarily determined characteristic value to the circuit characteristic regression model to obtain initial coefficients of the circuit characteristic regression model, and obtain an improved characteristic value for each of at least one transistor included in the block based on the circuit characteristic regression model reflecting the initial coefficients.

[0066] The present invention relates to a method for designing a minimum delay circuit by optimizing the width, which is one of the design elements of a transistor, using a regression analysis model, which is a machine learning technique. Regression analysis is an analytical method that predicts unexperimented results by utilizing experimental data. By training a model using delay as a result value, design elements capable of creating the minimum delay are predicted. In the present invention, by utilizing capacitance and current, which significantly affect circuit delay, a more accurate delay can be predicted through less model training, thereby enabling the identification of the widths of transistors that have the smallest delay.

[0067] In digital circuits, delay is determined by capacitance and current. Delay is proportional to capacitance and inversely proportional to current. Capacitance is proportional to the width of the transistor, and current is also proportional to the width of the transistor. By utilizing this, delay can be expressed in terms of the transistor widths.

[0068] The delay in a digital circuit is α / width of the width of the transistor through which current flows TR There is a relationship, and β / width for the width of all transistors TR There is a relationship. As shown in Equation 1 below, a model that expresses the delay of a single path in terms of transistor widths is called the Circuit Delay Regression Model (CDRM). A CDRM having a minimum value can mean that the delay of the corresponding path has a minimum value.

[0069] That is, in the present invention, the characteristics of a circuit or the characteristics of a path may refer to a delay, and the circuit characteristic regression model may refer to a Circuit Delay Regression Model (CDRM).

[0070]

[0071] Here, width TRi can refer to a transistor through which current passes within a path, and width TRj represents all transistors within a digital circuit. a is a coefficient multiplied by the width of the transistor, which represents the direct effect of the width of each transistor on the delay. b is a coefficient multiplied by the reciprocal of the transistor width, which represents the indirect effect of the reciprocal of the width on the delay. This primarily reflects effects related to current. C is a constant term, which represents a fixed base delay occurring in the circuit regardless of the transistor width. All coefficients described herein may refer to a, b, or C as described in Equation 1.

[0072] Equation 1 models the delay occurring in a specific path of a digital circuit using terms related to transistor widths. The first term is the sum of values ​​obtained by multiplying the width of the transistors through which current passes within the specific path by the coefficient 'a', representing the direct effect of transistor width on the delay. The second term is the sum of values ​​obtained by multiplying the reciprocal of the width of all transistors included in the entire digital circuit by the coefficient 'b', modeling the indirect effect of the reciprocal of the width on the delay. Finally, the constant C represents a fixed delay value that occurs independently of the width. Equation 1 enables optimization by mathematically expressing the circuit delay.

[0073] The coefficient 'a' is a value directly related to the transistors through which current passes within a specific path. It represents the direct influence of the width of each transistor in that path on path delay and numerically reflects the characteristics of the individual transistors within the path. Since it is calculated for a different set of transistors for each path, the coefficient 'a' models the path-specific delay characteristics.

[0074] The coefficient b is a value associated with all transistors included in the entire digital circuit. Multiplying by the reciprocal of the transistor width, coefficient b represents the indirect effect of changes in width on the delay throughout the digital circuit. Coefficient b models the collective contribution of all transistors within the circuit and mathematically describes the overall circuit delay characteristics by reflecting the inverse relationship between current and width.

[0075] The constant C represents a fundamental fixed delay value occurring throughout the entire path, regardless of transistor width. Constant C models a constant delay resulting from the structural characteristics of the digital circuit or environmental factors, independent of the specific transistor or path characteristics, and serves as a reference value for the regression model.

[0076] To optimize delay using CDRM, all paths corresponding to all input patterns must be modeled. Among the delays of each path, the slowest delay is called the critical delay, and the corresponding path is called the critical path. Equation 2 below represents the modeling of the critical path. By obtaining or updating the coefficients a, b, and C of the CDRM, it is possible to predict untested delay results and find the minimum delay.

[0077]

[0078] The processor can perform simulations to obtain or update the coefficients of the CDRM for delay optimization. The delay optimization process using the CDRM is as follows.

[0079] (1) The processor randomly sets the width of the transistors constituting the circuit to determine the initial coefficient of the CDRM, and extracts the delay result value for each of at least one path included in the digital circuit through simulation under the corresponding conditions.

[0080] (2) The processor can obtain or update the coefficients of the CDRM by performing learning based on the result value extracted in (1). Using the generated or updated CDRM, the delay corresponding to the untested transistor widths can be predicted.

[0081] (3) By finding the minimum value of CDRM, the processor can derive a transistor width set that minimizes the delay as an improved characteristic value or an additional improved characteristic value.

[0082] The process of the processor deriving an improvement characteristic value or an additional improvement characteristic value can be represented as shown in Equation 3 below.

[0083]

[0084] (4) The processor can perform a simulation with the transistor width set derived in (3) to calculate the delay, and based on this, can further update the CDRM.

[0085] (5) The processor can repeat the process from (2) to (4) through the updated CDRM. By setting an appropriate number of repetitions and repeating the process, a transistor width set that generates the minimum delay can be obtained and determined as the final improvement characteristic value.

[0086] The processor optimizes the circuit's delay using CDRM through the learning and exploration processes described above. More experimental data enables more accurate modeling, which allows for more precise delay optimization of digital logic circuits.

[0087] Equation 3 represents the process by which a processor analyzes the critical path of a digital circuit to derive a combination of transistor widths that minimizes delay—that is, an optimal set of transistor widths. The processor first calculates the CDRM value of the critical path and, based on this, calculates the minimum value of the CDRM to find the set of transistor widths that reaches that minimum value. In this process, the set of widths is composed of individual transistor widths and is optimized to minimize the delay of the critical path. Consequently, Equation 3 describes the process of deriving width combinations for delay optimization, and through iterative learning and optimization, the processor obtains the accurate optimal value.

[0088] FIG. 2 is a flowchart illustrating a regression analysis-based circuit characteristic optimization method for digital circuit design according to another embodiment of the present invention.

[0089] Figure 2 illustrates the step-by-step process of utilizing a Circuit Delay Regression Model (CDRM) for delay optimization of a digital circuit. This process performs iterative learning and optimization to improve circuit performance and consists of the following steps.

[0090] 1. Perform SPICE on a random width set and extract delay

[0091] The processor sets an initial random transistor width set and executes a SPICE simulation to extract delay data for each path under the corresponding conditions. This is a data collection step for generating an initial CDRM model. That is, the simulation used by the processor in this invention may be a simulation using SPICE (Simulation Program with Integrated Circuit Emphasis).

[0092] 2. CDRM fitting using delay data

[0093] The processor fits the coefficients of the CDRM model based on delay data extracted from SPICE. In this step, regression analysis is utilized to optimize the coefficients of the CDRM equation. The trained CDRM is modeled to predict delays even for unexperimented width combinations.

[0094] 3. Find the width set with the minimum value of the CDRM function

[0095] The processor uses a learned CDRM model to calculate the transistor width combination that minimizes the delay of the critical path. Mathematically, this can be expressed as argmin width (CDRM critical path It is represented as ), and in this process, the optimal width set with the minimum delay is derived.

[0096] 4. Perform SPICE with the found width set and extract delay

[0097] The optimized transistor width combination is reapplied to SPICE simulation to extract new delay data. This is a process of securing additional data necessary to update the existing CDRM model or improve accuracy.

[0098] 5. Check for repetition

[0099] The processor checks if the current number of iterations is less than a preset maximum number of iterations. If the current number of iterations is less than the maximum, the processor retrains the CDRM model using the data updated in the previous step and repeats the optimization process. Conversely, when the maximum number of iterations is reached, the final optimization result is obtained and the process terminates.

[0100] The processor incrementally improves the CDRM based on data and searches for the optimal transistor width combination that minimizes critical path delay. Through the entire process, the processor derives the optimized transistor width combination and effectively reduces circuit delay.

[0101] FIG. 3 is a diagram illustrating the blocking process of a digital circuit performed in a regression analysis-based circuit characteristic optimization device for digital circuit design according to an embodiment of the present invention.

[0102] Generally, digital circuits consist of a large number of transistors, so optimizing all the transistors constituting the circuit using the algorithm described in Figure 2 is an optimization problem in a very high-dimensional space, resulting in very high complexity. Therefore, a block-wise technique is used to optimize the entire circuit by dividing it into several blocks.

[0103] The processor can define a set of circuits that drive a specific node of a digital circuit as a single block. As shown in FIG. 3, by dividing the digital circuit (300) into multiple blocks (310, 320) based on a specific node, a high-dimensional problem can be mapped to a low-dimensional one, thereby allowing the problem to be solved with less complexity.

[0104] The processor can perform blocking based on logical criteria or blocking based on physical structure to divide digital circuits into multiple blocks.

[0105] In blocking based on logical criteria, a processor can analyze specific nodes or signal paths within a digital circuit to classify a set of circuits that drive signals or perform specific functions into a single block. For example, the processor can classify circuits by clock domain or arithmetic module (ALU, memory controller, etc.). In this process, the processor can classify circuits by considering signal flow analysis, the separation of input and output pins, and the relationships between logic gates and flip-flops, so that each block can be optimized independently. Additionally, blocks can be defined around circuits containing critical paths by utilizing path delay analysis under specific conditions or timing constraints.

[0106] In blocking based on physical structure, the processor can define blocks based on circuit placement and layout information. In digital circuit design, the processor can distinguish blocks using local clustering techniques to minimize the physical distance between components or reduce wiring complexity. In this method, adjacent components are grouped into a single block based on the location of the subcircuit to which each transistor belongs. For example, the processor can define a set of transistors densely packed in a specific area as a single block to minimize power consumption of the integrated circuit or to evenly distribute heat generation.

[0107] FIG. 4 is a flowchart illustrating a regression analysis-based circuit characteristic optimization method for digital circuit design according to another embodiment of the present invention.

[0108] When the processor operates according to a block-wise technique, optimization can be performed in parallel for each divided block, as shown in the flowchart of Fig. 4. First, optimization is performed for each block through iterative learning a certain number of times, and then the circuit is sized to the determined width of the transistors for each block. An optimized set of transistor widths is found by performing parallel optimization for each block again under changed conditions.

[0109] The processor obtains an improvement characteristic value, an additional improvement characteristic value, or a final improvement characteristic value from each of a plurality of blocks, and groups the improvement characteristic value, additional improvement characteristic value, or final improvement characteristic value obtained from each of the plurality of blocks to derive and use or output the improvement characteristic value, additional improvement characteristic value, or final improvement characteristic value of the input digital circuit to be optimized.

[0110] Although FIGS. 1, 2, and 4 describe the respective processes as being executed sequentially, this is merely an illustrative description, and a person skilled in the art may modify and adapt the process in various ways without departing from the essential characteristics of the embodiments of the present invention, such as changing the order described in FIGS. 1, 2, and 4, executing one or more processes in parallel, or adding other processes.

[0111] FIG. 5 is a diagram showing the optimization results obtained by applying a regression analysis-based circuit characteristic optimization method for digital circuit design according to an embodiment of the present invention.

[0112] Based on the critical path delay of the full adder, it can be confirmed that the delay was reduced by 29.47% compared to the 98 ps delay of the TSCM standard cell before optimization. The number of optimization iterations inside the block was set to 20, and the number of iterations for the outer loop was used to be approximately 6. In the problem of optimizing 28 transistor design elements, the transistor width set that minimizes the delay was found through a total of 130 experiments.

[0113] FIG. 6 is a diagram showing the hardware configuration of a regression analysis-based circuit characteristic optimization device for digital circuit design according to one embodiment of the present invention.

[0114] A regression analysis-based circuit characteristic optimization device (100) for digital circuit design includes at least one processor (110), a computer-readable storage medium (120), and a communication bus (150).

[0115] The processor (110) can be controlled to operate as a regression analysis-based circuit characteristic optimization device (100) for digital circuit design. For example, the processor (110) can execute one or more programs (121) stored in a computer-readable storage medium (120). One or more programs (121) may include one or more computer-executable instructions, and the computer-executable instructions may be configured to cause the regression analysis-based circuit characteristic optimization device (100) for digital circuit design to perform operations according to an exemplary embodiment when executed by the processor (110).

[0116] A computer-readable storage medium (120) is configured to store computer-executable instructions or program code, program data and / or other suitable forms of information. Computer-executable instructions or program code, program data and / or other suitable forms of information may also be provided through an input / output interface (130) or a communication interface (140). A program (121) stored in a computer-readable storage medium (120) includes a set of instructions executable by a processor (110). In one embodiment, the computer-readable storage medium (120) may be memory (volatile memory such as random access memory, non-volatile memory, or a suitable combination thereof), one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other forms of storage media that are accessed by a regression analysis-based circuit characteristic optimization device (100) for digital circuit design and can store desired information, or a suitable combination thereof.

[0117] The communication bus (150) interconnects various other components of the regression analysis-based circuit characteristic optimization device (100) for digital circuit design, including the processor (110) and the computer-readable storage medium (120).

[0118] A regression analysis-based circuit characteristic optimization device (100) for digital circuit design may also include one or more input / output interfaces (130) and one or more communication interfaces (140) that provide interfaces for one or more input / output devices. The input / output interface (130) and the communication interface (140) are connected to a communication bus (150). An input / output device (not shown) may be connected to other components of the regression analysis-based circuit characteristic optimization device (100) for digital circuit design through the input / output interface (130).

[0119] The processor (110) receives information about the digital circuit to be designed from the outside, arbitrarily determines a characteristic value for each of at least one transistor included in the digital circuit, mathematically models the characteristics of a path included in the digital circuit based on the characteristic value of the transistor included in the digital circuit to generate a circuit characteristic regression model, applies the arbitrarily determined characteristic value to the circuit characteristic regression model to obtain initial coefficients of the circuit characteristic regression model, and can obtain an improved characteristic value for each of at least one transistor included in the digital circuit based on the circuit characteristic regression model reflecting the initial coefficients.

[0120] A characteristic value for a transistor can be the width of the transistor.

[0121] The processor (110) can obtain a delay of the path for each of at least one path included in the digital circuit by performing a simulation using the characteristic value for each of at least one transistor included in the digital circuit.

[0122] When there are multiple paths, the processor (110) determines the critical path, which is the path with the greatest delay among the multiple paths, and can obtain the initial coefficients of the circuit characteristic regression model only for the critical path.

[0123] The processor (110) can generate a circuit characteristic regression model for each path and obtain initial coefficients for each circuit characteristic regression model using an arbitrarily determined characteristic value or a path delay.

[0124] The processor (110) can calculate the minimum value of the circuit characteristic regression model with the initial coefficients reflected, and determine the characteristic value of the transistor that makes the circuit characteristic regression model achieve the minimum value as the improved characteristic value.

[0125] The processor (110) can update the circuit characteristic regression model based on the improvement characteristic value and obtain additional improvement characteristic values ​​for each of at least one transistor included in the digital circuit based on the updated circuit characteristic regression model.

[0126] When the processor (110) obtains additional improvement characteristic values ​​more than a predetermined reference number of times, it can determine the last additional improvement characteristic value as the final improvement characteristic value and terminate the operation.

[0127] The processor (110) can obtain improvement characteristic values ​​for each of at least one transistor included in the digital circuit as a set based on a circuit characteristic regression model that reflects initial coefficients.

[0128] The processor (110) divides the digital circuit into at least two blocks based on information about the digital circuit being designed received from the outside, arbitrarily determines a characteristic value for each of at least one transistor included in each of the at least two blocks, mathematically models the characteristics of the path included in the block based on the characteristic value of the transistor included in the block to generate a circuit characteristic regression model, applies the arbitrarily determined characteristic value to the circuit characteristic regression model to obtain initial coefficients of the circuit characteristic regression model, and obtains an improved characteristic value for each of at least one transistor included in the block based on the circuit characteristic regression model reflecting the initial coefficients.

[0129] The present application also provides a computer storage medium. Program instructions are stored in the computer storage medium, and when the program instructions are executed by a processor, the regression analysis-based circuit characteristic optimization method for digital circuit design described above is realized.

[0130] A computer storage medium according to one embodiment of the present invention may be a U disk, SD card, PD optical drive, mobile hard disk, large capacity floppy drive, flash memory, multimedia memory card, server, etc., but is not necessarily limited thereto.

[0131] Although it is described that all components constituting the embodiments of the present invention described above are combined or operate in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all such components may be selectively combined in one or more ways to operate. Furthermore, while all such components may each be implemented as a single independent piece of hardware, they may also be implemented as a computer program having a program module that performs some or all of the combined functions in one or more pieces of hardware by selectively combining some or all of the components. Additionally, such a computer program may be stored on a computer-readable media such as a USB memory, CD disk, or flash memory, and read and executed by a computer to implement the embodiments of the present invention. Magnetic recording media, optical recording media, etc., may be included as recording media for the computer program.

[0132] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications, changes, and substitutions within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention and the accompanying drawings are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments and accompanying drawings. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

Claims

1. A memory for storing one or more programs for designing a digital circuit; and one or more processors for performing operations according to the one or more programs; wherein the processors, Information regarding a digital circuit to be designed is received from an external source, and a characteristic value for each of at least one transistor included in the digital circuit is arbitrarily determined, and A circuit characteristic regression model is generated by mathematically modeling the characteristics of a path included in the digital circuit based on the characteristic values ​​of a transistor included in the digital circuit, and The above arbitrarily determined characteristic value is applied to the circuit characteristic regression model to obtain the initial coefficients of the circuit characteristic regression model, and A regression analysis-based circuit characteristic optimization device for digital circuit design, which obtains an improved characteristic value for each of at least one transistor included in the digital circuit based on a circuit characteristic regression model reflecting the initial coefficients.

2. In Paragraph 1, The characteristic value for the above transistor is, A regression analysis-based circuit characteristic optimization device for digital circuit design, characterized by the width of a transistor.

3. In Paragraph 1, The above processor is, A regression analysis-based circuit characteristic optimization device for digital circuit design, characterized by performing a simulation using characteristic values ​​for each of at least one transistor included in the digital circuit to obtain a delay of each of at least one path included in the digital circuit.

4. In Paragraph 3, The above processor is, If there are multiple paths above, A regression analysis-based circuit characteristic optimization device for digital circuit design, characterized by determining a critical path which is the path with the largest delay among the plurality of paths above, and obtaining initial coefficients of a circuit characteristic regression model only for the critical path.

5. In Paragraph 3, The above processor is, A regression analysis-based circuit characteristic optimization device for digital circuit design, characterized by generating a circuit characteristic regression model for each of the above paths and obtaining initial coefficients for each of the above circuit characteristic regression models using the arbitrarily determined characteristic value or the delay of the above path.

6. In Paragraph 1, The above processor is, A regression analysis-based circuit characteristic optimization device for digital circuit design, characterized by calculating the minimum value of a circuit characteristic regression model reflecting the above initial coefficients, and determining the characteristic value of a transistor that causes the circuit characteristic regression model to achieve the minimum value as an improved characteristic value.

7. In Paragraph 6, The above processor is, A regression analysis-based circuit characteristic optimization device for digital circuit design, characterized by updating the circuit characteristic regression model based on the improvement characteristic value and obtaining an additional improvement characteristic value for each of at least one transistor included in the digital circuit based on the updated circuit characteristic regression model.

8. In Paragraph 7, The above processor is, A regression analysis-based circuit characteristic optimization device for digital circuit design, characterized in that when the above additional improvement characteristic value is obtained more than a predetermined reference number of times, the last additional improvement characteristic value is determined as the final improvement characteristic value and the operation is terminated.

9. In Paragraph 1, The above processor is, A regression analysis-based circuit characteristic optimization device for digital circuit design, characterized by obtaining an improved characteristic value for each of at least one transistor included in the digital circuit as a set based on a circuit characteristic regression model reflecting the initial coefficients.

10. In Paragraph 1, The above processor is, Based on information regarding the digital circuit to be designed received from the external source, the digital circuit is divided into at least two blocks, and For each of the above at least two blocks, a characteristic value for each of the at least one transistor included in the block is arbitrarily determined, and A circuit characteristic regression model is generated by mathematically modeling the characteristics of a path included in the above block based on the characteristic values ​​of a transistor included in the above block, and The above arbitrarily determined characteristic value is applied to the circuit characteristic regression model to obtain the initial coefficients of the circuit characteristic regression model, and A regression analysis-based circuit characteristic optimization device for digital circuit design, which obtains an improved characteristic value for each of at least one transistor included in the block based on a circuit characteristic regression model reflecting the initial coefficients.

11. A method performed in a device comprising a memory for storing one or more programs for designing a digital circuit and one or more processors for performing operations according to said one or more programs, A step of receiving information about a digital circuit to be designed from an external source, and arbitrarily determining a characteristic value for each of at least one transistor included in the digital circuit; A step of generating a circuit characteristic regression model by mathematically modeling the characteristics of a path included in the digital circuit based on the characteristic values ​​of a transistor included in the digital circuit; A step of obtaining initial coefficients of the circuit characteristic regression model by applying the above arbitrarily determined characteristic value to the circuit characteristic regression model; and A regression analysis-based circuit characteristic optimization method for digital circuit design, comprising the step of obtaining an improved characteristic value for each of at least one transistor included in the digital circuit based on a circuit characteristic regression model reflecting the initial coefficients.

12. In Paragraph 11, The step of arbitrarily determining a characteristic value for each of at least one transistor included in the digital circuit above is, A regression analysis-based circuit characteristic optimization method for digital circuit design, characterized by performing a simulation using characteristic values ​​for each of at least one transistor included in the digital circuit to obtain a delay of each of at least one path included in the digital circuit.

13. In Paragraph 12, If there are multiple paths above, The step of generating a circuit characteristic regression model by mathematically modeling the characteristics of a path included in the digital circuit based on the characteristic values ​​of a transistor included in the digital circuit is: Among the above multiple paths, determine the critical path which is the path with the greatest delay, and The step of obtaining initial coefficients of the circuit characteristic regression model by applying the above-determined arbitrarily determined characteristic value to the circuit characteristic regression model is, A regression analysis-based circuit characteristic optimization method for digital circuit design, characterized by obtaining initial coefficients of a circuit characteristic regression model only for the critical paths mentioned above.

14. In Paragraph 12, The step of arbitrarily determining a characteristic value for each of at least one transistor included in the digital circuit above is, A regression analysis-based circuit characteristic optimization method for digital circuit design, characterized by generating a circuit characteristic regression model for each of the above paths and obtaining initial coefficients for each of the above circuit characteristic regression models using the arbitrarily determined characteristic value or the delay of the above path.

15. A computer program stored on a computer-readable recording medium for executing on a computer the regression analysis-based circuit characteristic optimization method for digital circuit design described in any one of claims 11 to 14.

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