Substrate processing apparatus and method
A warp compensation layer with alternating main and buffer layers addresses substrate warpage in semiconductor devices by offsetting stress, maintaining flatness and preventing defects during manufacturing.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- WONIK IPS CO LTD
- Filing Date
- 2025-03-31
- Publication Date
- 2026-07-02
AI Technical Summary
The increasing integration density and miniaturization of semiconductor devices lead to substrate warpage due to tensile or compressive stress from material layer differences, hindering subsequent processes.
A warp compensation layer is formed on the substrate with alternating layers of a main layer and a buffer layer, where the buffer layer has a lower density than the main layer, applying tensile or compressive stress to offset the stress induced by the semiconductor structure, preventing warpage and defects.
The warp compensation layer effectively maintains substrate flatness and prevents defects by compensating for stress during semiconductor device manufacturing, ensuring a flat semiconductor device is formed even with increased stacking thickness.
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Figure KR2025004141_02072026_PF_FP_ABST
Abstract
Description
Substrate processing apparatus and method
[0001] The present technology relates to a semiconductor device, and more specifically, to a substrate processing device and method.
[0002] Semiconductor devices can be formed by depositing a material layer on a substrate and through processes such as ion implantation, patterning, and etching.
[0003] Material layers generally need to be deposited smoothly, but warpage can occur due to tensile or compressive stress caused by differences in properties between the substrate and the material layers during the deposition process. As the integration density and miniaturization required for semiconductor devices increase, the number of material layers stacked on the substrate increases, which further exacerbates substrate warpage and makes it impossible to proceed with subsequent processes.
[0004] To resolve this, a method of forming a warp compensation layer on one side of the substrate has been proposed.
[0005] FIG. 1 is a cross-sectional view of a substrate structure according to one embodiment.
[0006] Referring to FIG. 1, the substrate structure (10) may include a substrate (101) and a warping compensation layer (103).
[0007] The substrate (103) is generally flat and may include a first surface (101a) on which a semiconductor structure is formed and a second surface (101b) opposite thereto. A warping compensation layer (103) may be formed on the second surface (101b) of the substrate (103).
[0008] In one embodiment, the piggy compensation layer (103) may be a material film containing silicon and nitrogen, for example, a material film containing SiN3 or SiON.
[0009] The periphery compensation layer (103) is a single film and can be formed to have a uniform density throughout at a constant temperature.
[0010] By forming the warp compensation layer (103), tensile stress, for example, is applied to the substrate (101) to induce a desired level of warp (WPG11).
[0011] FIG. 2 is a cross-sectional view of a semiconductor device according to one embodiment.
[0012] Referring to FIG. 2, a semiconductor structure (20) can be formed on the first surface (101a) of the substrate structure (10) shown in FIG. 1. In one embodiment, the semiconductor structure (20) may have a structure in which an oxide film and a nitride film are alternately and repeatedly stacked, but is not limited thereto.
[0013] By forming a piping compensation layer (103) to apply tensile stress to the second surface (101b) and forming a semiconductor structure (20) on the first surface (101a) in a state where piping (WPG11) is induced, the piping (WPG12) induced by the tensile stress of the semiconductor structure (20) can be offset by the piping (WPG11) induced by the piping compensation layer (103).
[0014] As the stacking thickness of the semiconductor structure (20) increases, the compensation ability of the warp compensation layer (103) exceeds the limit, causing warp (R_WPG13) to occur and defects such as cracks to occur in the substrate structure (103).
[0015] However, since there is a limit to increasing the thickness of the piscide compensation layer (103) to resolve this, an ultimate solution to resolve the piscide is required.
[0016] Embodiments of the present technology can provide a substrate processing apparatus and method capable of removing warp threads generated during the manufacture of a semiconductor device.
[0017] A substrate processing device according to one embodiment of the present technology may be configured to include: a process chamber in which a processing space is formed; at least one gas supply device for injecting process gas into the process chamber; a plasma power supply unit that provides a plasma power source to the at least one gas supply device; at least one susceptor installed opposite to each of the at least one gas supply device and having a substrate placed on its upper surface; and a controller that forms a warp compensation layer in which a main layer and a buffer layer are alternately stacked at least once on one surface of a substrate loaded on the susceptor, wherein the density of the buffer layer is formed to be lower than the density of the main layer.
[0018] A substrate processing method according to one embodiment of the present technology may include: a step of providing a substrate to be processed; and a step of forming a warp compensation layer on one surface of the substrate in which a main layer and a buffer layer are alternately stacked at least once, wherein the density of the buffer layer is lower than the density of the main layer.
[0019] According to the present technology, by forming a warp compensation layer in which a main layer that causes warp to a substrate and a buffer layer that relieves stress on the substrate caused by the main layer are alternately stacked, it is possible to compensate for warp that occurs during the semiconductor device manufacturing process while preventing defects from occurring on the substrate.
[0020] FIG. 1 is a cross-sectional view of a substrate structure according to one embodiment.
[0021] FIG. 2 is a cross-sectional view of a semiconductor device according to one embodiment.
[0022] FIG. 3 is a cross-sectional view of a substrate structure according to one embodiment.
[0023] FIG. 4 is a cross-sectional view of a semiconductor device according to one embodiment.
[0024] FIG. 5 is a diagram illustrating a method for depositing a warp compensation layer according to one embodiment.
[0025] FIG. 6 is a diagram illustrating a method for depositing a warp compensation layer according to one embodiment.
[0026] FIGS. 7a and FIGS. 7b are drawings for explaining a method of depositing a warp compensation layer according to one embodiment.
[0027] FIG. 8 is a diagram illustrating the film characteristics of a warp-covering compensation layer according to one embodiment.
[0028] FIG. 9 is a diagram illustrating the pore characteristics and stress characteristics of a pore compensation layer according to one embodiment.
[0029] Figure 10 is a diagram illustrating the substrate warping characteristics according to the structure and deposition conditions of the warping compensation layer.
[0030] Figure 11 is a diagram illustrating stress characteristics according to the structure of the warp-covering layer.
[0031] FIG. 12 is a configuration diagram of a substrate processing device according to one embodiment.
[0032] FIG. 13 is a cross-sectional view in the AA' direction of the substrate processing device illustrated in FIG. 12.
[0033] FIG. 14 is a cross-sectional view in the BB' direction of the substrate processing device illustrated in FIG. 12.
[0034] A substrate processing device according to one embodiment of the present technology may include: a process chamber in which a processing space is formed; at least one gas supply device for injecting process gas into the process chamber; a plasma power supply unit that provides a plasma power source to the at least one gas supply device; at least one susceptor installed opposite to each of the at least one gas supply device and having a substrate placed on its upper surface; and a controller.
[0035] The controller can form a warp compensation layer in which a main layer and a buffer layer are alternately stacked at least once on one side of a substrate loaded on the susceptor, and control the buffer layer to be formed with a lower density than the main layer.
[0036] Hereinafter, embodiments of the present technology will be described in more detail with reference to the attached drawings.
[0037] FIG. 3 is a cross-sectional view of a substrate structure according to one embodiment.
[0038] Referring to FIG. 3, a substrate structure (30) according to one embodiment may include a substrate (301) and a warping compensation layer (303). The substrate (301) is generally flat in shape and may include a first surface (301a) on which a semiconductor structure is formed and a second surface (301b) opposite thereto. The warping compensation layer (303) may be formed on the second surface (301b) of the substrate (303).
[0039] The Wapigee compensation layer (303) may have a structure in which the main layer (303A) and the buffer layer (303B) are stacked alternately at least once.
[0040] In one embodiment, the main layer (303A) and the buffer layer (303B) may each be a material film containing silicon and nitrogen, for example, a material film containing SiN3 or SiON, and may be formed to have different densities. For example, the density of the main layer (303A) may be higher than the density of the buffer layer (303B).
[0041] In one embodiment, the main layer (303A) may be a material film containing silicon, and the buffer layer (303B) may be a material film containing silicon and nitrogen.
[0042] The warping compensation layer (303) can be formed of a material having the same stress as the stress caused by the semiconductor structure formed on the first surface (301a) of the substrate (301). For example, if the semiconductor structure causes tensile stress, the warping compensation layer (303) can also be formed of a material that causes tensile stress. If the semiconductor structure causes compressive stress, the warping compensation layer (303) can also be formed of a material that causes compressive stress.
[0043] FIG. 4 is a cross-sectional view of a semiconductor device according to one embodiment.
[0044] Referring to FIG. 4, a semiconductor structure (40) can be formed on the first surface (301a) of the substrate (301) included in the substrate structure (30) shown in FIG. 3. In one embodiment, the semiconductor structure (40) may have a structure in which an oxide film and a nitride film are alternately and repeatedly stacked, but is not limited thereto.
[0045] By forming a piping compensation layer (303) to apply tensile stress to the second surface (301b) of the substrate (301) and forming a semiconductor structure (40) on the first surface (301a) of the substrate (301) in a state in which piping (WPG21) is induced, the piping (WPG22) induced by the tensile stress of the semiconductor structure (40) can be offset by the piping (WPG21) induced by the piping compensation layer (103).
[0046] The warp compensation layer (303) according to the present technology includes a main layer (303A) that causes tensile stress in the substrate and a buffer layer (303B) that relieves tensile stress caused by the main layer (303A). Accordingly, even if the number of stacking cycles of the semiconductor structure (40) increases, warp does not occur in the substrate structure (30) and the semiconductor structure (40) formed on top thereof, and a semiconductor device (50) that is flat overall can be formed.
[0047] FIG. 4 illustrates an example in which a semiconductor structure (40) is formed on the first surface (301a) of a substrate (301) on which a warp compensation layer (303) is formed, but it is also possible to form the warp compensation layer (303) after forming the semiconductor structure (40) on the first surface (301a) of the substrate (301).
[0048] FIGS. 5 to 8 are drawings for explaining a method of depositing a warp compensation layer according to one embodiment.
[0049] Referring to FIG. 5, the main layer (303A) can be deposited by injecting silicon-containing gas and nitrogen-containing gas as process gases at a first temperature (T1), and the buffer layer (303B) can be deposited by injecting silicon-containing gas and nitrogen-containing gas as process gases at a second temperature (T2) lower than the first temperature (T1).
[0050] In one embodiment, the silicon-containing gas supplied when forming the main layer (303A) and the buffer layer (303B) may be, for example, SiH4.
[0051] In one embodiment, the nitrogen-containing gas supplied when forming the main layer (303A) and the buffer layer (303B) may include nitrogen gas (N2) and ammonia gas (NH3).
[0052] In one embodiment, the nitrogen-containing gas supplied when forming the main layer (303A) may be nitrogen gas (N2), and the nitrogen-containing gas supplied when forming the buffer layer (303B) may include nitrogen gas (N2) and ammonia gas (NH3). That is, the main layer (303A) may be formed without supplying ammonia gas (NH3), whereas the buffer layer (303B) may be formed by supplying ammonia gas (NH3).
[0053] In one embodiment, the main layer (303A) can be formed by supplying a nitrogen-containing gas, for example NH3, at a rate of 700-1200 sccm and a silicon-containing gas, for example SiH4, at a rate of 250-270 sccm at a first temperature (T1) of 500-600°C.
[0054] In one embodiment, the buffer layer (303B) can be formed at a second temperature (T2) of 300 to 400°C. The buffer layer (303B) can be formed by supplying a nitrogen-containing gas, for example NH3, at a rate of 10 to 15 times the supply rate when forming the main layer (303A), and supplying a silicon-containing gas, for example SiH4, at a rate of 1 / 5 to 1 / 3 times the supply rate when forming the main layer (303A).
[0055] The density of the main layer (303A) and the buffer layer (303B) can be controlled by controlling the supply amount of nitrogen-containing gas, for example, ammonia gas (NH3), when forming the buffer layer (303B) to be about 10 to 12 times higher than when forming the main layer (303A), and controlling the supply amount of silicon-containing gas when forming the buffer layer (303B) to be about 1 / 4 to 1 / 3 lower than when forming the main layer (303A).
[0056] When forming the main layer (303A), if only nitrogen gas (N2) is supplied without supplying ammonia gas (NH3), the density of the buffer layer (303B) may be lower than that of the main layer (303A) due to the hydrogen gas contained in the ammonia gas (NH3) supplied when forming the buffer layer (303B). At this time, the amount of silicon-containing gas supplied when forming the buffer layer (303B) can be controlled to be about 1 / 4 to 1 / 3 lower than when forming the main layer (303A).
[0057] Referring to FIG. 6, the main layer (303A) can be formed by applying a negative voltage (-V1) to the susceptor on which the substrate is placed, and the buffer layer (303B) can be formed by applying a positive voltage (+V0) to the susceptor.
[0058] In one embodiment, when forming the main layer (303A), a negative voltage (-V1) of -500 to -1000V may be applied to the susceptor, and when forming the buffer layer (303B), a positive voltage (+V0) of +500 to +1000V may be applied to the susceptor.
[0059] As illustrated in FIG. 7a, when a negative voltage (-V1) is applied to the susceptor (310) and a positive voltage (+V0) is applied to the gas supply device (200) that supplies process gas, the movement of ions toward the substrate (301) can be accelerated. Thus, the ion bombardment effect on the surface of the substrate (301) is amplified, and a high-density main layer (303A) can be formed.
[0060] At this time, a VHF (ultra-high frequency) power source with a center frequency band of 25 to 100 MHz or an HF (high frequency) power source with a center frequency band of 10 to 20 MHz can be applied to the gas supply device (200) as a plasma power source.
[0061] In one embodiment, when forming the main layer (303A), if nitrogen gas (N2) is supplied instead of ammonia gas (NH3) as the nitrogen-containing gas, VHF power can be applied to the gas supply device (200) to promote the dissociation of nitrogen gas (N2).
[0062] Meanwhile, when forming the buffer layer (303B), as shown in FIG. 7b, if a positive voltage (+V0) is applied to the susceptor (310) and a negative voltage (-V1) is applied to the gas supply device (200), the ion collision phenomenon is suppressed, and a low-density buffer layer (303B) can be formed.
[0063] At this time, an LF (low frequency) power source with a center frequency band of 300 to 500 kHz can be applied to the gas supply device (200) as a plasma power source.
[0064] Meanwhile, each main layer (303A) can be formed with a thickness of, for example, 500 to 1500 Å and each buffer layer (303B) can be formed with a thickness of 50 to 150 Å so that the thickness ratio of the main layer (303A) and the buffer layer (303B) is approximately 10:1 to 12:1.
[0065] The thickness of the warp compensation layer (303) can be determined according to the thickness of the semiconductor structure (40) formed on the substrate (301), and the thickness ratio of the semiconductor structure (40) to the warp compensation layer (303) can be 4:1 to 6:1, but is not limited thereto.
[0066] FIG. 8 is a diagram illustrating the film characteristics of a warp-covering compensation layer according to one embodiment.
[0067] As the main layer (303A) and the buffer layer (303B) are formed under the conditions described above, as shown in FIG. 8, the main layer (303A) can be formed with high density (D1) and the buffer layer (303B) can be formed with low density (D2).
[0068] FIG. 9 is a diagram illustrating the pore characteristics and stress characteristics of a pore compensation layer according to one embodiment.
[0069] As shown in FIG. 9 (a), when a main layer (303A) and a buffer layer (303B) with different densities are alternately stacked at least once to form a warp compensation layer (303), the warp (B) has the characteristic of increasing rather than converging (A) as the thickness of the semiconductor structure formed on the substrate structure increases.
[0070] Therefore, as shown in Fig. 9 (b), even if the thickness of the semiconductor structure (40) formed on the substrate (301) increases, the stress of the semiconductor structure (30) can be maintained at a constant level (D) without decreasing (C).
[0071] Figure 10 is a diagram illustrating the substrate warping characteristics according to the structure and deposition conditions of the warping compensation layer.
[0072] Referring to FIG. 10, it can be seen that when the WPG compensation layer is formed as a single film without applying a buffer layer, when the WPG compensation layer including the buffer layer is formed at a low temperature by applying a negative voltage to the susceptor, and when the WPG compensation layer including the buffer layer is formed at a low temperature by applying a positive voltage to the susceptor, the WPG does not converge but increases as the thickness of the semiconductor structure formed on the substrate structure increases.
[0073] In particular, it can be seen that the warping characteristics are significantly improved when a positive voltage is applied to the susceptor and a buffer layer is deposited at a low temperature compared to when this is not done.
[0074] Figure 11 is a diagram illustrating stress characteristics according to the structure of the warp-covering layer.
[0075] Referring to FIG. 11, when a warp compensation layer is formed as a single film without applying a buffer layer, or when a warp compensation layer including a buffer layer is formed at a low temperature by applying a positive voltage to a susceptor, it can be seen that the stress of the semiconductor structure (30) does not decrease as the thickness of the semiconductor structure formed on the substrate structure increases and remains constant.
[0076] FIG. 12 is a configuration diagram of a substrate processing device according to one embodiment, FIG. 13 is a cross-sectional view in the AA' direction of the substrate processing device shown in FIG. 12, and FIG. 14 is a cross-sectional view in the BB' direction of the substrate processing device shown in FIG. 12.
[0077] Referring to FIGS. 12 to 14, a substrate processing device (1000) according to one embodiment may include a process chamber (100), a plasma power supply unit (400), and a controller (500). The process chamber (100) may include a top lead (110) to which a gas supply device (200) is coupled, and a main body (111) to which a susceptor (310) is provided.
[0078] The controller (100) can control the general operation of the substrate processing device (1000).
[0079] A process chamber (100) has a plurality of substrate processing spaces, and processing processes such as deposition and etching are performed on each substrate. The process chamber (100) is provided with a main body (111) with an open top and a top lead (110) installed on the top of the main body (111) so as to be openable and closable. A plurality of, for example, four, gas supply devices (200) are formed on the top lead (110). A plasma power supply unit (400) that provides a plasma power source to the gas supply device (200) may be connected to the gas supply device (200).
[0080] When the top lead (110) is coupled to the upper part of the main body (111) and closes the interior of the main body (111), an internal space is formed inside the process chamber (100) where processing of the substrate (W), such as a deposition process, is performed.
[0081] Since the internal space of the process chamber (100) must generally be formed in a vacuum atmosphere, an exhaust section (141) for discharging process gas is formed on the bottom surface of the process chamber (100), and the exhaust section (141) is connected to an exhaust line connected to a pump provided on the outside.
[0082] Additionally, at least one substrate entry / exit port (113) is formed on the side wall of the main body (111) for bringing a substrate (W) into or taking out of the process chamber (100). A through hole (350) is formed through the bottom surface of the main body (111) to which a drive shaft (340) that supports a turntable (330) and moves up and down and rotates is inserted.
[0083] A heating unit (not shown) can maintain the interior of the process chamber (100) at a constant temperature. The heating means may be formed on the inner wall, outer wall, or inside the wall of the process chamber (100).
[0084] The susceptors (310) are means for supporting a substrate and are capable of moving up and down within the process chamber (100), each supporting a single substrate. Four susceptors (310) can be moved up and down independently. To this end, four susceptors (310) can each be provided horizontally inside the process chamber (100) in the shape of a disc. A heater (not shown) is provided inside the susceptor (310) to heat the substrate (W) to a constant process temperature.
[0085] A gas supply device (200) is spaced apart from each susceptor (310) and configured to be attachable to a top lead (110), and independently injects process gas into each susceptor (310). A gas supply source supplying various process gases is connected to each gas supply device (200) through a respective supply line. A flow control unit for controlling the supply of process gas is provided on each supply line.
[0086] The turntable (330) may be a disc-shaped plate having the same number of through holes (302) as the susceptor (310) and may be located on the upper side of the susceptor (310). When four susceptors (310) are provided, four turntable through holes (302) are formed on the turntable (330) through which each susceptor (310) can pass and move. The turntable through holes (302) may have the same shape as the shape of the susceptor (310).
[0087] A substrate support ring (320) is provided on the edge of each turntable through hole (302). Accordingly, the edge side of the turntable through hole (302) is formed as a stepped edge so that the substrate support ring (320) is supported on the stepped surface. Alternatively, the support ring (320) can be supported by a support pin (not shown) attached to a separate turntable through hole (302) without a stepped edge. FIG. 13 illustrates that the substrate (W) is supported by a support ring (320) having a stepped edge.
[0088] In addition, a drive shaft (340) is provided that penetrates the bottom surface of the process chamber (100) and is vertically connected to the turntable (330) to raise, lower, and rotate the turntable (330). The drive shaft (340) is vertically connected to the turntable (330) through the turntable support hole (305) and is connected to a driving means (not shown), such as an external motor, to raise, lower, and rotate the turntable (330).
[0089] Using the substrate processing apparatus shown in FIGS. 12 to 14, a semiconductor structure in which a warp compensation layer composed of a main layer and a buffer layer and different materials are alternately stacked can be deposited.
[0090] In particular, when forming the warp compensation layer, the controller (500) can form a warp compensation layer in which a main layer and a buffer layer are alternately stacked at least once on one side of the substrate (W), and control the formation so that the density of the buffer layer is lower than the density of the main layer.
[0091] Those skilled in the art to which the present invention described above pertains will understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the present invention.
[0092] According to the present technology, it is possible to compensate for warping that occurs during the semiconductor device manufacturing process while preventing defects from occurring on the substrate.
Claims
1. A process chamber in which a processing space is formed; At least one gas supply device for injecting process gas into the process chamber; A plasma power supply unit that provides a plasma power source to at least one gas supply device; At least one susceptor installed to face each of the above-mentioned at least one gas supply device and having a substrate placed on its upper surface; and A controller that forms a warp compensation layer in which a main layer and a buffer layer are alternately stacked at least once on one surface of a substrate loaded on the susceptor, wherein the density of the buffer layer is formed to be lower than the density of the main layer; A substrate processing device configured to include 2. In Paragraph 1, A substrate processing device in which the main layer and the buffer layer are each material films containing silicon and nitrogen.
3. In Paragraph 1, The above controller is a substrate processing device that controls the temperature of the process chamber to a first temperature when forming the main layer and controls the temperature of the process chamber to a second temperature lower than the first temperature when forming the buffer layer.
4. In Paragraph 3, A substrate processing apparatus in which the first temperature is 500~600℃ and the second temperature is 300~400℃.
5. In Paragraph 1, Each of the above main layer and the above buffer layer is a silicon nitride film formed by supplying a process gas containing silicon-containing gas and ammonia gas, and A substrate processing device in which the controller controls the ammonia gas supply amount to be 10 to 12 times higher than when the main layer is formed during the formation of the buffer layer, and controls the silicon-containing gas supply amount to be 1 / 4 to 1 / 3 lower.
6. In Paragraph 1, The above main layer is a silicon nitride film formed by supplying silicon-containing gas and nitrogen gas, and the above buffer layer is a silicon nitride film formed by supplying silicon-containing gas, nitrogen gas and ammonia gas. The above controller is a substrate processing device that controls the silicon-containing gas supply amount to be 1 / 4 to 1 / 3 lower than when the main layer is formed during the formation of the buffer layer.
7. In Paragraph 1, The above controller is a substrate processing device that applies a negative voltage to the susceptor when the main layer is formed and applies a positive voltage to the susceptor when the buffer layer is formed.
8. In Paragraph 7, A substrate processing device in which the above negative voltage is applied at -500 to -1000V and the above positive voltage is applied at +500 to +1000V.
9. In Paragraph 1, The above controller is, A substrate processing device that applies an ultra-high frequency power source with a center frequency band of 25 to 100 MHz or a high frequency power source with a center frequency band of 10 to 20 MHz to the gas supply device as a plasma power source when forming the main layer.
10. In Paragraph 1, The above controller is, A substrate processing device that applies a low-frequency power source with a center frequency band of 300 to 500 kHz to the gas supply device as the plasma power source when forming the buffer layer.
11. In Paragraph 1, The above controller is, A substrate processing device that controls the thickness ratio of each of the main layers and each of the buffer layers to 10:1 to 12:
1.
12. In Paragraph 11, The above controller is, A substrate processing apparatus that controls the thickness of each of the above main layers to 500 to 1500 Å and controls the thickness of each of the above buffer layers to 50 to 150 Å.
13. A step of providing a substrate to be processed; and A step of forming a warp compensation layer on one surface of the substrate in which a main layer and a buffer layer are alternately stacked at least once, wherein the density of the buffer layer is lower than the density of the main layer; A substrate processing method including 14. In Paragraph 13, A substrate processing method in which the main layer and the buffer layer are each material films containing silicon and nitrogen.
15. In Paragraph 13, A substrate processing method in which the main layer is formed at a first temperature and the buffer layer is formed at a second temperature lower than the first temperature.
16. In Paragraph 15, A substrate processing method in which the first temperature is 500~600℃ and the second temperature is 300~400℃.
17. In Paragraph 13, A substrate processing method wherein each of the main layer and the buffer layer is a silicon nitride film formed by supplying a process gas containing silicon-containing gas and ammonia gas, wherein the buffer layer is formed by controlling the ammonia gas supply amount to be 10 to 12 times higher than that of the main layer and controlling the silicon-containing gas supply amount to be 1 / 4 to 1 / 3 lower.
18. In Paragraph 13, The above main layer is a silicon nitride film formed by supplying silicon-containing gas and nitrogen gas, and the above buffer layer is a silicon nitride film formed by supplying silicon-containing gas, nitrogen gas and ammonia gas. A substrate processing method in which the above buffer layer is formed by controlling the silicon-containing gas supply amount to be 1 / 4 to 1 / 3 lower than that of the above main layer.
19. In Paragraph 13, A substrate processing method in which the main layer is formed by applying a negative voltage to a susceptor on which the substrate is placed, and the buffer layer is formed by applying a positive voltage to the susceptor.
20. In Paragraph 19, A substrate processing method in which the above negative voltage is applied at -500 to -1000V and the above positive voltage is applied at +500 to +1000V.
21. In Paragraph 13, A substrate processing method in which the above main layer is formed by applying a plasma power source with a center frequency band of 25 to 100 MHz or a high frequency power source of 10 to 20 MHz to a gas supply device that supplies process gas.
22. In Paragraph 13, A substrate processing method in which the above buffer layer is formed by applying a low-frequency power source with a center frequency band of 300 to 500 kHz as a plasma power source to a gas supply device that supplies process gas.
23. In Paragraph 13, A substrate processing method in which the thickness ratio of each of the main layers and each of the buffer layers is controlled to 10:1 to 12:
1.
24. In Paragraph 23, A substrate processing method in which the thickness of each of the above main layers is 500 to 1500 Å and the thickness of each of the above buffer layers is 50 to 150 Å.