Data communication apparatus and data communication system including same

Abstract

Disclosed are a data communication apparatus and a data communication system including same. The data communication apparatus comprises: a data transmission line; a first communication module that converts a TX signal at a voltage level, provided from an external apparatus, into a TX signal at a current level and outputs same to one side of the data transmission line; and a second communication module that converts an RX signal at a current level, provided via the data transmission line, into an RX signal at a voltage level, wherein the first communication module and the second communication module each include a mode switch that switches from a data transmission mode to a data reception mode or from a data reception mode to a data transmission mode in response to a communication direction control signal to thereby enable bidirectional communication.

Description

Data communication device and data communication system including the same

[0001] The present invention relates to a data communication device and a data communication system including the same, and more specifically, to a data communication device and a data communication system including the same that perform communication using only current signals by minimizing the amplitude of a voltage signal accompanying signal transmission.

[0002] The primary issue with high-speed wired communication is the parasitic capacitance existing between the transmission line and the ground signal, as well as the matching capacitance between the transmission lines. While the inductance and resistance components of the transmission line also have an impact, advancements in ultra-high-speed transmission line manufacturing technology have made these factors relatively negligible. Since signals are transmitted using voltage variations on high-speed transmission lines, the capacitance of the line increases the time constant and capacitive load, posing significant difficulties for high-speed data transmission or data communication over long distances.

[0003] Generally, if Vpp is defined as the signal voltage containing pulse period or phase information, the line capacitance is a factor that interferes with communication by causing effects such as signal distortion, attenuation, and phase delay.

[0004] High-speed serial communication techniques over wires known to date (MIPI, LVDS, USB 2.0, USB 3.0, SATA, etc.) have increased their speed by reducing the amplitude of the signal voltage to reduce the influence of capacitive loads and enabling high-speed serial signal transmission.

[0005] The current value (i) required for signal transmission can be defined by i = C * (dv / dt). That is, as the frequency component dv / dt (the amount of voltage variation over time) increases, the amount of current (i) required for signal transmission increases even though the value of C, which is the same capacitive load, is constant. In addition, the impedance on the signal line also acts as a resistor, increasing the time constant and hindering high-speed signal transmission.

[0006] Meanwhile, the volume of computing and transmitted data is increasing significantly due to the emergence of big data applications such as artificial intelligence (AI), virtual reality, and media streaming. The energy cost of DRAM access in computing systems is rising as system performance becomes more advanced.

[0007] [Prior Art Literature]

[0008] [Patent Literature]

[0009] (Patent Document 0001) Republic of Korea Registered Patent No. 10-2543177 (Published June 14, 2023) (Title of Invention: High-bandwidth memory device and system device including the device)

[0010] (Patent Document 0002) Republic of Korea Registered Patent No. 10-0817031 (Published Mar. 20, 2008) (Title of Invention: Single-wire Serial Communication Module)

[0011] (Patent Document 0003) Republic of Korea Published Patent No. 2017-0024223 (Published on Mar. 07, 2017) (Title of Invention: Device including a single-wire interface and data processing system including the same)

[0012] Accordingly, the technical problem of the present invention is based on this point, and the objective of the present invention is to provide a data communication device that performs communication using only current signals by applying a current signal-based communication technique to minimize the amplitude of the voltage signal accompanying signal transmission in actual implementation.

[0013] Another objective of the present invention is to provide a data communication system including the above-described data communication device.

[0014] To realize the purpose of the present invention as described above, a data communication device according to one embodiment comprises: a data transmission line; a first communication module connected to one side of the data transmission line and outputting to one side of the data transmission line a TX signal of a voltage level provided by an external device in order to communicate using only current, free from interference between a capacitive load existing in the data transmission line and the data transmission line; and a second communication module connected to the other side of the data transmission line and converting a RX signal of a current level provided via the data transmission line into an RX signal of a voltage level in order to communicate using only current, free from interference between a capacitive load existing in the data transmission line and the data transmission line, wherein the first communication module and the second communication module each include a mode switching switch to enable bidirectional communication by switching from a data transmission mode to a data reception mode or from a data reception mode to a data transmission mode by means of a communication direction control signal.

[0015] In one embodiment, the data transmission line may include a Through Silicon Via (TSV), a Through Glass Via (TGV), a Silicon Interposer, a Glass Interposer, and a PCB pattern.

[0016] In one embodiment, each of the first communication module and the second communication module includes a current conveyor comprising an EN-port into which an EN signal is input, a Y-port into which a common mode voltage (VCOM) is input, an X-port, and a ZP-port connected to the mode switching switch, and the current conveyor can convert a voltage level TX signal into a current level TX signal and simultaneously mirror and output the converted current level TX signal.

[0017] In one embodiment, the mode switching switch includes a first terminal connected to the ZP-port of the TX current conveyor, a second terminal connected to the X-port of the TX current conveyor, and a third terminal connected to an I / O pad connected to the data transmission line, and when the first terminal and the third terminal are connected, the ZP-port of the TX current conveyor and the I / O pad are connected, and when the second terminal and the third terminal are connected, the X-port of the TX current conveyor and the ZP-port of the TX current conveyor can be connected.

[0018] In one embodiment, each of the first communication module and the second communication module further includes a TX buffer into which a TX signal of the voltage level is input; a TX resistor connected to the output terminal of the TX buffer; and a TX switch connected to the TX resistor and the X-port of the current conveyor, and the current conveyor can be connected to the mode switching switch through a ZP-port.

[0019] In one embodiment, each of the first communication module and the second communication module may further include a second switch connected to the ZP-port of the current conveyor; and a resistor element or RC parallel circuit, one end of which is connected to the second switch and the other end of which is connected to the common mode voltage (VCOM).

[0020] In one embodiment, when the first communication module or the second communication module operates in a data reception mode, the receiving current passing through the data transmission line is applied to the X-port of the current conveyor of the communication module operating in the data reception mode, the common mode voltage (VCOM) is applied to the Y-port of the current conveyor, the receiving current mirrored with respect to the common mode voltage (VCOM) is output through the ZP-port of the current conveyor, and the mirrored current output through the ZP-port of the current conveyor can be converted into a voltage by the resistor element or RC parallel circuit.

[0021] In one embodiment, each of the first communication module and the second communication module may further include an RX buffer connected to the RC parallel circuit.

[0022] In one embodiment, the RX buffer may include any one of a Schmitt-trigger circuit, a logic buffer, and a comparator circuit.

[0023] In one embodiment, each of the first communication module and the second communication module may include: a transmission mode unit that converts a voltage level TX signal into a current level TX signal and outputs it to the data transmission line through an I / O pad; and a reception mode unit that converts a current level RX signal input from the data transmission line connected through the I / O pad into a voltage level RX signal.

[0024] In one embodiment, the transmission mode unit may include a first buffer comprising a front inverter that is enabled by a TX_EN signal and inverts the TX signal, and a rear inverter connected to the rear end of the front inverter and enabled by the TX_EN signal and inverts the signal inverted by the front inverter; and a voltage-current converter comprising a pull-up current source, a pull-down current source, a pull-up switch, and a pull-down switch.

[0025] In one embodiment, the transmission mode unit may include a buffer that is enabled by a TX_EN signal and buffers the TX signal.

[0026] In one embodiment, the transmission mode unit may further include a voltage-current converter connected to the downstream end of the buffer and providing a pull-up current source and a pull-down current source.

[0027] In one embodiment, the voltage-current converter may include a resistor.

[0028] In one embodiment, the receiving mode unit may include an RX current conveyor; a resistor element or RC parallel circuit that receives and charges a receiving current output through a ZP-port of the RX current conveyor to form a receiving voltage; and an RX buffer that outputs the receiving voltage formed by the resistor element or RC parallel circuit to the outside through an RX terminal.

[0029] In one embodiment, each of the first communication module and the second communication module includes a PAM4 signal generator, and the PAM4 signal generator may include: a first TX buffer into which a first TX signal of the voltage level is input; a second TX buffer into which a second TX signal of the voltage level is input; a first TX resistor connected to the output terminal of the first TX buffer; a second TX resistor connected to the output terminal of the second TX buffer; and a TX switch having one end connected to the first TX resistor and the second TX resistor and the other end connected to the X-port of the current conveyor.

[0030] In one embodiment, each of the first communication module and the second communication module includes a PAM4 signal generator, and the PAM4 signal generator may include: a first TX buffer into which a first TX signal of the voltage level is input; a second TX buffer into which a second TX signal of the voltage level is input; a first TX resistor having one end connected to the output terminal of the first TX buffer and the other end connected to the data transmission line; and a second TX resistor having one end connected to the output terminal of the second TX buffer and the other end connected to the data transmission line.

[0031] In one embodiment, each of the first communication module and the second communication module may further include an RX switch commonly connected to the ZP-port of the current conveyor and the mode switching switch; a resistor element or RC parallel circuit connected to the RX switch; and a PAM4 signal restorer that restores an RX signal passing through the resistor element or RC parallel circuit.

[0032] In one embodiment, the first communication module and the second communication module can each switch between a data transmission mode and a data reception mode, and in the data transmission mode, the TX switch is turned ON and the RX switch is turned OFF, and in the data reception mode, the TX switch is turned OFF and the RX switch is turned ON.

[0033] In one embodiment, in the data transmission mode, a transmission signal from the first TX buffer and the second TX buffer is output to the data transmission line, and in the data reception mode, a received signal can be restored from the RX buffer and output.

[0034] In one embodiment, the PAM4 signal recovery unit may include: a first comparator that compares the RX signal with a first reference voltage and outputs a first result value; a second comparator that compares the RX signal with a second reference voltage and outputs a second result value; a third comparator that compares the RX signal with a third reference voltage and outputs a third result value; and a logic encoder that represents the first to third result values ​​as a 2-bit RXA[1:0].

[0035] In one embodiment, the first communication module converts a first transmission signal provided from an external device into a first transmission current and outputs it to a data transmission line, and the second communication module outputs a first reception current that is opposite in phase to the first transmission current through the data transmission line to minimize voltage changes on the data transmission line. Here, the second communication module can mirror the first reception current to output a transmission signal restored to a first reception voltage.

[0036] In one embodiment, the second communication module converts a second transmission signal provided from an external device into a second transmission current and outputs it to a data transmission line, and the first communication module outputs a second reception current that is opposite in phase to the second transmission current through the data transmission line to minimize voltage changes on the data transmission line. Here, the first communication module can mirror the second reception current to output a transmission signal restored to a second reception voltage.

[0037] In one embodiment, each of the first communication module and the second communication module includes a receiver that receives an RX signal at the physical layer through the data transmission line, wherein the receiver may include a voltage generator that converts the current of the RX signal provided through the data transmission line into a voltage.

[0038] In one embodiment, the voltage generating unit may further include a variable resistor, one end of which is connected to the data transmission line and the other end of which is connected to the current conveyor.

[0039] To realize the above-described objective of the present invention, a data communication system according to one embodiment comprises: a data transmission line section including a plurality of data transmission lines arranged in parallel; and a first communication module section including a plurality of first communication modules arranged in parallel and connected to one end of the data transmission line section. It includes a plurality of second communication modules arranged in parallel, and a second communication module unit connected to the other end of the data transmission line unit, wherein the first communication module converts a voltage level TX signal provided by an external device into a current level TX signal and outputs it to one side of the data transmission line in order to communicate using only current, free from interference between the capacitive load present in the data transmission line and the data transmission line, and the second communication module converts a current level RX signal provided via the data transmission line into a voltage level RX signal in order to communicate using only current, free from interference between the capacitive load present in the data transmission line and the data transmission line, and the first communication module and the second communication module each include a mode switching switch to enable bidirectional communication by switching from a data transmission mode to a data reception mode or from a data reception mode to a data transmission mode by means of a communication direction control signal.

[0040] According to such a data communication device and a data communication system including the same, by applying a current signal-based communication technique that converts a voltage level TX signal into a current level TX signal and outputs it to one side of a data transmission line, and converts a current level RX signal provided via the data transmission line into a voltage level RX signal, the amplitude of the voltage signal accompanying signal transmission in the actual implementation can be minimized to 0V or less than tens of mV, thereby enabling communication to be performed using only current signals.

[0041] FIG. 1 is a cross-sectional view illustrating a 2.5D System in Package (SiP) processor module including High Bandwidth Memory (HBM).

[0042] Figure 2 is a diagram illustrating the switching activity of a capacitive load.

[0043] FIG. 3 illustrates a circuit configuration for explaining the connection structure between a first communication module and a second communication module that transmit and receive data signals at high speed.

[0044] FIG. 4 is a configuration diagram for explaining a data communication device according to an embodiment of the present invention.

[0045] Figure 5 is a circuit diagram modeling the case where the data transmission line shown in Figure 4 is configured as a single unit.

[0046] Figure 6 is a circuit diagram modeling the case where the data transmission line shown in Figure 4 is composed of two.

[0047] Figure 7 is a diagram showing the configuration of a typical I / O pad corresponding to the I / O pad shown in Figure 4.

[0048] Figure 8 is a diagram showing an ESD protection FET structure corresponding to the I / O pad shown in Figure 4.

[0049] Figure 9 illustrates the symbol of a current conveyor.

[0050] Figure 10 is a circuit diagram for explaining a current conveyor according to one example.

[0051] Figure 11 is a graph illustrating rail-to-rail input.

[0052] FIG. 12 is a graph for explaining the current characteristics of the p-MOSFET MP10 and n-MOSFET MN10 provided in the first driver shown in FIG. 10.

[0053] Figure 13 is a circuit diagram illustrating a current conveyor according to another example.

[0054] FIG. 14 is a drawing for explaining an example of the first communication module illustrated in FIG. 4.

[0055] FIG. 15 is a circuit diagram for explaining the first communication module illustrated in FIG. 14 operating in a data transmission mode.

[0056] FIG. 16 is a circuit diagram for explaining the first communication module illustrated in FIG. 14 operating in a data reception mode.

[0057] FIG. 17 is a drawing for explaining another example of the first communication module shown in FIG. 4.

[0058] Figure 18 is a circuit diagram of another application example in which the voltage-current converter of Figure 17 is replaced with a buffer and a resistor.

[0059] FIG. 19 is a diagram showing the data transmission line illustrated in FIG. 4 implemented with four lines.

[0060] FIG. 20 is a circuit diagram for explaining an example of a data communication device illustrated in FIG. 4.

[0061] FIG. 21 is a circuit diagram illustrating an example of the TX buffer shown in FIG. 20.

[0062] FIG. 22 is a circuit diagram illustrating another example of the TX buffer shown in FIG. 20.

[0063] FIG. 23 is a circuit diagram illustrating another example of the TX buffer shown in FIG. 20.

[0064] FIG. 24 is a configuration diagram for explaining a data communication system according to one embodiment of the present invention.

[0065] FIG. 25 is a circuit diagram for explaining the first communication module illustrated in FIG. 24.

[0066] FIG. 26 is a circuit diagram for explaining another example of the first communication module shown in FIG. 24.

[0067] FIG. 27 is a circuit diagram for explaining another example of the first communication module shown in FIG. 24.

[0068] FIG. 28 is a block diagram for explaining the first differential decoder (1210) illustrated in FIG. 24.

[0069] FIG. 29 is a configuration diagram for explaining a data communication system according to another embodiment of the present invention.

[0070] FIG. 30 is a circuit diagram for explaining a PAM4 signal generator and a PAM4 signal restorer provided in the first communication module illustrated in FIG. 24.

[0071] FIG. 31 is a block diagram illustrating the PAM4 signal restorer illustrated in FIG. 30.

[0072] FIG. 32 is a circuit diagram of another example for explaining the PAM4 signal generator and PAM4 signal restorer equipped in the first communication module shown in FIG. 24.

[0073] FIG. 33 is a waveform diagram showing the simulation results of each of the example and comparative example transmitting a data pattern to one data transmission line.

[0074] FIG. 34 is a configuration diagram for explaining a data communication system according to another embodiment of the present invention.

[0075] FIG. 35 is a configuration diagram for explaining a data communication system according to another embodiment of the present invention.

[0076] FIG. 36 is a circuit diagram for explaining the first communication module illustrated in FIG. 35.

[0077] FIG. 37 is a block diagram for explaining the first differential signal decoder illustrated in FIG. 35.

[0078] FIG. 38 is a drawing for explaining another example of a decoding unit added to the second communication module unit shown in FIG. 36.

[0079] FIG. 39 is a drawing for explaining another example of a decoding unit added to the second communication module unit shown in FIG. 36.

[0080] FIG. 40 is a circuit diagram for explaining an example of a receiving unit provided in a data communication device of the present invention.

[0081] FIGS. 41a, FIGS. 41b, and FIGS. 41c are graphs showing signal amplitude according to the output impedance of the X-port of the receiver shown in FIG. 40.

[0082] Hereinafter, the present invention will be described in more detail with reference to the attached drawings. Since the present invention is susceptible to various modifications and may take various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed forms, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the present invention.

[0083] In describing each drawing, similar reference numerals have been used for similar components. In the attached drawings, the dimensions of the structures are depicted enlarged compared to their actual size to ensure clarity of the invention.

[0084] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0085] In this application, terms such as "comprising" or "having" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0086] Furthermore, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0087] The terms described in this specification are defined as follows.

[0088] A "Processor Unit" is an IC responsible for logical operations in AI processors, GPUs, CPUs, SoCs, etc.

[0089] A "processor module" is a board or assembly composed of HBM and processor units.

[0090] "DDR RAM" includes DDR4, DDR5, DDR6, GDDR5, GDDR6, etc.

[0091] "TSV-Link" is a signal transmission wiring (data transmission path) connected via TSV between DRAM dies and interface dies inside HBM.

[0092] "T-Link" is a signal transmission wiring (data transmission path) connected between the processor unit and HBM via a silicon interposer or PCB.

[0093] The "Physical Layer (PHY)" is the layer that transmits and receives data in individual bit units as electrical signals, and is the layer that transmits and receives electrical signals on actual data transmission lines. This invention relates to the PHY.

[0094] The "data communication device" is configured to communicate high-speed signals using only current, free from the capacitive load of a data transmission line, and includes a first communication module disposed on one side, a second communication module disposed on the other side, and a single data transmission line connecting the first communication module and the second communication module. The first communication module and the second communication module can each selectively operate in a data transmission mode and a data reception mode according to a control signal. The "data communication device" supports bidirectional communication.

[0095] The "data communication system" is composed of two or more data communication devices and transmits data using two or more data transmission lines. The "data communication system" can be composed of various combinations of communication modules, such as 256 data transmission lines, 512 data transmission lines, 1024 data transmission lines, and 2048 data transmission lines.

[0096] "Data transmission line" or "communication line" refers to a means for transmitting signals made of electrical conductors, such as through silicon vias (TSVs), through glass vias (TGVs), silicon interposers, glass interposers, and PCBs.

[0097] The main data links between a processor unit, such as a GPU, CPU, or SoC, and DRAM are a Through-Silicon Via (TSV) link for the interior of HBM and a T-Line link for the HBM and the processor, as shown in Fig. 1.

[0098] FIG. 1 is a cross-sectional view illustrating a 2.5D System in Package (SiP) processor module including High Bandwidth Memory (HBM).

[0099] Referring to FIG. 1, the processor module may include an HBM device (10), a control device (20), an interposer (30), and a printed circuit board (PCB) (40).

[0100] The HBM device (10) may include memory dies (MD1 to MD4) and a base die (BD) (also called a buffer die). The memory dies (MD1 to MD4) and the base die (BD) may be stacked, and the stacked memory dies (MD1 to MD4) may be positioned on top of the base die (BD). First bumps (MB) may be formed between the stacked memory dies (MD1 to MD4) and the base die (BD), and through silicon vias (TSVs) penetrating the memory dies (MD1 to MD4) may be formed between the first bumps (MB). First direct access (DA) bumps (dab), first power bumps (pb1), and first main bumps (cadb1) may be disposed on the lower surface of the base die (BD). Here, the first main bumps (cadb1) may include command and address bumps, data bumps, and clock bumps. The TSV is referred to as a TSV-link, and the first main bumps (cadb1) may be referred to as a T-link.

[0101] Second main bumps (cadb2), second power bumps (pb2), and first control signal and data bumps (cdqb) may be disposed on the lower surface of the control unit (20). The second main bumps (cadb2) may include command and address bumps, data bumps, and clock bumps. The control unit (20) may be a graphic processing unit (GPU) die, a central processing unit (CPU) die, or a system on chip (SoC), etc.

[0102] The first bumps (MB), the first DA bumps (dab), the first and second power bumps (pb1, pb2), the first and second main bumps (cadb1, cadb2) and the first control signal and data bumps (cdb) may be microbumps.

[0103] Second DA bumps (DAFB), third power bumps (PBFB), and second control signal and data bumps (CDFB) may be disposed on the lower surface of the interposer (30). The interposer (30) may include DA lines (dal) connecting the first DA bumps (dab) and the second DA bumps (DAFB), command and address lines and data lines (cadl) connecting the first main bumps (cadb1) and the second main bumps (cadb2), and control signal and data lines (cdl) connecting the first control signal and data bumps (cdb) and the second control signal and data bumps (CDFB). Although not illustrated, it may additionally include power lines connecting the first power bumps (pb1) and the third power bumps (PBFB), and connecting the second power bumps (pb2) and the third power bumps (PBFB). The second DA bumps (DAFB), the third power bumps (PBFB), and the second control signal and data bumps (CDFB) may be flip-die bumps.

[0104] DA balls (DAB), power balls (PB), and control signal and data balls (CDB) may be arranged on the lower surface of the PCB (40). In the PCB (40), the second DA bumps (DAFB) and the DA balls (DAB) may be connected, the third power bumps (PBFB) and the power balls (PB) may be connected, and the second control signal and data bumps (CDFB) and the control signal and data balls (CDB) may be connected.

[0105] The processor module illustrated in Fig. 1 is combined using 2.5D SiP (System in Package) technology, which combines multiple semiconductor chips into a single package. Compared to 3D, 2.5D is a form in which interlayer connections are made horizontally, allowing multiple chips to be placed on the same substrate and communicate with each other through high-speed connections. By using 2.5D SiP technology, the processor and HBM memory are placed in physically close proximity and connected via an interposer to increase data transfer speeds. This structure enables high-performance processing units, such as CPUs, GPUs, and AI processors, to exchange data with memory very quickly.

[0106] With the advent of the big data era, memory designers are increasing data transfer speeds every year. For example, GDDR6 and HBM3 have reached up to 24 and 6.4 Gb / s / ch., respectively. Both TSV links and T-links have large parasitic capacitance (CIO). According to JEDEC standards, the parasitic capacitance (CIO) of the TSV link, the communication link of HBM2, and the T-link, the communication link of DDR5, is 2.4 pF and 0.9 pF, respectively.

[0107] High-speed data transmission under such heavy loads inevitably leads to heat issues, which result in high power consumption and a degradation of overall computing performance.

[0108] Meanwhile, in communication links connected to digital circuits, dynamic power consumption occurs due to the frequent switching activity of capacitive loads.

[0109] Figure 2 is a diagram illustrating the switching activity of a capacitive load.

[0110] Referring to Fig. 2, when the output of the Vout signal line switches from Low to High, the output load (CIO) is charged from the 0V (GND) level to the VDD power supply voltage by the power source. At this stage, half of the energy (1 / 2 CIO * VDD²) consumed to bring Vout to the VDD signal level from the source (i.e., the VDD power supply voltage source) is converted into heat by the on-resistance of the PMOS device, and the other half is stored in the output load (CIO).

[0111] When the output switches from High to Low, the charge stored in the output load (CIO) is released to ground (GND), and the remaining half of the energy at this stage is converted into heat through the on-resistance of the NMOS device. Therefore, at the end of a complete Low-to-High and High-to-Low switching cycle, the energy consumed per cycle is CIO*VDD² (J, Joule). This can be formulated as follows.

[0112] That is, the total energy required to drive the signal with low-to-high or high-to-low switching is given by the following equation (1).

[0113] [Formula 1]

[0114]

[0115] Total energy is converted into heat. In addition, as the data transmission speed increases, the number of times charging and discharging are performed per second increases, so high-speed data transmission typically generates power consumption and heat generation proportional to that speed.

[0116] As can be seen from the above equation (1), in order to reduce power consumption and heat generation, it is necessary to reduce the voltage applied to the capacitance component or reduce the capacitance value itself.

[0117] However, according to the above formula (1), since the energy value is proportional to the square of the voltage (VDD), it can be seen that reducing the voltage is more effective in reducing power consumption than reducing the capacitance.

[0118] FIG. 3 illustrates a circuit configuration for explaining the connection structure between a first communication module and a second communication module that transmit and receive data signals at high speed. In particular, it illustrates a circuit configuration of a physical layer (PHY) responsible for communication between a first communication module, which is an HBM device that transmits data at high speed, and a second communication module, which is a processor unit.

[0119] Referring to FIG. 3, a data transmission line is positioned between a first communication module and a second communication module to transmit a TX signal transmitted from the first communication module to the second communication module or transmit a TX signal transmitted from the second communication module to the first communication module.

[0120] The first and second communication modules transmit and receive data at the HBM physical layer or the data transmission / reception physical layer. That is, each of the first and second communication modules transmits data from the upper layer to the physical layer, and the physical layer converts it into a signal and transmits it. Conversely, when a signal received from the physical layer is transmitted to the communication module, the communication module restores it back into data that can be used by the upper layer. Each of the first and second communication modules converts the data received from the upper layer into a format transmittable by the physical layer (i.e., a bit stream), and converts the received bit stream back into data that the upper layer can understand.

[0121] If the first communication module includes a processor unit, the second communication module includes a logic interface die, and if the first communication module includes a logic interface die, the second communication module may include a processor unit.

[0122] Each of the first communication module and the second communication module includes a transmission unit (DRV) that transmits a TX signal to a data transmission line at the physical layer and a reception unit (RCV) that receives an RX signal through a data transmission line at the physical layer.

[0123] Since the signal transmission waveform of such a circuit has amplitudes of 0V and VDDIO (e.g., 0.8V to 1.2V), the energy consumption required for charging and discharging the load capacitance of the data transmission line is high.

[0124] The present invention proposes a method that enables high-speed data communication while reducing the range of charging and discharging voltages of parasitic capacitance (CIO) required for communication (data transmission) to 0V or less than a few mV.

[0125] FIG. 4 is a configuration diagram for explaining a data communication device according to an embodiment of the present invention.

[0126] Referring to FIG. 4, a data communication device according to one embodiment of the present invention includes a data transmission line (100), a first communication module (200) connected to one end of the data transmission line (100), and a second communication module (300) connected to the other end of the data transmission line (100).

[0127] The first communication module (200) includes a first EN port into which a first enable signal (EN_A) is input, a first TX_EN port into which a first transmit enable signal (TX_EN_A) is input, a first TX port into which a first TX signal is input, a first RX_EN port into which a first receive enable signal (RX_EN_A) is input, a first RX port into which a first RX signal is input, and a first PAD port connected to a first I / O pad of a data transmission line (100).

[0128] The second communication module (300) includes a second EN port into which a second enable signal (EN_B) is input, a second TX_EN port into which a second transmit enable signal (TX_EN_B) is input, a second TX port into which a second TX signal is input, a second RX_EN port into which a second receive enable signal (RX_EN_B) is input, a second RX port into which a second RX signal is input, and a second PAD port connected to a second I / O pad of the data transmission line (100).

[0129] The data communication device according to the present invention may refer to any apparatus including a first communication module (200) and a second communication module (300).

[0130] In some embodiments, the data communication device according to the present invention may be a computing system, and may be a portable computing system including a laptop computer, a tablet computer, a smartphone, a wearable device, a PMP (Portable Media Player), etc., or a fixed computing system such as a desktop computer, a server, a home appliance, etc.

[0131] In some embodiments, the data communication device according to the present invention may include a module comprising a board on which a first communication module (200) and a second communication module (300) are mounted, as a component of the aforementioned computing systems, automotive control systems, industrial control systems, etc.

[0132] In some embodiments, the first communication module (200) and the second communication module (300) may be semiconductor chips manufactured through a semiconductor process. In some embodiments, the first communication module (200) and the second communication module (300) may be included in a single semiconductor package, or in some embodiments, may be mounted on a printed circuit board as independent packages. The first communication module (200) may be, as a non-limiting example, an Application Processor (AP), an Application Specific Integrated Circuit (ASIC), an Application Specific Instruction Set Processor (ASIP), a Field Programmable Gate Array (FPGA), etc.The second communication module (300) may include, as a non-limiting example, nonvolatile memory such as EEPROM (non-volatile memory such as an Electrically Erasable Programmable Read-Only Memory), flash memory, PRAM (Phase Change Random Access Memory), RRAM (Resistance Random Access Memory), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), FRAM (Ferroelectric Random Access Memory), and volatile memory such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), mobile DRAM, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power DDR) SDRAM, GDDR (Graphic DDR) SDRAM, RDRAM (Rambus Dynamic Random Access Memory).

[0133] Additionally, if the first communication module (200) includes a processor unit that performs calculations and processes data, the second communication module (300) includes a logic interface die that provides a physical / logical interface for connection with other parts of the system to manage signal transmission and interface between various hardware devices, and if the first communication module (200) includes a logic interface die, the second communication module (300) may include a processor unit.

[0134] In addition, the first communication module (200) and the second communication module (300) may each be processor units that perform calculations and process data.

[0135] In addition, the first communication module (200) and the second communication module (300) may each be memory devices that store data.

[0136] The first communication module (200) and the second communication module (300) can communicate with each other through a data transmission line (100). The first communication module (200) can provide commands and addresses, such as a write command and a read command, to the second communication module (300) through the data transmission line (100). Additionally, the first communication module (200) may provide data to the second communication module (300) along with a write command, and may also receive data from the second communication module (300) following a read command.

[0137] In this specification, the signal provided by the first communication module (200) to the second communication module (300) and the signal received from the second communication module (300) through the data transmission line (100) may be referred to as a TX signal. Hereinafter, exemplary embodiments of the present disclosure will be described with reference mainly to the operation of the first communication module (200) writing the TX signal to the second communication module (300).

[0138] The data transmission line (100) may refer to a bus protocol for communication, such as DDR2, DDR4, GDDR, etc., as a non-limiting example, and may define at least one channel. In some embodiments, the data transmission line (100) may define independent channels for commands, addresses, and data, or may define a channel shared by two or more of commands, addresses, and data. The channel may include at least one signal line, and commands, addresses, and data may travel as electrical signals through at least one signal line.

[0139] As the amount of data required for processing in the data communication device according to the present invention increases, the amount of data processed in the first communication module (200) may increase. Accordingly, the first communication module (200) may communicate more frequently with the second communication module (300) through the data transmission line (100) for writing and / or reading data, and the power consumed by the second communication module (300) and the data transmission line (100) may increase.

[0140] As the data processing speed and the amount of data increase, for example, the power consumed by the second communication module (300) and the data transmission line (100) corresponding to the receiving side may increase more rapidly than the power consumed by the first communication module (200) corresponding to the transmitting side.

[0141] As described below with reference to the drawings, by applying a current signal-based communication technique between a first communication module (200) and a second communication module (300) that communicate with each other, the amplitude of the voltage signal accompanying the signal transmission in the actual implementation can be minimized, thereby reducing the power consumed in the data transmission line (100).

[0142] In this embodiment, the first communication module (200) and the second communication module (300) have the same circuit configuration and are arranged facing each other with respect to the data transmission line (100). The data communication device according to the present invention can perform bidirectional communication. That is, when the first communication module (200) operates in a data transmission mode, the second communication module (300) operates in a data reception mode. Meanwhile, when the second communication module (300) operates in a data transmission mode, the first communication module (200) operates in a data reception mode.

[0143] The data transmission line (100) can be implemented using a signal pattern on a PCB, TSV (Through Silicon Via), TGV (Through Glass Via), etc. Both ends of the data transmission line (100) are connected to a first communication module (200) and a second communication module (300) through I / O pads.

[0144] In each data transmission line (100), there is unintended parasitic capacitance between the virtual GND and the data transmission line (100). Additionally, there is parasitic capacitance between signal lines.

[0145] Such parasitic capacitance causes high-speed signal transmission to consume a large amount of driving power, and along with the resulting heat generation, becomes a major cause of communication signal quality degradation.

[0146] FIG. 5 is a circuit diagram modeling the case where the data transmission line shown in FIG. 4 is configured as one. FIG. 6 is a circuit diagram modeling the case where the data transmission line shown in FIG. 4 is configured as two.

[0147] Referring to FIGS. 4, 5 and 6, the data transmission line (100) has a first parasitic capacitive capacitance value (CS0, CS1, Cs2, Cs3, hereinafter Cs) with GND, and the multiple data transmission lines (100) have a second parasitic capacitive coupling capacitance value (Cp0, Cp1, hereinafter Cp).

[0148] In this specification, the first parasitic capacitance (Cs) and the second parasitic capacitance coupling capacitance (Cp) are collectively referred to as capacitance (CIO). The data transmission line (100) theoretically has a DC resistance close to about 0 Ohm, but typically has a series resistance value or impedance value (Rs) of less than 0 to 300 Ohm. It has fine inductance values ​​L0 and L1 through bonding wires, bumps, TSVs, or other conductive signal paths. Additionally, one end and the other end include a modeling of an I / O pad responsible for input / output with an external device of the semiconductor IC. This model of a single data transmission line is called the pi model (ð-model), and the L0, L1, and Rs components are considered to be very small values ​​and excluded from the formula, while the Cp0, Cp1, Cp2, Cp3, and Cp values ​​are expressed as a single representative value called CIO (Capacitance of I / O & I / O lain).

[0149] The equivalent model of the data transmission line (100) shown in FIGS. 5 and 6 is an example of one of the methods for modeling the electrical characteristics of various data transmission lines, and modeling of various types of data transmission lines is possible depending on the purpose.

[0150] FIG. 7 is a diagram showing the configuration of a typical I / O pad corresponding to the I / O pad shown in FIG. 4, and FIG. 8 is a diagram showing an ESD protection FET structure corresponding to the I / O pad shown in FIG. 4.

[0151] Referring to FIG. 7, the I / O pad includes two diodes connected in series. If the I / O pad is connected to the first communication module (200), one diode is connected to ground through the cathode and to the first communication module (200) through the anode. Additionally, the other diode is connected to the first communication module (200) through the cathode and to the VDD power supply voltage through the anode. Of course, if the I / O pad is connected to the second communication module (300), one diode is connected to ground through the cathode and to the second communication module (300) through the anode. Additionally, the other diode is connected to the second communication module (300) through the cathode and to the VDD power supply voltage through the anode.

[0152] Referring to FIG. 8, the I / O pad includes two diode-connected MOS transistors connected in series. When the I / O pad is connected to the first communication module (200), one MOS transistor is connected to the first communication module (200) through a common gate-drain connection and ground connection, and is connected to the first communication module (200) through a source. Additionally, the other MOS transistor is connected to the first communication module (200) through a drain, and is connected to the VDD power supply voltage through a common source-gate connection. Of course, when the I / O pad is connected to the second communication module (300), one MOS transistor is connected to the second communication module (300) through a common gate-drain connection and ground connection, and is connected to the second communication module (300) through a source. Additionally, the other MOS transistor is connected to the second communication module (300) through a drain, and is connected to the VDD power supply voltage through a common source-gate connection.

[0153] Each of the first communication module (200) and the second communication module (300) may include a current conveyor II+ (hereinafter referred to as the current conveyor) as a circuit that converts an input voltage signal into a current and outputs it upon transmission, and mirrors and outputs an input current upon reception.

[0154] Figure 9 illustrates the symbol of a current conveyor.

[0155] Referring to FIG. 9, the current conveyor includes a Y-port that receives a common mode voltage (VCOM) on a communication line, an X-port that receives a current, and a ZP-port that mirrors and outputs the input current. It also includes an enable pin (EN pin) that enables / disables the operating state of the current conveyor.

[0156] The relationship between the input and output signals of a current conveyor can be defined by the following matrix.

[0157]

[0158] According to the matrix definition of the relationship between the symbol of the current conveyor and signal input / output shown in Fig. 9, the current conveyor has the following characteristics.

[0159] - The Y-port is a high-impedance port that receives a voltage signal with an input current of "0".

[0160] - The voltage of the X-port is the same as the voltage of the Y-port, and it is a low-impedance port that receives a current signal.

[0161] - The ZP-port is a high-impedance port that mirrors the input (or output) current of the X-port 1:1 to have the same current output value as the X-port.

[0162] FIG. 10 is a circuit diagram illustrating a current conveyor according to one example. In this embodiment, the current conveyor illustrates a Balanced Output Rail-to-rail Current Conveyor ±.

[0163] Referring to FIG. 10, the current conveyor includes a core block (CORE) and a driving block (D2).

[0164] The core block (CORE) includes an upper differential input terminal (110), a lower differential input terminal (120), an upper current mirror terminal (130), a lower current mirror terminal (140), a switching terminal (150), a first capacitor (C1), and a second capacitor (C2), and receives VBP0, VBP1, and VBP2 as bias voltages for PMOS devices from a bias circuit block (not shown), and receives VBN0, VBN1, and VBN2 as bias voltages for NMOS devices. In the balanced output rail-to-rail second-generation current conveyor shown in FIG. 10, the illustration of the bias circuit block is omitted.

[0165] The core block (CORE) implements rail-to-rail input / output through an upper differential input terminal (110) and a lower differential input terminal (120) commonly connected to the Y-port and X-port, and outputs a first driving voltage (P_DRV) and a second driving voltage (N_DRV) to the driving block (D2) by mirroring the current applied by the bias voltage based on the voltage of the Y-port and the voltage of the X-port.

[0166] The upper differential input terminal (110) is composed of p-MOSFET MP0 and p-MOSFET MP1 connected in series, and p-MOSFET MP2 and p-MOSFET MP3 connected in parallel. p-MOSFET MP0 has a source to which a first power supply voltage (VDD) is applied, a gate to which a bias voltage (VBP0) is applied, and a drain connected to the source of p-MOSFET MP1. p-MOSFET MP1 has a source connected to the drain of p-MOSFET MP0, a gate to which a bias voltage (VBP1) is applied, and a drain connected to the source of p-MOSFET MP2 and the source of p-MOSFET MP3. p-MOSFET MP2 has a source connected to the drain of p-MOSFET MP1, a gate connected to the Y-port, and a drain connected to the lower current mirror terminal (140). p-MOSFET MP3 has a source connected to the drain of p-MOSFET MP1, a gate connected to the X-port, and a drain connected to the lower current mirror terminal (140). p-MOSFET MP2 and p-MOSFET MP3 are responsible for the input and perform the role of comparing the voltage of the Y-port and the voltage of the X-port to flow a current (tail current) (Ip) applied by the bias voltage toward the gate where the lower voltage is input. Here, the range of the operable input signal voltage (Common mode voltage) is approximately 0.8V to 0V, assuming the first power supply voltage (VDD) is approximately 1.0V.

[0167] The lower differential input terminal (120) consists of n-MOSFET MN0 and n-MOSFET MN1 connected in series, and n-MOSFET MN2 and n-MOSFET MN3 connected in parallel. n-MOSFET MN0 has a drain connected to the source of n-MOSFET MN1, a gate to which a bias voltage (VBN0) is applied, and a source to which a second power supply voltage (VSS) is applied. n-MOSFET MN1 has a drain connected to the source of n-MOSFET MN2 and the source of n-MOSFET MN3, a gate to which a bias voltage (VBN1) is applied, and a source connected to the drain of n-MOSFET MN0. n-MOSFET MN2 has a drain connected to the upper current mirror terminal (130), a gate connected to the Y-port, and a source connected to the drain of n-MOSFET MN1. n-MOSFET MN3 has a drain connected to the upper current mirror terminal (130), a gate connected to the X-port, and a source connected to the drain of n-MOSFET MN1. n-MOSFET MN2 and n-MOSFET MN3 are responsible for the input and perform the role of comparing the voltage of the Y-port and the voltage of the X-port to flow a current (In) applied by the bias voltage toward the gate where the higher voltage is input. Here, the range of the operable input signal voltage (Common mode voltage) is approximately 0.2V to 1.0V, assuming the first power supply voltage (VDD) is about 1.0V.

[0168] Since the upper differential input terminal (110) and the lower differential input terminal (120) are arranged as input stages of the current conveyor, a rail-to-rail input can be implemented. That is, when the power supply is 1.0V, a tail current (Ip, In) can be flowed so that the range of the input voltage (Common Mode Voltage) covers the entire range of the power supply voltage (first power supply voltage (VDD)). The range of such input voltages is illustrated in FIG. 11.

[0169] Figure 11 is a graph illustrating rail-to-rail input.

[0170] As shown in Fig. 11, the rail-to-rail input covers the entire range of input signals from 0V to VDD, so it has the advantage of operating over a wider range of input voltages compared to cases where the existing circuit receives an upper or lower input.

[0171] Referring again to FIG. 10, the upper current mirror terminal (130) is composed of p-MOSFET MP4, p-MOSFET MP5, p-MOSFET MP6, and p-MOSFET MP7 to define the current mirror. p-MOSFET MP4 has a source to which a first power supply voltage (VDD) is applied, a gate connected to the drain of p-MOSFET MP5 and the gate of p-MOSFET MP6, and a drain connected to the source of p-MOSFET MP5. Additionally, the drain of p-MOSFET MP4 is connected to the source of n-MOSFET MN3 of the lower differential input terminal (120). p-MOSFET MP5 has a source connected to the drain of p-MOSFET MP4, a gate connected to the gate of p-MOSFET MP7, and a drain connected to the gate of p-MOSFET MP4. Additionally, the source of p-MOSFET MP5 is connected to the source of n-MOSFET MN3 of the lower differential input terminal (120). p-MOSFET MP6 has a source to which the first power supply voltage (VDD) is applied, a gate connected to the drain of p-MOSFET MP5 and the gate of p-MOSFET MP4, and a drain connected to the source of p-MOSFET MP7. Additionally, the drain of p-MOSFET MP6 is connected to the source of n-MOSFET MN2 of the lower differential input terminal (120). p-MOSFET MP7 has a source connected to the drain of p-MOSFET MP6, a gate connected to the gate of p-MOSFET MP5, and a drain connected to the driving block (D2) and the switching terminal (150). Here, p-MOSFET MP5 and p-MOSFET MP7 are biased by a bias voltage (VBP1), and the bias voltages of p-MOSFET MP4 and p-MOSFET MP6 have the circuit characteristic of having the drain voltage of p-MOSFET MP5 applied.

[0172] If the gate area of ​​p-MOSFET MP4 is equal to the gate area of ​​p-MOSFET MP6, and the gate area of ​​p-MOSFET MP5 is equal to the gate area of ​​p-MOSFET MP7, then the current flowing through p-MOSFET MP6 and p-MOSFET MP7 is equal to the current flowing through p-MOSFET MP4 and p-MOSFET MP5. In this case, the saturation voltage of p-MOSFET MP5 becomes higher than the threshold voltage (Vth) of p-MOSFET MP4, and consequently, current is supplied to the drain of p-MOSFET MP7. Therefore, it has the characteristic of having a wider operating voltage range than a current mirror of a conventional structure.

[0173] At this time, when currents are applied to the drains of p-MOSFET MP4 and p-MOSFET MP6 with different values ​​due to the difference in input voltage of the lower differential input terminal (120), the final output current (I(MP7)) flowing through p-MOSFET MP7 is determined as a current ± @IN of the bias current due to the bias voltage (VBP1). Here, @ is the ratio of the current (In) to the difference in input voltage obtained from the upper differential input terminal (110) and the lower differential input terminal (120), which are the input stages of the current conveyor.

[0174] The lower current mirror section (140) is composed of n-MOSFET MN4, n-MOSFET MN5, n-MOSFET MN6, and n-MOSFET MN7 to define the current mirror. n-MOSFET MN4 has a drain connected to the source of n-MOSFET MN5, a gate connected to the gate of n-MOSFET MN6, and a source to which a second power supply voltage (VSS) is applied. Additionally, the drain of n-MOSFET MN4 is connected to the source of p-MOSFET MP3 of the upper differential input section (110). n-MOSFET MN5 has a drain connected to the switching section (150), a gate connected to the gate of n-MOSFET MN7, and a source connected to the drain of n-MOSFET MN4. Additionally, the source of n-MOSFET MN5 is connected to the source of p-MOSFET MP2 of the upper differential input section (110). n-MOSFET MN6 has a drain connected to the source of n-MOSFET MN7, a gate connected to the gate of n-MOSFET MN4, and a source to which the second power supply voltage (VSS) is applied. n-MOSFET MN7 has a drain connected to the switching terminal (150), a gate connected to the gate of n-MOSFET MN5, and a source connected to the drain of n-MOSFET MN6. Additionally, the drain of n-MOSFET MN7 is connected to the source of p-MOSFET MP2 of the upper differential input terminal (110). Here, n-MOSFET MN5 and n-MOSFET MN7 are biased by a bias voltage (VBN1), and the bias voltages of n-MOSFET MN4 and n-MOSFET MN6 have the circuit characteristic of having the source voltage of n-MOSFET MN5 applied.

[0175] If the gate area of ​​n-MOSFET MN4 is equal to the gate area of ​​n-MOSFET MN6, and the gate area of ​​n-MOSFET MN5 is equal to the gate area of ​​n-MOSFET MN7, then the current flowing through n-MOSFET MN6 and n-MOSFET MN7 is equal to the current flowing through n-MOSFET MN4 and n-MOSFET MN5. In this case, the saturation voltage of n-MOSFET MN5 becomes higher than the threshold voltage (Vth) of n-MOSFET MN4, and as a result, current is supplied to the source of n-MOSFET MN7. Therefore, it has the characteristic of having a wider operating voltage range than a current mirror of a general structure.

[0176] At this time, when currents are applied to the sources of n-MOSFET MN4 and n-MOSFET MN6 with different values ​​due to the difference in input voltage of the upper differential input terminal (110), the final output current (I(MN7)) flowing through n-MOSFET MN7 is determined as the current ± @IP of the bias current by VBN1. Here, @ is the ratio of the current (Ip) to the difference in input voltage obtained from the upper differential input terminal (110) and the lower differential input terminal (120), which are the input stages of the current conveyor.

[0177] In this embodiment, the upper current mirror section (130) and the lower current mirror section (140) employ a high-compliance current mirror.

[0178] The driving block (D2) includes a first driver (210) and a second driver (220), and outputs a normal output current through the ZP-port in response to a first driving voltage (P_DRV) and a second driving voltage (N_DRV).

[0179] The first driver (210) consists of a series-connected p-MOSFET MP10 and an n-MOSFET MN10. The p-MOSFET MP10 has a source to which the first power supply voltage (VDD) is applied, a gate connected to the upper current mirror terminal (130), and a drain connected to the X-port of the n-MOSFET MN10. The n-MOSFET MN10 has a source to which the second power supply voltage (VSS) is applied, a gate connected to the lower current mirror terminal (140), and a drain connected to the X-port of the p-MOSFET MP10. The first driver (210) performs the function of connecting the output to the X-port of the input stage to match the structure of the second-generation current conveyor.

[0180] FIG. 12 is a graph for explaining the current characteristics of the p-MOSFET MP10 and n-MOSFET MN10 provided in the first driver shown in FIG. 10.

[0181] As shown in FIG. 12, the output current (IMP) of the p-MOSFET MP10 is controlled by the first driving voltage (P_DRV), which is the output of the upper current mirror terminal (130). In the range where the output current (IMP) is greater than +4J, the p-MOSFET MP10 operates in a linear mode; in the range where it is less than +4J, the p-MOSFET MP10 has non-linear characteristics; and in the range of -4J or less, the p-MOSFET MP10 is cut-off and has the characteristic of no longer being able to drive the current. Here, J represents the quiescent current of the driving MOSFET, which is the standby mode current (i.e., the value of the current flowing before operation in the standby state). A Class AB driver is designed by defining the bias voltage range until the gate voltage of each driver MOS passes the threshold voltage and reaches the linear operation mode as a range of ±4J.

[0182] Meanwhile, the output current (IMN) of the n-MOSFET MN10 is controlled by the second driving voltage (N_DRV), which is the output of the lower current mirror terminal (140). In the range where the output current (IMN) is less than -4J, the n-MOSFET MN10 operates in a linear mode, in the range where it is greater than -4J, the n-MOSFET MN10 has non-linear characteristics, and in the range of +4J or more, the n-MOSFET MN10 is cut-off and has the characteristic of no longer being able to drive the current.

[0183] Therefore, in the zero-current region (i.e., no-signal region) where there is no signal, the current values ​​of p-MOSFET MP10 and n-MOSFET MN10 exist, but they have the smallest current values ​​in the operating mode; thus, such an output buffer stage is called a class AB stage. A driver having this function is called a class AB driver. Furthermore, using a current conveyor equipped with such a class AB driver offers the advantages of lowering current consumption during no-signal periods, appropriately adjusting the size of the output driver to suit the application, and enabling low-power operation characteristics and driving large currents.

[0184] Referring again to FIG. 10, the second driver (220) is composed of a series-connected p-MOSFET MP11 and an n-MOSFET MN11, identical in structure to the first driver (210). The p-MOSFET MP11 has a source to which VDD is applied, a gate connected to the gate of the p-MOSFET MP10 of the first driver (210), a drain of the n-MOSFET MN11, and a drain connected to the ZP-port. The n-MOSFET MN11 has a source to which VSS is applied, a lower current mirror terminal (140), a gate connected to the gate of the n-MOSFET MN10, and a drain connected to the drain of the p-MOSFET MP11 and the ZP-port. Unlike the first driver (210) being connected to the X port of the differential input stage of the upper differential input terminal (110) and the lower differential input terminal (120), the second driver (220) is connected to the ZP-port for output driving.

[0185] In FIG. 10, the first driver (210) of the core block (CORE) and the driving block (D2) is a circuit structure of a general folded cathode OPAMP having rail-to-rail input and output. The p-MOSFETs MP11 and NM11 defining the second driver (220) of the driving block (D2) are MOSFETs added to make the OPAMP a current conveyor.

[0186] The Y-port is connected to the positive input terminal (+) of the OPAMP, and the X-port is electrically connected to the negative input terminal (-) and output terminal (OUT) of the OPAMP by shorting them.

[0187] The gate input signal of the p-MOSFET MP10 of the first driver (210) for the high-level output of the OPAMP is connected to the gate of the p-MOSFET MP11 of the second driver (220) to produce a high-level output of the ZP-port. Additionally, the gate input signal of the n-MOSFET MN10 of the first driver (210) for the low-level output of the OPAMP is connected to the gate of the n-MOSFET MN11 of the second driver (220) to produce a high-level output of the ZP-port.

[0188] In order to satisfy the characteristics of the ZP-port among the matrix relationships defining the current conveyor, in this embodiment, p-MOSFET MP10 and p-MOSFET MP11, and n-MOSFET MN10 and n-MOSFET MN11 are each MOSFETs having the same gate channel length and channel width.

[0189] In actual commercial circuit configurations, each MOSFET can transmit or receive signals on a data transmission line by reflecting the characteristics of the data transmission line, and the current mirroring ratio of the X-port and Y-port in the transmitting and receiving current conveyors can be implemented as 1:N (where N is a positive decimal greater than 0 and less than 2). On the transmitting side, the signal is intentionally amplified or distorted to pre-emphasize the signal by reflecting the characteristics of the communication line, and on the receiving side, equalizing technology is applied to improve the SNR and facilitate signal judgment.

[0190] Figure 13 is a circuit diagram illustrating a current conveyor according to another example.

[0191] Referring to FIG. 13, the current conveyor (CC) includes a core block (CORE) and a driving block (D2).

[0192] The core block (CORE) is identical to the core block (CORE) shown in FIG. 10, so the same reference numeral is used and the detailed description is omitted.

[0193] The driving block (D2) includes a first driver (1210) and a second driver (2220), and outputs a first normal output current and a second normal output current through a first ZP-port (IZPP) and a second ZP-port (IZPN) in response to a first driving voltage (P_DRV) and a second driving voltage (N_DRV).

[0194] The first driver (1210) consists of a series-connected p-MOSFET MP10 and an n-MOSFET MN10. The p-MOSFET MP10 has a source to which the first power supply voltage (VDD) is applied, a gate connected to the upper current mirror terminal (1130), and a drain connected to the X-port of the n-MOSFET MN10. The n-MOSFET MN10 has a source to which the second power supply voltage (VSS) is applied, a gate connected to the lower current mirror terminal (1140), and a drain connected to the X-port of the p-MOSFET MP10. The first driver (1210) performs the function of connecting the output to the X-port of the input stage to match the structure of the second-generation current conveyor.

[0195] The second driver (2220) is composed of p-MOSFET MP11 and n-MOSFET MN11 connected in series in the same structure as the first driver (1210), p-MOSFET MP12 and p-MOSFET MP13 connected to n-MOSFET MN11 to output a first normal output current through a first ZP-port (IZPP), and n-MOSFET MN12 and n-MOSFET MN13 connected to p-MOSFET MP11 to output a second normal output current through a second ZP-port (IZPN).

[0196] p-MOSFET MP11 has a source to which VDD is applied, an upper current mirror terminal (1130), a gate commonly connected to the gate of p-MOSFET MP10, and a drain connected to the source of n-MOSFET MN12. n-MOSFET MN11 has a source to which VSS is applied, a lower current mirror terminal (1140), a gate commonly connected to the gate of n-MOSFET MN10, and a drain connected to the drain of p-MOSFET MP12.

[0197] p-MOSFET MP12 has a source to which VDD is applied, a gate and a drain commonly connected to the source of n-MOSFET MN11. p-MOSFET MP13 has a source to which VDD is applied, a drain connected to the gate of p-MOSFET MP12, and a drain connected to the first ZP-port. p-MOSFET MP12 and p-MOSFET MP13 function as current mirrors that source current.

[0198] n-MOSFET MN12 has a source connected to the drain of p-MOSFET MP11, a gate connected to the source and connected to the drain of p-MOSFET MP11, and a drain connected to VSS. n-MOSFET MN13 has a source connected to the second ZP-port, a gate connected to the gate of n-MOSFET MN12, and a drain connected to VSS. n-MOSFET MN12 and n-MOSFET MN13 function as current mirrors that sink the current.

[0199] Unlike the first driver (1210) being connected to the X-port of the differential input stage of the upper differential input terminal (1110) and the lower differential input terminal (1120), the second driver (2220) is connected to the first ZP-port (IZPP) and the second ZP-port (IZPN) for output driving.

[0200] Although a folded cascode OPAMP circuit with rail-to-rail input and output is illustrated in FIGS. 10 and 13 as an OPAMP usable as a current conveyor, a current conveyor with the same function can be designed by applying circuit structures such as a traditional current conveyor, cascode OPAMP, telescopic OPAMP, or two-stage OPAMP.

[0201] In this embodiment, the first communication module (200) and the second communication module (300) are arranged in a structure facing each other with respect to the data transmission line (100), and their circuit components are identical. Therefore, since the description of the second communication module (300) can be easily inferred from the description of the first communication module (200), the description below will focus on the first communication module (200).

[0202] FIG. 14 is a drawing for explaining an example of the first communication module illustrated in FIG. 4.

[0203] Referring to FIGS. 4 and FIGS. 14, the first communication module (200) includes a TX buffer (BTX0), a TX resistor (RTX0), a TX switch (S0), a TX current conveyor (TX_CC), a mode switching switch (S2), an RX switch (S1), an RC parallel circuit (RCP), and an RX buffer (BRX), and converts an input voltage signal into current and provides it to a transmission line (100).

[0204] The TX buffer (BTX0), TX resistor (RTX0), TX switch (S0), TX current conveyor (TX_CC), and mode switching switch (S2) are connected in series and connected to the TX current conveyor (TX_CC).

[0205] The TX current conveyor (TX_CC) includes an EN-port into which an EN signal is input, a Y-port into which a common mode voltage (VCOM) is input, an X-port connected to a TX switch (S0), and a ZP-port connected to a mode switching switch (S2). In this embodiment, the common mode voltage (VCOM) may correspond to half of the VDD power supply voltage.

[0206] The mode switching switch (S2) includes a first terminal (A), a second terminal (B), and a third terminal (S). At this time, when the first terminal (A) and the third terminal (S) are connected, the ZP-port of the TX current conveyor (TX_CC) and the I / O pad are connected. Also, when the second terminal (B) and the third terminal (S) are connected, the ZP-port of the TX current conveyor (TX_CC) and the X-port of the TX current conveyor (TX_CC) are connected.

[0207] The RX switch (S1) is connected between the ZP-port of the TX current conveyor (TX_CC) and the RC parallel circuit (RCP). The RC parallel circuit (RCP) has a resistor and a capacitor connected in parallel, with one end connected to the RX switch (S1) and the RX buffer (BRX), and the other end connected to the common mode voltage (VCOM). The RX buffer (BRX) is connected to the RC parallel circuit (RCP) to output an RX signal. In this embodiment, the RC parallel circuit (RCP) is shown between the RX switch (S1) and the RX buffer (BRX), but a resistor element alone may be placed between the RX switch (S1) and the RX buffer (BRX).

[0208] In this embodiment, the TX buffer (BTX0) is enabled according to the TX_EN signal and provides the TX signal to the TX resistor (RTX0). The operating voltage of the TX buffer (BTX0) is the VDD power supply voltage. The TX resistor (RTX0) is placed between the TX buffer (BTX0) and the X-port of the TX current conveyor (TX_CC), so that the voltage of the TX signal, which is a logic signal, can be easily converted into two types of currents applied to the X-port of the TX current conveyor (TX_CC). That is, for the logic signal voltage values ​​of 0 and 1, current values ​​of -1 and +1 of relative magnitude can be applied to the X-port of the TX current conveyor (TX_CC).

[0209] When the voltage of the power supply of the logic core generating the transmission signal and the power supply of the interface for signal transmission are different, or when different voltages must be used for the quality of the communication signal, the TX buffer (BTX0) may use a buffer including a voltage level shifter. The operating voltage of the voltage level shifter is the VDD power supply voltage.

[0210] At this time, when the value of the TX resistor (RTX0) is RTX, the voltage of the TX buffer (BTX0) is VDD, the common mode voltage (VCOM) is 1 / 2VDD, and the value of the TX buffer (BTX0) is 1, the current applied to the X-port of the TX current conveyor (TX_CC) is given by the following equation (2).

[0211] [Equation 2]

[0212]

[0213] On the other hand, when the value of the TX buffer (BTX0) is 0, the current applied to the X-port of the TX current conveyor (TX_CC) is as shown in the following equation (3).

[0214] [Equation 3]

[0215]

[0216] Since the common mode voltage (VCOM) is 1 / 2VDD, the above currents are (1 / 2VDD) / RTX and -(1 / 2VDD)RTX, respectively, and can be expressed as +1 and -1, respectively in relative magnitude.

[0217] When the TX buffer (BTX0) is disabled, the output of the TX buffer (BTX0) is floating, and the value of the current applied to the X-port of the TX current conveyor (TX_CC) is "0". Also, the value of the current mirrored to the ZP-port of the TX current conveyor (TX_CC) is "0". When this signal state is applied to the data transmission line (100), it has a relative magnitude of 0.

[0218] FIG. 15 is a circuit diagram illustrating the operation of the first communication module shown in FIG. 14 in a data transmission mode. In FIG. 15, the operating parts are indicated by solid lines, and the non-operating parts are indicated by dotted lines.

[0219] Referring to FIGS. 4, 14, and 15, for the data transmission mode, the EN signal and the TX_EN signal are activated to "1", and the RX_EN signal is deactivated to "0". At this time, the TX switch (S0) is turned ON, the RX switch (S1) is turned OFF, and the third terminal (S) of the mode switching switch (S2) is connected to the first terminal (A).

[0220] The TX signal is input to the X-port of the current conveyor (TX_CC) via the TX buffer (BTX0), T node (T0), TX resistor (RTX0), and TX switch (S0). The ZP-port of the current conveyor (TX_CC) is connected to an I / O pad through a mode switching switch (S2) to transmit a signal.

[0221] FIG. 16 is a circuit diagram illustrating the first communication module (200) shown in FIG. 14 operating in a data reception mode. In FIG. 16, the operating parts are indicated by solid lines, and the non-operating parts are indicated by dotted lines.

[0222] Referring to FIGS. 4, 14, and 16, for the data reception mode, the EN signal and the RX_EN signal are activated to "1", and the TX_EN signal is deactivated to "0". At this time, the TX switch (S0) is turned OFF, the RX switch (S1) is turned ON, and the third terminal (S) of the mode switching switch (S2) is connected to the second terminal (B).

[0223] The received signal input through the I / O pad is input to the X-port of the current conveyor (TX_CC) via the mode switching switch (S2). The ZP-port of the current conveyor (TX_CC) is connected to the RX buffer (BRX) via the RX switch (S1) to handle signal reception.

[0224] As described above, when a first transmission signal (TX_A) is provided to the first communication module (200) from an external device (not shown), the first communication module (200) converts the first transmission signal (TX_A) into a first transmission current and outputs it to one end of the data transmission line (100).

[0225] The second communication module (300) drives a first receiving current, which has the same level as the first transmitting current input via the data transmission line (100) and has the opposite sign (phase of 180 degrees), to the data transmission line (100), so that the current input from one end and the current input from the other end on the data transmission line (100) cancel each other out. Accordingly, the voltage change between the data transmission lines (100) that occurs during signal transmission is theoretically 0V, and in actual implementation, is controlled to be less than a few mV or tens of mV for a short period of time. At the same time, the first receiving current is mirrored to output a receiving signal as the first receiving voltage, thereby restoring the transmitting signal.

[0226] Meanwhile, when a second transmission signal (TX_B) is provided to the second communication module (300) from an external device (not shown), the second communication module (300) converts the second transmission signal (TX_B) into a second transmission current and outputs it to the other end of the data transmission line (100).

[0227] The first communication module (200) drives a second receiving current, which has the same level as the second transmitting current input via the data transmission line (100) and has the opposite sign (phase of 180 degrees), to the data transmission line (100), so that the current input from one end and the current input from the other end on the data transmission line (100) cancel each other out. Accordingly, the voltage change between the data transmission lines (100) that occurs during signal transmission is theoretically 0V, and in actual implementation, is controlled to a few mV or tens of mV or less for a short period of time. At the same time, the second receiving current is mirrored to output a receiving signal as a second receiving voltage, thereby restoring the transmitting signal.

[0228] In this embodiment, the reason why the current input at one end of the data transmission line (100) and the current input at the other end cancel each other out is explained in terms of voltage and current.

[0229] First, regarding voltage, the current conveyor contains an OPAMP circuit (shown in FIG. 10 as the first driver (210) of the core block (CORE) and driving block (D2)) that controls the voltage of the X-port to be equal to the voltage of the Y-port, as described above. When the OPAMP circuit is in operation, if the voltage of the X-port differs from that of the Y-port due to the current applied to the X-port, the OPAMP circuit inside the current conveyor detects this and immediately performs the function of actively supplying or consuming current to make the voltage of the X-port equal to the voltage of the Y-port. Due to this function, the voltage of the X-port is offset to the same value regardless of the value of the current input to the X-port, thereby allowing the voltage of the Y-port to be maintained at a constant level.

[0230] Meanwhile, from the perspective of current flow, when current is applied to the X-port of the current conveyor, the current temporarily attempts to raise or lower the voltage of the X-port. If a difference occurs between the voltage of the X-port and the voltage of the Y-port during this process, the OPAMP circuit inside the current conveyor detects this and immediately performs the function of drawing out or supplying the necessary amount of current to the X-port so that the voltage of the X-port and the voltage of the Y-port become equal. Due to this function, the currents cancel each other out, so the voltage of the X-port remains the same as that of the Y-port.

[0231] In each of the first communication module (200) and the second communication module (300), various methods may be employed in addition to the method of using a current conveyor as a circuit that converts an externally input voltage signal into current.

[0232] FIG. 17 is a drawing for explaining another example of the first communication module (200) illustrated in FIG. 4. In particular, the first communication module (200) including a voltage-current converter that replaces the current conveyor in data transmission mode is illustrated.

[0233] Referring to FIG. 17, the first communication module (200) includes a transmitting mode unit (TMP) and a receiving mode unit (RMP).

[0234] The transmission mode unit (TMP) includes a first buffer (310) and a voltage-current conversion unit (320), and converts a TX signal of a voltage level input from the outside into current and outputs it to a data transmission line (100) through an I / O pad.

[0235] Specifically, the first buffer (310) includes a front inverter that is enabled by a TX_EN signal to invert a TX signal, and a rear inverter connected to the rear of the front inverter and enabled by a TX_EN signal to invert a signal inverted by the front inverter.

[0236] The voltage-current converter (320) includes a pull-up current source (322), a pull-down current source (323), a pull-up switch (324), and a pull-down switch (325). The pull-up current source (322) and the pull-down current source (323) generate a first current. The pull-up current source (322) and the pull-down current source (323) may include a current source or a current mirror. The pull-up switch (324) controls the output of the first current generated from the pull-up current source (322) in response to a signal output from the downstream inverter of the first buffer (310). The pull-down switch (325) controls the output of the first current generated from the pull-down current source (323) in response to a signal output from the upstream inverter of the buffer (310).

[0237] Accordingly, a current corresponding to the transmission voltage signal, i.e., a first current, is applied to the data transmission line (100) connected through the I / O pad. That is, to convert the input voltage signal into a current, a current switch in which a pull-up switch (324) and a pull-down switch (325) are connected to a pull-up current source (322) and a pull-down current source (323) may be used.

[0238] The receiving mode unit (RMP) includes an RX current conveyor (RX_CC), an RC parallel circuit (RCP), and an RX buffer (BRX), and converts a receiving current input from a data transmission line (100) connected through an I / O pad into an RX signal of a voltage level.

[0239] Specifically, the RX current conveyor (RX_CC) includes an EN-port to which the RX_EN signal is applied, a Y-port to which the common mode voltage (VCOM) is applied, an X-port connected to a data transmission line (100) via an I / O pad, and a ZP-port connected to an RC parallel circuit (RCP). In transmission mode, when the TX_EN signal becomes high level and the RX_EN signal becomes low level, the X-port of the RX current conveyor (RX_CC) becomes High-Z state and does not affect transmission operation. In reception mode, when the TX_EN signal becomes low level and the RX_EN signal becomes high level, the output of the current source becomes High-Z state and does not affect the X-port input of the RX current conveyor (RX_CC).

[0240] The RC parallel circuit (RCP) includes a resistor (RRX) and a capacitor (CRX) connected in parallel, and receives the received current output through the ZP-port of the RX current conveyor (RX_CC) to charge and form a received voltage.

[0241] The RX buffer (BRX) is enabled by the RX_EN signal and outputs the received voltage formed by the RC parallel circuit (RCP) to the outside through the RX terminal.

[0242] As such, according to the first communication module (200) described in FIG. 17, the TX switch (S0), RX switch (S1), and mode switching switch (S2) in the first communication module (200) described in FIG. 14 or FIG. 16 can be removed, and the current source is involved only in the data transmission mode, and the RX current conveyor (RX_CC) is involved only in the reception mode, allowing for application in a structure.

[0243] FIG. 18 is a circuit diagram of another application example in which the voltage-current converter (310, 320) of FIG. 17 is replaced with a buffer and a resistor.

[0244] Referring to FIG. 18, the switches in FIG. 17 are removed, and the current conveyor is used only for receiving signals. A resistor is connected to one end of the buffer receiving the TX signal, and the other end is directly connected to a PAD connected to the data transmission line. The high or low voltage output of the buffer is converted into a pull-up or pull-down current signal through the TX resistor (RTX).

[0245] FIG. 19 is a diagram showing the data transmission line illustrated in FIG. 4 implemented with four lines.

[0246] Referring to FIG. 19, Cp existing between each data transmission line (100) refers to the parasitic capacitance existing between facing conductor data transmission lines when adjacent data transmission lines (100) are arranged in a plane or space. Although it actually varies depending on the structure and width of the wiring, it is described in this specification as a general term, Cp value.

[0247] FIG. 20 is a circuit diagram for explaining an example of a data communication device illustrated in FIG. 4.

[0248] Referring to FIG. 20, the first communication module (200) and the second communication module (300) are connected via a single data transmission line (100), and the operation is configured such that the first communication module (200) transmits a signal and the second communication module (300) receives a signal. The capacitive load of the single data transmission line (100) is briefly defined as CIO to explain the signal transmission process.

[0249] D_TX, where the transmission signal is input, is a port that receives the signal to be transmitted in the logic circuit.

[0250] The TX buffer (BTX) is responsible for outputting the value of a signal 1 or 0 to be transmitted from the logic circuit to a low impedance (low R-ON resistance) using a MOSFET connected to the VDD power supply voltage and the GND power supply.

[0251] The TX buffer (BTX) can be composed of a MOSFET having an ON resistance of at least 1 / 10 of the resistance value of the TX resistor (RTX). The output terminal of the TX buffer (BTX) is connected to one end of the TX resistor (RTX). Even if the voltage of node b, connected to the other end of the TX resistor (RTX), reaches the common mode voltage (VCOM), it has sufficient driving capability (or an ON resistance sufficiently small compared to TRX). Therefore, when driving the TX buffer (BTX), the signal transmission characteristics are superior as the "L" signal approaches 0V and the "H" signal approaches the VDD power supply voltage, respectively.

[0252] However, reducing ON resistance requires increasing the gate area, and since this increased area results in an increase in gate capacitance, it has a negative impact on operating speed and power consumption. Therefore, the size of the MOSFETs that make up the TX buffer (BTX), especially the output MOSFETs, must be carefully determined to suit the system characteristics.

[0253] In addition, if the operating voltage of the logic circuit (commonly referred to as the core voltage) and the VDD power supply voltage to be used for signal transmission are not the same, the TX buffer (BTX) includes a voltage level shifter function that includes a voltage level conversion function.

[0254] FIG. 21 is a circuit diagram illustrating an example of the TX buffer (BTX) shown in FIG. 20.

[0255] Referring to FIGS. 20 and 21, in the TX buffer (BTX), MOSFET P0 and MOSFET N0 are primary inverter-buffers that first invert and buffer the input values ​​of logic values. Also, in the TX buffer (BTX), MOSFET P1 and MOSFET N1 are secondary inverter-buffers that use large-sized FETs with a larger gate channel width and lower ON resistance compared to MOSFET P0 and MOSFET N0.

[0256] The TX buffer (BTX) of the first communication module (200) may have a control signal enable pin (EN pin) for enabling / disabling the operation state or when the current value to be output is 0 (high impedance, Hi-Z).

[0257] FIG. 22 is a circuit diagram illustrating another example of the TX buffer (BTX) shown in FIG. 20. In particular, an example is shown in which an enable pin (EN pin) is added to the TX buffer (BTX). FIG. 22 can also be used as an example of a circuit diagram that serves as the TX buffer of FIG. 18.

[0258] Referring to FIGS. 20 and 22, when the enable pin (EN pin) is "0", the GP signal is High (1) regardless of the input transmission signal IN, and the MOSFET P0 is turned OFF. The GN signal is Low (0), and the MOSFET N0 is turned OFF, thereby blocking the output of the TX buffer (BTX).

[0259] Meanwhile, when the enable pin (EN pin) is "1", the output of OUT is controlled in phase according to the signal of the data input IN.

[0260] The 3-input NOR gate and the 3-input NAND gate have a latch structure in which their respective outputs are connected to the inputs of the other side. When MOSFET P0 and MOSFET N0 are switching at high speed, they perform the function of generating a non-overlap gate control signal for the GP signal and GN signal so that MOSFET P0 and MOSFET N0 are simultaneously turned ON for a short time due to a mismatch in the rising delay and falling delay of the GP signal and GN signal, thereby preventing a short current from occurring from the VDD power supply voltage toward GND.

[0261] FIG. 23 is a circuit diagram illustrating another example of the TX buffer (BTX) shown in FIG. 20. In particular, another example is shown in which an enable pin (EN pin) is added to the TX buffer (BTX).

[0262] Referring to FIG. 20 and FIG. 23, when the enable pin (EN pin) is "0", MOSFET P1 is turned off and MOSFET N1 is turned off, thereby blocking the output of the TX buffer (BTX).

[0263] When the enable pin (EN pin) is "1", both MOSFET P1 and MOSFET N1 are turned on, and the output of the OUT terminal is controlled in phase according to the signal of the data input IN. Therefore, the TX buffer (BTX) shown in FIG. 23 is easy to control.

[0264] Referring again to FIG. 20, the TX resistor (RTX) performs the role of determining the signal current value transmitted from the first communication module (200), which is the transmitting side, to the second communication module (300), which is the receiving side. When the output of the TX buffer (BTX) is VDD power supply voltage (logic 1) and the value of the common mode voltage (VCOM) of the TX current conveyor (TX_CC) is 1 / 2 VDD, the signal current value generated by the TX resistor (RTX) is as follows in Equation (4).

[0265] [Equation 4]

[0266]

[0267] At this time, if VDD is set to 1.0V and the resistance value of the TX resistor (RTX) is set to 5KΩ, the common mode voltage (VCOM) becomes 0.5V, the signal current generated from the TX resistor (RTX) becomes +0.1mA, and a forward current of 0.1mA flows from VDD through the TX resistor (RTX) to line c, which is the X-port of the RX current conveyor (RX_CC).

[0268] In the same environment as above, when the output of the TX buffer (BTX) is 0V (logic 0), the equation for the current generated by the TX resistor (RTX) is as follows (5).

[0269] [Formula 5]

[0270]

[0271] The current value becomes -0.1mA, and a reverse current of 0.1mA flows from line b, which is the X-port of the RX current conveyor (RX_CC), toward the GND of the TX buffer (BTX).

[0272] As described above, when there is one TX buffer (BTX) and one TX resistor (RTX), two current signal levels can be generated.

[0273] In the manner described above, when there are two TX buffers (BTX) and two TX resistors (RTX), four different current signal levels can be generated. That is, when the EN signals of the TX buffers (BTX) are controlled individually, four different transmission signals can be received as inputs with logic values ​​in binary form, such as 11, 10, 01, and 00. For each of the four transmission signals, four different currents used for communication can be generated, such as +0.3mA, +0.1mA, -0.1mA, and -0.3mA. Therefore, the signal transmission capacity per unit transmission path can be increased.

[0274] The TX current conveyor (TX_CC) of the first communication module (200) and the RX current conveyor (RX_CC) of the second communication module (300) each include an X-port, which is a low-impedance port responsible for the input and output of current, a ZP-port that mirrors and outputs the current of the X-port, and a Y-port responsible for voltage input.

[0275] When the transmission signal D_TX is 1 (High), current i0 from the output a of the TX buffer (BTX) is input to line b, which is the X-port of the TX current conveyor (TX_CC), through the TX resistor (RTX) with reference to the VDD power supply voltage. At this time, the X-port of the TX current conveyor (TX_CC) connected to line b generates a current i1 in the GND direction that has the same current value as current i0 but the opposite sign, thereby maintaining a voltage level equal to the common mode voltage (VCOM) input to the Y-port.

[0276] At the same time, current i1 is mirrored to generate and output current i2 to data transmission line c connected to the ZP-port. Current i2 is a communication signal current output to data transmission line c, and is a current flowing from the ZP-port (data transmission line c) toward GND. Current i2 generally has a 1:1 ratio relationship with current i1, but the ratio can be set to be smaller or larger than 1 as needed.

[0277] Current i2 is connected to the X-port, a low-impedance port of the RX current conveyor (RX_CC), via data transmission line c. To maintain a voltage equal to the common-mode voltage (VCOM) connected to the Y-port, the X-port of the RX current conveyor (RX_CC) generates a current i3 from the VDD power supply voltage in the direction of data transmission line c that is equal to but opposite in sign to current i2, while simultaneously outputting current i4 to the ZP-port.

[0278] At this time, the data transmission line c theoretically performs the function of maintaining the common mode voltage (VCOM) level regardless of the magnitude and sign of the communication current i2 (when transmitting a logic 0 signal or a logic 1 signal) according to the definition of the current conveyor. Therefore, when transmitting a data signal according to the present invention, there is no voltage change in the data transmission line c, or only a very small change in ripple voltage at the level of a few mV is observed in response to a signal change faster than the response speed of the TX current conveyor (TX_CC) and the RX current conveyor (RX_CC).

[0279] In cases where very small voltage changes or no changes are observed in such data transmission lines c, compared to conventional technology which has transmitted data with large voltage signals such as 0.3V to 1.2V, the current consumed due to parasitic capacitance (CIO) of the data transmission line can be minimized or eliminated. This reduction in power consumption of the data transmission line enables signal transmission at higher speeds with less energy.

[0280] Furthermore, since there is almost no voltage change in data transmission line c during communication operations, the radiation of unnecessary EMI noise is reduced. In addition, when multiple data transmission lines are implemented in parallel, signal interference (crosstalk) caused by cross-coupling capacitance between data transmission lines can be minimized, thereby improving communication signal quality.

[0281] Due to these effects, signals can be transmitted at high speeds with lower power consumption over lower-quality data transmission lines, thereby reducing the manufacturing cost of high-speed parallel signal transmission systems, decreasing heat generation, and improving the reliability and lifespan of the system.

[0282] The current i4 output from the ZP-port of the RX current conveyor (RX_CC) is restored to the signal of the received voltage through the RX resistor (RRX) connected in series with the common mode voltage (VCOM) via line d.

[0283] The restored received voltage can be expressed by the formula (VCOM + i4 * RRX).

[0284] As in the example of the transmitting side above, when the transmitting current is +0.1mA and -0.1mA, the TX current conveyor (TX_CC) and the RX current conveyor (RX_CC) mirror the current in a 1:1 ratio, and the RX resistor (RRX) is set to 5KΩ, which is the same as the TX resistor (RTX), the common mode voltage (VCOM) becomes 0.5V, i4 becomes +0.1mA and -0.1mA respectively, and the receiving voltage becomes 1V and 0V respectively according to the above formula, so it can be confirmed that the transmitting signal is accurately transmitted to the receiving signal.

[0285] It is preferable for the RX resistor (RRX) to have a 1:1 ratio with the TX resistor (RTX) used for generating the transmission voltage, but it can be set to a value less than or greater than 1 if necessary, depending on the conditions of the data transmission line and the transmission speed. However, it is desirable that the range of the RX resistor (RRX) value be determined within a range where the value of (VCOM + i4*RRX) is less than 0 and not greater than 1. The RX capacitor (CRX) connected in parallel with the RX resistor (RRX) is a capacitance element with a very small value and is not a mandatory component. If necessary, the capacitance value of the RX capacitor (CRX) can be set so that the RC time constants of the RX resistor (RRX) and the RX capacitor (CRX) are appropriate for the transmission speed of the signal to be transmitted, and it can perform the role of a low-pass filter to improve the SNR (Signal-to-Noise Ratio) of the received signal.

[0286] It performs the role of amplifying the output current of the corresponding signal and outputting it as a logic value when the voltage generated on data transmission line c exceeds (is 1) or falls short (is 0) the threshold voltage on the input side of the RX buffer (BRX). Typically, a buffer consisting of two connected inverters is used, but to increase the SNR, an inverter with a Schmitt-trigger function can be used as the front-end inverter. Additionally, if the design ensures that the voltage fluctuation rate of data transmission line c does not change significantly near the logic threshold voltage, a comparator circuit or AMP circuit using the common mode voltage (VCOM) as the reference voltage is applied.

[0287] In addition, if the operating voltages of the transmitting / receiving system and the logic core differ, a voltage converter (i.e., a voltage level shifter) must be used additionally.

[0288] FIG. 24 is a configuration diagram for explaining a data communication system according to an embodiment of the present invention. FIG. 25 is a circuit diagram for explaining a first communication module illustrated in FIG. 24.

[0289] Referring to FIGS. 24 and 25, a data communication system according to another embodiment of the present invention includes a data transmission line section (1100), a first communication module section (1200) connected to one end of the data transmission line section (1100), a first differential decoder (1210), a second communication module section (1300) connected to the other end of the data transmission line section (1100), and a second differential decoder (1310).

[0290] The data transmission line section (1100) is configured to correspond to four parallel data transmission lines. The coupling capacitors between the data transmission lines are all expressed as Cp values. However, in the actual implementation of the data transmission lines, each Cp value generally has a different value, and that value is relatively smaller than the Cs values. For convenience of explanation, the values ​​of the coupling capacitances are collectively referred to as Cp in this specification.

[0291] It is obvious that the basic data communication device having the above four data transmission lines (1100) can be modularized in parallel to be applied as an extended data communication device handling, for example, 256, 512, or 1024 communication lines.

[0292] The first communication module section (1200) is defined by four first communication modules (200) arranged in parallel, and the second communication module section (1300) is defined by four second communication modules (300) arranged in parallel.

[0293] The first communication module (200) includes a TX buffer (BTX0), a TX resistor (RTX0), a TX switch (S0), a TX current conveyor (TX_CC), a mode switching switch (S2), an RX switch (S1), and an RC parallel circuit (RCP), and converts an input voltage signal into current and provides it to a transmission line (100).

[0294] The TX buffer (BTX0), TX resistor (RTX0), TX switch (S0), TX current conveyor (TX_CC), and mode switching switch (S2) are connected in series and connected to the TX current conveyor (TX_CC).

[0295] The TX current conveyor (TX_CC) includes an EN-port into which an EN signal is input, a Y-port into which a common mode voltage (VCOM) is input, an X-port connected to a TX switch (S0), and a ZP-port connected to a mode switching switch (S2). In this embodiment, the common mode voltage (VCOM) may correspond to half of the VDD power supply voltage.

[0296] The mode switching switch (S2) includes a first terminal (A), a second terminal (B), and a third terminal (S). At this time, when the first terminal (A) and the third terminal (S) are connected, the ZP-port of the TX current conveyor (TX_CC) and the I / O pad are connected. Also, when the second terminal (B) and the third terminal (S) are connected, the ZP-port of the TX current conveyor (TX_CC) and the X-port of the TX current conveyor (TX_CC) are connected.

[0297] The RX switch (S1) is connected between the ZP-port of the TX current conveyor (TX_CC) and the RC parallel circuit (RCP). The RC parallel circuit (RCP) has a resistor and a capacitor connected in parallel, with one end connected to the RX switch (S1) and the other end connected to the common mode voltage (VCOM). In this embodiment, the RC parallel circuit (RCP) is illustrated, but a resistor element alone may be used.

[0298] Only two signals are transmitted through four data transmission lines. At this time, the difference between the first data transmission line and the second data transmission line, and the difference between the third data transmission line and the fourth data transmission line are the signals to be transmitted.

[0299] FIG. 26 is a circuit diagram for explaining another example of the first communication module shown in FIG. 24.

[0300] Referring to FIG. 26, the switches in FIG. 25, namely the TX switch (S0), RX switch (S1), and mode switching switch (S2), are removed, and the current conveyor (RX_CC) is used only for receiving signals. Resistors are connected to one end of each buffer receiving the TX[0] and TX[1] signals, and the other end is directly connected to a PAD connected to the data transmission line. The high or low voltage output of each buffer is converted into a pull-up or pull-down current signal through the resistor RTX, respectively.

[0301] In FIG. 26, a TX resistor (RTX) is shown placed at the rear end of the TX buffer (BTX0), but the TX resistor (RTX) may be omitted. That is, it is possible to implement the method by removing the TX resistor (RTX) and controlling the on-resistance values ​​of the PMOS FET and NMOS FET provided in the terminal driver or output switch of the TX buffer (BTX0).

[0302] In one example, when using PMOS FETs and NMOS FETs of a termination driver, the circuit diagram shown in FIG. 22 can be used. That is, in FIG. 22, the Ron resistance value of MOSFET P0 is set to be equal to the resistance value of TX resistor (RTX), and the Ron resistance value of MOSFET N0 is set to be equal to the resistance value of TX resistor (RTX).

[0303] The Ron resistance value of the above MOSFET can be defined as shown in the following equation (6).

[0304] [Equation 6]

[0305]

[0306] Here, The channel length, is carrier movement, is the capacitance of the oxidation film, is channel width, is the gate-source voltage, and represents the threshold voltage.

[0307] In another example, when using PMOS FETs and NMOS FETs provided in the output switch of a termination driver, the circuit diagram shown in FIG. 23 may be used. That is, in FIG. 23, for example, MOSFET P0 and MOSFET N0 are designed to have very small on-resistance values, such as an idle (ideal) switch, and the Ron resistance values ​​of MOSFET P1 and MOSFET N1 are set to be equal to the resistance value of the TX resistor (RTX). In another example, the sum of the on-resistance values ​​of MOSFET P0 and MOSFET P1 is set to be equal to the resistance value of the TX resistor (RTX), and the sum of the ON resistance values ​​of MOSFET N0 and MOSFET N1 is set to be equal to the resistance value of the TX resistor (RTX).

[0308] FIG. 27 is a circuit diagram for explaining another example of the first communication module shown in FIG. 24.

[0309] Referring to FIG. 27, the switches in FIG. 25, namely the TX switch (S0), RX switch (S1), and mode switching switch (S2), have been removed, and the current conveyor (RX_CC) is used only for receiving the signal TX[0]. Resistors are connected to one end of each buffer receiving the TX[1] signal, and the other end is directly connected to a PAD connected to the data transmission line. The high or low voltage output of each buffer is converted into a pull-up or pull-down current signal through the resistor RTX, respectively.

[0310] FIG. 28 is a block diagram for explaining the first differential decoder (1210) illustrated in FIG. 24.

[0311] Referring to FIGS. 24 and 28, the first differential decoder (1210) includes a first comparator (COP1), a second comparator (COP1), and a logic encoder (LOE).

[0312] The first comparator (COP1) provides a first result value obtained by comparing signal RX[0] and signal RX[1] to the logic encoder (LOE), and the second comparator (COP1) provides a second result value obtained by comparing signal RX[2] and signal RX[3] to the logic encoder (LOE). The logic encoder (LOE) represents the first and second result values ​​as 2-bit signal RXD[1:0].

[0313] When transmitting a 2-level signal, 2 bits of data are transmitted as differential signals through four data transmission lines. That is, in the case of encoding that transmits the signal, a 1-bit signal is input, and the signal in the current phase is applied to one data transmission line and the signal in the reverse phase is applied to another data transmission line to be represented on the data transmission lines.

[0314] FIG. 29 is a configuration diagram for explaining a data communication system according to another embodiment of the present invention. In particular, a data communication system configured to correspond to four data communication devices is shown.

[0315] Referring to FIG. 29, a data communication system according to another embodiment of the present invention includes a data transmission line section (2100), a first communication module section (2200) connected to one end of the data transmission line section (2100), and a second communication module section (2300) connected to the other end of the data transmission line section (2100).

[0316] The data transmission line section (2100) is configured to correspond to four parallel data transmission lines. The coupling capacitors between the data transmission lines are all expressed as Cp values. However, in the actual implementation of the data transmission lines, it is common for each Cp value to have a different value, and that value is relatively smaller than the Cs values. For convenience of explanation, the values ​​of the coupling capacitances are collectively referred to as Cp in this specification.

[0317] It is obvious that the basic data communication device having the above four data transmission lines (2100) can be modularized in parallel to be applied as an extended data communication device handling, for example, 256, 512, or 1024 communication lines.

[0318] The first communication module section (2200) is defined by four first communication modules (200, described in FIG. 4) arranged in parallel, and the second communication module section (2300) is defined by four second communication modules (300, described in FIG. 4) arranged in parallel.

[0319] Here, the first enable signal (EN_A), the first TX enable signal (TX_EN_A), and the first RX enable signal (RX_EN_A) applied to the first communication module (2200) have a 1-bit value. Additionally, the first enable signal (EN_A), the first TX enable signal (TX_EN_A), and the first RX enable signal (RX_EN_A) are applied in common to each of the four parallel-arranged first communication modules (200). The first TX signal applied to the first communication module (2200) has an 8-bit value, and the first RX signal output from the first communication module (2200) has a 4-bit value. In addition, the first TX signal is applied independently to each of the four parallel-arranged first communication modules (200), and the first RX signal is output independently from each of the four parallel-arranged first communication modules (200).

[0320] Additionally, the second enable signal (EN_B), the second transmit enable signal (TX_EN_B), and the second receive enable signal (RX_EN_B) applied to the second communication module (2300) have a 1-bit value. Furthermore, the second enable signal (EN_B), the second transmit enable signal (TX_EN_B), and the second receive enable signal (RX_EN_B) are applied in common to each of the four parallel-arranged second communication modules (300). The second TX signal applied to the second communication module (2300) has an 8-bit value, and the second RX signal output from the second communication module (2300) has a 4-bit value. In addition, the second TX signal is independently applied to each of the four parallel second communication modules (300), and the second RX signal is independently output from each of the four parallel second communication modules (300).

[0321] Typically, for N (where N is a natural number) data transmission lines, since there are two transmittable signal levels, namely "0" and "1", the number of signals that can be transmitted at once is For example, 2 data transmission lines can send 4 different values, and 3 data transmission lines can send 8 different values.

[0322] Meanwhile, as explained in FIG. 24, if the signal stages transmitted over N data transmission lines are divided into M (where M is a natural number), the number of signals that can be transmitted at once is That is, if there are N data transmission lines and each data transmission line has M signal stages, the number of values ​​that can be transmitted is It increases. For example, if the signal stages transmitted over three data transmission lines are divided into four, the number of signals that can be transmitted at once is 64. Also, if the signal stages transmitted over four data transmission lines are divided into four, the number of signals that can be transmitted at once is 256.

[0323] FIG. 30 is a circuit diagram for explaining a PAM4 signal generator and a PAM4 signal restorer provided in the first communication module illustrated in FIG. 29. FIG. 31 is a block diagram for explaining the PAM4 signal restorer illustrated in FIG. 30.

[0324] Referring to FIGS. 29, 30, and 31, the first communication module (200) includes a PAM4 signal generator (PSG), a TX current conveyor (TX_CC), a mode switching switch (S2), an RX switch (S1), an RC parallel circuit (RCP), and a PAM4 signal restorer (PSR), and converts an input voltage signal into current and provides it to the data transmission line (100) of the data transmission line section (2100). In this embodiment, four first communication modules (200) constitute the first communication module section (2200), enabling PAM4 encoding and decoding per transmission line. That is, a 2-bit transmission signal is converted into a PAM4 signal having four signal levels through one communication module, and four such communication modules are grouped together to transmit signals to four transmission lines. The receiver is represented as a group of four receivers that distinguish 2 bits of signal per transmission line. This is an example of transmitting and receiving PAM4 signals in a single-ended manner per transmission line. In the above example, since there are 4 transmission lines and each transmission line can transmit 2 bits (4 levels, PAM4), the number of possible data cases that can be transmitted / received through the 4 transmission lines is 256 (i.e., 2^8).

[0325] The PAM4 signal generator (PSG) includes a first TX buffer (BTX0), a first TX resistor (RTX0), a second TX buffer (BTX1), a second TX resistor (RTX1), and a TX switch (S0). Here, PAM4 (Pulse Amplitude Modulation 4-level) is a modulation scheme that uses four different amplitudes in data transmission to transmit 2 bits of information per symbol, and is used for efficient signal transmission, particularly in high-speed data communication. Since PAM4 can transmit more information at once than binary, it has the advantage of being able to transmit more data within the same bandwidth.

[0326] The first TX buffer (BTX0) and the first TX resistor (RTX0), to which the TX_EN[0] signal and the TX[0] signal are applied, are connected in series and connected to one end of the TX switch (S0), and the second TX buffer (BTX1) and the second TX resistor (RTX1), to which the TX_EN[1] signal and the TX[1] signal are applied, are connected in series and connected to one end of the TX switch (S0).

[0327] The TX switch (S0) is commonly connected to the first TX resistor (RTX0) and the second TX resistor (RTX1) through one end, and connected to the X-port and mode switching switch (S2) of the TX current conveyor (TX_CC) through the other end.

[0328] The TX current conveyor (TX_CC) includes an EN-port into which an EN signal is input, a Y-port into which a common mode voltage (VCOM) is input, an X-port connected to a TX switch (S0), and a ZP-port connected to a mode switching switch (S2).

[0329] The mode switching switch (S2) includes a first terminal (A), a second terminal (B), and a third terminal (S). At this time, when the first terminal (A) and the third terminal (S) are connected, the ZP-port of the TX current conveyor (TX_CC) and the I / O pad are connected. Also, when the second terminal (B) and the third terminal (S) are connected, the ZP-port of the TX current conveyor (TX_CC) and the X-port of the TX current conveyor (TX_CC) are connected.

[0330] The RX switch (S1) is connected between the ZP-port of the TX current conveyor (TX_CC) and the RC parallel circuit (RCP). The RC parallel circuit (RCP) has a resistor and a capacitor connected in parallel, with one end connected to the RX switch (S1) and the RX buffer (BRX), and the other end connected to the common mode voltage (VCOM). The RX buffer (BRX) is connected to the RC parallel circuit (RCP).

[0331] In this embodiment, there are four types of signal levels transmitted or received from the data transmission line (100). That is, a "0" or "1" signal passing through the first TX buffer (BTX0) and the first TX resistor (RTX0) is applied to the TX current conveyor (TX_CC), and a "0" or "1" signal passing through the second TX buffer (BTX1) and the second TX resistor (RTX1) is applied to the TX current conveyor (TX_CC).

[0332] The PAM4 signal recovery unit (PSR) includes a first comparator (COP1), a second comparator (COP1), a third comparator (COP1), and a logic encoder (LOE) to recover the RX signal passing through the RC parallel circuit (RCP).

[0333] Specifically, the first comparator (COP1) provides a first result value obtained by comparing the RX signal (IN) with the first reference voltage (VREF[0]) to the logic encoder (LOE), the second comparator (COP1) provides a second result value obtained by comparing the RX signal (IN) with the second reference voltage (VREF[1]) to the logic encoder (LOE), and the third comparator (COP1) provides a third result value obtained by comparing the RX signal (IN) with the third reference voltage (VREF[2]) to the logic encoder (LOE). At this time, the first reference voltage (VREF[0]), the second reference voltage (VREF[1]), and the third reference voltage (VREF[2]) are used as reference voltages for comparing the input levels of each RX signal (IN).

[0334] The logic encoder (LOE) outputs the first to third result values ​​as a 2-bit RXA[1:0].

[0335] In this embodiment, when the first and second TX resistors (RTX0, RTX1) are used, for the values ​​of logic [1:0] 00, 01, 10, and 11 respectively, the ZP (XZ) output of the TX current conveyor (TX_CC) can be set to values ​​of -3, -1, +1, and +3 as relative magnitude currents. Additionally, when the first and second TX resistors (RTX0, RTX1) have different values, the weighted current value according to the value of the resistor is changed to generate various levels of transmission current values.

[0336] When the transmission signal is encoded into 2 bits, the TX_EN (Enable pin) signal consists of 2 bits and the TX (Data pin) consists of 2 bits. The transmission signal TX[1:0] is encoded into 4 values, and the encoded values ​​can be converted into current values ​​through the resistance of the first TX resistor (RTX0) and the second TX resistor (RTX1) and output to the data transmission line (100).

[0337] When the first communication module (200) operates in receiving mode, the RX buffer (BRX) described in FIG. 14 is not used, and a comparator is additionally used based on a reference value to distinguish four received values ​​and to decode the corresponding level.

[0338] Alternatively, if the data communication device uses multiple data transmission lines (100), encoded signals can be transmitted between each data transmission line (100), and data can be decoded and restored using the difference between the received signals.

[0339] FIG. 30 describes configuring two TX buffers and two resistors in the first communication module (200) to express four relative current values. In a similar manner, if three or more TX buffers and three or more resistors are configured in the first communication module (200), more relative current values ​​can be expressed, but this is omitted in the specification.

[0340] FIG. 32 is a circuit diagram of another example for explaining the PAM4 signal generator and PAM4 signal restorer equipped in the first communication module shown in FIG. 24.

[0341] Referring to FIG. 32, the switches in FIG. 30, namely the TX switch (S0), RX switch (S1), and mode switching switch (S2), are removed, and the current conveyor (RX_CC) is used only for receiving signals. Resistors are connected to one end of each buffer receiving the TX[0] and TX[1] signals, and the other end is directly connected to a PAD connected to a data transmission line. The high or low voltage output of each buffer is converted into a pull-up or pull-down current signal through the resistor RTX, respectively.

[0342] FIG. 33 is a waveform diagram showing the simulation results of each of the embodiment and the comparative example transmitting data patterns to one data transmission line. In particular, the simulation results of transmitting 16 data patterns to one data transmission line implemented with the technology of the present invention shown in FIG. 20 and the technology of the comparative example shown in FIG. 3 are shown.

[0343] Referring to FIG. 33, the comparative example and the example were simulated and measured under the same conditions. That is, the transmission speed was 1 GHz, the value of the CIO of the data transmission line was the same, and VDD was set to 1.0 V.

[0344] When transmitting the same transmission data, the peak-to-peak value of the voltage shown on the data transmission line c was measured to be about 7 mV for the example and about 849 mV for the comparative example. Therefore, it can be seen that the voltage amplitude measured on the data transmission line is about 1 / 120 or less smaller than that of the comparative example.

[0345] In addition, regarding the RMS current value consumed by the load CIO of the data transmission line under the same conditions, the example was simulated to consume approximately 43.9 μA, while the comparative example consumed approximately 4.97 mA. Therefore, it can be seen that the example consumes a small current of about 1 / 113 or less on the data transmission line compared to the comparative example.

[0346] Typically, if the amount of variation on the data transmission line (i.e., the amount of signal voltage change, the amount of charge energy of the load) occurring when transmitting data is large and the transmission speed is high, a limit on the balance of the DC level is necessary to improve the quality of the signal appearing on the data transmission line.

[0347] When the same data value (e.g., "0" or "1") is transmitted consecutively, the transmitted data deviates from the ideal high-band and low-band frequency transfer characteristic (Impedance) range of the data transmission line. This deviation can cause defects in the bit signal due to delays or imbalances in transient response, where the signal of the next converted value does not respond quickly.

[0348] Therefore, in conventional technology, the value of the transmitted data itself is not converted into a bit meaning and transmitted (i.e., NRZI method), but rather, in order to balance the DC level, additional overhead bits are included to balance the statistical balance of "0" and "1" (i.e., balance of DC levels), such as in encoding conversion standards like 3B4B, 4B5B, 5B6B, 8B10B, 64B / 66B, and 128B / 130B, and the data to be transmitted is encoded and transmitted in the form of data longer than the length of the transmitted data.

[0349] For example, 4B5B represents a method of converting 4-bit data into 5-bit data, and is a method of encoding 4-bit information into 5-bits for transmission. The 4B5B code is one of the line codes used in data communication, and it can reduce bit errors and increase signal stability.

[0350] The characteristic of 4B5B is that 4 bits are pre-block-coded into 5 bits so that "0" or "1" are not transmitted in a long sequence. At this time, there must be at least one transition within the 5-bit block code, and the data is structured so that three or more "0"s are not consecutive, thereby ensuring an overall balance between "0" and "1".

[0351] An example of a 4B5B code can be shown as in Table 1 below.

[0352] [Table 1]

[0353]

[0354] Referring to Table 1, the data bit "0000" is encoded as the code bit "11110", with one or more transitions and no three or more consecutive "0s". Also, the data bit "0001" is encoded as the code bit "01001", with one or more transitions and no three or more consecutive "0s". As such, while the conventional encoding method can improve the quality of the communication signal, it has the disadvantage that the amount of data that can be transmitted at the same data rate is reduced due to the additionally inserted overhead bits.

[0355] However, as can be seen from the comparison of the waveforms that appear during signal transmission (i.e., the voltage waveform of the transmission line (c) of the present invention and the voltage waveform of the transmission line (c) of the comparative example), the voltage fluctuation range and the energy required for charging / discharging the data transmission line are about 1 / 100 or less compared to the comparative example. Therefore, the present invention can significantly relax the limitations on DC level balance. Furthermore, to such an extent, sufficient signal quality can be guaranteed even with data transmission that does not require separate encoding for DC level balance.

[0356] FIG. 34 is a configuration diagram for explaining a data communication system according to another embodiment of the present invention. In particular, a data communication system configured to correspond to four data communication devices is shown.

[0357] Referring to FIG. 34, a data communication system according to another embodiment of the present invention includes a data transmission line section (3100), a first communication module section (3200) connected to one end of the data transmission line section (3100), and a second communication module section (3300) connected to the other end of the data transmission line section (3100).

[0358] The data transmission line section (3100) is configured to correspond to four parallel data transmission lines. The coupling capacitors between the data transmission lines are all expressed as Cp values. However, in the actual implementation of the data transmission lines, each Cp value generally has a different value, and that value is relatively smaller than the Cs values. For convenience of explanation, the values ​​of the coupling capacitances are collectively referred to as Cp in this specification.

[0359] It is obvious that the basic data communication device having the above four data transmission lines (3100) can be modularized in parallel to be applied as an extended data communication device handling 256, 512, or 1024 communication lines.

[0360] The first communication module section (3200) is defined by four first communication modules (200, described in FIG. 4 and FIG. 14) arranged in parallel, and the second communication module section (3300) is defined by four second communication modules (300, described in FIG. 4) arranged in parallel.

[0361] Here, the first enable signal (EN_A), the first TX enable signal (TX_EN_A), and the first RX enable signal (RX_EN_A) applied to the first communication module (3200) have a 1-bit value. Additionally, the first enable signal (EN_A), the first TX enable signal (TX_EN_A), and the first RX enable signal (RX_EN_A) are applied in common to each of the four parallel-arranged first communication modules (200). The first TX signal applied to the first communication module (3200) and the first RX signal output from the first communication module (3200) have a 4-bit value. In addition, the first TX signal is applied independently to each of the four parallel-arranged first communication modules (200), and the first RX signal is output independently from each of the four parallel-arranged first communication modules (200).

[0362] Additionally, the second enable signal (EN_B), the second transmit enable signal (TX_EN_B), and the second receive enable signal (RX_EN_B) applied to the second communication module (3300) have a 1-bit value. Furthermore, the second enable signal (EN_B), the second transmit enable signal (TX_EN_B), and the second receive enable signal (RX_EN_B) are applied in common to each of the four parallel-arranged second communication modules (300). The second TX signal applied to the second communication module (3300) and the second RX signal output from the second communication module (3300) have a 4-bit value. In addition, the second TX signal is independently applied to each of the four parallel second communication modules (300), and the second RX signal is independently output from each of the four parallel second communication modules (300).

[0363] Typically, for N (where N is a natural number) data transmission lines, since there are two transmittable signal levels, namely "0" and "1", the number of signals that can be transmitted at once is For example, 2 data transmission lines can send 4 different values, and 3 data transmission lines can send 8 different values.

[0364] Meanwhile, as explained in FIG. 34, if the signal stages transmitted over N data transmission lines are divided into M (where M is a natural number), the number of signals that can be transmitted at once is That is, if there are N data transmission lines and each data transmission line has M signal stages, the number of values ​​that can be transmitted is It increases. For example, if the signal stages transmitted over three data transmission lines are divided into four, the number of signals that can be transmitted at once is 64. Also, if the signal stages transmitted over four data transmission lines are divided into four, the number of signals that can be transmitted at once is 256.

[0365] In the configuration described in FIG. 34, in order to transmit / receive a differential signal from the first communication module (3200) to the second communication module (3300), the RX[3:0] of the circuits illustrated in FIG. 37, which will be described later, is additionally connected to the RX_B[3:0] pin of the second communication module (3300) to obtain the result of RXD[1:0]. At this time, an encoding unit for encoding transmitted data must be added to the first communication module (3200), and a decoding unit for decoding received data must be added to the second communication module (3300). Similarly, the configuration for transmitting / receiving a differential signal from the second communication module (3300) to the first communication module (3200) is also similar to the configuration described above.

[0366] FIG. 35 is a configuration diagram for explaining a data communication system according to another embodiment of the present invention. FIG. 36 is a circuit diagram for explaining the first communication module illustrated in FIG. 35.

[0367] Referring to FIGS. 35 and 36, a data communication system according to another embodiment of the present invention includes a data transmission line section (4100), a first communication module section (4200) connected to one end of the data transmission line section (4100), a first differential signal decoder (4210), a second communication module section (4300) connected to the other end of the data transmission line section (4100), and a second differential signal decoder (4310).

[0368] The data transmission line section (4100) is configured to correspond to four parallel data transmission lines. The coupling capacitors between the data transmission lines are all expressed as Cp values. However, in the actual implementation of the data transmission lines, it is common for each Cp value to have a different value, and that value is relatively smaller than the Cs values. For convenience of explanation, the values ​​of the coupling capacitances are collectively referred to as Cp in this specification.

[0369] It is obvious that the basic data communication device having the above four data transmission lines (4100) can be modularized in parallel to be applied as an extended data communication device handling, for example, 256, 512, or 1024 communication lines.

[0370] The first communication module section (4200) is defined by four first communication modules (200) arranged in parallel, and the second communication module section (4300) is defined by four second communication modules (300) arranged in parallel.

[0371] The first communication module (200) includes a first TX buffer (BTX0), a first TX resistor (RTX0), a second TX buffer (BTX1), a second TX resistor (RTX1), a TX switch (S0), a TX current conveyor (TX_CC), a mode switching switch (S2), an RX switch (S1), and an RC parallel circuit (RCP), and converts an input voltage signal into current and provides it to the data transmission line section (4100). In this embodiment, only two signals are transmitted through four data transmission lines. At this time, the difference between the first data transmission line and the second data transmission line, and the difference between the third data transmission line and the fourth data transmission line, are the signals to be transmitted. Transmitting one data value (bit) through two data transmission lines in this manner is used for very important information, such as clock information, or for stable signal transmission using a sufficiently large signal difference between two signals in a noisy system. Although the transmission efficiency is low, it is used for stable signal transmission in noisy systems.

[0372] The first TX buffer (BTX0) and the first TX resistor (RTX0), to which the TX_EN[0] signal and the TX[0] signal are applied, are connected in series and connected to one end of the TX switch (S0), and the second TX buffer (BTX1) and the second TX resistor (RTX1), to which the TX_EN[1] signal and the TX[1] signal are applied, are connected in series and connected to one end of the TX switch (S0).

[0373] The TX switch (S0) is commonly connected to the first TX resistor (RTX0) and the second TX resistor (RTX1) through one end, and connected to the X-port and mode switching switch (S2) of the TX current conveyor (TX_CC) through the other end.

[0374] The TX current conveyor (TX_CC) includes an EN-port into which an EN signal is input, a Y-port into which a common mode voltage (VCOM) is input, an X-port connected to a TX switch (S0), and a ZP-port connected to a mode switching switch (S2).

[0375] The mode switching switch (S2) includes a first terminal (A), a second terminal (B), and a third terminal (S). At this time, when the first terminal (A) and the third terminal (S) are connected, the ZP-port of the TX current conveyor (TX_CC) and the I / O pad are connected. Also, when the second terminal (B) and the third terminal (S) are connected, the ZP-port of the TX current conveyor (TX_CC) and the X-port of the TX current conveyor (TX_CC) are connected.

[0376] The RX switch (S1) is connected between the ZP-port of the TX current conveyor (TX_CC) and the RC parallel circuit (RCP). The RC parallel circuit (RCP) has a resistor and a capacitor connected in parallel, with one end connected to the RX switch (S1) and the other end connected to the common mode voltage (VCOM). In this embodiment, the RC parallel circuit (RCP) is illustrated, but a resistor element alone may be substituted and placed in the RC parallel circuit (RCP).

[0377] FIG. 36 describes configuring two TX buffers and two resistors in the first communication module (200) to express four relative current values. In a similar manner, if three or more TX buffers and three or more resistors are configured in the first communication module (200), more relative current values ​​can be expressed, but this is omitted in the specification.

[0378] FIG. 37 is a block diagram illustrating the first differential signal decoder illustrated in FIG. 35. Referring to FIG. 35 and FIG. 37, the first differential signal decoder (4210) includes a first comparator (COP1), a second comparator (COP1), and a logic encoder (LOE).

[0379] The first comparator (COP1) provides a first result value obtained by comparing signal RX[0] and signal RX[1] to the logic encoder (LOE), and the second comparator (COP1) provides a second result value obtained by comparing signal RX[2] and signal RX[3] to the logic encoder (LOE). The logic encoder (LOE) represents the first and second result values ​​as 2-bit signal RXD[1:0].

[0380] When transmitting a 2-level signal, 2 bits of data are transmitted as differential signals through four data transmission lines. That is, in the case of encoding that transmits the signal, a 1-bit signal is input, and the signal in the current phase is applied to one data transmission line and the signal in the reverse phase is applied to another data transmission line to be represented on the data transmission lines.

[0381] FIG. 38 is a drawing for explaining another example of a decoding unit added to the second communication module unit shown in FIG. 36.

[0382] Referring to FIG. 38, a decoding unit according to another example includes a first comparator (COP1), a second comparator (COP1), a third comparator (COP3), a fourth comparator (COP4), and a logic encoder (LOE).

[0383] The first comparator (COP1) provides a first result value obtained by comparing signal RX[0] and signal RX[3] to the logic encoder (LOE), and the second comparator (COP1) provides a second result value obtained by comparing signal RX[0] and signal RX[1] to the logic encoder (LOE). Additionally, the third comparator (COP3) provides a third result value obtained by comparing signal RX[1] and signal RX[2] to the logic encoder (LOE), and the fourth comparator (COP4) provides a fourth result value obtained by comparing signal RX[2] and signal RX[3] to the logic encoder (LOE). The logic encoder (LOE) represents the first to fourth result values ​​as an n-bit signal RXD[n:0].

[0384] This is a method used for at least 3-level signal transmission (PAM3 or higher). In this example, the explanation is based on the 4-level signal transmission method (PAM4).

[0385] Data of specific bit values ​​designated by the encoder and decoder is transmitted and received as differential signals through four data transmission lines. For the received signals, four comparators are used to compare the differences between the signals input from the following four data transmission lines.

[0386] Encoding (used during transmission) and decoding (used during reception) logic is required to select and transmit valid values ​​from the results of these comparators that do not overlap, and to receive them.

[0387] Meanwhile, in the configuration described in FIG. 34, in order to transmit / receive a PAM4 signal from the first communication module (4200) to the second communication module (4300), the RX[3:0] of the circuits shown in FIG. 38 and FIG. 39, which will be described later, is additionally connected to the RX_B[3:0] pin of the second communication module (4300) to obtain results such as RXD[n:0] or RXD[m:0], respectively. At this time, an encoding unit for encoding transmitted data must be added to the first communication module (4200), and a decoding unit for decoding received data must be added to the second communication module (4300). Similarly, the configuration for transmitting / receiving a differential signal from the second communication module (4300) to the first communication module (4200) is also similar to the configuration described above.

[0388] FIG. 39 is a drawing for explaining another example of a decoding unit added to the second communication module unit shown in FIG. 36.

[0389] Referring to FIG. 39, a decoding unit according to another example includes a first comparator (COP1), a second comparator (COP1), a third comparator (COP3), a fourth comparator (COP4), a fifth comparator (COP5), a sixth comparator (COP6), and a logic encoder (LOE).

[0390] The first comparator (COP1) provides a first result value obtained by comparing signal RX[0] and signal RX[2] to the logic encoder (LOE), and the second comparator (COP1) provides a second result value obtained by comparing signal RX[1] and signal RX[3] to the logic encoder (LOE). Additionally, the third comparator (COP3) provides a third result value obtained by comparing signal RX[0] and signal RX[3] to the logic encoder (LOE), and the fourth comparator (COP4) provides a fourth result value obtained by comparing signal RX[0] and signal RX[1] to the logic encoder (LOE). Additionally, the fifth comparator (COP5) provides the fifth result value obtained by comparing signal RX[1] and signal RX[2] to the logic encoder (LOE), and the sixth comparator (COP6) provides the sixth result value obtained by comparing signal RX[2] and signal RX[3] to the logic encoder (LOE). The logic encoder (LOE) represents the first through sixth result values ​​as m-bit signal RXD[m:0].

[0391] This is a method used for signal transmission of at least 3 levels (PAM3 or higher). In this example, a 4-level signal transmission method is described.

[0392] Data with specific bit values ​​designated by the encoder and decoder is transmitted and received as differential signals via four transmission lines. Six comparators are used to compare the signals input from each of the four transmission lines. Encoding logic (used during transmission) and decoding logic (used during reception) are required to select and transmit valid values ​​that do not overlap with the results of these comparators.

[0393] The decoding unit illustrated in FIG. 39 additionally includes a first comparator (COP1) that compares signal RX[0] and signal RX[2] and a second comparator (COP1) that compares signal RX[1] and signal RX[3] compared to the decoding unit illustrated in FIG. 38. Accordingly, among the values ​​determined by the four comparators, the cases where the comparison values ​​are duplicated can be further subdivided to increase the number of data cases that can be expressed through data encoding and data decoding.

[0394] FIG. 40 is a circuit diagram for explaining an example of a receiver unit provided in a data communication device of the present invention. In particular, it is a circuit diagram for explaining an example of a receiver unit (RCV) shown in FIG. 3.

[0395] Referring to FIG. 40, the receiver (500) includes a voltage generator (540) that converts the current of an RX signal provided through a transmission line into a voltage, and a voltage comparator module (530) that differentially compares the RX signals converted into voltage by the voltage generator (540).

[0396] The voltage generation unit (540) includes a plurality of variable resistors (Rin) connected to a transmission line at one end, a plurality of current conveyors (CC) connected to the other end of the variable resistors (Rin), and a plurality of RC parallel circuits arranged between the current conveyors (CC) and the voltage comparator module (530).

[0397] The variable resistor (Rin) is placed between the pad and the X-port of the current conveyor.

[0398] Each of the current conveyors (CC) is connected one-to-one to the four transmission lines of the link unit via a variable resistor (Rin).

[0399] Each RC parallel circuit includes a resistor (RRX) and a capacitor (CRX), one end of which is connected to the ZP-port of the current conveyors (CC) and the other end of which is connected to the common mode voltage (or common ground voltage). The resistor (RRX) converts the current of the RX signal provided through the ZP-port of the current conveyors (CC) into voltage, and the capacitor (CRX) improves signal quality by bypassing high-frequency components or adjusting the frequency response. The capacitor (CRX), together with the resistor (RRX), can perform high-frequency noise removal and equalization functions.

[0400] Specifically, to generate the voltage value (RXA[3:0]) of the transmitted signal, a resistor (RRX) is placed between the ZP-port of the current conveyor (CC) and the common mode voltage (VCOM) to convert the current, which is the transmitted signal, into voltage. Additionally, a capacitor (CRX) is placed between the ZP-port of the current conveyor (CC) and the common mode voltage (VCOM) to cooperate with the resistor (RRX) in the process of converting the current, which is the transmitted signal, into voltage, and can operate as a passive filter for high-frequency noise removal or equalization.

[0401] In FIG. 40, the voltage generation unit (540) is shown to include a plurality of RC parallel circuits, but the capacitor (CRX) connected between the PAD and the common mode voltage (or common ground voltage) may be used optionally. That is, the capacitor (CRX) may be omitted from the voltage generation unit (510).

[0402] The voltage comparator module (530) includes a comparator (or OPAMP) having six differential inputs for distinguishing RX signals from four RXA[3:0] outputs. When the four transmission lines are named A, B, C, and D, and each transmission line is connected to the receiver's PAD[0], PAD[1], PAD[2], and PAD[3], the voltage comparator module (530) compares the PAD signals of RX[0]=(AB), RX[1]=(BC), RX[2]=(CD), RX[3]=(DA), RX[4]=(AC), and RX[5]=(BD), respectively, and outputs the values ​​of RX[0:5] as input values ​​to the decoder circuit. In this embodiment, A represents RXA[0], B represents RXA[1], C represents RXA[2], and D represents RXA[3].

[0403] The CLK input used in the voltage comparator module (530) is used selectively as needed depending on the type of voltage comparator. The voltage comparator is a circuit that detects a differential signal, that is, the difference between the positive input voltage and the negative input voltage, and converts it into a digital signal [High (1) or Low (0)].

[0404] In this embodiment, the purpose of the variable resistor (Rin), that is, the reason why a variable resistor for impedance matching is required for the X-port, is explained as follows.

[0405] In order to receive the current transmitted from the transmission unit (DRV, shown in FIG. 3), the current conveyor of the receiving unit (RCV) drives the opposite current of the current transmitted to the X-port. At this time, when the value of the impedance of the transmission line matches the output impedance of the X-port, the received signal can ensure optimal rising time and falling time without overshoot or undershoot, thereby improving communication quality.

[0406] Transmission lines inevitably vary in shape, length, and configuration, such as PCBs, TSVs, and wires. Consequently, the impedance values ​​of the transmission lines may differ. Therefore, it is necessary to match (or make the impedances equal) the output impedance of the X-port of the receiver with the impedance of the transmission line.

[0407] To achieve such impedance matching, the present invention inserts a variable resistor capable of changing and adjusting its resistance value between the PAD of the receiving unit, which is the receiving end, and the X-port of the current conveyor.

[0408] FIGS. 41a, FIG. 41b, and FIG. 41c are graphs showing signal amplitudes according to the output impedance of the X-port of the receiver shown in FIG. 40. In particular, FIG. 41a is a graph showing the waveform when the output impedance of the X-port of the receiver shown in FIG. 40 is low, FIG. 41b is a graph showing the waveform when the output impedance of the RCV X-port of the receiver shown in FIG. 40 is high, and FIG. 41c is a graph showing the waveform when the output impedance of the RCV X-port of the receiver shown in FIG. 40 is appropriate.

[0409] Referring to Fig. 41a, when the output impedance of the X-port is smaller than the impedance of the transmission line, waveforms of overshoot and undershoot that interfere with communication are generated. In this case, by increasing the resistance value of the variable resistor (Rin) to control the output impedance of the X-port to match the impedance of the transmission line, it is possible to generate a signal waveform used for stable communication as shown in Fig. 41c.

[0410] Referring to Fig. 41b, when the output impedance of the X-port is greater than the impedance of the transmission line, there is no overshoot or undershoot, but the rising time and falling time are significantly increased. In this case, by reducing the resistance value of the variable resistor (Rin) to control the output impedance of the X-port to match the impedance of the transmission line, it is possible to ensure optimal rising time and falling time as shown in Fig. 41c, thereby generating a signal waveform used for stable communication.

[0411] As described above, according to the present invention, by applying a current signal-based communication technique that converts a voltage level TX signal into a current level TX signal and outputs it to one side of a data transmission line, and converts a current level RX signal provided via the data transmission line into a voltage level RX signal, the amplitude of the voltage signal accompanying signal transmission in actual implementation can be minimized to less than 0V or tens of mV, thereby enabling communication to be performed using only current signals.

[0412] Although the invention has been described above with reference to embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims.

[0413] <Explanation of Symbols>

[0414] 10: HBM device 20: Control unit

[0415] 30 : Interposer 40 : Printed circuit board

[0416] 100 : Data transmission line 200 : First communication module

[0417] 300: Second communication module 110: Upper differential input terminal

[0418] 120: Lower differential input terminal 130: Upper current mirror terminal

[0419] 140: Lower current mirror section 150: Switching section

[0420] 210: 1st driver 220: 2nd driver

[0421] 310: First buffer 320: Voltage-current converter

[0422] 1100, 2100, 3100, 4100: Data transmission line section

[0423] 1200, 2200, 3200, 4200: 1st communication module

[0424] 1300, 2300, 3300, 4300: 2nd communication module

[0425] CORE : Core Block D2 : Driving Block

[0426] BTX0 : TX buffer RTX0 : TX resistor

[0427] S0 : TX switch TX_CC : TX current conveyor

[0428] S2: Mode switching switch S1: RX switch

[0429] RCP: RC parallel circuit BRX: RX buffer

[0430] TMP: Transmitting mode unit RMP: Receiving mode unit

[0431] RX_CC : RX Current Conveyor BRX : RX Buffer

[0432] RCP: RC parallel circuit PSG: PAM4 signal generator

[0433] PSR: PAM4 signal restorer 500: Receiver

[0434] 540: Voltage generation unit 530: Voltage comparator module

Claims

1. Data transmission line; A first communication module connected to one side of the data transmission line and converting a voltage level TX signal provided by an external device into a current level TX signal and outputting it to one side of the data transmission line in order to communicate using only current, free from interference between a capacitive load existing in the data transmission line and the data transmission line; and It includes a second communication module connected to the other side of the data transmission line and converting a current-level RX signal provided via the data transmission line into a voltage-level RX signal in order to communicate using only current, free from interference between a capacitive load existing in the data transmission line and the data transmission line. A data communication device characterized in that the first communication module and the second communication module each include a mode switching switch to enable bidirectional communication by switching from a data transmission mode to a data reception mode or from a data reception mode to a data transmission mode by a communication direction control signal.

2. A data communication device according to claim 1, characterized in that the data transmission line includes a Through Silicon Via (TSV), a Through Glass Via (TGV), a Silicon Interposer, a Glass Interposer, and a PCB pattern.

3. In paragraph 1, each of the first communication module and the second communication module is, A current conveyor comprising an EN-port into which an EN signal is input, a Y-port into which a common mode voltage (VCOM) is input, an X-port, and a ZP-port connected to the mode switching switch, and A data communication device characterized by the above-described current conveyor converting a voltage level TX signal into a current level TX signal and simultaneously mirroring and outputting the converted current level TX signal.

4. In paragraph 3, the mode switching switch comprises a first terminal connected to the ZP-port of the current conveyor, a second terminal connected to the X-port of the current conveyor, and a third terminal connected to an I / O pad connected to the data transmission line. When the first terminal and the third terminal are connected, the ZP-port and I / O pad of the current conveyor are connected, and A data communication device characterized in that when the second terminal and the third terminal are connected, the X-port of the current conveyor and the I / O pad are connected.

5. In paragraph 3, each of the first communication module and the second communication module is, A TX buffer into which a TX signal of the above voltage level is input; A TX resistor connected to the output terminal of the above TX buffer; and It further includes the TX resistor and a TX switch connected to the X-port of the current conveyor, A data communication device characterized in that the above current conveyor is connected to the above mode switching switch through a ZP-port.

6. In paragraph 5, each of the first communication module and the second communication module is, A second switch connected to the ZP-port of the current conveyor; and A data communication device characterized by further including an RC parallel circuit or resistor element, one end of which is connected to the second switch and the other end of which is connected to the common mode voltage (VCOM).

7. In paragraph 6, when the first communication module or the second communication module operates in a data reception mode, The receiving current passing through the above data transmission line is applied to the X-port of the current conveyor of the communication module operating in data reception mode, and The common mode voltage (VCOM) is applied to the Y-port of the corresponding current conveyor, and The current mirrored from the received current based on the above common mode voltage (VCOM) is output through the ZP-port of the corresponding current conveyor, and A data communication device characterized in that the mirrored current output through the ZP-port of the corresponding current conveyor is converted into a voltage by the RC parallel circuit or the resistor element.

8. In paragraph 6, each of the first communication module and the second communication module is, A data communication device characterized by further including an RX buffer connected to the above RC parallel circuit or the above resistor element.

9. A data communication device according to claim 8, wherein the RX buffer comprises any one of a Schmitt-trigger circuit, a logic buffer, and a comparator circuit.

10. In paragraph 1, each of the first communication module and the second communication module is, A transmission mode unit that converts a TX signal of the above voltage level into a signal of the above current level and outputs it to the data transmission line through an I / O pad; and A data communication device characterized by including a receiving mode unit that converts a current level signal input from a data transmission line connected through the I / O pad into a voltage level RX signal.

11. In Clause 10, the transmission mode unit is, A first buffer comprising a front-end inverter enabled by a TX_EN signal to invert the TX signal, and a rear-end inverter connected to the rear end of the front-end inverter and enabled by the TX_EN signal to invert the signal inverted by the front-end inverter; and A data communication device characterized by including a voltage-current converter connected to the output terminal of the first buffer and the I / O pad, and including a pull-up current source, a pull-down current source, a pull-up switch, and a pull-down switch.

12. In Clause 10, the transmission mode unit is, A data communication device characterized by including a buffer that is enabled by a TX_EN signal and buffers the TX signal.

13. In Clause 12, the transmission mode unit is, A data communication device characterized by further including a voltage-current converter connected to the downstream end of the above buffer and providing a pull-up current source and a pull-down current source.

14. A data communication device according to claim 13, wherein the voltage-current converter comprises a resistor.

15. In Clause 10, the above receiving mode unit is, RX current conveyor connected to the above I / O pad; An RC parallel circuit or resistor element that receives and charges a receiving current output through the ZP-port of the above RX current conveyor to form a receiving voltage; and A data communication device characterized by including an RX buffer that outputs a received voltage formed by the above RC parallel circuit or the above resistor element to the outside through the RX terminal.

16. In paragraph 3, each of the first communication module and the second communication module is, A first TX buffer into which a first TX signal of the above voltage level is input; A second TX buffer into which a second TX signal of the above voltage level is input; A first TX resistor connected to the output terminal of the first TX buffer; A second TX resistor connected to the output terminal of the second TX buffer; and A data communication device characterized by including a TX switch, one end of which is connected to the first TX resistor and the second TX resistor, and the other end of which is connected to the X-port of the current conveyor.

17. In paragraph 3, each of the first communication module and the second communication module includes a PAM4 signal generator, and The above PAM4 signal generator is, A first TX buffer into which a first TX signal of the above voltage level is input; A second TX buffer into which a second TX signal of the above voltage level is input; A first TX resistor, one end of which is connected to the output terminal of the first TX buffer and the other end of which is connected to the data transmission line; and A data communication device characterized by including a second TX resistor, one end of which is connected to the output terminal of the second TX buffer and the other end of which is connected to the data transmission line.

18. In paragraph 13, each of the first communication module and the second communication module is, An RX switch commonly connected to the ZP-port of the current conveyor and the mode switching switch; An RC parallel circuit or resistor element connected to the above RX switch; and A data communication device characterized by further including a PAM4 signal restorer that restores an RX signal passing through the above RC parallel circuit or the above resistor element.

19. In paragraph 18, each of the first communication module and the second communication module can switch between a data transmission mode and a data reception mode, and In the above data transmission mode, the TX switch is turned ON and the RX switch is turned OFF, and A data communication device characterized in that, in the above data reception mode, the TX switch is OFF and the RX switch is ON.

20. A data communication device according to claim 19, characterized in that, in the data transmission mode, a transmission signal from the first TX buffer and the second TX buffer is output to the data transmission line, and in the data reception mode, a received signal is restored from the RX buffer and output.

21. In paragraph 18, the above PAM4 signal restorer is, A first comparator that compares the above RX signal with a first reference voltage and outputs a first result value; A second comparator that compares the above RX signal with a second reference voltage and outputs a second result value; A third comparator that compares the above RX signal with a third reference voltage and outputs a third result value; and A data communication device characterized by including a logic encoder that represents the first to third result values ​​as a 2-bit RXA[1:0].

22. A data communication device according to claim 1, wherein the first communication module converts a first transmission signal provided from an external device into a first transmission current and outputs it to a data transmission line, and the second communication module outputs a first reception current that is opposite in phase to the first transmission current through the data transmission line to minimize voltage changes on the data transmission line.

23. A data communication device according to claim 22, wherein the second communication module outputs a transmission signal restored to a first reception voltage by mirroring a first reception current.

24. A data communication device according to claim 1, wherein the second communication module converts a second transmission signal provided from an external device into a second transmission current and outputs it to a data transmission line, and the first communication module outputs a second reception current that is opposite in phase to the second transmission current through the data transmission line to minimize voltage changes on the data transmission line.

25. A data communication device according to claim 24, wherein the first communication module outputs a transmission signal restored to a second reception voltage by mirroring a second reception current.

26. In paragraph 1, each of the first communication module and the second communication module includes a receiver that receives an RX signal at the physical layer through the data transmission line, A data communication device characterized in that the receiving unit includes a voltage generating unit that converts the current of an RX signal provided through the data transmission line into a voltage.

27. A data communication device according to claim 26, wherein the voltage generating unit further comprises a variable resistor, one end of which is connected to the data transmission line and the other end of which is connected to the current conveyor.

28. A data transmission line section comprising a plurality of parallel data transmission lines; A first communication module unit comprising a plurality of first communication modules arranged in parallel and connected to one end of the data transmission line unit; and It includes a plurality of second communication modules arranged in parallel, and a second communication module unit connected to the other end of the data transmission line unit, The first communication module converts a voltage-level TX signal provided by an external device into a current-level TX signal and outputs it to one side of the data transmission line in order to communicate using only current, free from interference between a capacitive load present in the data transmission line and the data transmission line. The second communication module converts a current-level RX signal provided via the data transmission line into a voltage-level RX signal in order to communicate using only current, free from interference between a capacitive load present in the data transmission line and the data transmission line. A data communication system characterized in that the first communication module and the second communication module each include a mode switching switch to enable bidirectional communication by switching from a data transmission mode to a data reception mode or from a data reception mode to a data transmission mode by means of a communication direction control signal.

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