Array substrate, display device and photomask group

Abstract

An array substrate, a display device and a photomask group. The array substrate comprises a base substrate, a gate metal layer, a source-drain metal layer, a pixel electrode layer and a common electrode layer. The gate metal layer comprises a plurality of gate lines. The source-drain metal layer comprises a plurality of data lines. The pixel electrode layer comprises a plurality of pixel electrode patterns located in a display area. The array substrate further comprises a functional metal layer and an organic layer. The array substrate further comprises a functional metal layer and an organic layer, wherein the organic layer is located between the source-drain metal layer and the pixel electrode layer; and the functional metal layer is located on the side of the pixel electrode layer close to the base substrate. The functional metal layer comprises a plurality of functional metal lines, wherein the orthographic projection of each functional metal line on the base substrate is located between the orthographic projections of two adjacent pixel electrode patterns on the base substrate; and the orthographic projections of each functional metal line and each pixel electrode pattern on the base substrate both overlap with the orthographic projection of the organic layer on the base substrate. Therefore, the functional metal layer can be used in various application scenarios, and the impact on the aperture ratio can also be prevented. In addition, the compatibility of photomasks for different schemes can also be achieved.

Description

Array substrate, display device and photomask assembly Technical Field

[0001] Embodiments of this disclosure relate to an array substrate, a display device, and a mask assembly. Background Technology

[0002] In the field of display technology, liquid crystal displays (LCDs) have advantages such as being lightweight, thin, low power consumption, high brightness, and high image quality.

[0003] Typically, a thin-film transistor liquid crystal display (TFT-LCD) includes an array substrate, a counter substrate, and a liquid crystal layer sandwiched between the array substrate and the counter substrate. TFT-LCDs utilize changes in the electric field intensity on the liquid crystal layer between the array substrate and the counter substrate to alter the orientation of liquid crystal molecules within the liquid crystal layer, thereby controlling the intensity of light transmission to display images. Summary of the Invention

[0004] At least one embodiment of this disclosure provides an array substrate including a display area and a peripheral area at least partially surrounding the display area, comprising: a substrate; a gate metal layer located on the substrate, including a plurality of gate lines extending along a first direction and arranged along a second direction in the display area, the first direction and the second direction being intersected; a source / drain metal layer located on the side of the gate metal layer away from the substrate, including a plurality of data lines arranged along the first direction and extending along the second direction in the display area; a pixel electrode layer located on the side of the source / drain metal layer away from the substrate, including a plurality of pixel electrode patterns in the display area; and a common electrode layer located on the side of the source / drain metal layer away from the substrate, wherein each of the pixel electrode patterns is located on the substrate. The orthographic projection of the pixel electrode is located within the area jointly defined by the orthographic projections of two adjacent data lines along the first direction and two adjacent gate lines along the second direction on the substrate. The plurality of pixel electrode patterns are arranged in an array on the substrate. The array substrate further includes a functional metal layer and an organic layer. The organic layer is located between the source / drain metal layer and the pixel electrode layer. The functional metal layer is located on the side of the pixel electrode layer closer to the substrate. The functional metal layer includes a plurality of functional metal lines. The orthographic projection of each functional metal line on the substrate is located between the orthographic projections of two adjacent pixel electrode patterns on the substrate. The orthographic projections of each functional metal line and each pixel electrode pattern on the substrate overlap with the orthographic projection of the organic layer on the substrate.

[0005] For example, in an array substrate provided in one embodiment of this disclosure, the functional metal layer is located on the side of the organic layer away from the substrate, or the functional metal layer is located between the organic layer and the source / drain metal layer, or the functional metal layer is located on the side of the gate metal layer close to the substrate.

[0006] For example, in an array substrate provided in one embodiment of this disclosure, the functional metal layer is located on the side of the organic layer close to the substrate, and the common electrode layer or the pixel electrode layer is in direct contact with the organic layer.

[0007] For example, in an embodiment of this disclosure, the array substrate further includes a first transition via exposing a portion of the traces in the gate metal layer and a second transition via exposing a portion of the traces in the source / drain metal layer. The traces in the gate metal layer and the traces in the source / drain metal layer are respectively connected to the pixel electrode layer or the common electrode layer through the first transition via and the second transition via to connect the two traces. The organic layer includes a first organic layer preset via, and the orthographic projection of the first organic layer preset via and the second transition via on the substrate falls within the orthographic projection of the first organic layer preset via on the substrate.

[0008] For example, in an array substrate provided in one embodiment of this disclosure, the orthographic projections of a plurality of first transition vias and a plurality of second transition vias on the substrate fall within the orthographic projection of a first organic layer preset via on the substrate.

[0009] For example, in an embodiment of the array substrate provided in this disclosure, the peripheral region further includes a bonding region, the array substrate further includes a plurality of conductive pads located in the bonding region, the organic layer further includes a second organic layer preset via, and the orthographic projection of the plurality of conductive pads on the substrate falls within the orthographic projection of the second organic layer preset via on the substrate.

[0010] For example, in an embodiment of the array substrate provided in this disclosure, the plurality of conductive pads include a first type of conductive pad, which includes: a first conductive pad located in the gate metal layer; a first conductive pad via exposing a portion of the first conductive pad; and a second conductive pad located in the pixel electrode layer or the common electrode layer, wherein the first conductive pad is directly connected to the second conductive pad through the first conductive pad via.

[0011] For example, in an embodiment of the array substrate provided in this disclosure, the plurality of conductive pads includes a second type of conductive pad, the second type of conductive pad including: a third conductive pad located in the functional metal layer; a second conductive pad via exposing a portion of the third conductive pad; and a fourth conductive pad located in the pixel electrode layer or the common electrode layer, wherein the third conductive pad is directly connected to the fourth conductive pad through the second conductive pad via.

[0012] For example, in one embodiment of this disclosure, the array substrate further includes: a gate metal insulating layer located between the gate metal layer and the source / drain metal layer, the gate metal insulating layer including a plurality of gate metal insulating layer preset vias, and the source / drain metal layer further including a first source / drain metal layer connection structure located within each of the gate metal insulating layer preset vias.

[0013] For example, in an embodiment of the array substrate provided in this disclosure, the source / drain metal layer further includes a second source / drain metal layer connection structure connected to the first source / drain metal layer connection structure. The second source / drain metal layer connection structure is located on the side of the first source / drain metal layer connection structure away from the substrate. The second source / drain metal layer connection structure is connected to the traces in the gate metal layer through the first source / drain metal layer connection structure. The array substrate further includes a second transition via exposing a portion of the traces in the source / drain metal layer and a third transition via exposing a portion of the second source / drain metal layer connection structure. The traces in the source / drain metal layer and the second source / drain metal layer connection structure are respectively connected to the pixel electrode layer or the common electrode layer through the second transition via and the third transition via, so that the traces in the source / drain metal layer are connected to the second source / drain metal layer connection structure.

[0014] For example, in an array substrate provided in an embodiment of this disclosure, the projection of the pre-set via of the gate metal insulating layer onto the substrate overlaps with the traces in the gate metal layer and the traces in the source / drain metal layer. The traces in the gate metal layer and the traces in the source / drain metal layer are directly connected through the first source / drain metal layer connection structure located in the gate metal insulating layer.

[0015] For example, in an embodiment of the array substrate provided in this disclosure, the peripheral region further includes a bonding region, and the array substrate further includes a plurality of conductive pads located in the bonding region. The plurality of conductive pads includes a first type of conductive pad, which includes: a fifth conductive pad located in the gate metal layer; a third conductive pad via exposing a portion of the fifth conductive pad; a sixth conductive pad located in the source / drain metal layer; a fourth conductive pad via exposing a portion of the sixth conductive pad; and a seventh conductive pad located in the pixel electrode layer or the common electrode layer. The third conductive pad via includes one of the plurality of gate metal insulating layer preset vias. The fifth conductive pad and the sixth conductive pad are directly connected through a first source / drain metal layer connection structure located within the preset via of the gate metal insulating layer. The seventh conductive pad is directly connected to the sixth conductive pad through the sixth conductive pad via.

[0016] For example, in an embodiment of the array substrate provided in this disclosure, the peripheral region further includes a bonding region, the functional metal layer is located on the side of the source / drain metal layer away from the substrate, and the plurality of conductive pads further includes a second type of conductive pad, the second type of conductive pad including: an eighth conductive pad located in the functional metal layer; a fifth conductive pad via exposing a portion of the eighth conductive pad; and a ninth conductive pad located in the pixel electrode layer or the common electrode layer, the eighth conductive pad being directly connected to the ninth conductive pad through the fifth conductive pad via.

[0017] For example, in an array substrate provided in an embodiment of this disclosure, the second type of conductive pad further includes a dummy conductive pad located in the source / drain metal layer and a dummy conductive pad via located in the gate metal insulating layer. The dummy conductive pad is not connected to the eighth conductive pad. The dummy conductive pad via includes one of the plurality of gate metal insulating layer preset vias. The dummy conductive pad is connected to a first source / drain metal layer connection structure located in the dummy conductive pad via.

[0018] For example, in an embodiment of the array substrate provided in this disclosure, the functional metal layer is located on the side of the gate metal layer near the substrate. The plurality of conductive pads further includes a second type of conductive pad, which includes: a tenth conductive pad located in the functional metal layer; a sixth conductive pad via exposing a portion of the tenth conductive pad; an eleventh conductive pad located in the source / drain metal layer; a seventh conductive pad via exposing a portion of the eleventh conductive pad; and a twelfth conductive pad located in the pixel electrode layer or the common electrode layer. The sixth conductive pad via includes one of the plurality of gate metal insulating layer preset vias. The tenth conductive pad and the eleventh conductive pad are connected through a first source / drain metal layer connection structure located within the preset via of the gate metal insulating layer. The eleventh conductive pad is directly connected to the twelfth conductive pad through the seventh conductive pad via.

[0019] For example, in an array substrate provided in one embodiment of this disclosure, the pixel electrode layer is located on the side of the common electrode layer away from the substrate, the functional metal layer is located between the organic layer and the source / drain metal layer, and the array substrate further includes a gate metal insulating layer located on the side of the gate metal layer away from the substrate, an active layer located between the gate metal insulating layer and the source / drain metal layer, a passivation layer located between the source / drain metal layer and the functional metal layer, a passivation layer located between the functional metal layer and the organic layer, a common electrode metal layer located on the side of the common electrode layer away from the substrate, and a passivation layer located between the common electrode metal layer and the pixel electrode layer.

[0020] For example, in an embodiment of the array substrate provided in this disclosure, the pixel electrode layer is located on the side of the common electrode layer away from the substrate, the functional metal layer is located on the side of the gate metal layer close to the substrate, and the array substrate further includes a passivation layer between the functional metal layer and the gate metal layer, a gate metal insulating layer on the side of the gate metal layer away from the substrate, an active layer between the gate metal insulating layer and the source / drain metal layer, a passivation layer between the source / drain metal layer and the organic layer, a common electrode metal layer on the side of the common electrode layer away from the substrate, and a passivation layer between the common electrode metal layer and the pixel electrode layer.

[0021] For example, in an array substrate provided in an embodiment of this disclosure, the pixel electrode layer is located on the side of the common electrode layer away from the substrate, and each pixel electrode pattern includes a plurality of strip-shaped pixel electrodes extending along the second direction and arranged along the first direction, with a slit between two adjacent strip-shaped pixel electrodes along the first direction.

[0022] For example, in an embodiment of the array substrate provided in this disclosure, the source / drain metal layer further includes source / drain electrodes, the pixel electrode further includes a pixel electrode connection structure connected to the pixel electrode pattern, the array substrate further includes a fourth transition via exposing the source / drain electrodes, the pixel electrode connection structure is connected to the source / drain electrodes through the fourth transition via, the organic layer further includes a third organic layer preset via, the common electrode layer includes a common electrode layer via, the orthographic projection of the fourth transition via on the substrate falls within the orthographic projection of the third organic layer preset via and the common electrode via on the substrate, and the orthographic projection of the third organic layer preset via on the substrate falls within the orthographic projection of the common electrode layer via on the substrate.

[0023] For example, in an array substrate provided in an embodiment of this disclosure, the gate metal layer further includes a first alignment pattern for aligning at least one of the source / drain metal layer, the pixel electrode layer, the common electrode layer, the functional metal layer, and the organic layer with the first alignment pattern, and the functional metal layer further includes a second alignment pattern for aligning at least one of the gate metal layer, the source / drain metal layer, the pixel electrode layer, the common electrode layer, and the organic layer with the second alignment pattern.

[0024] For example, in an array substrate provided in one embodiment of this disclosure, the orthographic projection of the first alignment pattern on the substrate and the orthographic projection of the second alignment pattern on the substrate do not overlap.

[0025] For example, in an array substrate provided in one embodiment of this disclosure, the thickness of the organic layer ranges from 1.5 μm to 3.0 μm.

[0026] For example, in an array substrate provided in one embodiment of this disclosure, each of the functional metal lines extends along the second direction, and the orthographic projection of each of the functional metal lines on the substrate overlaps with the orthographic projection of one of the plurality of data lines on the substrate.

[0027] For example, in an embodiment of the present disclosure, the array substrate further includes a common electrode metal layer that is in direct contact with the common electrode layer. The common electrode metal layer is located on the side of the common electrode layer away from the substrate. The common electrode metal layer includes a plurality of common electrode metal lines. Each of the common electrode metal lines is located between two adjacent pixel electrode patterns. The plurality of common electrode metal lines includes a common electrode metal line extending along the second direction. The orthographic projection of the common electrode metal line extending along the second direction on the substrate overlaps with the orthographic projection of one of the plurality of data lines on the substrate.

[0028] At least one embodiment of this disclosure provides a display device, including any of the array substrates described above, a counter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate.

[0029] At least one embodiment of this disclosure provides a mask set, including: a plurality of masks, the plurality of masks including a gate metal layer mask for forming the gate metal layer and a functional metal layer mask for forming the functional metal layer, wherein the gate metal layer mask includes a first alignment mark to form a first alignment pattern, and the functional metal layer mask includes a second alignment mark to form a second alignment pattern.

[0030] The functional metal layer in the array substrate provided in this disclosure can be used in a variety of application scenarios, can avoid the impact on the aperture ratio, and can also achieve compatibility of different mask schemes. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0032] Figure 1 is a schematic diagram of an array substrate provided in an embodiment of this disclosure;

[0033] Figure 2 is a partial enlarged schematic diagram of an array substrate provided in an embodiment of this disclosure;

[0034] Figure 3 is a schematic cross-sectional view of Figure 2 along the cutting line AA;

[0035] Figure 4 is another cross-sectional view of Figure 2 along the cutting line AA;

[0036] Figure 5 is another cross-sectional view of Figure 2 along the cutting line AA;

[0037] Figure 6 is a schematic diagram of a film layer and its mask corresponding to the array substrate shown in Figure 3;

[0038] Figure 7 is a schematic diagram of a film layer and its mask corresponding to the array substrate shown in Figure 4;

[0039] Figure 8 is a schematic diagram of a film layer and its mask corresponding to the array substrate shown in Figure 5;

[0040] Figure 9 is a planar schematic diagram of the wiring transition of an array substrate provided in an embodiment of this disclosure;

[0041] Figure 10 is a schematic cross-sectional view of Figure 9 along the cutting line BB;

[0042] Figure 11 is another cross-sectional view of Figure 9 along the cutting line BB;

[0043] Figure 12 is another cross-sectional view of Figure 9 along the cutting line BB;

[0044] Figure 13 is a partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1;

[0045] Figure 14 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1;

[0046] Figure 15 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1;

[0047] Figure 16 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1;

[0048] Figure 17 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1;

[0049] Figure 18 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1;

[0050] Figure 19 is a schematic diagram of another film layer and its mask corresponding to the array substrate shown in Figure 3;

[0051] Figure 20 is a schematic diagram of another film layer and its mask corresponding to the array substrate shown in Figure 4;

[0052] Figure 21 is a schematic diagram of another film layer and its mask corresponding to the array substrate shown in Figure 5;

[0053] Figure 22 is another cross-sectional view of Figure 9 along the cutting line BB;

[0054] Figure 23 is another cross-sectional view of Figure 9 along the cutting line BB;

[0055] Figure 24 is another cross-sectional view of Figure 9 along the cutting line BB;

[0056] Figure 25 is a cross-sectional schematic diagram of a wiring connection provided in an embodiment of this disclosure;

[0057] Figure 26 is a cross-sectional schematic diagram of another wiring connection provided in an embodiment of this disclosure;

[0058] Figure 27 is a cross-sectional schematic diagram of a wiring connection provided in an embodiment of this disclosure;

[0059] Figure 28 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1;

[0060] Figure 29 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1;

[0061] Figure 30 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1;

[0062] Figure 31 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1;

[0063] Figure 32 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1;

[0064] Figure 33 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1;

[0065] Figure 34 is a partial enlarged schematic diagram of an array substrate provided in an embodiment of this disclosure;

[0066] Figure 35 is a schematic cross-sectional view of Figure 34 along section line II;

[0067] Figure 36 is a schematic diagram of another cross-section along section line II in Figure 34;

[0068] Figure 37 is a schematic cross-sectional view of Figure 34 along section line II;

[0069] Figure 38 is a schematic cross-sectional view of Figure 34 along the cutting line JJ;

[0070] Figure 39 is another cross-sectional view of Figure 34 along the cutting line JJ;

[0071] Figure 40 is a cross-sectional view of Figure 34 along the cutting line JJ;

[0072] Figure 41 is a schematic diagram of a planar structure of a gate metal layer and a functional metal layer provided in an embodiment of the present disclosure;

[0073] Figure 42 shows the etching results using the scheme shown in Figure 22;

[0074] Figure 43 is a schematic diagram of a display device provided in an embodiment of the present disclosure; and

[0075] Figure 44 is a schematic diagram of the planar structure of a mask provided in an embodiment of this disclosure. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0077] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0078] The components or structures in the accompanying drawings are not drawn to scale. For clarity, the dimensions of the components or structures may be exaggerated or reduced, but this should not be used to limit the scope of this disclosure. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components may be omitted.

[0079] Unless otherwise defined, the features such as "parallel," "perpendicular," and "identical" used in the embodiments of this disclosure include strictly defined cases of "parallel," "perpendicular," and "identical," as well as cases involving a certain degree of error, such as "approximately parallel," "approximately perpendicular," and "approximately identical." For example, the aforementioned "approximately" may indicate that the difference between the compared objects is within 10% or 5% of the average value of the compared objects. Unless otherwise specified in the following embodiments of this disclosure, the quantity of a component or element is implied to mean that the component or element may be one or more, or can be understood as at least one. "At least one" refers to one or more, and "more" refers to at least two. In the embodiments of this disclosure, "same-layer arrangement" refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). Here, "same-layer" does not always mean that the multiple film layers have the same thickness or that the multiple film layers have the same height in a cross-sectional view.

[0080] Liquid crystal displays (LCDs) typically use nematic liquid crystals. LCDs need to operate within the temperature range of the nematic liquid crystal; the operating temperature range of the LCD is the range in which the nematic phase exists. The transition temperature between the smectic and nematic phases of the liquid crystal is usually denoted by Tsn; the temperature at which the nematic phase transforms into a liquid is the clearing point temperature of the liquid crystal, denoted by Tni. When the operating temperature of the LCD is below Tsn, the liquid crystal is in the smectic phase or solid (non-nematic phase), exceeding the operating temperature range of the LCD (Tni~Tsn), and the LCD cannot function properly.

[0081] Using heating wires to heat the liquid crystal within the cell solves the technical problem of LCDs failing to operate normally at ambient temperatures below Tsn. There are two basic designs for the in-cell heating wire. One is a horizontally laid-out design, where the heating wire is formed using the gate metal layer or source / drain metal layer of the LCD; this design inevitably leads to a significant reduction in aperture ratio. The other is a vertically laid-out design, but this design has a more complex film layer and is prone to signal interference. Besides in-cell heating, introducing a metal layer within the cell has many other applications, such as in-cell touch control.

[0082] This disclosure provides an array substrate, a display device, and a mask assembly. The array substrate includes a display area and a peripheral area at least partially surrounding the display area. The array substrate includes a substrate, a gate metal layer, a source / drain metal layer, a pixel electrode layer, and a common electrode layer. The gate metal layer is located on the substrate and includes a plurality of gate lines extending along a first direction and arranged along a second direction in the display area, the first and second directions intersecting. The source / drain metal layer is located on the side of the gate metal layer away from the substrate and includes a plurality of data lines arranged along the first direction and extending along the second direction in the display area. The pixel electrode layer is located on the side of the source / drain metal layer away from the substrate and includes a plurality of pixel electrode patterns in the display area. The common electrode layer is located on the side of the source / drain metal layer away from the substrate. The orthographic projection of each pixel electrode pattern onto the substrate lies within the area jointly defined by the orthographic projections of two adjacent data lines along the first direction and two adjacent gate lines along the second direction onto the substrate. The plurality of pixel electrode patterns are arranged in an array on the substrate. The array substrate also includes a functional metal layer and an organic layer. The organic layer is located between the source / drain metal layer and the pixel electrode layer, while the functional metal layer is located on the side of the pixel electrode layer closest to the substrate. The functional metal layer includes multiple functional metal lines, and the orthographic projection of each functional metal line onto the substrate lies between the orthographic projections of two adjacent pixel electrode patterns onto the substrate. The orthographic projections of each functional metal line and each pixel electrode pattern onto the substrate overlap with the orthographic projection of the organic layer onto the substrate.

[0083] In the array substrate provided in this embodiment, the array substrate includes a functional metal layer. The functional metal lines of the functional metal layer are located between two adjacent pixel electrode patterns. Thus, the array substrate can realize functions such as in-cell heating and in-cell touch control through the functional metal layer. The functional metal lines are separately disposed in the functional metal layer rather than shared with other metal layers, which can avoid adverse effects on the pixel aperture ratio.

[0084] The array substrate includes an organic layer. The orthographic projections of each functional metal line and pixel electrode pattern onto the substrate overlap with the orthographic projection of the organic layer onto the substrate. On one hand, when the organic layer is located between the functional metal layer and the source / drain metal layer, the orthographic projections of the functional metal lines of the functional metal layer onto the substrate overlap with the orthographic projections of the organic layer onto the substrate. The organic layer can shield the coupling between the functional metal lines and the signal lines on the source / drain metal layer and the gate metal layer, reduce the overlap capacitance between the functional metal lines and the signal lines, and improve the display effect. On the other hand, when the organic layer is located on the side of the functional metal layer and the source / drain metal layer away from the substrate, the pixel electrode layer or common electrode layer has better contact adhesion with the organic layer. By making the orthographic projection of the pixel electrode pattern on the substrate overlap with the orthographic projection of the organic layer on the substrate, the pixel electrode layer or common electrode layer can be directly formed on the organic layer. The pixel electrode layer or common electrode layer is in direct contact with the organic layer, which can reduce the number of passivation layers in the array substrate, reduce costs, and simplify the process. Moreover, when the functional metal layer is located on the side of the organic layer closer to the substrate, the number of film layers on the side of the organic layer away from the substrate is smaller, the structure is simpler, the manufacturing process is simplified, the total thickness of the film layers on the side of the organic layer away from the substrate is reduced, the risk of film peeling and translation is reduced, the quality of film formation is guaranteed, and the product yield is improved. Furthermore, by ensuring that the orthographic projections of each functional metal line and pixel electrode pattern onto the substrate overlap with the orthographic projection of the organic layer onto the substrate, mask compatibility for different design schemes can be achieved. Different design schemes, where the functional metal layer is located on the side of the organic layer furthest from the substrate or on the side closest to the substrate, can be implemented using a single mask, provided the aforementioned effect is achieved. This enables mask compatibility for different design schemes, reduces costs, and allows for the creation of different design schemes and products simply by adjusting the relative positions of the masks within the same set of masks, based on varying requirements.

[0085] The array substrate, display device, and mask assembly provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0086] This disclosure provides an array substrate. Figure 1 is a structural schematic diagram of an array substrate provided in this disclosure; Figure 2 is a partial enlarged schematic diagram of an array substrate provided in this disclosure; Figure 3 is a cross-sectional schematic diagram of Figure 2 along the cutting line AA; Figure 4 is another cross-sectional schematic diagram of Figure 2 along the cutting line AA; Figure 5 is another cross-sectional schematic diagram of Figure 2 along the cutting line AA.

[0087] As shown in Figures 1 to 5, the array substrate includes a display area A0 and a peripheral area B0 at least partially surrounding the display area A0. The array substrate includes a substrate 101, a gate metal layer 110, a source / drain metal layer 120, a pixel electrode layer 140, and a common electrode layer 131. The gate metal layer 110 is located on the substrate 101 and includes a plurality of gate lines 111 extending along a first direction X and arranged along a second direction Y in the display area A0, with the first direction X and the second direction Y intersecting. The source / drain metal layer 120 is located on the side of the gate metal layer 110 away from the substrate 101 and includes a plurality of data lines 121 arranged along the first direction X and extending along the second direction Y in the display area A0. The pixel electrode layer 140 is located on the side of the source / drain metal layer 120 away from the substrate 101 and includes a plurality of pixel electrode patterns 141 in the display area A0. The common electrode layer 131 is located on the side of the source / drain metal layer 120 away from the substrate 101. The orthographic projection of each pixel electrode pattern 141 onto the substrate 101 lies within the area jointly defined by the orthographic projections of two adjacent data lines 121 along the first direction X and two adjacent gate lines 111 along the second direction Y onto the substrate 101. Multiple pixel electrode patterns 141 are arranged in an array on the substrate 101. The array substrate also includes a functional metal layer 150 and an organic layer 160. The organic layer 160 is located between the source / drain metal layer 120 and the pixel electrode layer 140, and the functional metal layer 150 is located on the side of the pixel electrode layer 140 closest to the substrate 101.

[0088] Figure 2 schematically illustrates the relative positional relationship between the pixel electrode pattern 141 and the data line 121 and gate line 111, without limiting the shape of the pixel electrode pattern 141. For example, the shape of the pixel electrode pattern 141 can be block-shaped or strip-shaped, which will not be elaborated here. Figures 3 to 5 schematically show the pixel electrode layer 140 located on the side of the common electrode layer 131 away from the substrate 101. Thus, the common electrode layer 131 can shield the signal of the functional metal layer 150, avoiding adverse effects on the pixel electrode layer 140 and improving the display effect. However, this embodiment of the present disclosure does not limit this; for example, the pixel electrode layer can be located on the side of the common electrode layer closer to the substrate. For example, the materials of the common electrode layer 131 and the pixel electrode layer 140 can be indium tin oxide (ITO).

[0089] Figure 3 shows the functional metal layer 150 located on the side of the organic layer 160 away from the substrate 101. Figure 4 shows the functional metal layer 150 located between the organic layer 160 and the source / drain metal layers 120. Figure 5 shows the functional metal layer 150 located on the side of the gate metal layer 110 close to the substrate 101. The third direction Z shown in Figures 3 to 5 is perpendicular to the first direction X and the second direction Y.

[0090] As shown in Figures 2 to 5, the functional metal layer 150 includes a plurality of functional metal lines 151. The orthographic projection of each functional metal line 151 onto the substrate 101 lies between the orthographic projections of two adjacent pixel electrode patterns 141 onto the substrate 101. The orthographic projections of each functional metal line 151 and each pixel electrode pattern 141 onto the substrate 101 overlap with the orthographic projection of the organic layer 160 onto the substrate 101. Figure 2 schematically shows the functional metal lines 151 extending along the second direction Y. This disclosure does not limit the extension direction or the number of functional metal lines 151.

[0091] In the array substrate provided in this embodiment, the array substrate includes a functional metal layer. The functional metal lines of the functional metal layer are located between two adjacent pixel electrode patterns. Thus, the array substrate can realize functions such as in-cell heating and in-cell touch control through the functional metal layer. The functional metal lines are separately disposed in the functional metal layer rather than shared with other metal layers, which can avoid adverse effects on the pixel aperture ratio.

[0092] The array substrate includes an organic layer. The orthographic projections of each functional metal line and each pixel electrode pattern onto the substrate overlap with the orthographic projection of the organic layer onto the substrate. On one hand, as shown in FIG3, when the organic layer 160 is located between the functional metal layer 150 and the source / drain metal layer 120, the orthographic projections of the functional metal lines 151 of the functional metal layer 150 onto the substrate 101 overlap with the orthographic projections of the organic layer 160 onto the substrate 101. The organic layer 160 can shield the coupling between the functional metal lines 151 and the signal lines on the source / drain metal layer 120 and the gate metal layer 110, reduce the overlap capacitance between the functional metal lines 151 and the signal lines, and improve the display effect. On the other hand, as shown in Figures 4 and 5, when the organic layer 160 is located on the side of the functional metal layer 150 and the source / drain metal layer 120 away from the substrate 101, the pixel electrode layer 140 or the common electrode layer 131 has good contact adhesion with the organic layer 160. By making the orthographic projection of the pixel electrode pattern 141 on the substrate 101 overlap with the orthographic projection of the organic layer 160 on the substrate 101, the pixel electrode layer 140 or the common electrode layer 131 can be directly formed on the organic layer 160. The direct contact between electrode layer 131 and organic layer 160 reduces the number of passivation layers in the array substrate, lowering costs and simplifying the process. Furthermore, the functional metal layer 150 is located on the side of organic layer 160 closest to substrate 101, resulting in fewer film layers on the side of organic layer 160 furthest from substrate 101, a simpler structure, simplified fabrication, reduced total film thickness on the furthest side of organic layer 160, reduced risk of film peeling and translation, ensuring film quality, and improving product yield. For example, as shown in FIG. 4, functional metal layer 150 is located between organic layer 160 and source / drain metal layer 120, thus reducing coupling between functional metal layer 150 and gate metal layer 110. For example, as shown in FIG. 5, functional metal layer 150 is located on the side of gate metal layer 110 closest to substrate 101, thus reducing coupling between functional metal layer 150 and source / drain metal layer 120. Furthermore, by ensuring that the orthographic projections of each functional metal line and pixel electrode pattern onto the substrate overlap with the orthographic projection of the organic layer onto the substrate, mask compatibility for different design schemes can be achieved. Different design schemes, where the functional metal layer is located on the side of the organic layer furthest from or near the substrate, can be implemented using a single mask, provided the aforementioned effect is achieved. For example, the three structural designs shown in Figures 3 to 5 can be implemented using the same set of masks. This achieves mask compatibility for different design schemes, reduces costs, and allows for the creation of different design schemes and products simply by adjusting the relative positions of the masks for each layer within the same set of masks, based on varying requirements.

[0093] In some examples, as shown in Figures 3 to 5, the array substrate may further include a common electrode metal layer 132 that is in direct contact with the common electrode layer 131. The common electrode metal layer 132 is located on the side of the common electrode layer 131 away from the substrate 101, and includes a plurality of common electrode metal lines 1320, each common electrode metal line 1320 being located between two adjacent pixel electrode patterns 141. This improves the signal uniformity of the common electrode layer 131 and enhances the display effect. Of course, this disclosure does not limit the common electrode metal layer, and it may not be provided. For example, common electrode metal lines can be fabricated on other metal layers, which will not be elaborated here.

[0094] Figure 6 is a schematic diagram of a film layer and its mask corresponding to the array substrate shown in Figure 3; Figure 7 is a schematic diagram of a film layer and its mask corresponding to the array substrate shown in Figure 4; Figure 8 is a schematic diagram of a film layer and its mask corresponding to the array substrate shown in Figure 5.

[0095] As shown in Figures 3 and 6, the functional metal layer 150 of the array substrate is located on the side of the organic layer 160 away from the substrate 101. The film layers of the array substrate include a gate metal layer 110, a gate metal insulating layer GI, an active layer ACT, a source / drain metal layer 120, a passivation layer PVX1, an organic layer 160, a passivation layer PVX2, a functional metal layer 150, a passivation layer PVX3, a common electrode layer 131, a common electrode metal layer 132, a passivation layer PVX4, and a pixel electrode layer 140, which are sequentially formed on the substrate 101. The array substrate includes four metal layers, one insulating layer, one active layer ACT, four passivation layers, one organic layer 160, one common electrode layer 131, and one pixel electrode layer 140. The four metal layers are the gate metal layer 110, the source / drain metal layer 120, the functional metal layer 150, and the common electrode metal layer 132. The gate metal insulating layer GI and the passivation layer are used for signal isolation.

[0096] For example, as shown in FIG6, the masks forming each film layer of the array substrate of FIG3 include gate metal layer mask 210, active layer mask ACT2, source / drain metal layer mask 220, organic layer mask 260, functional metal layer mask 250, common electrode mask 230, passivation layer mask 290, and pixel electrode layer mask 240.

[0097] For example, the common electrode layer 131 and common electrode metal layer 132 of the array substrate shown in Figures 6 to 8 are schematically shown to be fabricated using a single mask process. Of course, this disclosure is not limited to this; the common electrode layer and common electrode metal layer can also be fabricated using two mask processes, which will not be elaborated further here. For example, the active layer ACT and source / drain metal layer 120 of the array substrate shown in Figures 6 to 8 are schematically shown to be fabricated using two mask processes. Of course, this disclosure is not limited to this; the active layer and source / drain metal layer can also be fabricated using a single mask process, which will not be elaborated further here.

[0098] For example, vias on multiple passivation layers in embodiments of this disclosure can be formed by a passivation layer mask through a one-step etching process, and the vias on multiple passivation layers can be formed by one-step etching through the uppermost passivation layer mask.

[0099] As shown in Figures 4 and 7, the functional metal layer 150 of the array substrate is located between the organic layer 160 and the source / drain metal layer 120. The film layers of the array substrate include a gate metal layer 110, a gate metal insulating layer GI, an active layer ACT, a source / drain metal layer 120, a passivation layer PVX1, a functional metal layer 150, a passivation layer PVX2, an organic layer 160, a common electrode layer 131, a common electrode metal layer 132, a passivation layer PVX3, and a pixel electrode layer 140, which are sequentially formed on the substrate 101. The array substrate includes four metal layers, one insulating layer, one active layer ACT, three passivation layers, one organic layer 160, one common electrode layer 131, and one pixel electrode layer 140. The four metal layers are the gate metal layer 110, the source / drain metal layer 120, the functional metal layer 150, and the common electrode metal layer 132. The gate metal insulating layer GI and the passivation layer are used for signal isolation.

[0100] For example, as shown in FIG7, the masks forming each layer of the array substrate of FIG4 include gate metal layer mask 210, active layer mask ACT2, source / drain metal layer mask 220, functional metal layer mask 250, organic layer mask 260, common electrode mask 230, passivation layer mask 290, and pixel electrode layer mask 240.

[0101] As shown in Figures 5 and 8, the functional metal layer 150 of the array substrate is located on the side of the gate metal layer 110 close to the substrate 101. The film layers of the array substrate include the functional metal layer 150, passivation layer PVX1, gate metal layer 110, gate metal insulating layer GI, active layer ACT, source / drain metal layer 120, passivation layer PVX2, organic layer 160, common electrode layer 131, common electrode metal layer 132, passivation layer PVX3, and pixel electrode layer 140 sequentially formed on the substrate 101. The array substrate includes four metal layers, one insulating layer, one active layer ACT, three passivation layers, one organic layer 160, one common electrode layer 131, and one pixel electrode layer 140. The four metal layers are the gate metal layer 110, source / drain metal layer 120, functional metal layer 150, and common electrode metal layer 132, respectively. The gate metal insulating layer GI and the passivation layer are used for signal isolation.

[0102] For example, as shown in FIG8, the masks forming each film layer of the array substrate of FIG5 include a functional metal layer mask 250, a gate metal layer mask 210, an active layer mask ACT2, a source / drain metal layer mask 220, an organic layer mask 260, a common electrode mask 230, a passivation layer mask 290, and a pixel electrode layer mask 240.

[0103] As shown in Figures 4 and 5, and Figures 7 and 8, when the functional metal layer 150 is located on the side of the organic layer 160 closest to the substrate 101, the pixel electrode layer 140 or the common electrode layer 131 can be directly formed on the organic layer 160. Therefore, the array substrate shown in Figures 4 and 5 has fewer film layers, reducing costs and simplifying the process. Furthermore, the array substrate shown in Figures 4 and 5 also has relatively fewer film layers on the side of the organic layer 160 furthest from the substrate 101, resulting in a simpler structure, simplified manufacturing process, reduced total thickness of the film layers on the side of the organic layer 160 furthest from the substrate 101, reduced risk of film peeling and translation, ensured film quality, and improved product yield.

[0104] As shown in Figures 6 to 8, the three array substrates include the same number of masks, differing only in their relative positions. The functional metal lines 151 of the functional metal layer 150 are positioned between adjacent pixel electrode patterns 141. The influence of the functional metal layer 150 on the structural design of the display area A0 is limited to the structural design between adjacent pixel electrode patterns 141. Therefore, as shown in Figures 3, 4, and 5, in the display area A0, the three array substrates differ only in the position of the functional metal lines 151 of the functional metal layer 150; the structure of each film layer of the array substrate remains unchanged. Using the same set of masks, by adjusting the vertical order of the functional metal layer mask 250, the three array substrates shown in Figures 3, 4, and 5 can be obtained respectively, without the need to fabricate different masks. Therefore, in the display area A0, the three array substrates can be formed using the same set of masks, achieving mask compatibility.

[0105] The structural design of each film layer on the array substrate also includes trace connection design, and the peripheral area of ​​the array substrate also includes bonding area design. The following section explains the mask compatibility of the trace connection design and the bonding area design.

[0106] Figure 9 is a plan view of the wiring transition of an array substrate provided in an embodiment of the present disclosure; Figure 10 is a cross-sectional view of Figure 9 along the cutting line BB; Figure 11 is another cross-sectional view of Figure 9 along the cutting line BB; Figure 12 is another cross-sectional view of Figure 9 along the cutting line BB.

[0107] For example, Figure 10 uses the membrane structure shown in Figure 6, Figure 11 uses the membrane structure shown in Figure 7, and Figure 12 uses the membrane structure shown in Figure 8.

[0108] As shown in Figures 9 to 12, the array substrate further includes a first transition via V1 exposing a portion of the trace 112 in the gate metal layer 110 and a second transition via V2 exposing a portion of the trace 122 in the source / drain metal layer 120. The trace 112 in the gate metal layer 110 and the trace 122 in the source / drain metal layer 120 are connected to the pixel electrode layer 140 through the first transition via V1 and the second transition via V2, respectively, so that the two traces are connected. The organic layer 160 includes a first organic layer preset via 161. The orthographic projection of the first organic layer preset via V1 and the second transition via V2 onto the substrate 101 falls within the orthographic projection of the first organic layer preset via 161 onto the substrate 101. For example, the traces in the gate metal layer and the traces in the source / drain metal layer can also be connected to the common electrode layer through the first transition via and the second transition via, respectively, so that the two traces are connected.

[0109] When the traces 112 in the gate metal layer 110 and 122 in the source / drain metal layer 120 are connected via the pixel electrode layer 140 or the common electrode layer 131, the first connection via V1 and the second connection via V2 will pass through the organic layer 160 because the organic layer 160 is located on the side of the source / drain metal layer 120 away from the substrate 101. By including a first organic layer preset via 161 in the organic layer 160, the first connection via V1 and the second connection via V2 can be formed in a single etching process, avoiding the organic layer 160 from affecting the formation of the first connection via V1 and the second connection via V2. In addition, the first organic layer preset via 161 in the organic layer 160 can also reduce the thickness at the connection point, improving the film formation quality and accuracy at the connection point.

[0110] As shown in Figures 6 and 10, when the first transition via V1 and the second transition via V2 are formed through the passivation layer mask 290, the gate metal insulating layer GI and passivation layers PVX1, PVX2, PVX3, and PVX4 are etched. As shown in Figures 7 and 11, when the first transition via V1 and the second transition via V2 are formed through the passivation layer mask 290, the gate metal insulating layer GI and passivation layers PVX1, PVX2, and PVX3 are etched. As shown in Figures 8 and 12, when the first transition via V1 and the second transition via V2 are formed through the passivation layer mask 290, the gate metal insulating layer GI and passivation layers PVX2 and PVX3 are etched.

[0111] As shown in Figures 6 to 12, although the depths and passivation layer quantities of the first transition via V1 and the second transition via V2 in the wiring transition designs of the three array substrates are different, different depths can be etched by using different amounts of etching solution, resulting in transition vias of different depths. Therefore, for the wiring transition design, only an opening for forming the first organic layer preset via 161 needs to be reserved on the organic layer mask 260, and different depths of the first transition via V1 and the second transition via V2 can be formed through the opening on the passivation layer mask 290 using different amounts of etching solution. The structure of each film layer of the three array substrates remains unchanged. Using the same set of masks, different depths of the first transition via V1 and the second transition via V2 can be etched using different amounts of etching solution, resulting in the transition structures shown in Figures 10 to 12, without the need to fabricate separate masks. Therefore, for the routing and connection design, the three array substrates can be formed using the same set of masks, which can achieve mask compatibility.

[0112] In some examples, as shown in Figure 9, the orthographic projections of multiple first transition vias V1 and multiple second transition vias V2 onto the substrate 101 fall within the orthographic projection of a first organic layer preset via 161 onto the substrate 101. This simplifies the structural design, reduces the film thickness in the transition region, improves film quality and yield, and simplifies the structural design of the organic layer mask 260.

[0113] In some examples, as shown in Figure 1, the peripheral region B0 also includes a bonding region B1, and the array substrate further includes multiple conductive pads 170 located in the bonding region B1. The organic layer 160 also includes a second organic layer preset via 162, and the orthographic projection of the multiple conductive pads 170 onto the substrate 101 falls within the orthographic projection of the second organic layer preset via 162 onto the substrate 101. When a portion of the structure of the conductive pad 170 is located on the side of the organic layer 160 close to the substrate 101, a portion of the structure of the conductive pad 170 will pass through the organic layer 160. By including the second organic layer preset via 162 in the organic layer 160, the organic layer 160 can be prevented from affecting the formation of the conductive pads 170. The second organic layer preset via 162 in the organic layer 160 can also reduce the thickness of the bonding region B1, improving the film quality and film formation accuracy of the conductive pads.

[0114] Figure 13 is a partial schematic diagram of the bonding region of the array substrate shown in Figure 1; Figure 14 is another partial schematic diagram of the bonding region of the array substrate shown in Figure 1; Figure 15 is another partial schematic diagram of the bonding region of the array substrate shown in Figure 1.

[0115] For example, Figure 13 uses the film structure shown in Figure 6, Figure 14 uses the film structure shown in Figure 7, and Figure 15 uses the film structure shown in Figure 8. Figures 13 to 15 show the bonding structure of the traces located in the gate metal layer.

[0116] Figure 13 to Figure 15 shows (a) a partially enlarged schematic diagram of the conductive pad in the bonding area and (b) a cross-sectional schematic diagram along the cutting line CC.

[0117] As shown in Figures 1 and 13 to 15, the plurality of conductive pads 170 include a first conductive pad 171. For example, the first conductive pad 171 is used for bonding traces located in the gate metal layer 110. The first conductive pad 171 includes a first conductive pad 1711, a first conductive pad via 1701, and a second conductive pad 1712. The first conductive pad 1711 is located in the gate metal layer 110, the first conductive pad via 1701 exposes a portion of the first conductive pad 1711, and the second conductive pad 1712 is located in the pixel electrode layer 140 or the common electrode layer 131. Figures 13 to 15 schematically show the second conductive pad 1712 located in the pixel electrode layer 140. The first conductive pad 1711 is directly connected to the second conductive pad 1712 through the first conductive pad via 1701. Thus, bonding of traces located in the gate metal layer 110 can be achieved.

[0118] As shown in Figures 13 to 15, for the bonding structure of the traces located on the gate metal layer 110, the differences in the bonding structures of the three array substrates at this location lie only in the position of the gate metal layer 110, the number of passivation layers, or the position of the passivation layers. For example, as shown in Figure 13, the first conductive pad via 1701 passes through the gate metal insulating layer GI and passivation layers PVX1, PVX2, PVX3, and PVX4. For example, as shown in Figure 14, the first conductive pad via 1701 passes through the gate metal insulating layer GI and passivation layers PVX1, PVX2, and PVX3. For example, as shown in Figure 15, the first conductive pad via 1701 passes through the gate metal insulating layer GI and passivation layers PVX1 and PVX2. For the bonding structure of the traces located in the gate metal layer 110, the structure of each film layer remains unchanged. The first conductive pad vias 1701 can be etched in one step using the passivation layer mask 290 in Figures 6 to 8. Although the three first conductive pad vias 1701 have different depths and different amounts of passivation layer etched, different depths can be obtained by using different amounts of etching solution. Thus, first conductive pad vias 1701 of different depths can be obtained. Therefore, using the same set of masks, the same result can be achieved by adjusting the vertical position or number of each mask, without the need to fabricate different masks separately. Therefore, the three array substrates can be formed using the same set of masks, achieving mask compatibility.

[0119] Figure 16 is another partial schematic diagram of the bonding region of the array substrate shown in Figure 1; Figure 17 is another partial schematic diagram of the bonding region of the array substrate shown in Figure 1; Figure 18 is another partial schematic diagram of the bonding region of the array substrate shown in Figure 1.

[0120] For example, Figure 16 uses the film structure shown in Figure 6, Figure 17 uses the film structure shown in Figure 7, and Figure 18 uses the film structure shown in Figure 8. Figures 16 to 18 show the bonding structure of the traces located in the functional metal layer.

[0121] Figure 16 to Figure 18 shows (a) a partially enlarged schematic diagram of the conductive pad in the bonding area, and (b) a cross-sectional schematic diagram along the cutting line DD.

[0122] As shown in Figures 1 and 16 to 18, the plurality of conductive pads 170 include a second type of conductive pad 172. The second type of conductive pad 172 includes a third conductive pad 1723, a second conductive pad via 1702, and a fourth conductive pad 1724. The third conductive pad 1723 is located in the functional metal layer 150, and the second conductive pad via 1702 exposes a portion of the third conductive pad 1723. The fourth conductive pad 1724 is located in the pixel electrode layer 140 or the common electrode layer 131. Figures 16 to 18 schematically show a second conductive pad 1712 located in the pixel electrode layer 140. The third conductive pad 1723 is directly connected to the fourth conductive pad 1724 through the second conductive pad via 1702. This allows for the bonding of traces located in the functional metal layer 150.

[0123] As shown in Figures 16 to 18, for the bonding structure of the traces located on the functional metal layer 150, the only difference between the bonding structures of the three array substrates at this location lies in the position of the functional metal layer 150, the number of passivation layers, or the position of the passivation layers. For example, as shown in Figure 16, the second conductive pad via 1702 passes through passivation layers PVX3 and PVX4. For example, as shown in Figure 17, the second conductive pad via 1702 passes through passivation layers PVX2 and PVX3. For example, as shown in Figure 18, the second conductive pad via 1702 passes through the gate metal insulating layer GI and passivation layers PVX2 and PVX3. For the bonding structure of the traces located in the functional metal layer 150, the structure of each film layer remains unchanged. The second conductive pad vias 1702 can be etched in one step using the passivation layer mask 290 in Figures 6 to 8. Although the depths of the three second conductive pad vias 1702 are different, and the number of passivation layers etched is different, different depths can be obtained by using different etching solutions with different etching amounts, thus achieving second conductive pad vias 1702 of different depths. Therefore, using the same set of masks, the same result can be achieved by adjusting the vertical position or number of each mask, without the need to fabricate different masks separately. Thus, the three array substrates can be formed using the same set of masks, achieving mask compatibility.

[0124] Figure 19 is a schematic diagram of another film layer and its mask corresponding to the array substrate shown in Figure 3; Figure 20 is a schematic diagram of another film layer and its mask corresponding to the array substrate shown in Figure 4; Figure 21 is a schematic diagram of another film layer and its mask corresponding to the array substrate shown in Figure 5.

[0125] As shown in Figures 3 and 19, the functional metal layer 150 of the array substrate is located on the side of the organic layer 160 away from the substrate 101. The film layers of the array substrate include a gate metal layer 110, a gate metal insulating layer GI, an active layer ACT, a source / drain metal layer 120, a passivation layer PVX1, an organic layer 160, a passivation layer PVX2, a functional metal layer 150, a passivation layer PVX3, a common electrode layer 131, a common electrode metal layer 132, a passivation layer PVX4, and a pixel electrode layer 140, which are sequentially formed on the substrate 101. The array substrate includes four metal layers, one insulating layer, one active layer ACT, four passivation layers, one organic layer 160, one common electrode layer 131, and one pixel electrode layer 140. The four metal layers are the gate metal layer 110, the source / drain metal layer 120, the functional metal layer 150, and the common electrode metal layer 132. The gate metal insulating layer GI and the passivation layer are used for signal isolation.

[0126] For example, as shown in FIG19, the masks forming each film layer of the array substrate of FIG3 include gate metal layer mask 210, active layer mask ACT2, gate metal insulating layer mask GI2, source drain metal layer mask 220, organic layer mask 260, functional metal layer mask 250, common electrode mask 230, passivation layer mask 290, and pixel electrode layer mask 240.

[0127] As shown in Figures 4 and 20, the functional metal layer 150 of the array substrate is located between the organic layer 160 and the source / drain metal layer 120. The film layers of the array substrate include a gate metal layer 110, a gate metal insulating layer GI, an active layer ACT, a source / drain metal layer 120, a passivation layer PVX1, a functional metal layer 150, a passivation layer PVX2, an organic layer 160, a common electrode layer 131, a common electrode metal layer 132, a passivation layer PVX3, and a pixel electrode layer 140, which are sequentially formed on the substrate 101. The array substrate includes four metal layers, one insulating layer, one active layer ACT, three passivation layers, one organic layer 160, one common electrode layer 131, and one pixel electrode layer 140. The four metal layers are the gate metal layer 110, the source / drain metal layer 120, the functional metal layer 150, and the common electrode metal layer 132. The gate metal insulating layer GI and the passivation layer are used for signal isolation.

[0128] For example, as shown in FIG20, the masks forming each film layer of the array substrate of FIG4 include gate metal layer mask 210, active layer mask ACT2, gate metal insulating layer mask GI2, source drain metal layer mask 220, functional metal layer mask 250, organic layer mask 260, common electrode mask 230, passivation layer mask 290, and pixel electrode layer mask 240.

[0129] As shown in Figures 5 and 21, the functional metal layer 150 of the array substrate is located on the side of the gate metal layer 110 close to the substrate 101. The film layers of the array substrate include the functional metal layer 150, passivation layer PVX1, gate metal layer 110, gate metal insulating layer GI, active layer ACT, source / drain metal layer 120, passivation layer PVX2, organic layer 160, common electrode layer 131, common electrode metal layer 132, passivation layer PVX3, and pixel electrode layer 140 sequentially formed on the substrate 101. The array substrate includes four metal layers, one insulating layer, one active layer ACT, three passivation layers, one organic layer 160, one common electrode layer 131, and one pixel electrode layer 140. The four metal layers are the gate metal layer 110, source / drain metal layer 120, functional metal layer 150, and common electrode metal layer 132, respectively. The gate metal insulating layer GI and the passivation layer are used for signal isolation.

[0130] For example, as shown in FIG21, the masks forming each film layer of the array substrate of FIG5 include a functional metal layer mask 250, a gate metal layer mask 210, an active layer mask ACT2, a gate metal insulating layer mask GI2, a source / drain metal layer mask 220, an organic layer mask 260, a common electrode mask 230, a passivation layer mask 290, and a pixel electrode layer mask 240.

[0131] As shown in Figures 4 and 5, and Figures 20 and 21, when the organic layer 160 is located on the side of the functional metal layer 150 and the source / drain metal layer 120 away from the substrate 101, the pixel electrode layer 140 or the common electrode layer 131 can be directly formed on the organic layer 160. Therefore, the array substrate shown in Figures 4 and 5 has fewer film layers, reducing costs and simplifying the process. Furthermore, the array substrate shown in Figures 4 and 5 also has relatively fewer film layers on the side of the organic layer 160 away from the substrate 101, resulting in a simpler structure, simplified fabrication process, reduced total thickness of the film layers on the side of the organic layer 160 away from the substrate 101, reduced risk of film peeling and translation, ensured film quality, and improved product yield.

[0132] As shown in Figures 19 to 21, the three array substrates include the same number of masks, differing only in their relative positions. As shown in Figures 3, 4, and 5, in display area A0, the three array substrates differ only in the position of the functional metal lines 151 of the functional metal layer 150. The structure of each film layer of the array substrate remains unchanged. Using the same set of masks, by adjusting the vertical order of the functional metal layer masks 250, the three array substrates shown in Figures 3, 4, and 5 can be obtained respectively, without the need to fabricate different masks. Therefore, in display area A0, the three array substrates can be formed using the same set of masks, achieving mask compatibility.

[0133] Figure 22 is another cross-sectional view of Figure 9 along the cutting line BB; Figure 23 is another cross-sectional view of Figure 9 along the cutting line BB; Figure 24 is another cross-sectional view of Figure 9 along the cutting line BB.

[0134] For example, Figure 22 uses the membrane structure shown in Figure 19, Figure 23 uses the membrane structure shown in Figure 20, and Figure 24 uses the membrane structure shown in Figure 21.

[0135] As shown in Figures 22 to 24, the gate metal insulating layer GI includes multiple gate metal insulating layer preset vias GI01, and the source / drain metal layer 120 also includes a first source / drain metal layer connection structure 123 located within each gate metal insulating layer preset via GI01. The gate metal insulating layer preset vias GI01 and the first source / drain metal layer connection structure 123 located therewith not only facilitate the connection between traces of different layers, but also reduce the depth of the connection vias, thereby improving product quality and yield.

[0136] In some examples, as shown in Figures 22 to 24, the source / drain metal layer 120 further includes a second source / drain metal layer connection structure 124 connected to the first source / drain metal layer connection structure 123. The second source / drain metal layer connection structure 124 is located on the side of the first source / drain metal layer connection structure 123 away from the substrate 101. The second source / drain metal layer connection structure 124 is connected to the trace 112 in the gate metal layer 110 through the first source / drain metal layer connection structure 123. The second source / drain metal layer connection structure 124 can facilitate the connection between traces of different layers and can further reduce the depth of the connection vias, thereby improving product quality and yield.

[0137] In some examples, as shown in Figures 22 to 24, the array substrate further includes a second transition via V2 exposing a portion of the trace 122 within the source / drain metal layer 120 and a third transition via V3 exposing a portion of the second source / drain metal layer connection structure 124. The trace 122 within the source / drain metal layer 120 and the second source / drain metal layer connection structure 124 are connected to the pixel electrode layer 140 through the second transition via V2 and the third transition via V3, respectively, so that the trace 122 within the source / drain metal layer 120 is connected to the second source / drain metal layer connection structure 124. Thus, the trace 122 within the source / drain metal layer 120 can be connected to the trace 112 within the gate metal layer 110. When the trace 122 in the source / drain metal layer 120 is connected to the trace 112 in the gate metal layer 110 via the pixel electrode layer 140, the first source / drain metal layer connection structure 123 and the second source / drain metal layer connection structure 124 reduce the depth of the third transition via V3, avoiding over-etching and improving product yield and quality. For example, the trace 112 in the gate metal layer 110 and the trace 122 in the source / drain metal layer 120 can also be connected to the common electrode layer 131 to connect the two traces.

[0138] In some examples, as shown in Figures 22 to 24, the second adapter via V2 and the third adapter via V3 have approximately the same depth. This simplifies the manufacturing process and improves product yield and quality.

[0139] In some examples, as shown in Figures 9 and 22 to 24, the orthographic projections of the second transition via V2 and the third transition via V3 onto the substrate 101 fall within the orthographic projection of the first organic layer preset via 161 onto the substrate 101. This allows the second transition via V2 and the third transition via V3 to be formed in a single etching process, preventing the organic layer 160 from affecting their formation. Furthermore, the first organic layer preset via 161 of the organic layer 160 can also reduce the thickness at the transition location, improving the film quality and precision at the transition location.

[0140] As shown in Figures 19 and 22, when the second transition via V2 and the third transition via V3 are formed through the passivation layer mask 290, passivation layers PVX1, PVX2, PVX3, and PVX4 need to be etched. As shown in Figures 20 and 23, when the second transition via V2 and the third transition via V3 are formed through the passivation layer mask 290, passivation layers PVX1, PVX2, and PVX3 need to be etched. As shown in Figures 21 and 24, when the second transition via V2 and the third transition via V3 are formed through the passivation layer mask 290, passivation layers PVX2 and PVX3 need to be etched.

[0141] As shown in Figures 19 to 24, although the depths and passivation layer quantities of the second transition via V2 and the third transition via V3 in the wiring transition designs of the three array substrates are different, different depths can be etched by using different amounts of etching solution, resulting in transition vias of varying depths. Therefore, for the wiring transition design, only an opening for forming the first organic layer preset via 161 needs to be pre-reserved on the organic layer mask 260. Through the opening on the passivation layer mask 290, different amounts of etching solution can be used to form the second transition via V2 and the third transition via V3 of different depths. The structure of each film layer on the three array substrates remains unchanged. Using the same set of masks, the transition structures shown in Figures 22 to 24 can be obtained respectively, without the need to fabricate different masks. Therefore, for the wiring transition design, the three array substrates can be formed using the same set of masks, achieving mask compatibility.

[0142] Figure 25 is a cross-sectional schematic diagram of a wiring connection provided in an embodiment of the present disclosure; Figure 26 is a cross-sectional schematic diagram of another wiring connection provided in an embodiment of the present disclosure; Figure 27 is a cross-sectional schematic diagram of a wiring connection provided in an embodiment of the present disclosure.

[0143] For example, Figure 25 uses the membrane structure shown in Figure 19, Figure 26 uses the membrane structure shown in Figure 20, and Figure 27 uses the membrane structure shown in Figure 21.

[0144] As shown in Figures 25 to 27, the gate metal insulating layer GI includes multiple gate metal insulating layer preset vias GI01, and the source / drain metal layer 120 also includes a first source / drain metal layer connection structure 123 located within each gate metal insulating layer preset via GI01. The orthogonal projection of the gate metal insulating layer preset via GI01 onto the substrate 101 overlaps with the traces 112 in the gate metal layer 110 and the traces 122 in the source / drain metal layer 120. The traces 112 in the gate metal layer 110 and the traces 122 in the source / drain metal layer 120 are directly connected through the first source / drain metal layer connection structure 123 located within the gate metal insulating layer GI. This simplifies the connection between the traces on the gate metal layer 110 and the source / drain metal layer 120, thus simplifying the trace design.

[0145] In some examples, as shown in Figures 25 to 27, for the wiring structure design where the trace 112 in the gate metal layer 110 and the trace 122 in the source / drain metal layer 120 are directly connected by the first source / drain metal layer connection structure 123, the only difference between the three array substrates at this location is the number and position of the passivation layer P. The structure of each film layer remains unchanged, and the same set of masks can be used. The design can be achieved by adjusting the vertical position or number of each mask, without the need to fabricate different masks separately. Therefore, the three array substrates can be formed using the same set of masks, achieving mask compatibility.

[0146] Figure 28 is another partial schematic diagram of the bonding region of the array substrate shown in Figure 1; Figure 29 is another partial schematic diagram of the bonding region of the array substrate shown in Figure 1; Figure 30 is another partial schematic diagram of the bonding region of the array substrate shown in Figure 1.

[0147] For example, Figure 28 uses the film structure shown in Figure 19, Figure 29 uses the film structure shown in Figure 20, and Figure 30 uses the film structure shown in Figure 21. Figures 28 to 30 show the bonding structure of the traces located in the gate metal layer.

[0148] Figures 28 to 30 show: (a) a partially enlarged schematic diagram of the conductive pad in the bonding area, (b) a cross-sectional schematic diagram along the cutting line EE, and (c) a cross-sectional schematic diagram along the cutting line FF.

[0149] In some examples, as shown in Figures 1 and 28 to 30, the array substrate further includes a plurality of conductive pads 170 located in the bonding region B1. The plurality of conductive pads 170 includes a first conductive pad 171. For example, the first conductive pad 171 is used for bonding traces located in the gate metal layer 110. The first conductive pad 171 includes a fifth conductive pad 1715, a third conductive pad via 1703, a sixth conductive pad 1716, a fourth conductive pad via 1704, and a seventh conductive pad 1717. The fifth conductive pad 1715 is located in the gate metal layer 110, the third conductive pad via 1703 exposes a portion of the fifth conductive pad 1715, the sixth conductive pad 1716 is located in the source / drain metal layer 120, the fourth conductive pad via 1704 exposes a portion of the sixth conductive pad 1716, and the seventh conductive pad 1717 is located in the pixel electrode layer 140. The third conductive pad via 1703 includes one of a plurality of gate metal insulating layer preset vias GI01. The fifth conductive pad 1715 and the sixth conductive pad 1716 are directly connected through a first source / drain metal layer connection structure 123 located within the gate metal insulating layer preset via GI01. The seventh conductive pad 1717 is directly connected to the sixth conductive pad 1716 through the fourth conductive pad via 1704.

[0150] As shown in Figures 28 to 30, for the bonding structure of the traces located on the gate metal layer 110, the only differences among the three array substrates at this location are the position of the gate metal layer 110, the number of passivation layers, and their positions. For example, as shown in Figure 28, the third conductive pad via 1703 can be a pre-set via GI01 in the gate metal insulating layer; the fourth conductive pad via 1704 passes through passivation layers PVX1, PVX2, PVX3, and PVX4. For example, as shown in Figure 29, the third conductive pad via 1703 can be a pre-set via GI01 in the gate metal insulating layer; the fourth conductive pad via 1704 passes through passivation layers PVX1, PVX2, and PVX3. For example, as shown in Figure 30, the third conductive pad via 1703 can be a pre-set via GI01 in the gate metal insulating layer; the third conductive pad via 1703 passes through passivation layers PVX2 and PVX3. As shown in Figures 28 to 30, for the bonding structure of the traces located in the gate metal layer 110, the structure of each film layer remains unchanged. The third conductive pad via 1703 can be formed using the gate metal insulating layer mask GI2 in Figures 19 to 21; the fourth conductive pad via 1704 can be etched in one step using the passivation layer mask 290 in Figures 19 to 21. Although the three fourth conductive pad vias 1704 have different depths and different amounts of passivation layer etched, different depths can be obtained by using different amounts of etching solution. Therefore, using the same set of masks, the same setup can be achieved by adjusting the vertical position or number of each mask, without the need to fabricate separate masks. The three array substrates can be formed using the same set of masks, achieving mask compatibility.

[0151] Figure 31 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1; Figure 32 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1; Figure 33 is another partial schematic diagram of the bonding area of ​​the array substrate shown in Figure 1.

[0152] For example, Figure 31 uses the film structure shown in Figure 19, Figure 32 uses the film structure shown in Figure 20, and Figure 33 uses the film structure shown in Figure 21. Figures 31 to 33 show the bonding structure of the traces located in the functional metal layer.

[0153] Figures 31 to 33 show: (a) a partially enlarged schematic diagram of the conductive pad in the bonding area, (b) a cross-sectional schematic diagram along the cutting line GG, and (c) a cross-sectional schematic diagram along the cutting line HH.

[0154] In some examples, as shown in Figures 1, 31, and 32, the functional metal layer 150 is located on the side of the source / drain metal layer 120 away from the substrate 101, and a plurality of conductive pads 170 include a second type of conductive pad 172. For example, the second type of conductive pad 172 is used for bonding traces located in the functional metal layer 150. The second type of conductive pad 172 includes an eighth conductive pad 1728, a fifth conductive pad via 1705, and a ninth conductive pad 1729. The eighth conductive pad 1728 is located in the functional metal layer 150, the fifth conductive pad via 1705 exposes a portion of the eighth conductive pad 1728, and the ninth conductive pad 1729 is located in the pixel electrode layer 140 or the common electrode layer 131. Figures 31 and 32 schematically show the ninth conductive pad 1729 located in the pixel electrode layer 140. The eighth conductive pad 1728 is directly connected to the ninth conductive pad 1729 through the fifth conductive pad via 1705. This allows for the bonding of traces located in the functional metal layer 150.

[0155] As shown in Figures 31 and 32, the bonding structure of the traces in the functional metal layer 150 differs at this location only in the passivation layers through which the fifth conductive pad via 1705 passes. For example, as shown in Figure 31, the fifth conductive pad via 1705 passes through passivation layers PVX3 and PVX4. For example, as shown in Figure 32, the fifth conductive pad via 1705 passes through passivation layers PVX2 and PVX3. The structure of each film layer remains unchanged; the same set of masks is used, and the passivation layer mask can be adjusted to achieve the desired result without the need for separate mask fabrication. Therefore, the array substrates shown in Figures 31 and 32 can be formed using the same set of masks, achieving mask compatibility.

[0156] In some examples, as shown in Figures 31 and 32, the fifth conductive pad via 1705 can be etched in one step through the passivation layer mask 290 in Figures 19 and 20, respectively.

[0157] In some examples, as shown in Figures 1 and 33, the functional metal layer 150 is located on the side of the gate metal layer near the substrate 101, and the plurality of conductive pads 170 further include a second type of conductive pad 172. For example, the second type of conductive pad 172 is used for bonding traces located in the functional metal layer 150. The second type of conductive pad 172 includes a tenth conductive pad 17210, a sixth conductive pad via 1706, an eleventh conductive pad 17211, a seventh conductive pad via 1707, and a twelfth conductive pad 17212. The tenth conductive pad 17210 is located in the functional metal layer 150, the sixth conductive pad via 1706 exposes a portion of the tenth conductive pad 17210, the eleventh conductive pad 17211 is located in the source / drain metal layer 120, the seventh conductive pad via 1707 exposes a portion of the eleventh conductive pad 17211, and the twelfth conductive pad 17212 is located in the pixel electrode layer 140 or the common electrode layer. Figure 33 schematically shows the second conductive pad 1712 located in the pixel electrode layer 140. The sixth conductive pad via 1706 includes one of a plurality of gate metal insulating layer preset vias GI01. As shown in Figures 21 and 33, when the gate metal insulating layer mask GI2 forms the gate metal insulating layer preset via GI01, the passivation layer PVX1 located below the gate metal insulating layer GI can be etched simultaneously, thereby forming the sixth conductive pad via 1706. The tenth conductive pad 17210 and the eleventh conductive pad 17211 are connected through the first source / drain metal layer connection structure 123 located in the gate metal insulating layer preset via GI01, and the eleventh conductive pad 17211 is directly connected to the twelfth conductive pad 17212 through the seventh conductive pad via 1707. Thus, the traces of the functional metal layer 150 are bonded through the second conductive pad 172.

[0158] In some examples, as shown in Figures 31 and 32, the second type of conductive pad 172 further includes a dummy conductive pad 1731 located in the source / drain metal layer 120 and a dummy conductive pad via 1732 located in the gate metal insulating layer GI. The dummy conductive pad 1731 is not connected to the eighth conductive pad 1728. The dummy conductive pad via 1732 includes one of a plurality of gate metal insulating layer preset vias GI01. The dummy conductive pad 1731 is connected to the first source / drain metal layer connection structure 123 located within the dummy conductive pad via 1732. The dummy conductive pad 1731 and the dummy conductive pad via 1732 do not serve a connection function in the second type of conductive pad 172 of the array substrate shown in Figures 31 and 32. However, by using dummy conductive pads 1731 and dummy conductive pad vias 1732, the mask of the array substrate shown in Figures 31 and 32 can be made compatible with the mask shown in Figure 33. When the functional metal layer 150 is adjusted from the side of the source / drain metal layer 120 away from the substrate 101 in Figures 31 and 32 to the side of the gate metal layer closer to the substrate 101 in Figure 33, the dummy conductive pads 1731 located in the source / drain metal layer 120 are connected to the functional metal layer 150 through the first source / drain metal layer connection structure 123 in the dummy conductive pad via 1732. The dummy conductive pads 1731 located in the source / drain metal layer 120 are then connected to the twelfth conductive pad 17212 through the seventh conductive pad via 1707. Thus, the bonding of the traces of the functional metal layer 150 can be achieved.

[0159] By including a preset dummy conductive pad 1731 and a dummy conductive pad via 1732 in the second type of conductive pad 172 of the array substrates in Figures 31 and 32, the preset dummy conductive pad 1731 and the dummy conductive pad via 1732 can achieve structural compatibility between the second type of conductive pad 172 of Figures 31 and 32 and the second type of conductive pad 172 shown in Figure 33. Therefore, the same set of photomasks can be used, and the bonding structure of Figures 31 to 33 can be achieved by adjusting the vertical position or number of each photomask, without the need to fabricate different photomasks separately. Thus, the three array substrates can be formed using the same set of photomasks, achieving photomask compatibility.

[0160] In some examples, as shown in Figures 3 to 5, each functional metal line 151 extends along the second direction Y, and the orthographic projection of each functional metal line 151 onto the substrate 101 overlaps with the orthographic projection of one of the multiple data lines 121 onto the substrate 101. This minimizes the adverse effects of the functional metal lines 151 on the pixel aperture. This disclosure does not limit the extension direction or number of the functional metal lines 151. For example, multiple functional metal lines 151 can also be arranged in a one-to-one correspondence with multiple data lines 121.

[0161] In some examples, as shown in Figures 3 to 5, in the overlapping functional metal lines 151 and data lines 121, the orthographic projection of the functional metal line 151 onto the substrate 101 can lie entirely within the orthographic projection of the data line 121 onto the substrate 101. This minimizes the adverse effects of the functional metal line 151 on the pixel aperture.

[0162] In some examples, as shown in Figures 3 to 5, the common electrode metal layer 132 includes a plurality of common electrode metal lines 1320. These common electrode metal lines 1320 extend along a second direction Y. The orthographic projection of each common electrode metal line 1320 extending along the second direction Y onto the substrate 101 overlaps with the orthographic projection of one of the plurality of data lines 121 onto the substrate 101. This minimizes the adverse effects of the common electrode metal lines 1320 extending along the second direction Y on the pixel aperture. This disclosure does not limit the extension direction or number of the common electrode metal lines 1320. For example, the plurality of common electrode metal lines 1320 may also be arranged in a one-to-one correspondence with the plurality of data lines 121.

[0163] In some examples, as shown in Figures 3 to 5, in the overlapping common electrode metal lines 1320 and data lines 121, the orthographic projection of the common electrode metal line 1320 onto the substrate 101 can be completely located within the orthographic projection of the data line 121 onto the substrate 101.

[0164] Figure 34 is a partially enlarged schematic diagram of an array substrate provided in an embodiment of this disclosure. Figure 35 is a cross-sectional schematic diagram along section line II of Figure 34; Figure 36 is another cross-sectional schematic diagram along section line II of Figure 34; Figure 37 is a cross-sectional schematic diagram along section line II of Figure 34. As shown in Figures 34 to 37, the array substrate includes a substrate 101, a gate metal layer 110, a source / drain metal layer 120, a pixel electrode layer 140, and a common electrode layer 131. The gate metal layer 110 is located on the substrate 101 and includes a plurality of gate lines 111 extending along a first direction X and arranged along a second direction Y in the display area, wherein the first direction X and the second direction Y are intersected. The source / drain metal layer 120 is located on the side of the gate metal layer 110 away from the substrate 101 and includes a plurality of data lines 121 arranged along the first direction X and extending along the second direction Y in the display area. The pixel electrode layer 140 is located on the side of the source / drain metal layer 120 away from the substrate 101, and includes a plurality of pixel electrode patterns 141 located in the display area. A common electrode layer 131 is located on the side of the source / drain metal layer 120 away from the substrate 101. The orthographic projection of each pixel electrode pattern 141 onto the substrate 101 lies within the area jointly defined by the orthographic projections of two adjacent data lines 121 along the first direction X and two adjacent gate lines 111 along the second direction Y onto the substrate 101. The plurality of pixel electrode patterns 141 are arranged in an array on the substrate 101. The array substrate also includes a functional metal layer 150 and an organic layer 160. The organic layer 160 is located between the source / drain metal layer 120 and the pixel electrode layer 140, and the functional metal layer 150 is located on the side of the pixel electrode layer 140 closer to the substrate 101. Therefore, this array substrate has the beneficial technical effects described above, which will not be repeated here.

[0165] In some examples, Figure 35 can adopt the membrane structure shown in Figure 6, Figure 36 can adopt the membrane structure shown in Figure 7, and Figure 37 can adopt the membrane structure shown in Figure 8. For example, Figure 35 can adopt the membrane structure shown in Figure 19, Figure 36 can adopt the membrane structure shown in Figure 20, and Figure 37 can adopt the membrane structure shown in Figure 21.

[0166] In some examples, as shown in Figures 34 to 37, the pixel electrode layer 140 is located on the side of the common electrode metal layer 132 away from the substrate 101, and each pixel electrode pattern 141 includes a plurality of strip-shaped pixel electrodes 1411 extending along the second direction Y and arranged along the first direction X, with a slit between two adjacent strip-shaped pixel electrodes 1411 along the first direction X.

[0167] Figure 38 is a cross-sectional view of Figure 34 along section line JJ; Figure 39 is another cross-sectional view of Figure 34 along section line JJ; Figure 40 is a cross-sectional view of Figure 34 along section line JJ. As shown in Figures 38 to 40, the source / drain metal layer 120 further includes a source / drain electrode 125, the pixel electrode further includes a pixel electrode connection structure 142 connected to the pixel electrode pattern 141, and the array substrate further includes a fourth transition via V4 exposing the source / drain electrode 125. The pixel electrode connection structure 142 is connected to the source / drain electrode 125 through the fourth transition via V4. Thus, the pixel electrode pattern 141 can be connected to the source / drain electrode 125.

[0168] For example, as shown in Figures 34 and 38, the source / drain electrode 125, the gate line 111 overlapping with the source / drain electrode 125, the data line 121 overlapping with the gate line 111, and the active layer can form a driving transistor TFT. The driving transistor TFT is connected to the pixel electrode pattern 141 through the pixel electrode connection structure 142, thereby realizing liquid crystal deflection.

[0169] In some examples, as shown in Figures 38 to 40, the organic layer 160 further includes a third organic layer preset via 163, and the common electrode layer 131 includes a common electrode layer via 1310. The orthographic projection of the fourth transition via V4 on the substrate 101 falls within the orthographic projections of the third organic layer preset via 163 and the common electrode layer via 1310 on the substrate 101. When the source / drain electrode 125 in the source / drain metal layer 120 is connected to the pixel electrode pattern 141, since the organic layer 160 is located between the source / drain metal layer 120 and the pixel electrode layer 140, and the pixel electrode layer 140 is located on the side of the common electrode layer 131 away from the substrate 101, the fourth transition via V4 will pass through the organic layer 160 and the common electrode layer 131. By ensuring that the orthographic projection of the fourth transition via V4 on the substrate 101 falls within the orthographic projections of the third organic layer preset via 163 and the common electrode layer via 1310 on the substrate 101, the fourth transition via V4 can be formed in a single etching process, avoiding the influence of the organic layer 160 and the common electrode layer 131 on the formation of the fourth transition via V4. Furthermore, the third organic layer preset via 163 in the organic layer 160 can reduce the thickness at that location, improving the film formation quality and precision at that location.

[0170] In some examples, as shown in Figures 38 to 40, the orthographic projection of the third organic layer via 163 onto the substrate 101 falls within the orthographic projection of the common electrode layer via 1310 onto the substrate 101. While there are no size requirements between the third organic layer via 163 and the common electrode layer via 1310 in the structure shown in Figure 38, in the structures shown in Figures 39 and 40, the common electrode layer 131 is formed directly on the organic layer 160. By ensuring that the orthographic projection of the third organic layer via 163 onto the substrate 101 falls within the orthographic projection of the common electrode layer via 1310 onto the substrate 101, mask compatibility for the three array substrates shown in Figures 38 to 40 can be achieved.

[0171] As shown in Figures 38 to 40, although the depths of the fourth transition vias V4 and the number of passivation layers etched are different for the three array substrates, different depths can be etched by using different amounts of etching solution, resulting in transition vias of varying depths. The structure of each film layer at this location remains unchanged for the three array substrates. Using the same set of masks and different amounts of etching solution to etch the third transition vias V3 to different depths, the connection structures shown in Figures 38 to 40 can be obtained respectively, without the need to fabricate separate masks. Therefore, the three array substrates can be formed using the same set of masks, achieving mask compatibility.

[0172] Figure 41 is a schematic planar structure of a gate metal layer and a functional metal layer provided in an embodiment of this disclosure. The gate metal layer 110 and the functional metal layer 150 can be used in the array substrate described above.

[0173] As shown in Figure 41, the gate metal layer 110 further includes a first alignment pattern 181. This first alignment pattern 181 can be used to align at least one of the aforementioned source / drain metal layer 120, pixel electrode layer 140, common electrode layer 131, functional metal layer 150, and organic layer 160 with the first alignment pattern 181. The functional metal layer 150 further includes a second alignment pattern 182. This second alignment pattern 182 can be used to align at least one of the gate metal layer 110, source / drain metal layer 120, pixel electrode layer 140, common electrode layer 131, and organic layer 160 with the second alignment pattern 182.

[0174] For example, in the film layer schemes of the three array substrates described above, as shown in Figures 6 to 8, the bottom layer of the array substrates shown in Figures 6 and 7 is a gate metal layer 110 formed on the substrate 101, while the bottom layer of the array substrate shown in Figure 8 is a functional metal layer 150 formed on the substrate 101. By ensuring that both the gate metal layer 110 and the functional metal layer 150 include alignment patterns, alignment between film layers can be achieved when the same set of masks is used in the three schemes of Figures 6 to 8, improving the quality and precision of the film layers and better realizing the mask compatibility of the three schemes of Figures 6 to 8.

[0175] In some examples, as shown in FIG41, the orthographic projection of the first alignment pattern 181 on the substrate 101 does not overlap with the orthographic projection of the second alignment pattern 182 on the substrate 101. This avoids mutual interference between the first alignment pattern 181 and the second alignment pattern 182, and prevents subsequent film layers from matching with the alignment patterns. For example, in the film layer scheme shown in FIG6, a gate metal layer 110 is formed first, including the first alignment pattern 181. The subsequently formed functional metal layer 150 includes the second alignment pattern 182. By ensuring that the second alignment pattern 182 does not overlap with the first alignment pattern 181, the second alignment pattern 182 avoids affecting the first alignment pattern 181, and prevents subsequent film layers of the functional metal layer 150 from matching with the first alignment pattern 181.

[0176] In some examples, as shown in Figures 41(a) and (b), the gate metal layer 110 includes a plurality of first alignment patterns 181 located on the outer periphery of the gate metal layer 110. For example, the plurality of first alignment patterns 181 are located on opposite sides of each other on the outer periphery of the gate metal layer 110. Similarly, the functional metal layer 150 includes a plurality of second alignment patterns 182 located on the outer periphery of the functional metal layer 150. For example, the plurality of second alignment patterns 182 are located on opposite sides of each other on the outer periphery of the functional metal layer 150. This improves the alignment effect of the alignment patterns and enhances the matching between the film layers. Figure 41 is only used to schematically illustrate the alignment patterns of the gate metal layer 110 and the functional metal layer 150; other structures do not limit the gate metal layer 110 and the functional metal layer 150.

[0177] The embodiments disclosed herein do not limit the number and position of the first alignment pattern 181 and the second alignment pattern 182.

[0178] In some examples, as shown in Figure 41(c), both the first alignment pattern 181 and the second alignment pattern 182 include horizontal line segments and multiple vertical line segments. This facilitates the identification and comparison of the alignment patterns. For example, the arrangement of the multiple vertical line segments in the first alignment pattern 181 and the second alignment pattern 182 is not uniform. For example, the arrangement of the multiple vertical line segments along the horizontal direction changes from sparse to dense or from dense to sparse. Therefore, when identifying the first alignment pattern 181 and the second alignment pattern 182, the positions can be adjusted according to the density of the vertical line segments, improving alignment efficiency. For example, the first alignment pattern 181 and the second alignment pattern 182 may have the same shape. This can further improve identification efficiency.

[0179] In some examples, the passivation layer on the side of the organic layer closest to the substrate can be processed using a high-temperature process. For example, the high-temperature process ranges from 280°C to 330°C. Conversely, the passivation layer on the side of the organic layer furthest from the substrate can be processed using a low-temperature process. For example, the low-temperature process ranges from 220°C to 230°C. Low-temperature processes can avoid adverse effects on the organic layer and also ensure a high yield of the film formed on the side of the organic layer furthest from the substrate.

[0180] For example, in the film layers of the array substrate shown in Figure 6, the passivation layer PVX1 of the organic layer 160 near the substrate 101 is processed using a high-temperature process, while the passivation layers PVX2, PVX3, and PVX4 of the organic layer 160 away from the substrate 101 are processed using a low-temperature process. For example, in the film layers of the array substrate shown in Figures 7 and 8, the passivation layers PVX1 and PVX2 of the organic layer 160 near the substrate 101 are processed using a high-temperature process, while the passivation layer PVX3 of the organic layer 160 away from the substrate 101 is processed using a low-temperature process.

[0181] In some examples, the thickness of the organic layer ranges from 1.5 μm to 3.0 μm. For example, thicknesses of the organic layer are 1.6 μm, 1.8 μm, 2.0 μm, 2.3 μm, 2.5 μm, and 2.8 μm, etc., which will not be elaborated further here. This allows for better signal shielding, reduced load, and improved display performance.

[0182] In some examples, the organic film layer can be made of resin, acrylic acid, polyimide, zeolite diazide compounds, or other organic materials. These will not be elaborated upon further here.

[0183] Figure 42 shows the etching results using the scheme shown in Figure 22. As shown in Figures 22 and 42, by pre-setting the via GI01 in the gate metal insulating layer and the first source / drain metal layer connection structure 123 located therein, the depth of the connection via is reduced, improving product quality and yield. As shown in Figure 42, the over-etching amount of the connection vias in each metal film layer is significantly reduced, improving product quality and yield.

[0184] This disclosure also provides a display device. FIG43 is a schematic diagram of a display device provided in an embodiment of this disclosure. As shown in FIG43, the display device includes any of the array substrates 100 described above, an opposing substrate 210 disposed opposite to the array substrate, and a liquid crystal layer 220 located between the array substrate and the opposing substrate. Thus, the display device has the beneficial effects corresponding to the beneficial effects of the array substrate, which will not be described in detail here.

[0185] For example, the display device can be any product or component with display function, such as a television, laptop, tablet, mobile phone, navigator, wearable device, virtual reality device, etc.

[0186] This disclosure also provides a mask set. Figure 44 is a schematic planar structure diagram of a mask provided in this disclosure embodiment. This mask set is used to fabricate the array substrate described above. The mask set includes multiple masks, including a gate metal layer mask 210 for forming the gate metal layer described above and a functional metal layer mask 250 for forming the functional metal layer. The gate metal layer mask 210 includes a first alignment mark 211 to form the first alignment pattern described above. The functional metal layer mask 250 includes a second alignment mark 251 to form the second alignment pattern 182 described above. By including alignment marks in both the gate metal layer mask 210 and the functional metal layer mask 250, this mask set can be used to form different array substrates described above, achieving mask compatibility. For example, when the gate metal layer mask 210 is used as the first process, the first alignment mark 211 of the gate metal layer mask 210 can form a first alignment pattern for use in the alignment of subsequent masks. For example, when the functional metal layer mask 250 is used as the first process, the second alignment mark 251 of the functional metal layer mask 250 can form a second alignment pattern 182 for use in the alignment of subsequent processes.

[0187] The following points need to be explained:

[0188] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0189] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0190] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising a display area and a peripheral area at least partially surrounding the display area, comprising: Substrate; A gate metal layer, located on the substrate, includes a plurality of gate lines extending along a first direction and arranged along a second direction in the display area, wherein the first direction and the second direction are intersected. The source / drain metal layer is located on the side of the gate metal layer away from the substrate and includes a plurality of data lines arranged along a first direction and extending along a second direction in the display area. A pixel electrode layer, located on the side of the source / drain metal layer away from the substrate, includes a plurality of pixel electrode patterns located in the display area; as well as A common electrode layer is located on the side of the source / drain metal layer away from the substrate. The pixel electrode patterns are located within the area defined by the orthographic projections of two adjacent data lines along the first direction and two adjacent gate lines along the second direction onto the substrate. The plurality of pixel electrode patterns are arranged in an array on the substrate. The array substrate further includes a functional metal layer and an organic layer. The organic layer is located between the source / drain metal layer and the pixel electrode layer. The functional metal layer is located on the side of the pixel electrode layer closest to the substrate. The functional metal layer includes a plurality of functional metal lines, and the orthographic projection of each functional metal line onto the substrate lies between the orthographic projections of two adjacent pixel electrode patterns onto the substrate. The orthographic projections of each of the functional metal lines and each of the pixel electrode patterns on the substrate overlap with the orthographic projections of the organic layer on the substrate.

2. The array substrate according to claim 1, wherein, The functional metal layer is located on the side of the organic layer away from the substrate, or the functional metal layer is located between the organic layer and the source / drain metal layer, or the functional metal layer is located on the side of the gate metal layer close to the substrate.

3. The array substrate according to claim 1, wherein, The functional metal layer is located on the side of the organic layer closest to the substrate, and the common electrode layer or the pixel electrode layer is in direct contact with the organic layer.

4. The array substrate according to any one of claims 1-3, further comprising a first transition via exposing a portion of the wiring in the gate metal layer and a second transition via exposing a portion of the wiring in the source / drain metal layer, wherein the wiring in the gate metal layer and the wiring in the source / drain metal layer are respectively connected to the pixel electrode layer or the common electrode layer through the first transition via and the second transition via, so that the two wirings are connected. The organic layer includes a first organic layer preset via, and the first and second transition vias are projected onto the substrate in the orthographic projection of the first organic layer preset via onto the substrate.

5. The array substrate according to claim 4, wherein, The orthographic projections of the plurality of first transition vias and the plurality of second transition vias on the substrate fall within the orthographic projection of a first organic layer preset via on the substrate.

6. The array substrate according to any one of claims 1-5, wherein, The peripheral region further includes a bonding region, and the array substrate further includes a plurality of conductive pads located in the bonding region. The organic layer also includes a second organic layer pre-set via, and the orthographic projection of the plurality of conductive pads on the substrate falls within the orthographic projection of the second organic layer pre-set via on the substrate.

7. The array substrate according to claim 6, wherein, The plurality of conductive pads includes a first type of conductive pad, which comprises: A first conductive pad is located in the gate metal layer; A first conductive pad via is provided to expose a portion of the first conductive pad; and The second conductive pad is located in the pixel electrode layer or the common electrode layer. The first conductive pad is directly connected to the second conductive pad through a through-hole in the first conductive pad.

8. The array substrate according to claim 6, wherein, The plurality of conductive pads includes a second type of conductive pad, the second type of conductive pad comprising: A third conductive electronic pad is located in the functional metal layer; A second conductive pad via is provided to expose a portion of the third conductive pad; and The fourth conductive pad is located in the pixel electrode layer or the common electrode layer. The third conductive pad is directly connected to the fourth conductive pad through the through-hole of the second conductive pad.

9. The array substrate according to any one of claims 1-8, further comprising: A gate metal insulating layer is located between the gate metal layer and the source / drain metal layers. The gate metal insulating layer includes a plurality of gate metal insulating layer preset vias, and the source drain metal layer also includes a first source drain metal layer connection structure located within each of the gate metal insulating layer preset vias.

10. The array substrate according to claim 9, wherein, The source / drain metal layer further includes a second source / drain metal layer connection structure connected to the first source / drain metal layer connection structure. The second source / drain metal layer connection structure is located on the side of the first source / drain metal layer connection structure away from the substrate. The second source / drain metal layer connection structure is connected to the traces in the gate metal layer through the first source / drain metal layer connection structure. The array substrate further includes a second transition via exposing a portion of the traces within the source / drain metal layer and a third transition via exposing a portion of the connection structure of the second source / drain metal layer. The traces within the source / drain metal layer and the connection structure of the second source / drain metal layer are respectively connected to the pixel electrode layer or the common electrode layer through the second transition via and the third transition via, so that the traces within the source / drain metal layer are connected to the connection structure of the second source / drain metal layer.

11. The array substrate according to claim 9, wherein, The vias in the gate metal insulating layer overlap with the traces in the gate metal layer and the traces in the source / drain metal layer in their orthogonal projection onto the substrate. The traces in the gate metal layer and the traces in the source / drain metal layer are directly connected through the first source / drain metal layer connection structure located in the gate metal insulating layer.

12. The array substrate according to any one of claims 9-11, wherein, The peripheral region further includes a bonding region, and the array substrate further includes a plurality of conductive pads located in the bonding region. The plurality of conductive pads includes a first type of conductive pad, which comprises: The fifth conductive electronic pad is located in the gate metal layer; The third conductive pad has a via, exposing a portion of the fifth conductive pad; The sixth conductive electronic pad is located in the source / drain metal layer; The fourth conductive pad via exposes a portion of the sixth conductive pad; and The seventh conductive electronic pad is located in the pixel electrode layer or the common electrode layer. The third conductive pad via includes one of the plurality of gate metal insulating layer preset vias. The fifth conductive pad and the sixth conductive pad are directly connected through a first source-drain metal layer connection structure located in the gate metal insulating layer preset via. The seventh conductive pad is directly connected to the sixth conductive pad through the sixth conductive pad via.

13. The array substrate according to any one of claims 9-12, wherein, The peripheral region further includes a bonding region, the functional metal layer is located on the side of the source / drain metal layer away from the substrate, and the plurality of conductive pads further include a second type of conductive pad, the second type of conductive pad comprising: The eighth conductive electronic pad is located in the functional metal layer; The fifth conductive pad via exposes a portion of the eighth conductive pad; and The ninth conductive electronic pad is located in the pixel electrode layer or the common electrode layer. The eighth conductive pad is directly connected to the ninth conductive pad through the through-hole of the fifth conductive pad.

14. The array substrate according to claim 13, wherein, The second type of conductive pad further includes a dummy conductive pad located in the source / drain metal layer and a dummy conductive pad via located in the gate metal insulating layer. The dummy conductive pad is not connected to the eighth conductive pad. The dummy conductive pad via includes one of the plurality of gate metal insulating layer preset vias. The dummy conductive pad is connected to a first source / drain metal layer connection structure located in the dummy conductive pad via.

15. The array substrate according to any one of claims 9-12, wherein, The functional metal layer is located on the side of the gate metal layer closest to the substrate. The plurality of conductive pads further includes a second type of conductive pad, which includes: The tenth conductive electronic pad is located in the functional metal layer; The sixth conductive pad via exposes a portion of the tenth conductive pad. The eleventh conductive electronic pad is located in the source / drain metal layer; The seventh conductive pad via exposes a portion of the eleventh conductive pad; and The twelfth conductive electronic pad is located in the pixel electrode layer or the common electrode layer. The sixth conductive pad via includes one of the plurality of gate metal insulating layer preset vias. The tenth conductive pad and the eleventh conductive pad are connected by a first source-drain metal layer connection structure located in the gate metal insulating layer preset via. The eleventh conductive pad is directly connected to the twelfth conductive pad through the seventh conductive pad via.

16. The array substrate according to claim 3, wherein, The pixel electrode layer is located on the side of the common electrode layer away from the substrate, and the functional metal layer is located between the organic layer and the source / drain metal layer. The array substrate further includes a gate metal insulating layer located on the side of the gate metal layer away from the substrate, an active layer located between the gate metal insulating layer and the source / drain metal layer, a passivation layer located between the source / drain metal layer and the functional metal layer, a passivation layer located between the functional metal layer and the organic layer, a common electrode metal layer located on the side of the common electrode layer away from the substrate, and a passivation layer located between the common electrode metal layer and the pixel electrode layer.

17. The array substrate according to claim 3, wherein, The pixel electrode layer is located on the side of the common electrode layer away from the substrate, and the functional metal layer is located on the side of the gate metal layer closer to the substrate. The array substrate further includes a passivation layer between the functional metal layer and the gate metal layer, a gate metal insulating layer on the side of the gate metal layer away from the substrate, an active layer between the gate metal insulating layer and the source / drain metal layer, a passivation layer between the source / drain metal layer and the organic layer, a common electrode metal layer on the side of the common electrode layer away from the substrate, and a passivation layer between the common electrode metal layer and the pixel electrode layer.

18. The array substrate according to any one of claims 1-17, wherein, The pixel electrode layer is located on the side of the common electrode layer away from the substrate. Each of the pixel electrode patterns includes a plurality of strip-shaped pixel electrodes extending along the second direction and arranged along the first direction, with a slit between two adjacent strip-shaped pixel electrodes along the first direction.

19. The array substrate according to claim 18, wherein, The source / drain metal layer further includes source / drain electrodes, and the pixel electrode further includes a pixel electrode connection structure connected to the pixel electrode pattern. The array substrate further includes a fourth transition via exposing the source / drain electrodes, and the pixel electrode connection structure is connected to the source / drain electrodes through the fourth transition via. The organic layer further includes a third organic layer pre-set via, the common electrode layer includes a common electrode layer via, and the orthographic projection of the fourth transition via on the substrate falls within the orthographic projections of the third organic layer pre-set via and the common electrode via on the substrate. The orthographic projection of the pre-set via of the third organic layer onto the substrate falls within the orthographic projection of the via of the common electrode layer onto the substrate.

20. The array substrate according to any one of claims 1-19, wherein, The gate metal layer further includes a first alignment pattern for aligning at least one of the source / drain metal layer, the pixel electrode layer, the common electrode layer, the functional metal layer, and the organic layer with the first alignment pattern, and the functional metal layer further includes a second alignment pattern for aligning at least one of the gate metal layer, the source / drain metal layer, the pixel electrode layer, the common electrode layer, and the organic layer with the second alignment pattern.

21. The array substrate according to claim 20, wherein, The orthographic projection of the first alignment pattern onto the substrate does not overlap with the orthographic projection of the second alignment pattern onto the substrate.

22. The array substrate according to any one of claims 1-21, wherein, The thickness of the organic layer ranges from 1.5 μm to 3.0 μm.

23. The array substrate according to any one of claims 1-22, wherein, Each of the functional metal lines extends along the second direction, and the orthographic projection of each of the functional metal lines on the substrate overlaps with the orthographic projection of one of the plurality of data lines on the substrate.

24. The array substrate according to any one of claims 1-23, further comprising a common electrode metal layer in direct contact with the common electrode layer. in, The common electrode metal layer is located on the side of the common electrode layer away from the substrate, and the common electrode metal layer includes a plurality of common electrode metal lines, each of which is located between two adjacent pixel electrode patterns. The plurality of common electrode metal lines include a common electrode metal line extending along the second direction, and the orthographic projection of the common electrode metal line extending along the second direction on the substrate overlaps with the orthographic projection of one of the plurality of data lines on the substrate.

25. A display device comprising an array substrate according to any one of claims 1-24, an opposing substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the opposing substrate.

26. A mask assembly for fabricating the array substrate of claim 20, comprising: Multiple photomasks, including a gate metal layer photomask for forming the gate metal layer and a functional metal layer photomask for forming the functional metal layer, wherein the gate metal layer photomask includes a first alignment mark to form a first alignment pattern, and the functional metal layer photomask includes a second alignment mark to form a second alignment pattern.

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