Display panel and display apparatus

Abstract

Disclosed in the present application are a display panel and a display apparatus. Each pixel circuit of the display panel comprises a driving transistor and a storage capacitor, and a light-shielding layer in the display panel comprises driving light-shielding portions corresponding to driving transistors, wherein driving light-shielding portions in two sub-pixels which are adjacent to each other in a first direction are connected, and driving light-shielding portions in two sub-pixels which are adjacent to each other in a second direction are electrically connected by means of an electrical connection line.

Description

Display panel and display device Technical Field

[0001] This application relates to the field of displays, and in particular to a display panel and display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) display technology is a new type of display technology that has gradually attracted attention due to its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and has occupied a certain position in the field of panel display technology.

[0003] In current LTPO (Low Temperature Polysilicon Oxide) technology display devices, the bottom gate of some transistors is made of a light-shielding layer. However, due to the high impedance of the light-shielding layer, there is a potential difference between the middle and edge regions of the light-shielding layer when transmitting corresponding control signals. This means that the control signals of the display panel have different potentials in different regions, which leads to abnormal display of the display panel. Summary of the Invention

[0004] This application provides a display panel and a display device to improve the technical problem of abnormal display in existing display panels.

[0005] To address the above issues, the technical solution provided in this application is as follows:

[0006] In a first aspect, this application provides a display panel comprising a plurality of sub-pixels arranged in a first direction and a second direction, at least one of the sub-pixels comprising a pixel circuit, the pixel circuit comprising a driving transistor and a storage capacitor connected thereto; wherein, the display panel comprises:

[0007] The light-shielding layer includes a driving light-shielding portion corresponding to the driving transistor, and in the first direction, the driving light-shielding portions in two adjacent sub-pixels are connected;

[0008] The first active layer includes the active portion of the driving transistor;

[0009] The first gate layer includes the gate of the driving transistor and one plate of the storage capacitor;

[0010] The second active layer includes the other plate of the storage capacitor;

[0011] The display panel further includes an electrical connection line extending along the second direction, in which the driving light-shielding portions within two adjacent sub-pixels are electrically connected via the electrical connection line.

[0012] In a second aspect, this application also proposes a display device that includes the aforementioned display panel. Attached Figure Description

[0013] Figure 1 is a simplified structural diagram of the display panel of this application;

[0014] Figure 2 is an equivalent circuit diagram of the pixel circuit in the display panel of this application;

[0015] Figure 3 is a schematic diagram of the film layer in the display panel of this application;

[0016] Figure 4 is a layer stacking diagram of a sub-pixel in the display panel of this application;

[0017] Figure 5 is a structural diagram of the first gate layer in Figure 4;

[0018] Figure 6 is a structural diagram of the first active layer in Figure 4;

[0019] Figure 7 is a stack-up diagram of the first gate layer and the first active layer in Figure 4;

[0020] Figure 8 is a structural diagram of the light-shielding layer in Figure 4;

[0021] Figure 9 is a stack-up diagram of the first gate layer and the light-shielding layer in Figure 4;

[0022] Figure 10 is a structural diagram of the second active layer in Figure 4;

[0023] Figure 11 is a structural diagram of the second gate layer in Figure 4;

[0024] Figure 12 is a stack-up diagram of the light-shielding layer, the first gate layer, the first active layer, the second active layer, and the second gate layer in Figure 4;

[0025] Figure 13 is a structural diagram of the first source-drain layer in Figure 4;

[0026] Figure 14 is a stack-up diagram of the light-shielding layer, the first gate layer, the first active layer, the second active layer, the second gate layer, and the first source / drain layer in Figure 4.

[0027] Figure 15 is a structural diagram of the second source-drain layer in Figure 4;

[0028] Figure 16 is a stacked image of the film layers of some sub-pixels in Figure 1;

[0029] Figure 17 is a stacked diagram of Figure 4 and the anode layer. Embodiments of the present invention

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application.

[0031] In the description of this application, it should be understood that the terms "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, and "at least one" can mean one, two, or more, unless otherwise explicitly specified.

[0033] Please refer to Figures 1 to 17. This application provides a display panel 100, which may include a display section 200 and a gate circuit 300 located on one side of the display section 200. The gate circuit 300 is used to input control signals to the display section 200.

[0034] In this embodiment, please refer to FIG1. ​​The display unit 200 includes a plurality of sub-pixels PX arranged along a first direction and a second direction. Each sub-pixel PX is provided with a light-emitting device EL and a pixel circuit PC connected to the light-emitting device EL. The gate circuit 300 is used to input a gate control signal to the transistor in the pixel circuit PC.

[0035] In this embodiment, the pixel circuit PC includes a driving transistor T1 and a storage capacitor Cst connected together, and the display panel 100 includes a light-shielding layer 121, a first active layer 123, a first gate layer 125 and a second active layer 127.

[0036] In this embodiment, the light-shielding layer 121 includes a driving light-shielding portion T1L corresponding to the driving transistor T1. In the first direction X, the driving light-shielding portions T1L in two adjacent sub-pixels PX are connected. The first active layer 123 includes the active portion of the driving transistor T1. The first gate layer 125 includes the gate of the driving transistor T1 and one plate of the storage capacitor Cst. The second active layer 127 includes the other plate of the storage capacitor Cst.

[0037] In this embodiment, the display panel 100 further includes an electrical connection line 50 extending along the second direction Y. In the second direction Y, the driving light-shielding parts T1L in two adjacent sub-pixels PX are electrically connected through the electrical connection line 50.

[0038] This application provides an electrical connection line 50 extending along the second direction Y, which makes two adjacent driving light-shielding parts T1L in the second direction Y electrically connected. That is, the driving light-shielding parts T1L in different sub-pixels PX are electrically connected to each other in the first direction X and the second direction Y. This reduces the impedance of the driving light-shielding parts T1L, improves the potential difference in different areas of the light-shielding layer 121, and improves the display effect of the display panel 100.

[0039] The technical solution of this application will now be described in conjunction with specific embodiments.

[0040] Referring to Figure 1, the display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. A display unit 200 is provided within the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is enclosed by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple sub-pixels PX that perform their display functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the sub-pixels PX within the display area AA in displaying information.

[0041] Please refer to Figure 1. A bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit. The bonding terminal 400 transmits the signals input from the external circuit to the data traces, thereby driving the display panel 100 to display the image. For example, the bonding terminal 400 can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0042] In this embodiment, the gate circuit 300 is disposed in the non-display area NA, and the gate circuit 300 may be disposed on both sides of the display area AA; the gate circuit 300 may include multiple cascaded gate driving units, and the structure of the gate driving units is not specifically limited in this application.

[0043] In this embodiment, multiple light-emitting devices EL and pixel circuits PC that drive the light-emitting devices EL can be arrayed in the display area AA. The pixel circuit PC can be 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C, etc. In the following embodiment, the 8T2C pixel circuit PC is used as an example for explanation.

[0044] Please refer to Figure 2. The pixel circuit PC may include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a first light-emitting transistor T5, a second light-emitting transistor T6, a storage capacitor Cst, and a boost capacitor Cboost. The storage capacitor Cst includes a first plate Cst1 and a second plate Cst2.

[0045] Referring to Figure 2, the drain of switching transistor T2 is connected to the data line Data, the source of switching transistor T2 is connected to the first node A, and the switching gate T2G of switching transistor T2 is connected to the switching control line Pscan1; the drain of driving transistor T1 is connected to the first node A, the source of driving transistor T1 is connected to the second node B, and the driving gate T1G of driving transistor T1 is connected to the third node Q; the drain of compensation transistor T3 is connected to the third node Q, the source of compensation transistor T3 is connected to the second node B, and the compensation gate T3G of compensation transistor T3 is connected to the compensation control line Nscan1; the drain of the first reset transistor T4 is connected to the first reset signal line Vi1, the source of the first reset transistor T4 is connected to the third node Q, and the gate T4G of the first reset transistor T4 is connected to the first reset control line Nscan2; the drain of the second reset transistor T7 is connected to the second reset signal line Vi2, the source of the second reset transistor T7 is connected to the anode of the light-emitting device EL, and the gate T7G of the second reset transistor T7 is connected to the second reset control line Psc an2; The drain of the first light-emitting transistor T5 is connected to the high potential line VDD, the source of the first light-emitting transistor T5 is connected to the first node A, and the first light-emitting gate T5G of the first light-emitting transistor T5 is connected to the light-emitting control line EM; The drain of the second light-emitting transistor T6 is connected to the second node B, the source of the second light-emitting transistor T6 is connected to the anode of the light-emitting device EL, and the second light-emitting gate T6G of the second light-emitting transistor T6 is connected to the light-emitting control line EM; The drain of the third reset transistor T8 is connected to the third reset signal line Vi3, the source of the third reset transistor T8 is connected to the first node A, and the third reset gate T8G of the third reset transistor T8 is connected to the second reset control line Pscan2; The first plate Cst1 of the storage capacitor Cst is connected to the third node Q, and the second plate Cst1 of the storage capacitor Cst is connected to the high potential line VDD; One plate of the boost capacitor Cboost is connected to the switch control line Pscan1, and the other plate of the boost capacitor Cboost is connected to the third node Q; The cathode of the light-emitting device EL is connected to the low potential line VSS.

[0046] It should be noted that the data signal lines connected to the switching transistor T2 in different sub-pixels PX are different. This application only uses one of them as an example for illustration.

[0047] It should be noted that the light-emitting device EL in this application can be an organic light-emitting diode, a Mini LED, a Micro LED, a standard-sized LED, or other light-emitting sources.

[0048] In this embodiment, the high potential line VDD is used to provide a constant high voltage level to the pixel circuit PC, and the low potential line VSS is used to provide a constant low voltage level to the pixel circuit PC.

[0049] In this embodiment, the switching transistor T2, driving transistor T1, second reset transistor T7, third reset transistor T8, first light-emitting transistor T5, second light-emitting transistor T6, compensation transistor T3, and first reset transistor T4 can be either P-type transistors or N-type transistors. This application uses the example where the switching transistor T2, driving transistor T1, second reset transistor T7, third reset transistor T8, first light-emitting transistor T5, and second light-emitting transistor T6 are all P-type transistors, and the compensation transistor T3 and first reset transistor T4 are N-type transistors for illustration.

[0050] In this embodiment, the source is only the output terminal of this application, and the drain is only the input terminal of this application; the only difference between the two is their naming.

[0051] In the following embodiments, the first direction is perpendicular to the extension direction of the data line, and the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°, for example, the first direction X is the horizontal direction and the second direction Y is the vertical direction.

[0052] The film structure of the pixel circuit PC of this application will be described below with reference to the structure in Figure 2.

[0053] Referring to Figure 3, the display area AA and non-display area NA of the display panel 100 may be provided with a substrate 110 and an array driving layer 120 disposed on the substrate 110. Within the display area AA, the display panel 100 may also be provided with a pixel definition layer PDL disposed on the array driving layer 120, a light-emitting device layer disposed on the same layer as the pixel definition layer PDL, and an encapsulation layer TFE disposed on the pixel definition layer PDL. The film layer structure within the display area AA is described below.

[0054] In this embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate, as well as a transparent substrate, can be used.

[0055] In this embodiment, the substrate 110 is used to support the various film layers disposed on the substrate 110. The substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0056] In this embodiment, the substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 stacked together. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0057] Please refer to Figure 3. The array driving layer 120 may include multiple thin-film transistors. The thin-film transistors may be etch-block type, back-channel etch type, or classified into bottom-gate thin-film transistors, top-gate thin-film transistors, etc., according to the position of the gate and the active layer, or classified into N-type thin-film transistors and P-type thin-film transistors according to their performance. The thin-film transistors in Figure 3 do not represent the structural diagram of any transistor in Figure 2, but are only schematic diagrams of each film layer of the display panel 100 of this application.

[0058] Referring to Figure 3, the array driving layer 120 may include a barrier insulating layer BF disposed on the substrate 110, a light-shielding layer 121 embedded in the barrier insulating layer BF, a buffer layer 122 disposed on the barrier insulating layer BF, a first active layer 123 disposed on the buffer layer 122, a first insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first insulating layer 124, a second insulating layer 126 disposed on the first gate layer 125, a second active layer 127 disposed on the second insulating layer 126, and a second active layer 128 disposed on the second active layer 129. The third insulating layer 128 on the 7, the second gate layer 129 disposed on the third insulating layer 128, the fourth insulating layer 130 disposed on the second gate layer 129, the first source-drain layer 131 disposed on the fourth insulating layer 130, the first planarization layer 132 disposed on the first source-drain layer 131, the second source-drain layer 133 disposed on the first planarization layer 132, and the second planarization layer 134 disposed on the second source-drain layer 133, the light-emitting device layer and the pixel definition layer PDL disposed on the second planarization layer 134, and the encapsulation layer TFE disposed on the pixel definition layer PDL.

[0059] Please refer to Figure 3. The light-shielding layer 121 is disposed on the second barrier layer 114. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 can be made of black light-shielding material, such as black light-shielding metal or black organic material.

[0060] Please refer to Figure 3. The buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may be composed of a compound consisting of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide film or a stacked structure of silicon oxide and silicon nitride.

[0061] In this embodiment, the light-shielding layer 121 can also be embedded within the buffer layer 122.

[0062] Please refer to Figure 3. The first active layer 123 is disposed on the buffer layer 122, and the second active layer 127 is disposed on the second insulating layer 126. In this application, the material of the first active layer 123 can be silicon semiconductor, such as low temperature polycrystalline silicon, and the material of the second active layer 127 can be oxide semiconductor, such as metal oxide, etc. Since the pixel circuit PC has N-type transistors and P-type transistors, the display area AA of this application is provided with metal oxide semiconductor and low temperature polycrystalline silicon semiconductor.

[0063] Please refer to Figure 3. The first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 are respectively disposed on the corresponding metal layer or semiconductor layer, and are disposed separately as different metal layers or semiconductor layers. The materials of the first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 can be inorganic materials composed of at least two elements in silicon oxynitride or organic materials with planarity.

[0064] Please refer to Figure 3. The first gate layer 125 and the second gate layer 129 are respectively disposed on the corresponding insulating layers. The materials of the first gate layer 125 and the second gate layer 129 can be copper, molybdenum, or molybdenum-titanium alloy, etc.

[0065] Please refer to Figure 3. The first source-drain layer 131 is disposed on the fourth insulating layer 130, and the second source-drain layer 133 is disposed on the first planarization layer 132. The materials of the first source-drain layer 131 and the second source-drain layer 133 can be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0066] Please refer to Figure 3. The first planarization layer 132 and the second planarization layer 134 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first planarization layer 132 and the second planarization layer 134 can be inorganic materials composed of silicon oxynitride or organic materials with flatness.

[0067] Please refer to Figure 3. The light-emitting device layer may include multiple light-emitting devices EL. Each light-emitting device EL has an anode AN, a light-emitting unit, and a cathode CA that are connected to the pixel circuit.

[0068] As shown in Figure 3, the two plates of the storage capacitor Cst in the display area AA of this application are respectively made of the material of the first gate layer 125 and the material of the second active layer 127. For example, the first plate Cst1 is located in the first gate layer 125 and the second plate Cst2 is located in the second active layer 127. The metal layer and an insulating layer between the original second active layer 127 and the first gate layer 125 are removed, reducing the number of film layers in the display panel 100, simplifying the manufacturing process of the display panel 100, and reducing the cost of the display panel 100.

[0069] Please refer to Figures 1 and 17. The multiple sub-pixels PX include multiple repeating units RU arranged along the first direction X and the second direction Y. Each repeating unit RU has two sub-pixels PX, and the patterns of some film layers in the two pixel circuits PC within a repeating unit RU are symmetrically arranged with the center line of the repeating unit RU as the axis. This center line can be parallel to the second direction Y. For example, the patterns of the first active layer 123, the first gate layer 125, the second active layer 127, the second gate layer 129, and the first source-drain layer 131 within the repeating unit RU are symmetrically arranged with the center line as the axis. The partial patterns in the light-shielding layer 121 and the second source-drain layer 133 within different pixel circuits PC have small differences.

[0070] It should be noted that due to limitations in processes and equipment, the film patterns in different pixel circuit PCs of this application have slight differences in actual products. Therefore, the symmetrical arrangement of this application is only within the error range. At the same time, in order to set up connection points with the upper structure, some structures widen the pattern in the area where the connection point is located, so that the pattern is asymmetrical, which is also within the error range.

[0071] It should be noted that the structure of the pixel circuit PC and the film layer structure described above in this application are applicable to all sub-pixels PX in this application.

[0072] The technical solution of this application is described below using the structure of each film layer in the two pixel circuits PC in a repeating unit RU as an example. For example, the repeating unit RU includes a first pixel circuit PC1 and a second pixel circuit PC2.

[0073] Please refer to Figures 4 and 5. Figure 4 is a film layer stacking diagram of a repeating unit RU in the display panel 100 of this application, and Figure 5 is a structural diagram of the first gate layer 125 in Figure 4. The pattern in the first gate layer 125 within a repeating unit RU can be symmetrically arranged.

[0074] Referring to Figure 5, the first gate layer 125 includes a first reset signal line Vi1, a switch control line Pscan1, a light emission control line EM, and a second reset control line Pscan2 extending along the first direction X. The first reset signal line Vi1, the switch control line Pscan1, the light emission control line EM, and the second reset control line Pscan2 are arranged sequentially at intervals along the second direction Y, and the first reset signal line Vi1, the switch control line Pscan1, the light emission control line EM, and the second reset control line Pscan2 within a repeating unit RU are connected to each other.

[0075] Referring to Figure 5, the first gate layer 125 also includes a first plate Cst1 of the storage capacitor Cst disposed between the switch control line Pscan1 and the light emission control line EM. The first plate Cst1 is spaced apart from the switch control line Pscan1 and the light emission control line EM, and the distance between the first plate Cst1 and the switch control line Pscan1 is greater than the distance between the first plate Cst1 and the light emission control line EM. At the same time, the two first plates Cst1 in a repeating unit RU are spaced apart.

[0076] Please refer to Figures 4 and 6. Figure 6 is a structural diagram of the first active layer 123 in Figure 4. The patterns in the first active layer 123 within a repeating unit RU are symmetrically arranged.

[0077] Please refer to Figure 6. The first active layer 123 includes the switching active part T2A of the switching transistor T2, the first light-emitting active part T5A of the first light-emitting transistor T5, the driving active part T1A of the driving transistor T1, the second light-emitting active part T6A of the second light-emitting transistor T6, the second reset active part T7A of the second reset transistor T7, the third reset active part T8A of the third reset transistor T8, the first extension ET1, and the second extension ET2.

[0078] Please refer to Figure 6. The switching active part T2A, the first light-emitting active part T5A, and the driving active part T1A are connected to the first connection point N1. The driving active part T1A and the second light-emitting active part T6A are connected to the second connection point N2. The first extension section ET1, the second light-emitting active part T6A, and the second reset active part T7A are connected to the third connection point N3. The first extension section ET1 extends from the third connection point N3 towards the side closer to the first light-emitting active part T5A. The third reset active part T8A is spaced apart from the above active parts and is located between the first extension section ET1 and the first light-emitting active part T5A. The second extension section ET2 is connected to the first connection point N1 and is located between the driving active part T1A and the first light-emitting active part T5A. At the same time, the two first light-emitting active parts T5A in a repeating unit RU are connected at the end away from the first node.

[0079] Please refer to Figure 6. The active switch part T2A, the first light-emitting active part T5A, the second light-emitting active part T6A, the second reset active part T7A, and the third reset active part T8A extend along the second direction Y and are strip-shaped. The first extension segment ET1 extends along the first direction X and is strip-shaped. The active drive part T1A can be U-shaped.

[0080] Please refer to Figure 7, which is a stack-up diagram of the first gate layer 125 and the first active layer 123 in Figure 4.

[0081] Please refer to Figure 7. The light-emitting control line EM and the first light-emitting active part T5A have an overlapping portion. The light-emitting control line EM in the overlapping portion is multiplexed as the first light-emitting gate T5G. The first light-emitting active part T5A in the overlapping portion is the channel of the first light-emitting transistor T5. The end of the first light-emitting active part T5A away from the first connection point N1 is multiplexed as the drain T5D of the first light-emitting transistor T5. The end of the first light-emitting active part T5A close to the first connection point N1 is multiplexed as the source T5S of the first light-emitting transistor T5. That is, the structure of the area where the first connection point N1 is located is the first node A in the pixel circuit PC.

[0082] Please refer to Figure 7. The light-emitting control line EM and the second light-emitting active part T6A have an overlapping portion. The light-emitting control line EM in the overlapping portion is multiplexed as the second light-emitting gate T6G. The second light-emitting active part T6A in the overlapping portion is the channel of the second light-emitting transistor T6. The end of the second light-emitting active part T6A away from the second connection point N2 is multiplexed as the source T6S of the second light-emitting transistor T6. The end of the second light-emitting active part T6A near the second connection point N2 is multiplexed as the drain T6D of the second light-emitting transistor T6. That is, the structure of the area where the second connection point N2 is located is the second node B in the pixel circuit PC. The structure of the area where the third connection point N3 is located is the position in the pixel circuit PC that is connected to the anode AN.

[0083] Please refer to Figure 7. The second reset control line Pscan2 and the second reset active part T7A have an overlapping portion. The second reset control line Pscan2 in the overlapping portion is multiplexed as the second reset gate T7G. The second reset active part T7A in the overlapping portion is the channel of the second reset transistor T7. The end of the second reset active part T7A near the third connection point N3 is multiplexed as the source T7S of the second reset transistor T7. The end of the second reset active part T7A away from the third connection point N3 is multiplexed as the drain T7D of the second reset transistor T7.

[0084] Please refer to Figure 7. The second reset control line Pscan2 and the third reset active part T8A have an overlapping portion. The second reset control line Pscan2 in the overlapping portion is multiplexed as the third reset gate T8G. The third reset active part T8A in the overlapping portion is the channel of the third reset transistor T8. The end of the third reset active part T8A near the light-emitting control line EM is multiplexed as the source T8S of the third reset transistor T8, and the end of the third reset active part T8A away from the light-emitting control line EM is multiplexed as the drain T8D of the third reset transistor T8.

[0085] Please refer to Figure 7. The switch control line Pscan1 and the active switch section T2A have an overlapping portion. The switch control line Pscan1 in the overlapping portion is multiplexed as the switch gate T2G. The active switch section T2A in the overlapping portion is the channel of the switch transistor T2. The end of the active switch section T2A near the first connection point N1 is multiplexed as the source T2S of the switch transistor T2, and the end of the active switch section T2A away from the first connection point N1 is multiplexed as the drain T2D of the switch transistor T2.

[0086] Please refer to Figures 4 and 8. Figure 8 is a structural diagram of the light-shielding layer 121 in Figure 4. The pattern in the light-shielding layer 121 within a repeating unit RU can be arranged symmetrically or asymmetrically. For example, the pattern in the light-shielding layer 121 in Figure 8 is arranged asymmetrically.

[0087] Please refer to Figure 8. The light-shielding layer 121 includes a reset light-shielding part T4L, a compensation light-shielding part T3L, and a driving light-shielding part T1L, which are spaced apart along the second direction Y. The reset light-shielding part T4L and the compensation light-shielding part T3L both extend along the first direction X. In the first direction X, the driving light-shielding parts T1L in two adjacent sub-pixels PX are connected, the reset light-shielding parts T4L in two adjacent sub-pixels PX are connected, and the compensation light-shielding parts T3L in two adjacent sub-pixels PX are connected.

[0088] In the structure shown in Figure 8, the light-shielding layer 121 also includes a first connecting segment CT1 connected to the driving light-shielding part T1L. The first connecting segment CT1 is located between the driving light-shielding part T1L and the compensating light-shielding part T3L, and the end of the first connecting segment CT1 away from the driving light-shielding part T1L is spaced apart from the compensating light-shielding part T3L. The electrical connector is electrically connected to the first connecting segment CT1.

[0089] It should be noted that in some repeating units RU, since the corresponding electrical connection line 50 is not set inside the pixel circuit PC, that is, the first connection segment CT1 is not required in the repeating unit RU. Therefore, the pattern in the light-shielding layer 121 in the corresponding repeating unit RU can be symmetrically arranged.

[0090] Please refer to Figure 9, which is a stack-up diagram of the first gate layer 125 and the light-shielding layer 121 in Figure 4.

[0091] In the structure shown in Figure 9, the reset light-shielding part T4L is disposed between the first reset signal line Vi1 and the switch control line Pscan1, the compensation light-shielding part T3L is disposed between the switch control line Pscan1 and the drive light-shielding part T1L, and the compensation light-shielding part T3L overlaps with part of the switch control line Pscan1, and the drive light-shielding part T1L overlaps with the first electrode plate Cst1.

[0092] In this embodiment, since the driving light-shielding part T1L can also serve as a shielding structure, the outer contour area of ​​the driving light-shielding part T1L in this application can be larger than the area of ​​the first electrode plate Cst1, and the orthographic projection of the first electrode plate Cst1 on the light-shielding layer 121 can be located within the driving light-shielding part T1L.

[0093] Please refer to Figures 10 to 12. Figure 10 is a structural diagram of the second active layer 127 in Figure 4. Figure 11 is a structural diagram of the second gate layer 129 in Figure 4. Figure 12 is a stack-up diagram of the first gate layer 125, the light-shielding layer 121, the first active layer 123, the second active layer 127, and the second gate layer 129 in Figure 4. The patterns in the second active layer 127 within a repeating unit RU can be symmetrically arranged, and the patterns in the second gate layer 129 within a repeating unit RU can be symmetrically arranged.

[0094] In the structure of Figure 10, the second active layer 127 includes the first reset active part T4A of the first reset transistor T4 and the compensation active part T3A of the compensation transistor T3. The first reset active part T4A and the compensation active part T3A both extend along the second direction Y and are elongated. The first reset active part T4A and the compensation active part T3A are connected at the fourth connection point N4.

[0095] In the structure of Figure 10, the second active layer 127 also includes a second electrode Cst2 of the storage capacitor Cst, and the second electrode Cst2 in a repeating unit RU is connected to each other, and the second electrode Cst2 is disposed opposite to the first electrode Cst1. The outer contour area of ​​the first electrode Cst1 can be smaller than the outer contour area of ​​the second electrode Cst2, and the outer contour area of ​​the second electrode Cst2 is smaller than the outer contour area of ​​the driving light shield T1L.

[0096] In the structure of FIG11, the second gate layer 129 includes a first reset control line Nscan2, a compensation control line Nscan1 and a third reset signal line Vi3 arranged at intervals along the second direction Y. The first reset control line Nscan2 and the compensation control line Nscan1 both extend along the first direction X.

[0097] In the structure of Figure 12, the first reset control line Nscan2 and the reset light-shielding part T4L both overlap with the first reset active part T4A. The first reset control line Nscan2 in the overlapping part is multiplexed as the first reset gate T4G. The first reset active part T4A in the overlapping part is the channel of the first reset transistor T4. The end of the first reset active part T4A near the fourth connection point N4 is multiplexed as the source T4S of the first reset transistor T4. The end of the first reset active part T4A away from the fourth connection point N4 is multiplexed as the drain T4D of the first reset transistor T4. That is, the structure of the area where the fourth connection point N4 is located is the third node Q in the pixel circuit PC, and the control signals transmitted by the first reset control line Nscan2 and the reset light-shielding part T4L are the same.

[0098] In the structure shown in Figure 12, the compensation shading section T3L and the compensation control line Nscan1 both overlap with the compensation active section T3A of the compensation transistor T3. The compensation control line Nscan1 in the overlapping section is multiplexed as the compensation gate T3G. The compensation active section T3A in the overlapping section is the channel of the compensation transistor T3. The end of the compensation active section T3A near the fourth connection point N4 is multiplexed as the drain T3D of the compensation transistor T3, and the end of the compensation active section T3A away from the fourth connection point N4 is multiplexed as the source T3S of the compensation transistor T3. The control signals transmitted by the compensation shading section T3L and the compensation control line Nscan1 are the same.

[0099] In the structure shown in Figure 12, the first reset control line Nscan2 and the reset light-shielding part T4L overlap, and the compensation control line Nscan1 and the compensation light-shielding part T3L overlap. Furthermore, the area of ​​the overlap between the first reset control line Nscan2 and the active part of the first reset transistor T4 is larger than the area of ​​the overlap between the reset light-shielding part T4L and the active part of the first reset transistor T4; and the area of ​​the overlap between the compensation light-shielding part T3L and the active part of the compensation transistor T3 is larger than the area of ​​the overlap between the compensation control line Nscan1 and the active part of the compensation transistor T3.

[0100] Please refer to Figures 4, 13 and 14. Figure 13 is a structural diagram of the first source-drain layer 131 in Figure 4. Please refer to Figure 14. Figure 14 is a stack-up diagram of the first gate layer 125, the first active layer 123, the second active layer 127, the second gate layer 129 and the first source-drain layer 131 in Figure 4. The pattern in the first source-drain layer 131 within a repeating unit RU can be symmetrically arranged.

[0101] Please refer to Figures 13 and 14. The first source-drain layer 131 includes a lateral fan-out line FIAH and a second reset signal line Vi2. The lateral fan-out line FIAH is located on the side of the first reset signal line Vi1 away from the switch control line Pscan1. The second reset signal line Vi2 is located between the third reset signal line Vi3 and the second reset control line Pscan2.

[0102] Please refer to Figure 14. The first source-drain layer 131 also includes a third connection segment CT3. One end of the third connection segment CT3 passes through a via and is connected to the first reset signal line Vi1. The other end of the third connection segment CT3 passes through a via and is connected to the end of the first reset active part T4A away from the fourth connection point N4.

[0103] Please refer to Figure 14. The first source-drain layer 131 also includes a fourth connection segment CT4. One end of the fourth connection segment CT4 passes through a via and is connected to the data line Data. The other end of the fourth connection segment CT4 passes through a via and is connected to the end of the active switch T2A away from the first connection point N1.

[0104] Please refer to Figure 14. The first source-drain layer 131 also includes a fifth connection segment CT5. One end of the fifth connection segment CT5 passes through a via and is connected to one end of the fourth connection point N4 of the compensation active part T3A. The other end of the fifth connection segment CT5 passes through the clearance hole HL0 in the second electrode plate Cst2 and is connected to the first electrode plate Cst1.

[0105] Please refer to Figure 14. The first source-drain layer 131 also includes a sixth connection segment CT6. One end of the sixth connection segment CT6 passes through a via and is connected to the end of the compensation active part T3A away from the fourth connection point N4. The other end of the sixth connection segment CT6 passes through a via and is connected to the end of the second light-emitting active part T6A away from the third connection point N3.

[0106] Please refer to Figure 14. The first source-drain layer 131 also includes a seventh connection segment CT7. One end of the seventh connection segment CT7 passes through a via and is connected to the end of the first extension segment ET1 away from the third connection point N3. The other end of the seventh connection segment CT7 passes through a via and is connected to the upper metal layer.

[0107] Please refer to Figure 14. The first source-drain layer 131 also includes an eighth connection segment CT8. One end of the eighth connection segment CT8 passes through a via and is connected to the second extension segment ET2. The other end of the eighth connection segment CT8 passes through a via and is connected to the end of the third reset active part T8A near the light emission control line EM.

[0108] In this embodiment, the third reset signal line Vi3 includes a reset horizontal segment Vi3a and a reset extension segment Vi3b. The reset horizontal segment Vi3a extends along the first direction X, and the reset extension segment Vi3b extends along the second direction Y. The reset extension segment Vi3b has an overlapping portion with the eighth connection segment CT8, which is equivalent to the reset extension segment Vi3b overlapping with the area where the first node is located.

[0109] Please refer to Figure 14. The first source-drain layer 131 also includes a ninth connection segment CT9. One end of the ninth connection segment CT9 passes through a via and is connected to the reset extension segment Vi3b. The other end of the ninth connection segment CT9 passes through a via and is connected to the end of the third reset active part T8A away from the light emission control line EM. The two ninth connection segments CT9 in a repeating unit RU are electrically connected at the position where they overlap with the reset extension segment Vi3b.

[0110] Please refer to Figures 13 and 14. The first source-drain layer 131 also includes a first sub-line 510 constituting the electrical connection line 50. The first sub-line 510 includes a first transverse segment 511 and a first longitudinal segment 512 connected to each other. The first transverse segment 511 is disposed along a first direction X, and the first longitudinal segment 512 is disposed along a second direction Y. The orthographic projection of the first transverse segment 511 on the light-shielding layer 121 is located between the driving light-shielding part T1L and the compensation light-shielding part T3L, and has an overlapping portion with the first connecting segment CT1. The first transverse segment 511 passes through the first via HL1 and is electrically connected to the first connecting segment CT1.

[0111] In this embodiment, the first transverse segments 511 in a repeating unit RU are connected to each other, and the first longitudinal segments 512 in a repeating unit RU are shared. Meanwhile, the first longitudinal segment 512 includes a first part 512a close to the first transverse segment 511 and a second part 512b away from the first transverse segment 511. The end of the first part 512a close to the second part 512b passes through a via and is electrically connected to the second electrode plate Cst2. The end of the second part 512b away from the first part 512a passes through a via and is connected to the end of the first light-emitting active part T5A away from the first connection point N1.

[0112] In this embodiment, the line width of the first part 512a is greater than the line width of the second part 512b.

[0113] Please refer to Figures 4 and 15. Figure 15 is a structural diagram of the second source-drain layer 133 in Figure 4, showing an asymmetric pattern arrangement in the second source-drain layer 133 within a repeating unit RU.

[0114] Please refer to Figures 4 and 15. The second source-drain layer 133 includes a high-potential line VDD arranged along the first direction X, a second sub-line 520 constituting the electrical connection line 50, and a data line Data. The high-potential line VDD, the second sub-line 520, and the data line Data all extend along the second direction Y.

[0115] In this embodiment, the second source-drain layer 133 further includes a second connection segment CT2. One end of the second connection segment CT2 is connected to the second sub-line 520, and the other end of the second connection segment CT2 is connected to the high potential line VDD. The end of the first lateral segment 511 that is away from the first longitudinal segment 512 overlaps with the high potential line VDD, and the high potential line VDD passes through the second via HL2 and is electrically connected to the first lateral segment 511.

[0116] It should be noted that, referring to Figure 15, within a repeating unit RU, the pixel circuit PC on the left side may include a high-potential line VDD, a second sub-line 520, and a data line Data arranged along the first direction X, and the pixel circuit PC on the right side may include a data line Data, a vertical fan-out line FIAZ, and a high-potential line VDD arranged along the first direction X. Each column of sub-pixels PX corresponds to one high-potential line VDD and one data line Data, and each sub-pixel PX within each repeating unit RU is provided with a vertical fan-out line FIAZ, which can be electrically connected to the horizontal fan-out line FIAH.

[0117] It should be noted that the second sub-line 520 exists only in some repeating units RU, and in different repeating units RU, the position of the second sub-line 520 can be set as a first reset connection line Vi1c, a second reset connection line Vi2c, and a third reset connection line Vi3c extending along the second direction Y.

[0118] For example, please refer to Figure 16. Figure 16 shows two rows of sub-pixels PX, and each row of sub-pixels PX includes four repeating units RU. In the two repeating units RU in the third column, the left sub-pixel PX is provided with a first reset connection line Vi1c. In the second direction Y, two adjacent first reset signal lines Vi1 are electrically connected through the first reset connection line Vi1c. In the two repeating units RU in the second column, the left sub-pixel PX is provided with a second reset connection line Vi2c. In the second direction Y, two adjacent second reset signal lines Vi2 are connected through the first reset connection line Vi1c. The two reset connection lines Vi2c are electrically connected; in the two repeating units RU in the first column, the left sub-pixel PX is provided with a third reset connection line Vi3c, and in the second direction Y, two adjacent third reset signal lines Vi3 are electrically connected through the third reset connection line Vi3c; in the two repeating units RU in the fourth column, the left sub-pixel PX is provided with a second sub-line 520, and in the second direction Y, the high potential line VDD, the first sub-line 510, the second electrode plate Cst2 and the driving light shield T1L of the two adjacent rows are connected to each other and all transmit high level.

[0119] In the structure shown in Figure 16, the first reset connection line Vi1c, the second reset connection line Vi2c, the third reset connection line Vi3c, and the electrical connection line 50 are arranged sequentially at intervals in the first direction X.

[0120] It should be noted that the first reset connection line Vi1c, the second reset connection line Vi2c, the third reset connection line Vi3c and the electrical connection line 50 can all be spaced apart by one repeating unit RU, or they can be designed differently according to the differences in the signals transmitted by the different connection lines; for example, the number of repeating units RU between two adjacent first reset connection lines Vi1c is less than the number of repeating units RU between the other three types of connection lines.

[0121] It should be noted that, in the first direction X, the third reset connection line Vi3c, the second reset connection line Vi2c, the first reset connection line Vi1c, and the electrical connection line 50 are arranged in sequence at intervals.

[0122] In this embodiment, the present application provides a longitudinal electrical connection line 50 to electrically connect the driving light-shielding part T1L, the second plate Cst2 of the storage capacitor Cst, and the high-potential line VDD located in the light-shielding layer 121 to each other, so that the structure for transmitting high-potential signals forms a horizontal and vertical mesh structure, reducing the impedance of the driving light-shielding part T1L, improving the potential difference in different areas of the light-shielding layer 121, and improving the display effect of the display panel 100.

[0123] Please refer to Figure 17, which is a stacked diagram of the pattern and anode layer in Figure 4 of this application.

[0124] Please refer to Figure 17. The display panel 100 may include a first pixel circuit PC1 and a second pixel circuit PC2, as well as a first anode AN1 connected to the first pixel circuit PC1 and a second anode AN2 connected to the second pixel circuit PC2. The first anode overlaps with both the first pixel circuit PC1 and the second pixel circuit PC2. In order to avoid the influence of the high potential line VDD on the anode potential as much as possible, the first anode and the second anode AN2 of this application are set to avoid the high potential line VDD as much as possible.

[0125] In this embodiment, the first pixel circuit PC1 can be one of the red sub-pixel PX, the green sub-pixel PX, and the blue sub-pixel PX, and the second pixel circuit PC2 can be the other of the red sub-pixel PX, the green sub-pixel PX, and the blue sub-pixel PX.

[0126] It should be noted that the transmission wire of the present application extends along the first direction X or the second direction Y, which only means that the wire extends in that direction, and does not mean that the wire is a straight line. For example, the wire of the present application can be a bent curve or a broken line.

[0127] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0128] The technical solutions provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions in the embodiments of this application.

Claims

1. A display panel comprising a plurality of sub-pixels arranged in a first direction and a second direction, at least one of the sub-pixels comprising a pixel circuit, the pixel circuit comprising a driving transistor and a storage capacitor connected thereto; wherein, The display panel includes: The light-shielding layer includes a driving light-shielding portion corresponding to the driving transistor, and in the first direction, the driving light-shielding portions in two adjacent sub-pixels are connected; The first active layer includes the active portion of the driving transistor; The first gate layer includes the gate of the driving transistor and one plate of the storage capacitor; The second active layer includes the other plate of the storage capacitor; The display panel further includes an electrical connection line extending along the second direction, in which the driving light-shielding portions within two adjacent sub-pixels are electrically connected via the electrical connection line.

2. The display panel according to claim 1, wherein, The pixel circuit further includes a switching transistor, a compensation transistor, and a first reset transistor. The switching transistor and the driving transistor are connected to a first node, the driving transistor and the compensation transistor are connected to a second node, and the first reset transistor is connected to the driving transistor and the compensation transistor to a third node. The light-shielding part further includes a reset light-shielding part corresponding to the reset transistor and a compensation light-shielding part corresponding to the compensation transistor. The reset light-shielding part, the compensation light-shielding part and the driving light-shielding part are arranged at intervals along the second direction. In the first direction, the reset light-shielding parts in two adjacent sub-pixels are connected, and the compensation light-shielding parts in two adjacent sub-pixels are connected.

3. The display panel according to claim 2, wherein, The light-shielding layer further includes a first connecting segment connected to the driving light-shielding part. The first connecting segment is disposed between the driving light-shielding part and the compensating light-shielding part, and the end of the first connecting segment away from the driving light-shielding part is spaced apart from the compensating light-shielding part.

4. The display panel according to claim 3, wherein, The display panel also includes: A first source-drain layer is disposed on the side of the second active layer away from the first active layer. The first source-drain layer includes a first sub-line constituting the electrical connection line. The first sub-line includes a first transverse segment and a first longitudinal segment connected to each other. The first transverse segment is disposed along the first direction, and the first longitudinal segment is disposed along the second direction. Wherein, the orthographic projection of the first transverse segment on the light-shielding layer is located between the driving light-shielding part and the compensating light-shielding part, and has an overlapping portion with the first connecting segment. The first transverse segment passes through the first through hole and is electrically connected to the first connecting segment.

5. The display panel according to claim 4, wherein, The display panel also includes: The second source-drain layer is disposed on the side of the first source-drain layer away from the second active layer. The second source-drain layer includes a high-potential line arranged along the first direction, a second sub-line constituting the electrical connection line, and a data line. The high-potential line, the second sub-line, and the data line all extend along the second direction. The second sub-line is electrically connected to the first transverse segment.

6. The display panel according to claim 5, wherein, The second source-drain layer further includes a second connection segment, one end of which is connected to the second sub-line, and the other end of which is connected to the high-potential line; Wherein, the end of the first transverse segment away from the first longitudinal segment overlaps with the high-potential line, and the high-potential line passes through the second via and is electrically connected to the first transverse segment.

7. The display panel according to claim 4, wherein, The pixel circuit also includes a first light-emitting transistor connected to the first node; The first longitudinal segment includes a first part located near the first transverse segment and a second part located away from the first transverse segment. The end of the first part near the second part is electrically connected to the electrode of the storage capacitor located in the second active layer, and the end of the second part away from the first part is connected to the active part of the first light-emitting transistor.

8. The display panel according to claim 7, wherein, The line width of the first part is greater than the line width of the second part.

9. The display panel according to claim 1, wherein, The outer contour area of ​​both plates of the storage capacitor is smaller than the outer contour area of ​​the driving light-shielding part.

10. The display panel according to claim 9, wherein, The outer contour area of ​​the electrode plate of the storage capacitor located in the second active layer is greater than the outer contour area of ​​the electrode plate of the storage capacitor located in the first gate layer.

11. The display panel according to any one of claims 2 to 10, wherein, The display panel also includes: The second gate layer is disposed on the side of the second active layer away from the first active layer. The second gate layer includes a first reset control line and a compensation control line arranged along the second direction. Both the first reset control line and the compensation control line extend along the first direction. Wherein, the first reset control line and the reset light-shielding part both have overlapping portions with the active portion of the first reset transistor, the compensation light-shielding part and the compensation control line both have overlapping portions with the active portion of the compensation transistor, and the control signals transmitted by the first reset control line and the reset light-shielding part are the same, and the control signals transmitted by the compensation light-shielding part and the compensation control line are the same.

12. The display panel according to claim 11, wherein, The area of ​​the first reset control line and the overlapping portion with the active portion of the first reset transistor is greater than the area of ​​the reset light-shielding portion and the overlapping portion with the active portion of the first reset transistor. The area of ​​the overlapping portion of the compensation shading part and the active part of the compensation transistor is greater than the area of ​​the overlapping portion of the compensation control line and the active part of the compensation transistor.

13. The display panel according to any one of claims 2 to 10, wherein, The first gate layer further includes a first reset signal line connected to the drain of the first reset transistor, and the first reset signal line extends along the first direction; The display panel further includes a first reset connection line extending along the second direction. In the second direction, two adjacent first reset signal lines are electrically connected through the first reset connection line, and the first reset connection line and the electrical connection line are spaced apart in the first direction.

14. The display panel according to claim 13, wherein, The pixel circuit further includes a second reset transistor, the drain of which is connected to a second reset signal line, and the source of which is connected to the anode of the light-emitting device. The display panel further includes a second reset connection line extending along the second direction. Two adjacent second reset signal lines are electrically connected through the second reset connection line, and the first reset connection line, the second reset connection line, and the electrical connection line are arranged at intervals in the first direction.

15. The display panel according to claim 14, wherein, The pixel circuit further includes a third reset transistor, the drain of which is connected to a third reset signal line, and the source of which is connected to the switching transistor and the driving transistor. The display panel further includes a third reset connection line extending along the second direction. Two adjacent third reset signal lines are electrically connected through the third reset connection line, and the first reset connection line, the second reset connection line, the third reset connection line, and the electrical connection line are arranged at intervals in the first direction.

16. The display panel according to claim 15, wherein, In the first direction X, the third reset connection line, the second reset connection line, the first reset connection line, and the electrical connection line are all located in the same metal film layer.

17. The display panel according to claim 14, wherein, The third reset signal line includes a reset horizontal segment and a reset extension segment. The reset horizontal segment extends along the first direction, and the reset extension segment extends along the second direction, and the reset extension segment overlaps with the area where the first node is located.

18. The display panel according to any one of claims 1 to 10, wherein, The plurality of sub-pixels include a plurality of repeating units arranged along the first direction and the second direction, each repeating unit having two sub-pixels; In one of the repeating units, the patterns of partial film layers in the two pixel circuits are symmetrically arranged with the center line of the repeating unit as the axis, and the center line is parallel to the second direction.

19. The display panel according to any one of claims 1 to 10, wherein, The material of the first active layer includes silicon semiconductor, and the material of the second active layer includes oxide semiconductor.

20. A display device, wherein, The display device includes a display panel as described in any one of 1 to 19 above.

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